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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.30 97.92 95.84 93.38 100.00 98.52 99.00 96.47


Total test records in report: 988
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T50 /workspace/coverage/default/2.lc_ctrl_sec_cm.3471695018 Jul 13 06:31:04 PM PDT 24 Jul 13 06:31:30 PM PDT 24 117073155 ps
T814 /workspace/coverage/default/34.lc_ctrl_state_post_trans.3171545389 Jul 13 06:33:01 PM PDT 24 Jul 13 06:33:09 PM PDT 24 76213328 ps
T815 /workspace/coverage/default/10.lc_ctrl_sec_mubi.2931045901 Jul 13 06:31:53 PM PDT 24 Jul 13 06:32:08 PM PDT 24 543426886 ps
T816 /workspace/coverage/default/47.lc_ctrl_sec_mubi.3962352158 Jul 13 06:33:49 PM PDT 24 Jul 13 06:34:06 PM PDT 24 293629650 ps
T817 /workspace/coverage/default/25.lc_ctrl_state_post_trans.382435011 Jul 13 06:32:44 PM PDT 24 Jul 13 06:32:48 PM PDT 24 339725366 ps
T818 /workspace/coverage/default/35.lc_ctrl_state_post_trans.692747293 Jul 13 06:33:11 PM PDT 24 Jul 13 06:33:19 PM PDT 24 312707368 ps
T819 /workspace/coverage/default/12.lc_ctrl_errors.823693611 Jul 13 06:31:56 PM PDT 24 Jul 13 06:32:12 PM PDT 24 1295082051 ps
T820 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.48593015 Jul 13 06:31:09 PM PDT 24 Jul 13 06:31:20 PM PDT 24 1532212301 ps
T821 /workspace/coverage/default/36.lc_ctrl_state_failure.3131034165 Jul 13 06:33:08 PM PDT 24 Jul 13 06:33:31 PM PDT 24 538166506 ps
T822 /workspace/coverage/default/3.lc_ctrl_errors.2439838561 Jul 13 06:31:06 PM PDT 24 Jul 13 06:31:16 PM PDT 24 839743554 ps
T232 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.827924881 Jul 13 06:31:13 PM PDT 24 Jul 13 06:31:14 PM PDT 24 38453575 ps
T823 /workspace/coverage/default/0.lc_ctrl_jtag_access.418773339 Jul 13 06:30:59 PM PDT 24 Jul 13 06:31:07 PM PDT 24 448244773 ps
T824 /workspace/coverage/default/21.lc_ctrl_security_escalation.3758048251 Jul 13 06:32:25 PM PDT 24 Jul 13 06:32:39 PM PDT 24 268491526 ps
T825 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.537495295 Jul 13 06:33:38 PM PDT 24 Jul 13 06:33:54 PM PDT 24 1966112989 ps
T826 /workspace/coverage/default/4.lc_ctrl_prog_failure.3738985533 Jul 13 06:31:20 PM PDT 24 Jul 13 06:31:25 PM PDT 24 363933340 ps
T827 /workspace/coverage/default/4.lc_ctrl_sec_mubi.4144327053 Jul 13 06:31:19 PM PDT 24 Jul 13 06:31:34 PM PDT 24 717150052 ps
T111 /workspace/coverage/default/3.lc_ctrl_sec_cm.572341160 Jul 13 06:31:20 PM PDT 24 Jul 13 06:31:48 PM PDT 24 132162787 ps
T828 /workspace/coverage/default/6.lc_ctrl_state_failure.3829484627 Jul 13 06:32:20 PM PDT 24 Jul 13 06:32:47 PM PDT 24 1101086982 ps
T829 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2915055107 Jul 13 06:31:54 PM PDT 24 Jul 13 06:32:05 PM PDT 24 1150143732 ps
T830 /workspace/coverage/default/31.lc_ctrl_stress_all.3015533042 Jul 13 06:33:00 PM PDT 24 Jul 13 06:34:00 PM PDT 24 5502798784 ps
T831 /workspace/coverage/default/31.lc_ctrl_smoke.3603435628 Jul 13 06:32:57 PM PDT 24 Jul 13 06:33:01 PM PDT 24 37758485 ps
T832 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2082328040 Jul 13 06:32:16 PM PDT 24 Jul 13 06:32:23 PM PDT 24 432126237 ps
T833 /workspace/coverage/default/48.lc_ctrl_stress_all.3385685198 Jul 13 06:33:49 PM PDT 24 Jul 13 06:42:49 PM PDT 24 21050219635 ps
T834 /workspace/coverage/default/9.lc_ctrl_jtag_access.508739489 Jul 13 06:31:52 PM PDT 24 Jul 13 06:31:54 PM PDT 24 112825576 ps
T835 /workspace/coverage/default/32.lc_ctrl_prog_failure.3072657791 Jul 13 06:33:00 PM PDT 24 Jul 13 06:33:04 PM PDT 24 350487757 ps
T836 /workspace/coverage/default/4.lc_ctrl_security_escalation.2250025167 Jul 13 06:31:20 PM PDT 24 Jul 13 06:31:32 PM PDT 24 3042976449 ps
T837 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3549751204 Jul 13 06:31:18 PM PDT 24 Jul 13 06:31:30 PM PDT 24 207176808 ps
T838 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3950915295 Jul 13 06:32:11 PM PDT 24 Jul 13 06:32:58 PM PDT 24 1484711198 ps
T839 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3270838643 Jul 13 06:33:47 PM PDT 24 Jul 13 06:33:59 PM PDT 24 836636805 ps
T840 /workspace/coverage/default/8.lc_ctrl_errors.1156282994 Jul 13 06:31:44 PM PDT 24 Jul 13 06:31:58 PM PDT 24 1142711006 ps
T841 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3939551298 Jul 13 06:32:25 PM PDT 24 Jul 13 06:32:27 PM PDT 24 15951472 ps
T842 /workspace/coverage/default/47.lc_ctrl_state_failure.413562604 Jul 13 06:33:48 PM PDT 24 Jul 13 06:34:22 PM PDT 24 863617708 ps
T843 /workspace/coverage/default/5.lc_ctrl_stress_all.2934470475 Jul 13 06:31:19 PM PDT 24 Jul 13 06:32:49 PM PDT 24 2462834087 ps
T844 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.211582059 Jul 13 06:33:19 PM PDT 24 Jul 13 06:33:29 PM PDT 24 193450908 ps
T845 /workspace/coverage/default/41.lc_ctrl_state_failure.3060741187 Jul 13 06:33:28 PM PDT 24 Jul 13 06:33:54 PM PDT 24 1360432155 ps
T846 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1249289660 Jul 13 06:33:27 PM PDT 24 Jul 13 06:33:29 PM PDT 24 12878733 ps
T847 /workspace/coverage/default/19.lc_ctrl_alert_test.1866354119 Jul 13 06:32:27 PM PDT 24 Jul 13 06:32:29 PM PDT 24 57003558 ps
T848 /workspace/coverage/default/49.lc_ctrl_jtag_access.2121699316 Jul 13 06:33:57 PM PDT 24 Jul 13 06:34:02 PM PDT 24 679413290 ps
T849 /workspace/coverage/default/24.lc_ctrl_smoke.3245209788 Jul 13 06:32:33 PM PDT 24 Jul 13 06:32:38 PM PDT 24 51918082 ps
T850 /workspace/coverage/default/11.lc_ctrl_state_post_trans.1529789267 Jul 13 06:31:54 PM PDT 24 Jul 13 06:32:03 PM PDT 24 577922071 ps
T81 /workspace/coverage/default/12.lc_ctrl_stress_all.3779970246 Jul 13 06:31:55 PM PDT 24 Jul 13 06:32:16 PM PDT 24 2434010702 ps
T851 /workspace/coverage/default/36.lc_ctrl_sec_mubi.4033605726 Jul 13 06:33:12 PM PDT 24 Jul 13 06:33:24 PM PDT 24 1819879225 ps
T852 /workspace/coverage/default/40.lc_ctrl_state_failure.501890401 Jul 13 06:33:21 PM PDT 24 Jul 13 06:33:44 PM PDT 24 426060033 ps
T853 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1676556493 Jul 13 06:33:36 PM PDT 24 Jul 13 06:33:39 PM PDT 24 74413267 ps
T854 /workspace/coverage/default/38.lc_ctrl_smoke.3466311644 Jul 13 06:33:18 PM PDT 24 Jul 13 06:33:19 PM PDT 24 45063057 ps
T855 /workspace/coverage/default/40.lc_ctrl_errors.1220374072 Jul 13 06:33:19 PM PDT 24 Jul 13 06:33:33 PM PDT 24 800230160 ps
T856 /workspace/coverage/default/43.lc_ctrl_stress_all.1806497499 Jul 13 06:33:38 PM PDT 24 Jul 13 06:34:32 PM PDT 24 5845177054 ps
T857 /workspace/coverage/default/12.lc_ctrl_smoke.1724674541 Jul 13 06:31:58 PM PDT 24 Jul 13 06:32:01 PM PDT 24 724538985 ps
T858 /workspace/coverage/default/21.lc_ctrl_alert_test.1556638780 Jul 13 06:32:27 PM PDT 24 Jul 13 06:32:29 PM PDT 24 17212558 ps
T859 /workspace/coverage/default/13.lc_ctrl_stress_all.4120818185 Jul 13 06:32:06 PM PDT 24 Jul 13 06:34:18 PM PDT 24 23813237387 ps
T860 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3372477282 Jul 13 06:33:01 PM PDT 24 Jul 13 06:33:17 PM PDT 24 339513996 ps
T861 /workspace/coverage/default/42.lc_ctrl_jtag_access.1762660962 Jul 13 06:33:26 PM PDT 24 Jul 13 06:33:33 PM PDT 24 971228194 ps
T862 /workspace/coverage/default/31.lc_ctrl_prog_failure.812790852 Jul 13 06:32:58 PM PDT 24 Jul 13 06:33:02 PM PDT 24 104734146 ps
T137 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.171322761 Jul 13 06:27:03 PM PDT 24 Jul 13 06:27:05 PM PDT 24 27060361 ps
T129 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2025879982 Jul 13 06:26:22 PM PDT 24 Jul 13 06:26:23 PM PDT 24 17987806 ps
T125 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.749628471 Jul 13 06:26:22 PM PDT 24 Jul 13 06:26:26 PM PDT 24 133541227 ps
T158 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3229624604 Jul 13 06:26:21 PM PDT 24 Jul 13 06:26:23 PM PDT 24 24257527 ps
T162 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4008567073 Jul 13 06:26:42 PM PDT 24 Jul 13 06:26:45 PM PDT 24 47537429 ps
T134 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3113104850 Jul 13 06:26:40 PM PDT 24 Jul 13 06:26:41 PM PDT 24 45511424 ps
T126 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.187256611 Jul 13 06:26:40 PM PDT 24 Jul 13 06:26:44 PM PDT 24 1606600749 ps
T135 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2864355658 Jul 13 06:26:27 PM PDT 24 Jul 13 06:26:29 PM PDT 24 92589246 ps
T163 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1159710752 Jul 13 06:26:45 PM PDT 24 Jul 13 06:27:04 PM PDT 24 697667838 ps
T131 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097207277 Jul 13 06:26:29 PM PDT 24 Jul 13 06:26:31 PM PDT 24 96358386 ps
T159 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2019891092 Jul 13 06:26:48 PM PDT 24 Jul 13 06:27:00 PM PDT 24 443010832 ps
T168 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1288982872 Jul 13 06:26:45 PM PDT 24 Jul 13 06:26:48 PM PDT 24 399168030 ps
T220 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3952643002 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:29 PM PDT 24 72053869 ps
T205 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1091166248 Jul 13 06:26:35 PM PDT 24 Jul 13 06:26:37 PM PDT 24 14866843 ps
T169 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3622770679 Jul 13 06:26:38 PM PDT 24 Jul 13 06:26:39 PM PDT 24 65840364 ps
T206 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1428212192 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 12995849 ps
T863 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.713325433 Jul 13 06:26:44 PM PDT 24 Jul 13 06:26:46 PM PDT 24 127905437 ps
T221 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3915572092 Jul 13 06:26:56 PM PDT 24 Jul 13 06:26:58 PM PDT 24 30526201 ps
T864 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2256976417 Jul 13 06:26:42 PM PDT 24 Jul 13 06:26:44 PM PDT 24 28239867 ps
T160 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.703084441 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:28 PM PDT 24 298661105 ps
T170 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3971368799 Jul 13 06:26:30 PM PDT 24 Jul 13 06:26:32 PM PDT 24 49558081 ps
T127 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.987181734 Jul 13 06:27:01 PM PDT 24 Jul 13 06:27:04 PM PDT 24 179520773 ps
T144 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1640529189 Jul 13 06:26:35 PM PDT 24 Jul 13 06:26:37 PM PDT 24 18403566 ps
T130 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3417312002 Jul 13 06:26:54 PM PDT 24 Jul 13 06:26:58 PM PDT 24 85450420 ps
T207 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.513753005 Jul 13 06:26:13 PM PDT 24 Jul 13 06:26:14 PM PDT 24 22007774 ps
T138 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1794916878 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:59 PM PDT 24 69222100 ps
T865 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2545985600 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:36 PM PDT 24 36231378 ps
T176 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3815061130 Jul 13 06:26:50 PM PDT 24 Jul 13 06:26:52 PM PDT 24 482674147 ps
T866 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1327587888 Jul 13 06:26:50 PM PDT 24 Jul 13 06:26:51 PM PDT 24 82488746 ps
T132 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.94072809 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 145663392 ps
T133 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1407506919 Jul 13 06:26:55 PM PDT 24 Jul 13 06:27:00 PM PDT 24 1741591091 ps
T867 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1681353678 Jul 13 06:26:37 PM PDT 24 Jul 13 06:26:39 PM PDT 24 21202275 ps
T161 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.200008458 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:36 PM PDT 24 175601122 ps
T868 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1595334821 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 40882164 ps
T208 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.680644798 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:30 PM PDT 24 20106876 ps
T209 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3845037724 Jul 13 06:26:35 PM PDT 24 Jul 13 06:26:36 PM PDT 24 336954352 ps
T152 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3607983963 Jul 13 06:26:56 PM PDT 24 Jul 13 06:27:00 PM PDT 24 213159235 ps
T869 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1539730655 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:36 PM PDT 24 13803164 ps
T870 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.993404391 Jul 13 06:26:48 PM PDT 24 Jul 13 06:26:50 PM PDT 24 79515157 ps
T210 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.500518950 Jul 13 06:26:21 PM PDT 24 Jul 13 06:26:24 PM PDT 24 75257067 ps
T136 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3924477632 Jul 13 06:26:57 PM PDT 24 Jul 13 06:27:02 PM PDT 24 87665157 ps
T871 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3117967490 Jul 13 06:26:45 PM PDT 24 Jul 13 06:26:46 PM PDT 24 25387935 ps
T153 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2718386063 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 56988197 ps
T872 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3246907339 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 19109505 ps
T211 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.796052860 Jul 13 06:26:58 PM PDT 24 Jul 13 06:27:00 PM PDT 24 15111747 ps
T873 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.310160832 Jul 13 06:26:29 PM PDT 24 Jul 13 06:26:31 PM PDT 24 27374452 ps
T147 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2030621784 Jul 13 06:26:13 PM PDT 24 Jul 13 06:26:15 PM PDT 24 317792886 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3212716567 Jul 13 06:26:22 PM PDT 24 Jul 13 06:26:29 PM PDT 24 2840004515 ps
T875 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.63491423 Jul 13 06:26:35 PM PDT 24 Jul 13 06:26:37 PM PDT 24 17391393 ps
T212 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1780754878 Jul 13 06:27:01 PM PDT 24 Jul 13 06:27:03 PM PDT 24 15512968 ps
T876 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.127342286 Jul 13 06:27:04 PM PDT 24 Jul 13 06:27:06 PM PDT 24 480181786 ps
T877 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.738382566 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:57 PM PDT 24 48561337 ps
T878 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1286780970 Jul 13 06:26:19 PM PDT 24 Jul 13 06:26:20 PM PDT 24 176323292 ps
T879 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.507655206 Jul 13 06:26:41 PM PDT 24 Jul 13 06:26:55 PM PDT 24 2148576216 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1103351388 Jul 13 06:26:41 PM PDT 24 Jul 13 06:26:43 PM PDT 24 75773215 ps
T881 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.884737968 Jul 13 06:26:54 PM PDT 24 Jul 13 06:26:57 PM PDT 24 224892396 ps
T882 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2823328346 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:57 PM PDT 24 26590580 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1848645292 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:22 PM PDT 24 38321479 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2147300507 Jul 13 06:26:45 PM PDT 24 Jul 13 06:26:59 PM PDT 24 514338363 ps
T885 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1861263635 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:31 PM PDT 24 137182566 ps
T886 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1304962631 Jul 13 06:26:54 PM PDT 24 Jul 13 06:26:55 PM PDT 24 67285408 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2404407956 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:57 PM PDT 24 85294145 ps
T888 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1026930110 Jul 13 06:27:04 PM PDT 24 Jul 13 06:27:06 PM PDT 24 95669678 ps
T889 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2775135293 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:37 PM PDT 24 107804680 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3539912757 Jul 13 06:26:22 PM PDT 24 Jul 13 06:26:25 PM PDT 24 88441215 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1678109862 Jul 13 06:26:45 PM PDT 24 Jul 13 06:26:49 PM PDT 24 297666553 ps
T151 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3501582022 Jul 13 06:26:56 PM PDT 24 Jul 13 06:27:00 PM PDT 24 159860785 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3988643326 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:29 PM PDT 24 46712559 ps
T150 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1698508322 Jul 13 06:26:14 PM PDT 24 Jul 13 06:26:16 PM PDT 24 21632094 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1511077646 Jul 13 06:26:14 PM PDT 24 Jul 13 06:26:16 PM PDT 24 119123237 ps
T142 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3027213414 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 154470022 ps
T894 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.910291164 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:37 PM PDT 24 262792037 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1560678280 Jul 13 06:26:21 PM PDT 24 Jul 13 06:26:22 PM PDT 24 250420096 ps
T148 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2969449913 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:32 PM PDT 24 110487192 ps
T896 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2462807766 Jul 13 06:26:36 PM PDT 24 Jul 13 06:26:39 PM PDT 24 86027866 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.815213209 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:38 PM PDT 24 109563234 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3858333230 Jul 13 06:26:13 PM PDT 24 Jul 13 06:26:17 PM PDT 24 105525382 ps
T899 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3734217794 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:43 PM PDT 24 1496803257 ps
T900 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2351616616 Jul 13 06:26:54 PM PDT 24 Jul 13 06:26:56 PM PDT 24 29783392 ps
T901 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.953687238 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 40655726 ps
T213 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2507881697 Jul 13 06:26:21 PM PDT 24 Jul 13 06:26:23 PM PDT 24 72151261 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.445256444 Jul 13 06:26:40 PM PDT 24 Jul 13 06:26:49 PM PDT 24 406903351 ps
T903 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2852213480 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:56 PM PDT 24 79386236 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.390601869 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:22 PM PDT 24 136222808 ps
T905 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2596383974 Jul 13 06:26:14 PM PDT 24 Jul 13 06:26:16 PM PDT 24 95870528 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2654131216 Jul 13 06:26:27 PM PDT 24 Jul 13 06:26:29 PM PDT 24 56852868 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1777997240 Jul 13 06:26:37 PM PDT 24 Jul 13 06:26:39 PM PDT 24 71667557 ps
T908 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2363629508 Jul 13 06:27:03 PM PDT 24 Jul 13 06:27:06 PM PDT 24 44271419 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1788248601 Jul 13 06:26:48 PM PDT 24 Jul 13 06:26:51 PM PDT 24 79661728 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1347313507 Jul 13 06:26:45 PM PDT 24 Jul 13 06:26:48 PM PDT 24 523530941 ps
T911 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3071971071 Jul 13 06:26:54 PM PDT 24 Jul 13 06:26:56 PM PDT 24 33909935 ps
T912 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3091715193 Jul 13 06:26:42 PM PDT 24 Jul 13 06:26:53 PM PDT 24 2079735706 ps
T141 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2707557579 Jul 13 06:26:47 PM PDT 24 Jul 13 06:26:50 PM PDT 24 59818442 ps
T913 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3343417787 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:58 PM PDT 24 103219915 ps
T914 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3355819831 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:05 PM PDT 24 19337889 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3105618589 Jul 13 06:26:30 PM PDT 24 Jul 13 06:26:45 PM PDT 24 6162122578 ps
T143 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.679948624 Jul 13 06:26:41 PM PDT 24 Jul 13 06:26:44 PM PDT 24 414993650 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2063688743 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:25 PM PDT 24 125639305 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2727241989 Jul 13 06:26:15 PM PDT 24 Jul 13 06:26:17 PM PDT 24 53140229 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.846783370 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:22 PM PDT 24 144363678 ps
T919 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1980675166 Jul 13 06:26:43 PM PDT 24 Jul 13 06:26:45 PM PDT 24 31058696 ps
T920 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2803018149 Jul 13 06:26:56 PM PDT 24 Jul 13 06:26:59 PM PDT 24 45856859 ps
T921 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2878418669 Jul 13 06:26:38 PM PDT 24 Jul 13 06:26:39 PM PDT 24 29043403 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.544818629 Jul 13 06:26:19 PM PDT 24 Jul 13 06:26:20 PM PDT 24 22588959 ps
T923 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1932487246 Jul 13 06:26:57 PM PDT 24 Jul 13 06:27:00 PM PDT 24 25595159 ps
T139 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3746674954 Jul 13 06:26:54 PM PDT 24 Jul 13 06:26:58 PM PDT 24 79498174 ps
T924 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1653631102 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:35 PM PDT 24 33839823 ps
T925 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3725891853 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:36 PM PDT 24 29022654 ps
T926 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2116419842 Jul 13 06:26:57 PM PDT 24 Jul 13 06:27:00 PM PDT 24 97916654 ps
T927 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.169083465 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:57 PM PDT 24 12527061 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.410049451 Jul 13 06:26:31 PM PDT 24 Jul 13 06:26:33 PM PDT 24 22462755 ps
T929 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3669398737 Jul 13 06:26:57 PM PDT 24 Jul 13 06:27:00 PM PDT 24 223543762 ps
T930 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3462239467 Jul 13 06:26:14 PM PDT 24 Jul 13 06:26:16 PM PDT 24 27563046 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1343879033 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:43 PM PDT 24 2579817002 ps
T932 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1121081864 Jul 13 06:26:49 PM PDT 24 Jul 13 06:26:51 PM PDT 24 46726736 ps
T214 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4211583914 Jul 13 06:26:41 PM PDT 24 Jul 13 06:26:42 PM PDT 24 19577513 ps
T933 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3084728071 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:57 PM PDT 24 74757250 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1975093730 Jul 13 06:26:38 PM PDT 24 Jul 13 06:26:41 PM PDT 24 258028820 ps
T935 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3651742484 Jul 13 06:26:54 PM PDT 24 Jul 13 06:26:55 PM PDT 24 25530683 ps
T140 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3106145606 Jul 13 06:26:38 PM PDT 24 Jul 13 06:26:41 PM PDT 24 220749146 ps
T936 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2332279908 Jul 13 06:26:56 PM PDT 24 Jul 13 06:26:59 PM PDT 24 37024405 ps
T145 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2795476880 Jul 13 06:26:56 PM PDT 24 Jul 13 06:27:02 PM PDT 24 445516229 ps
T215 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3884173608 Jul 13 06:26:48 PM PDT 24 Jul 13 06:26:49 PM PDT 24 42564654 ps
T937 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.791548761 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:30 PM PDT 24 24395082 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.60955237 Jul 13 06:26:27 PM PDT 24 Jul 13 06:26:29 PM PDT 24 12899947 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.397948465 Jul 13 06:26:29 PM PDT 24 Jul 13 06:26:33 PM PDT 24 2789985620 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.8332648 Jul 13 06:26:14 PM PDT 24 Jul 13 06:26:18 PM PDT 24 94603625 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3269602657 Jul 13 06:26:36 PM PDT 24 Jul 13 06:26:38 PM PDT 24 633248746 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.627992311 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:23 PM PDT 24 276030943 ps
T216 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.185722335 Jul 13 06:26:56 PM PDT 24 Jul 13 06:26:58 PM PDT 24 19014826 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.693202434 Jul 13 06:26:29 PM PDT 24 Jul 13 06:26:31 PM PDT 24 76030692 ps
T149 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.830455933 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:24 PM PDT 24 105761462 ps
T146 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2562033791 Jul 13 06:26:19 PM PDT 24 Jul 13 06:26:22 PM PDT 24 116220141 ps
T944 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2573289710 Jul 13 06:27:03 PM PDT 24 Jul 13 06:27:08 PM PDT 24 190239478 ps
T945 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3633352542 Jul 13 06:26:37 PM PDT 24 Jul 13 06:26:38 PM PDT 24 33855103 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4181471228 Jul 13 06:26:42 PM PDT 24 Jul 13 06:26:55 PM PDT 24 2483067745 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1151344138 Jul 13 06:26:50 PM PDT 24 Jul 13 06:26:52 PM PDT 24 53109860 ps
T948 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1611992100 Jul 13 06:26:45 PM PDT 24 Jul 13 06:26:47 PM PDT 24 127254465 ps
T949 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2642494353 Jul 13 06:26:34 PM PDT 24 Jul 13 06:26:37 PM PDT 24 137251990 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1336299087 Jul 13 06:26:22 PM PDT 24 Jul 13 06:26:27 PM PDT 24 214175944 ps
T951 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.157204340 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:57 PM PDT 24 128396891 ps
T952 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1964321602 Jul 13 06:27:01 PM PDT 24 Jul 13 06:27:03 PM PDT 24 88190294 ps
T156 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.795329524 Jul 13 06:26:55 PM PDT 24 Jul 13 06:26:59 PM PDT 24 492557294 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.682795056 Jul 13 06:26:48 PM PDT 24 Jul 13 06:26:57 PM PDT 24 8562632437 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4250414286 Jul 13 06:26:28 PM PDT 24 Jul 13 06:26:32 PM PDT 24 513939158 ps
T217 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.749196631 Jul 13 06:26:56 PM PDT 24 Jul 13 06:26:58 PM PDT 24 48658243 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1606356152 Jul 13 06:26:21 PM PDT 24 Jul 13 06:26:22 PM PDT 24 228513155 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1739590264 Jul 13 06:26:14 PM PDT 24 Jul 13 06:26:15 PM PDT 24 26922549 ps
T957 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4257437588 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:04 PM PDT 24 19567964 ps
T958 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.190056785 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:04 PM PDT 24 25484818 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.243819583 Jul 13 06:26:27 PM PDT 24 Jul 13 06:26:29 PM PDT 24 62068296 ps
T960 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.242134673 Jul 13 06:26:13 PM PDT 24 Jul 13 06:26:17 PM PDT 24 270226683 ps
T155 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4275810310 Jul 13 06:26:43 PM PDT 24 Jul 13 06:26:46 PM PDT 24 235382912 ps
T961 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.157551598 Jul 13 06:26:57 PM PDT 24 Jul 13 06:27:00 PM PDT 24 217074729 ps
T962 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.32838320 Jul 13 06:26:12 PM PDT 24 Jul 13 06:26:14 PM PDT 24 139577647 ps
T963 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1835658093 Jul 13 06:27:02 PM PDT 24 Jul 13 06:27:04 PM PDT 24 16337836 ps
T964 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3573433106 Jul 13 06:27:01 PM PDT 24 Jul 13 06:27:03 PM PDT 24 18627541 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2801439230 Jul 13 06:26:43 PM PDT 24 Jul 13 06:26:44 PM PDT 24 71240567 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1041166442 Jul 13 06:26:39 PM PDT 24 Jul 13 06:26:41 PM PDT 24 100189119 ps
T157 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4227148891 Jul 13 06:27:04 PM PDT 24 Jul 13 06:27:08 PM PDT 24 80474297 ps
T967 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1310702846 Jul 13 06:26:13 PM PDT 24 Jul 13 06:26:37 PM PDT 24 1248085131 ps
T968 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.52487088 Jul 13 06:26:13 PM PDT 24 Jul 13 06:26:17 PM PDT 24 228699917 ps
T969 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1342646289 Jul 13 06:26:59 PM PDT 24 Jul 13 06:27:01 PM PDT 24 155353444 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3132866254 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:23 PM PDT 24 333473296 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.933444275 Jul 13 06:26:29 PM PDT 24 Jul 13 06:26:33 PM PDT 24 188232887 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2506753083 Jul 13 06:26:27 PM PDT 24 Jul 13 06:26:30 PM PDT 24 40243743 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.347993959 Jul 13 06:26:18 PM PDT 24 Jul 13 06:26:36 PM PDT 24 15518025711 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3960739346 Jul 13 06:26:20 PM PDT 24 Jul 13 06:26:23 PM PDT 24 87525188 ps
T975 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2588435181 Jul 13 06:26:14 PM PDT 24 Jul 13 06:26:17 PM PDT 24 327210474 ps
T976 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2519890805 Jul 13 06:26:44 PM PDT 24 Jul 13 06:26:47 PM PDT 24 168728979 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1356903259 Jul 13 06:26:43 PM PDT 24 Jul 13 06:26:45 PM PDT 24 38885962 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3860782303 Jul 13 06:26:49 PM PDT 24 Jul 13 06:26:51 PM PDT 24 23868587 ps
T218 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3800434764 Jul 13 06:26:15 PM PDT 24 Jul 13 06:26:17 PM PDT 24 131611914 ps
T979 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.860992453 Jul 13 06:26:29 PM PDT 24 Jul 13 06:26:38 PM PDT 24 691025731 ps
T219 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2681298176 Jul 13 06:26:45 PM PDT 24 Jul 13 06:26:47 PM PDT 24 19597501 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3045641962 Jul 13 06:26:41 PM PDT 24 Jul 13 06:26:44 PM PDT 24 263994347 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3328521215 Jul 13 06:26:19 PM PDT 24 Jul 13 06:26:33 PM PDT 24 2067714291 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1567750676 Jul 13 06:26:44 PM PDT 24 Jul 13 06:26:46 PM PDT 24 117272869 ps
T983 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2744138895 Jul 13 06:26:30 PM PDT 24 Jul 13 06:26:32 PM PDT 24 136866167 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.79375054 Jul 13 06:26:41 PM PDT 24 Jul 13 06:26:43 PM PDT 24 40584085 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2380945176 Jul 13 06:26:27 PM PDT 24 Jul 13 06:26:32 PM PDT 24 49056683 ps
T986 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3566781525 Jul 13 06:26:42 PM PDT 24 Jul 13 06:26:46 PM PDT 24 1016982834 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2634371752 Jul 13 06:26:15 PM PDT 24 Jul 13 06:26:17 PM PDT 24 499665021 ps
T988 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.459062063 Jul 13 06:26:42 PM PDT 24 Jul 13 06:26:47 PM PDT 24 520963016 ps
T154 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2983450824 Jul 13 06:26:56 PM PDT 24 Jul 13 06:27:01 PM PDT 24 375787698 ps

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3640139220
Short name T4
Test name
Test status
Simulation time 87752521121 ps
CPU time 473.17 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:39:24 PM PDT 24
Peak memory 332932 kb
Host smart-b5a0d1fb-edf8-48ca-b7ca-7be12894178d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3640139220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3640139220
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3237974979
Short name T12
Test name
Test status
Simulation time 354014278 ps
CPU time 10.38 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 218292 kb
Host smart-f3a61d70-bde5-4c60-aee0-29a1d67e4419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237974979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3237974979
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1863008819
Short name T277
Test name
Test status
Simulation time 706254128 ps
CPU time 14.71 seconds
Started Jul 13 06:32:00 PM PDT 24
Finished Jul 13 06:32:16 PM PDT 24
Peak memory 225992 kb
Host smart-ca8874c8-1e22-4878-bc4e-5b1684b818f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863008819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1863008819
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.749628471
Short name T125
Test name
Test status
Simulation time 133541227 ps
CPU time 2.56 seconds
Started Jul 13 06:26:22 PM PDT 24
Finished Jul 13 06:26:26 PM PDT 24
Peak memory 218908 kb
Host smart-195dc132-6b13-4cb0-9cb6-c7b3818c24ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749628
471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.749628471
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2622000173
Short name T16
Test name
Test status
Simulation time 402192765 ps
CPU time 14.48 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:31 PM PDT 24
Peak memory 218180 kb
Host smart-d5d8bac0-dd1c-4841-936e-f97eaed12be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622000173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
622000173
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1955816632
Short name T49
Test name
Test status
Simulation time 860783008 ps
CPU time 34.64 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:40 PM PDT 24
Peak memory 282680 kb
Host smart-5ad2172b-d2fb-46fc-9f5f-64478f8bd200
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955816632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1955816632
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1386224503
Short name T175
Test name
Test status
Simulation time 457375656 ps
CPU time 12.48 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:31:57 PM PDT 24
Peak memory 225972 kb
Host smart-d10b34a6-ec6d-4599-b627-967e8472e9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386224503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1386224503
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1319944451
Short name T48
Test name
Test status
Simulation time 423090230 ps
CPU time 8.61 seconds
Started Jul 13 06:33:05 PM PDT 24
Finished Jul 13 06:33:14 PM PDT 24
Peak memory 224836 kb
Host smart-655ae0ec-5605-45d4-8c38-e1ae9fa2ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319944451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1319944451
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.187256611
Short name T126
Test name
Test status
Simulation time 1606600749 ps
CPU time 3.18 seconds
Started Jul 13 06:26:40 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 222024 kb
Host smart-d03ab782-09c9-42f6-99f4-7d91a5321766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187256611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.187256611
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1085264311
Short name T92
Test name
Test status
Simulation time 37892058485 ps
CPU time 239.67 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:36:48 PM PDT 24
Peak memory 496832 kb
Host smart-aef21e0d-e8fe-4e12-8112-991c2dc0ca66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1085264311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1085264311
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3457476670
Short name T24
Test name
Test status
Simulation time 668299856 ps
CPU time 2.8 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:46 PM PDT 24
Peak memory 217052 kb
Host smart-de29dbbc-e2ab-433a-bfb8-710a376e1fb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457476670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3457476670
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1090445939
Short name T13
Test name
Test status
Simulation time 30842213 ps
CPU time 1.05 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 208928 kb
Host smart-9c57528c-2e1d-4d97-8385-f8888457ac68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090445939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1090445939
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1428212192
Short name T206
Test name
Test status
Simulation time 12995849 ps
CPU time 1.1 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 209296 kb
Host smart-5ddd4e07-a484-47fa-9f46-a413b324e0b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428212192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1428212192
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3808370023
Short name T1
Test name
Test status
Simulation time 61260748762 ps
CPU time 276.34 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:35:57 PM PDT 24
Peak memory 300260 kb
Host smart-ac6a5c23-e192-41e3-aced-3b41abe79b13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3808370023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3808370023
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2795476880
Short name T145
Test name
Test status
Simulation time 445516229 ps
CPU time 4.22 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:27:02 PM PDT 24
Peak memory 217516 kb
Host smart-856fb4c5-677f-4a40-b7e3-06a5f1b6564d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795476880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2795476880
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1407506919
Short name T133
Test name
Test status
Simulation time 1741591091 ps
CPU time 3.5 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 217472 kb
Host smart-77b24d52-647f-4be8-8adb-0446a143e4bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407506919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1407506919
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.830455933
Short name T149
Test name
Test status
Simulation time 105761462 ps
CPU time 3.28 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:24 PM PDT 24
Peak memory 222260 kb
Host smart-9660d16c-1012-4e35-ac00-3254223b99c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830455933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.830455933
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3375468596
Short name T60
Test name
Test status
Simulation time 13041755605 ps
CPU time 186.86 seconds
Started Jul 13 06:31:14 PM PDT 24
Finished Jul 13 06:34:22 PM PDT 24
Peak memory 315800 kb
Host smart-8dd16f1c-bf6b-429a-9908-0bbfd19af7f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375468596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3375468596
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1466187309
Short name T39
Test name
Test status
Simulation time 13588156802 ps
CPU time 45.76 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:32:28 PM PDT 24
Peak memory 226024 kb
Host smart-e73d813a-e61f-4ca3-a2ec-3dc645951257
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466187309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1466187309
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3106145606
Short name T140
Test name
Test status
Simulation time 220749146 ps
CPU time 2.86 seconds
Started Jul 13 06:26:38 PM PDT 24
Finished Jul 13 06:26:41 PM PDT 24
Peak memory 222196 kb
Host smart-f92285c3-d96d-4eaf-b6e2-27f2e0deb842
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106145606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3106145606
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1292805447
Short name T123
Test name
Test status
Simulation time 2149353297 ps
CPU time 82.86 seconds
Started Jul 13 06:32:20 PM PDT 24
Finished Jul 13 06:33:44 PM PDT 24
Peak memory 267288 kb
Host smart-5d0195a0-a5a5-4461-863d-9d69eeb51360
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292805447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1292805447
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2573289710
Short name T944
Test name
Test status
Simulation time 190239478 ps
CPU time 3.53 seconds
Started Jul 13 06:27:03 PM PDT 24
Finished Jul 13 06:27:08 PM PDT 24
Peak memory 218040 kb
Host smart-75cf5cdc-2a37-4526-b376-834bce27c6c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573289710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2573289710
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3800434764
Short name T218
Test name
Test status
Simulation time 131611914 ps
CPU time 1.72 seconds
Started Jul 13 06:26:15 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 209296 kb
Host smart-a6231ce2-ede1-47e2-b993-31ad92907337
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800434764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3800434764
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2802497285
Short name T101
Test name
Test status
Simulation time 240743056791 ps
CPU time 483.73 seconds
Started Jul 13 06:32:11 PM PDT 24
Finished Jul 13 06:40:16 PM PDT 24
Peak memory 317472 kb
Host smart-54c44512-3c89-445c-b09a-50b1697e19cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2802497285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2802497285
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1483270209
Short name T121
Test name
Test status
Simulation time 29227526 ps
CPU time 0.94 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:46 PM PDT 24
Peak memory 211924 kb
Host smart-b2fa0659-f583-4851-9a9b-fe890a0b35da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483270209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1483270209
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3729691188
Short name T231
Test name
Test status
Simulation time 11443587 ps
CPU time 0.82 seconds
Started Jul 13 06:31:00 PM PDT 24
Finished Jul 13 06:31:01 PM PDT 24
Peak memory 208736 kb
Host smart-dd6aff85-915a-459c-badc-dd61d4037a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729691188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3729691188
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3272924272
Short name T516
Test name
Test status
Simulation time 574977191 ps
CPU time 9.64 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:20 PM PDT 24
Peak memory 225056 kb
Host smart-aa0b084b-ebe2-4337-ba8c-b0433816c811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272924272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3272924272
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.827924881
Short name T232
Test name
Test status
Simulation time 38453575 ps
CPU time 0.81 seconds
Started Jul 13 06:31:13 PM PDT 24
Finished Jul 13 06:31:14 PM PDT 24
Peak memory 208656 kb
Host smart-47276116-4c79-454f-8f36-6fdb8d0b2939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827924881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.827924881
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2470123504
Short name T234
Test name
Test status
Simulation time 32838261 ps
CPU time 0.93 seconds
Started Jul 13 06:31:14 PM PDT 24
Finished Jul 13 06:31:16 PM PDT 24
Peak memory 208876 kb
Host smart-afea0a4e-ad7a-40d7-b0ce-f54ac45261e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470123504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2470123504
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.928804075
Short name T233
Test name
Test status
Simulation time 12317389 ps
CPU time 0.82 seconds
Started Jul 13 06:31:31 PM PDT 24
Finished Jul 13 06:31:32 PM PDT 24
Peak memory 208900 kb
Host smart-26c7a0e7-b4c9-4986-acf6-e3dde48f2d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928804075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.928804075
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3942968165
Short name T229
Test name
Test status
Simulation time 32134407 ps
CPU time 0.96 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:31:44 PM PDT 24
Peak memory 208952 kb
Host smart-c679a733-9c7a-47d6-b86e-b756c4c8b33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942968165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3942968165
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1314943349
Short name T19
Test name
Test status
Simulation time 857060391 ps
CPU time 21.94 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:44 PM PDT 24
Peak memory 251008 kb
Host smart-6c63fb21-37db-4b42-ab24-85ff61b96966
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314943349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1314943349
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1511077646
Short name T893
Test name
Test status
Simulation time 119123237 ps
CPU time 1.48 seconds
Started Jul 13 06:26:14 PM PDT 24
Finished Jul 13 06:26:16 PM PDT 24
Peak memory 209224 kb
Host smart-d33a0a61-aa8f-41df-874f-30ede142714d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511077646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1511077646
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2030621784
Short name T147
Test name
Test status
Simulation time 317792886 ps
CPU time 2.58 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:26:15 PM PDT 24
Peak memory 221780 kb
Host smart-d8762f8e-ffc0-48f3-a743-f0441981f018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030621784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2030621784
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2562033791
Short name T146
Test name
Test status
Simulation time 116220141 ps
CPU time 2.02 seconds
Started Jul 13 06:26:19 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 222056 kb
Host smart-d7675b41-3b99-438b-a4dd-ca08a433ac60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562033791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2562033791
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3607983963
Short name T152
Test name
Test status
Simulation time 213159235 ps
CPU time 2.67 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 217476 kb
Host smart-d8a30240-c277-4a25-8fc5-6766ece9d850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607983963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3607983963
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2969449913
Short name T148
Test name
Test status
Simulation time 110487192 ps
CPU time 3.18 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:32 PM PDT 24
Peak memory 222304 kb
Host smart-8729c210-2f9a-4850-926f-476513caacd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969449913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2969449913
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2707557579
Short name T141
Test name
Test status
Simulation time 59818442 ps
CPU time 2.21 seconds
Started Jul 13 06:26:47 PM PDT 24
Finished Jul 13 06:26:50 PM PDT 24
Peak memory 221824 kb
Host smart-d9ebce98-cab1-4951-9c31-072d2e849865
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707557579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2707557579
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.4109278496
Short name T45
Test name
Test status
Simulation time 12989290099 ps
CPU time 232.44 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:37:20 PM PDT 24
Peak memory 283936 kb
Host smart-4e79df6d-2146-4881-85d5-891ed0957f79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4109278496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.4109278496
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2328947213
Short name T15
Test name
Test status
Simulation time 1969092484 ps
CPU time 17.16 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:33:03 PM PDT 24
Peak memory 218164 kb
Host smart-7571b066-2c91-4f8a-94ea-92f739245e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328947213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2328947213
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.8332648
Short name T940
Test name
Test status
Simulation time 94603625 ps
CPU time 3.49 seconds
Started Jul 13 06:26:14 PM PDT 24
Finished Jul 13 06:26:18 PM PDT 24
Peak memory 209220 kb
Host smart-a23506e7-9d97-4f62-91bb-438d77646d88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8332648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash.8332648
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1739590264
Short name T956
Test name
Test status
Simulation time 26922549 ps
CPU time 0.92 seconds
Started Jul 13 06:26:14 PM PDT 24
Finished Jul 13 06:26:15 PM PDT 24
Peak memory 209500 kb
Host smart-832e7af4-a751-4e34-b330-6ec64a441df1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739590264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1739590264
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2727241989
Short name T917
Test name
Test status
Simulation time 53140229 ps
CPU time 1.1 seconds
Started Jul 13 06:26:15 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 217896 kb
Host smart-ac566218-0b02-4d02-b016-50602ea42ea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727241989 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2727241989
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.513753005
Short name T207
Test name
Test status
Simulation time 22007774 ps
CPU time 0.99 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:26:14 PM PDT 24
Peak memory 209284 kb
Host smart-7c04eefc-2f53-4472-b8bc-aca8cc419b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513753005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.513753005
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2588435181
Short name T975
Test name
Test status
Simulation time 327210474 ps
CPU time 2.63 seconds
Started Jul 13 06:26:14 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 209132 kb
Host smart-083075a0-b245-4b1c-8cf2-cb626bb53ba1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588435181 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2588435181
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.52487088
Short name T968
Test name
Test status
Simulation time 228699917 ps
CPU time 3.09 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 216984 kb
Host smart-d7663f46-3b1b-45a0-bf46-73a647a62552
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52487088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.lc_ctrl_jtag_csr_aliasing.52487088
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1310702846
Short name T967
Test name
Test status
Simulation time 1248085131 ps
CPU time 23.32 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:26:37 PM PDT 24
Peak memory 209180 kb
Host smart-9fb43a9d-9737-48bf-9be4-88afd03f7152
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310702846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1310702846
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3858333230
Short name T898
Test name
Test status
Simulation time 105525382 ps
CPU time 3.11 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 210696 kb
Host smart-4600cbed-894b-4b2a-9bc9-7654b1598ce2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858333230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3858333230
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.242134673
Short name T960
Test name
Test status
Simulation time 270226683 ps
CPU time 3.19 seconds
Started Jul 13 06:26:13 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 217604 kb
Host smart-1e2fd1df-195e-48a0-a371-5c66b3446baf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242134
673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.242134673
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.32838320
Short name T962
Test name
Test status
Simulation time 139577647 ps
CPU time 1.67 seconds
Started Jul 13 06:26:12 PM PDT 24
Finished Jul 13 06:26:14 PM PDT 24
Peak memory 209360 kb
Host smart-4dd5596b-bcb4-4d95-9bae-855387d69ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32838320 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.32838320
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3462239467
Short name T930
Test name
Test status
Simulation time 27563046 ps
CPU time 1.08 seconds
Started Jul 13 06:26:14 PM PDT 24
Finished Jul 13 06:26:16 PM PDT 24
Peak memory 209280 kb
Host smart-519ff63d-9984-4a04-a2a1-5329aeeaef56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462239467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3462239467
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1698508322
Short name T150
Test name
Test status
Simulation time 21632094 ps
CPU time 1.66 seconds
Started Jul 13 06:26:14 PM PDT 24
Finished Jul 13 06:26:16 PM PDT 24
Peak memory 217732 kb
Host smart-d06d096b-7e79-47de-96b9-8c5992594aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698508322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1698508322
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.500518950
Short name T210
Test name
Test status
Simulation time 75257067 ps
CPU time 1.78 seconds
Started Jul 13 06:26:21 PM PDT 24
Finished Jul 13 06:26:24 PM PDT 24
Peak memory 209308 kb
Host smart-7312d9ed-e045-4df0-a1b8-84b4c99abb4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500518950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.500518950
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.390601869
Short name T904
Test name
Test status
Simulation time 136222808 ps
CPU time 1.67 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 209244 kb
Host smart-cc4a9eed-fb16-499b-9386-b42a07dafa32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390601869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.390601869
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2507881697
Short name T213
Test name
Test status
Simulation time 72151261 ps
CPU time 1.26 seconds
Started Jul 13 06:26:21 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 218164 kb
Host smart-d792d97b-66fe-4543-abbf-a5bcca7edd4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507881697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2507881697
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2025879982
Short name T129
Test name
Test status
Simulation time 17987806 ps
CPU time 1.03 seconds
Started Jul 13 06:26:22 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 217476 kb
Host smart-1b4c162c-ed4a-4bb6-ad24-5146e3679396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025879982 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2025879982
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1560678280
Short name T895
Test name
Test status
Simulation time 250420096 ps
CPU time 1.16 seconds
Started Jul 13 06:26:21 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 209200 kb
Host smart-12c574ac-c76f-4e3e-87ae-f7ec6e3e1719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560678280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1560678280
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.846783370
Short name T918
Test name
Test status
Simulation time 144363678 ps
CPU time 1.52 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 209104 kb
Host smart-173f57c3-ddb6-4831-ad90-a3c404ca6d68
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846783370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.846783370
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.347993959
Short name T973
Test name
Test status
Simulation time 15518025711 ps
CPU time 17.63 seconds
Started Jul 13 06:26:18 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 209300 kb
Host smart-575f8125-9c7f-4d8e-822d-c1873607fefe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347993959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.347993959
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3328521215
Short name T981
Test name
Test status
Simulation time 2067714291 ps
CPU time 13.31 seconds
Started Jul 13 06:26:19 PM PDT 24
Finished Jul 13 06:26:33 PM PDT 24
Peak memory 209184 kb
Host smart-65d287aa-29ea-484e-b442-93204c5ca489
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328521215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3328521215
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2596383974
Short name T905
Test name
Test status
Simulation time 95870528 ps
CPU time 1.82 seconds
Started Jul 13 06:26:14 PM PDT 24
Finished Jul 13 06:26:16 PM PDT 24
Peak memory 210848 kb
Host smart-3887b0b0-2669-4f61-a870-d7e5fd1770e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596383974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2596383974
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3960739346
Short name T974
Test name
Test status
Simulation time 87525188 ps
CPU time 3.17 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 217988 kb
Host smart-9d4b28f0-9222-4572-a145-c715e4d94cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396073
9346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3960739346
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2634371752
Short name T987
Test name
Test status
Simulation time 499665021 ps
CPU time 1.53 seconds
Started Jul 13 06:26:15 PM PDT 24
Finished Jul 13 06:26:17 PM PDT 24
Peak memory 209220 kb
Host smart-bc6826f7-801e-4f37-963e-6f11813d7150
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634371752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2634371752
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1848645292
Short name T883
Test name
Test status
Simulation time 38321479 ps
CPU time 1.41 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 211296 kb
Host smart-b845da50-6425-455e-997a-33a4b0d2a3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848645292 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1848645292
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3229624604
Short name T158
Test name
Test status
Simulation time 24257527 ps
CPU time 1.05 seconds
Started Jul 13 06:26:21 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 209292 kb
Host smart-ee4f5741-0f07-42b3-80ac-67124c2a7e46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229624604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3229624604
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2063688743
Short name T916
Test name
Test status
Simulation time 125639305 ps
CPU time 3.74 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:25 PM PDT 24
Peak memory 217384 kb
Host smart-d643fc6f-cd43-4739-86bb-47960fe1dc0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063688743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2063688743
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3651742484
Short name T935
Test name
Test status
Simulation time 25530683 ps
CPU time 1.23 seconds
Started Jul 13 06:26:54 PM PDT 24
Finished Jul 13 06:26:55 PM PDT 24
Peak memory 218896 kb
Host smart-f1778677-22e1-49a1-9897-352819517f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651742484 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3651742484
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3071971071
Short name T911
Test name
Test status
Simulation time 33909935 ps
CPU time 1.05 seconds
Started Jul 13 06:26:54 PM PDT 24
Finished Jul 13 06:26:56 PM PDT 24
Peak memory 209276 kb
Host smart-e14fb809-dad5-4d8e-8531-4ffe31dd434a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071971071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3071971071
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3084728071
Short name T933
Test name
Test status
Simulation time 74757250 ps
CPU time 1.05 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 209236 kb
Host smart-32b9a926-06b5-4153-9140-fee5452f7dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084728071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3084728071
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3417312002
Short name T130
Test name
Test status
Simulation time 85450420 ps
CPU time 3.17 seconds
Started Jul 13 06:26:54 PM PDT 24
Finished Jul 13 06:26:58 PM PDT 24
Peak memory 217424 kb
Host smart-8d4f6125-1d30-4130-a53a-d744b41eac03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417312002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3417312002
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3746674954
Short name T139
Test name
Test status
Simulation time 79498174 ps
CPU time 3.61 seconds
Started Jul 13 06:26:54 PM PDT 24
Finished Jul 13 06:26:58 PM PDT 24
Peak memory 217484 kb
Host smart-82b0b699-843c-4ebf-8e5b-996610390a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746674954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3746674954
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2116419842
Short name T926
Test name
Test status
Simulation time 97916654 ps
CPU time 1.37 seconds
Started Jul 13 06:26:57 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 217664 kb
Host smart-2aac4650-2535-49ff-8d90-613dcc5a0769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116419842 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2116419842
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.185722335
Short name T216
Test name
Test status
Simulation time 19014826 ps
CPU time 1 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:26:58 PM PDT 24
Peak memory 209296 kb
Host smart-295d8a15-bd4c-4deb-b4f7-49b6cd676b0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185722335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.185722335
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1342646289
Short name T969
Test name
Test status
Simulation time 155353444 ps
CPU time 1.41 seconds
Started Jul 13 06:26:59 PM PDT 24
Finished Jul 13 06:27:01 PM PDT 24
Peak memory 211320 kb
Host smart-1f4195f5-ee53-407a-b777-6f46809c0f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342646289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1342646289
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1794916878
Short name T138
Test name
Test status
Simulation time 69222100 ps
CPU time 3.03 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:59 PM PDT 24
Peak memory 217440 kb
Host smart-c78f7e52-e170-45dc-a8f1-777991ff60bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794916878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1794916878
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2823328346
Short name T882
Test name
Test status
Simulation time 26590580 ps
CPU time 1.39 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 219312 kb
Host smart-f61b0074-5802-4bc4-bb71-e4c3fbae5d38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823328346 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2823328346
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.796052860
Short name T211
Test name
Test status
Simulation time 15111747 ps
CPU time 0.89 seconds
Started Jul 13 06:26:58 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 209236 kb
Host smart-c92fc0a2-f547-46f2-99f4-75b134b5277f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796052860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.796052860
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2852213480
Short name T903
Test name
Test status
Simulation time 79386236 ps
CPU time 1.08 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:56 PM PDT 24
Peak memory 209244 kb
Host smart-6c4aa532-be69-4d8e-859a-14edc977557a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852213480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2852213480
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.884737968
Short name T881
Test name
Test status
Simulation time 224892396 ps
CPU time 2.67 seconds
Started Jul 13 06:26:54 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 217424 kb
Host smart-3e32ab2b-8229-4f17-8a9c-5f4c9d71c008
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884737968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.884737968
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2983450824
Short name T154
Test name
Test status
Simulation time 375787698 ps
CPU time 2.88 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:27:01 PM PDT 24
Peak memory 221540 kb
Host smart-0f768725-6fcf-4576-8f25-7a6af681abda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983450824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2983450824
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2332279908
Short name T936
Test name
Test status
Simulation time 37024405 ps
CPU time 1.75 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:26:59 PM PDT 24
Peak memory 222212 kb
Host smart-ee40a8b4-7df7-40b7-a059-5e381eac9f30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332279908 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2332279908
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.749196631
Short name T217
Test name
Test status
Simulation time 48658243 ps
CPU time 0.95 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:26:58 PM PDT 24
Peak memory 209216 kb
Host smart-4a754f7e-e772-458f-bdb9-d0a4e7dff27a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749196631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.749196631
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3669398737
Short name T929
Test name
Test status
Simulation time 223543762 ps
CPU time 1.92 seconds
Started Jul 13 06:26:57 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 217532 kb
Host smart-c3e8933a-48ab-4756-ad66-128cbc2e6b51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669398737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3669398737
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3924477632
Short name T136
Test name
Test status
Simulation time 87665157 ps
CPU time 3.58 seconds
Started Jul 13 06:26:57 PM PDT 24
Finished Jul 13 06:27:02 PM PDT 24
Peak memory 218356 kb
Host smart-9727007a-cbe5-4df0-9b9d-6792ee4056e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924477632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3924477632
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2803018149
Short name T920
Test name
Test status
Simulation time 45856859 ps
CPU time 1.25 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:26:59 PM PDT 24
Peak memory 217600 kb
Host smart-ba451e38-7a7b-477c-a53c-b06c0cb048ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803018149 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2803018149
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2351616616
Short name T900
Test name
Test status
Simulation time 29783392 ps
CPU time 1.16 seconds
Started Jul 13 06:26:54 PM PDT 24
Finished Jul 13 06:26:56 PM PDT 24
Peak memory 209296 kb
Host smart-d7548e4f-dece-4e67-befb-544a1f1baa3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351616616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2351616616
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.157204340
Short name T951
Test name
Test status
Simulation time 128396891 ps
CPU time 1.37 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 209408 kb
Host smart-4bb36d3e-a76e-454b-b0db-24bdfe16890b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157204340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.157204340
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3343417787
Short name T913
Test name
Test status
Simulation time 103219915 ps
CPU time 2.67 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:58 PM PDT 24
Peak memory 217468 kb
Host smart-f1c9e13d-7b72-49ad-9297-1cddcc9e53ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343417787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3343417787
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.795329524
Short name T156
Test name
Test status
Simulation time 492557294 ps
CPU time 3.36 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:59 PM PDT 24
Peak memory 217476 kb
Host smart-dbf51139-e49e-468a-ad61-17647d421717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795329524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.795329524
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3355819831
Short name T914
Test name
Test status
Simulation time 19337889 ps
CPU time 1.28 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 217676 kb
Host smart-9717cbb3-aa44-4b3a-bd87-e2bbd1482fd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355819831 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3355819831
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.169083465
Short name T927
Test name
Test status
Simulation time 12527061 ps
CPU time 0.86 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 209208 kb
Host smart-ccc89c55-5721-4962-96ac-a63c644f43ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169083465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.169083465
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2404407956
Short name T887
Test name
Test status
Simulation time 85294145 ps
CPU time 1.15 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 209292 kb
Host smart-c1329b69-4fbc-4878-a5da-59b0c1a4e09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404407956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2404407956
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1932487246
Short name T923
Test name
Test status
Simulation time 25595159 ps
CPU time 1.73 seconds
Started Jul 13 06:26:57 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 217876 kb
Host smart-4988cc38-e0ae-40cf-be97-3884e0c8092c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932487246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1932487246
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4257437588
Short name T957
Test name
Test status
Simulation time 19567964 ps
CPU time 1.28 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:04 PM PDT 24
Peak memory 219592 kb
Host smart-125a3efc-d61b-42be-96c5-e043891f9d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257437588 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4257437588
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.190056785
Short name T958
Test name
Test status
Simulation time 25484818 ps
CPU time 0.88 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:04 PM PDT 24
Peak memory 209148 kb
Host smart-20b7771f-badd-4d03-b084-fcf90643368a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190056785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.190056785
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1595334821
Short name T868
Test name
Test status
Simulation time 40882164 ps
CPU time 1.59 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 217480 kb
Host smart-48cd8f7a-4d3a-477a-854f-854826d6cceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595334821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1595334821
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1964321602
Short name T952
Test name
Test status
Simulation time 88190294 ps
CPU time 2.22 seconds
Started Jul 13 06:27:01 PM PDT 24
Finished Jul 13 06:27:03 PM PDT 24
Peak memory 217384 kb
Host smart-1bd9cbe2-243f-4d6e-89ae-7ef2f039a82b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964321602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1964321602
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.127342286
Short name T876
Test name
Test status
Simulation time 480181786 ps
CPU time 2 seconds
Started Jul 13 06:27:04 PM PDT 24
Finished Jul 13 06:27:06 PM PDT 24
Peak memory 217480 kb
Host smart-f89f6891-0e89-4446-8e64-2cb38143e8d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127342286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.127342286
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3246907339
Short name T872
Test name
Test status
Simulation time 19109505 ps
CPU time 1.15 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 217808 kb
Host smart-83d30911-b778-46d4-bd66-3f96a8bbfaff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246907339 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3246907339
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1780754878
Short name T212
Test name
Test status
Simulation time 15512968 ps
CPU time 1.18 seconds
Started Jul 13 06:27:01 PM PDT 24
Finished Jul 13 06:27:03 PM PDT 24
Peak memory 209264 kb
Host smart-ad984801-600e-4273-932f-c48324f6a20a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780754878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1780754878
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2363629508
Short name T908
Test name
Test status
Simulation time 44271419 ps
CPU time 1.53 seconds
Started Jul 13 06:27:03 PM PDT 24
Finished Jul 13 06:27:06 PM PDT 24
Peak memory 211304 kb
Host smart-cc7f274e-d95d-4f93-8a51-dcbfb93d1d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363629508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2363629508
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2718386063
Short name T153
Test name
Test status
Simulation time 56988197 ps
CPU time 2.18 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 221572 kb
Host smart-de9ccae8-8454-457a-af6a-d8925790655c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718386063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2718386063
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1835658093
Short name T963
Test name
Test status
Simulation time 16337836 ps
CPU time 1.47 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:04 PM PDT 24
Peak memory 219720 kb
Host smart-6f0f4cb8-d9bb-4c13-a34a-a7984e63b3bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835658093 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1835658093
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.171322761
Short name T137
Test name
Test status
Simulation time 27060361 ps
CPU time 1.41 seconds
Started Jul 13 06:27:03 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 209344 kb
Host smart-7975f993-fde6-453b-a87e-aaa57a40f850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171322761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.171322761
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3027213414
Short name T142
Test name
Test status
Simulation time 154470022 ps
CPU time 1.61 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 217452 kb
Host smart-d7f7440c-ac95-4a43-8307-34d8b4186df9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027213414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3027213414
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4227148891
Short name T157
Test name
Test status
Simulation time 80474297 ps
CPU time 2.29 seconds
Started Jul 13 06:27:04 PM PDT 24
Finished Jul 13 06:27:08 PM PDT 24
Peak memory 221808 kb
Host smart-bd4b0426-c3bd-4302-960c-983de06b3ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227148891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.4227148891
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3573433106
Short name T964
Test name
Test status
Simulation time 18627541 ps
CPU time 1.29 seconds
Started Jul 13 06:27:01 PM PDT 24
Finished Jul 13 06:27:03 PM PDT 24
Peak memory 217348 kb
Host smart-25c162f5-3e8c-4fe7-b498-ae258390d754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573433106 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3573433106
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1026930110
Short name T888
Test name
Test status
Simulation time 95669678 ps
CPU time 0.93 seconds
Started Jul 13 06:27:04 PM PDT 24
Finished Jul 13 06:27:06 PM PDT 24
Peak memory 209296 kb
Host smart-1150efb3-9f84-4d7d-98d9-814e03affb5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026930110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1026930110
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.953687238
Short name T901
Test name
Test status
Simulation time 40655726 ps
CPU time 1.52 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 209296 kb
Host smart-22940baa-83b5-411a-a2ab-c2c17d36d9e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953687238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.953687238
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.987181734
Short name T127
Test name
Test status
Simulation time 179520773 ps
CPU time 2.99 seconds
Started Jul 13 06:27:01 PM PDT 24
Finished Jul 13 06:27:04 PM PDT 24
Peak memory 218536 kb
Host smart-15fc7921-30a3-4f19-8524-c2bfb3447061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987181734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.987181734
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.94072809
Short name T132
Test name
Test status
Simulation time 145663392 ps
CPU time 1.99 seconds
Started Jul 13 06:27:02 PM PDT 24
Finished Jul 13 06:27:05 PM PDT 24
Peak memory 221900 kb
Host smart-8206fb64-883b-4eab-bdea-d3fa2b0936e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94072809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_e
rr.94072809
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.791548761
Short name T937
Test name
Test status
Simulation time 24395082 ps
CPU time 1.34 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:30 PM PDT 24
Peak memory 209292 kb
Host smart-93a2506b-20ea-4188-a528-79eeb4273bfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791548761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.791548761
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2654131216
Short name T906
Test name
Test status
Simulation time 56852868 ps
CPU time 1.91 seconds
Started Jul 13 06:26:27 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 209364 kb
Host smart-87574627-88e0-42c7-b74d-81fa18b2f7bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654131216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2654131216
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1606356152
Short name T955
Test name
Test status
Simulation time 228513155 ps
CPU time 1.13 seconds
Started Jul 13 06:26:21 PM PDT 24
Finished Jul 13 06:26:22 PM PDT 24
Peak memory 211400 kb
Host smart-69ffcd2d-a42c-40a3-8da5-b6734af3c7a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606356152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1606356152
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.410049451
Short name T928
Test name
Test status
Simulation time 22462755 ps
CPU time 1.41 seconds
Started Jul 13 06:26:31 PM PDT 24
Finished Jul 13 06:26:33 PM PDT 24
Peak memory 218172 kb
Host smart-dcef6741-5a62-4cc4-a20f-5038ccb12e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410049451 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.410049451
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.544818629
Short name T922
Test name
Test status
Simulation time 22588959 ps
CPU time 0.84 seconds
Started Jul 13 06:26:19 PM PDT 24
Finished Jul 13 06:26:20 PM PDT 24
Peak memory 209228 kb
Host smart-7bc8040a-38b5-4688-9be5-03ce8586919a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544818629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.544818629
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3539912757
Short name T890
Test name
Test status
Simulation time 88441215 ps
CPU time 2.53 seconds
Started Jul 13 06:26:22 PM PDT 24
Finished Jul 13 06:26:25 PM PDT 24
Peak memory 209044 kb
Host smart-d551e96e-a6ae-41fa-9f6c-a830d66592c2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539912757 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3539912757
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.703084441
Short name T160
Test name
Test status
Simulation time 298661105 ps
CPU time 7.7 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:28 PM PDT 24
Peak memory 217120 kb
Host smart-a10c9691-e5d1-4ddd-8526-9e812962e956
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703084441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.703084441
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3212716567
Short name T874
Test name
Test status
Simulation time 2840004515 ps
CPU time 6.49 seconds
Started Jul 13 06:26:22 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 209216 kb
Host smart-1db1055c-1f31-4e86-a02f-bd56a3e97f87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212716567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3212716567
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3132866254
Short name T970
Test name
Test status
Simulation time 333473296 ps
CPU time 2 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 210628 kb
Host smart-916ad362-f18d-4afd-b583-363613f0aeef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132866254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3132866254
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1336299087
Short name T950
Test name
Test status
Simulation time 214175944 ps
CPU time 3.94 seconds
Started Jul 13 06:26:22 PM PDT 24
Finished Jul 13 06:26:27 PM PDT 24
Peak memory 209216 kb
Host smart-11fc6444-94a9-4015-afff-2af3c1f01b65
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336299087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1336299087
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1286780970
Short name T878
Test name
Test status
Simulation time 176323292 ps
CPU time 1.15 seconds
Started Jul 13 06:26:19 PM PDT 24
Finished Jul 13 06:26:20 PM PDT 24
Peak memory 209296 kb
Host smart-1a67c56f-e401-44ae-bbeb-83eb98fa34b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286780970 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1286780970
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.693202434
Short name T943
Test name
Test status
Simulation time 76030692 ps
CPU time 1.05 seconds
Started Jul 13 06:26:29 PM PDT 24
Finished Jul 13 06:26:31 PM PDT 24
Peak memory 209236 kb
Host smart-332b6e65-e633-4a91-bc1e-01a6c70e5e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693202434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.693202434
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.627992311
Short name T942
Test name
Test status
Simulation time 276030943 ps
CPU time 3.5 seconds
Started Jul 13 06:26:20 PM PDT 24
Finished Jul 13 06:26:23 PM PDT 24
Peak memory 217488 kb
Host smart-78763968-d70e-4923-85d9-77983b1fb20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627992311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.627992311
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2864355658
Short name T135
Test name
Test status
Simulation time 92589246 ps
CPU time 1.45 seconds
Started Jul 13 06:26:27 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 217484 kb
Host smart-ed9b8cde-350e-4177-94c0-3caa9bc96c74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864355658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2864355658
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.243819583
Short name T959
Test name
Test status
Simulation time 62068296 ps
CPU time 1.21 seconds
Started Jul 13 06:26:27 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 209340 kb
Host smart-2abb15ca-6316-486e-a149-e12e6ed3d1ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243819583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.243819583
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.680644798
Short name T208
Test name
Test status
Simulation time 20106876 ps
CPU time 0.96 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:30 PM PDT 24
Peak memory 209852 kb
Host smart-56cb314f-0d05-41cb-ad26-6e15d77abdcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680644798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.680644798
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3988643326
Short name T892
Test name
Test status
Simulation time 46712559 ps
CPU time 1.06 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 219136 kb
Host smart-217b20c1-1643-4464-ac05-b3b20d4bf9a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988643326 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3988643326
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.60955237
Short name T938
Test name
Test status
Simulation time 12899947 ps
CPU time 1.02 seconds
Started Jul 13 06:26:27 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 209252 kb
Host smart-9d0f0883-d191-42e9-9505-8f13f9fcfce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60955237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.60955237
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2506753083
Short name T972
Test name
Test status
Simulation time 40243743 ps
CPU time 1.67 seconds
Started Jul 13 06:26:27 PM PDT 24
Finished Jul 13 06:26:30 PM PDT 24
Peak memory 209084 kb
Host smart-8769d86a-a29f-4780-a7c5-d8f261c7f418
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506753083 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2506753083
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.397948465
Short name T939
Test name
Test status
Simulation time 2789985620 ps
CPU time 2.91 seconds
Started Jul 13 06:26:29 PM PDT 24
Finished Jul 13 06:26:33 PM PDT 24
Peak memory 209204 kb
Host smart-fe5daad1-ba41-498a-abaf-75cdce21e60d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397948465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.397948465
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3105618589
Short name T915
Test name
Test status
Simulation time 6162122578 ps
CPU time 14.58 seconds
Started Jul 13 06:26:30 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 209200 kb
Host smart-07acff4e-6032-46ee-bed1-99d99fec14eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105618589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3105618589
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.933444275
Short name T971
Test name
Test status
Simulation time 188232887 ps
CPU time 3.08 seconds
Started Jul 13 06:26:29 PM PDT 24
Finished Jul 13 06:26:33 PM PDT 24
Peak memory 210880 kb
Host smart-63293b6d-8dfa-48fd-b3f3-7c02785df84e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933444275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.933444275
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097207277
Short name T131
Test name
Test status
Simulation time 96358386 ps
CPU time 1.76 seconds
Started Jul 13 06:26:29 PM PDT 24
Finished Jul 13 06:26:31 PM PDT 24
Peak memory 217504 kb
Host smart-3d258878-846f-4fd2-a502-f5ff04df64f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209720
7277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097207277
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2744138895
Short name T983
Test name
Test status
Simulation time 136866167 ps
CPU time 1.55 seconds
Started Jul 13 06:26:30 PM PDT 24
Finished Jul 13 06:26:32 PM PDT 24
Peak memory 209232 kb
Host smart-883d7eaf-f86b-40b0-8218-435a4cad0b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744138895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2744138895
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3971368799
Short name T170
Test name
Test status
Simulation time 49558081 ps
CPU time 1.5 seconds
Started Jul 13 06:26:30 PM PDT 24
Finished Jul 13 06:26:32 PM PDT 24
Peak memory 209316 kb
Host smart-d8e3a307-87cf-489c-85ab-22513110c8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971368799 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3971368799
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.310160832
Short name T873
Test name
Test status
Simulation time 27374452 ps
CPU time 1.28 seconds
Started Jul 13 06:26:29 PM PDT 24
Finished Jul 13 06:26:31 PM PDT 24
Peak memory 209292 kb
Host smart-75743e2f-d635-4c7b-9cc5-a241eef82933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310160832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.310160832
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2380945176
Short name T985
Test name
Test status
Simulation time 49056683 ps
CPU time 3.62 seconds
Started Jul 13 06:26:27 PM PDT 24
Finished Jul 13 06:26:32 PM PDT 24
Peak memory 218552 kb
Host smart-e9aa357b-9967-4948-975d-39b30a15687e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380945176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2380945176
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4211583914
Short name T214
Test name
Test status
Simulation time 19577513 ps
CPU time 1.22 seconds
Started Jul 13 06:26:41 PM PDT 24
Finished Jul 13 06:26:42 PM PDT 24
Peak memory 209376 kb
Host smart-fde98d36-fcc2-4222-8e1b-7e339eb8e519
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211583914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4211583914
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2462807766
Short name T896
Test name
Test status
Simulation time 86027866 ps
CPU time 2.42 seconds
Started Jul 13 06:26:36 PM PDT 24
Finished Jul 13 06:26:39 PM PDT 24
Peak memory 217092 kb
Host smart-9482d758-89b0-4c55-8d20-5a3489d33f48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462807766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2462807766
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3845037724
Short name T209
Test name
Test status
Simulation time 336954352 ps
CPU time 1.08 seconds
Started Jul 13 06:26:35 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 219108 kb
Host smart-9ed04585-3f1d-42ae-acd4-70ffe08cd491
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845037724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3845037724
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3622770679
Short name T169
Test name
Test status
Simulation time 65840364 ps
CPU time 1.06 seconds
Started Jul 13 06:26:38 PM PDT 24
Finished Jul 13 06:26:39 PM PDT 24
Peak memory 218708 kb
Host smart-b182f10a-04ba-4c83-8827-0add026dea29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622770679 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3622770679
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1091166248
Short name T205
Test name
Test status
Simulation time 14866843 ps
CPU time 1.14 seconds
Started Jul 13 06:26:35 PM PDT 24
Finished Jul 13 06:26:37 PM PDT 24
Peak memory 209276 kb
Host smart-5febe3c2-bb99-4f3e-b30d-31e9a7a5bac9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091166248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1091166248
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.910291164
Short name T894
Test name
Test status
Simulation time 262792037 ps
CPU time 1.57 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:37 PM PDT 24
Peak memory 209136 kb
Host smart-66751182-1068-4387-ba4c-3f404471c76a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910291164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.910291164
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1343879033
Short name T931
Test name
Test status
Simulation time 2579817002 ps
CPU time 14.87 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:43 PM PDT 24
Peak memory 209332 kb
Host smart-0733b3f9-643e-4508-9357-0ebc98ecab9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343879033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1343879033
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.860992453
Short name T979
Test name
Test status
Simulation time 691025731 ps
CPU time 8.21 seconds
Started Jul 13 06:26:29 PM PDT 24
Finished Jul 13 06:26:38 PM PDT 24
Peak memory 208908 kb
Host smart-a932d39c-0687-43ed-b51d-71a123bd8e78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860992453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.860992453
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1861263635
Short name T885
Test name
Test status
Simulation time 137182566 ps
CPU time 2.51 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:31 PM PDT 24
Peak memory 217416 kb
Host smart-e6d101ae-43fa-488c-82df-8cacc0274fb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861263635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1861263635
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2642494353
Short name T949
Test name
Test status
Simulation time 137251990 ps
CPU time 2.87 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:37 PM PDT 24
Peak memory 220552 kb
Host smart-63edf1e0-ad2d-4657-abe7-16cbb8188bd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264249
4353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2642494353
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4250414286
Short name T954
Test name
Test status
Simulation time 513939158 ps
CPU time 2.83 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:32 PM PDT 24
Peak memory 209232 kb
Host smart-81609496-bde7-46ae-bbfd-4b5beee0da0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250414286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.4250414286
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3952643002
Short name T220
Test name
Test status
Simulation time 72053869 ps
CPU time 1 seconds
Started Jul 13 06:26:28 PM PDT 24
Finished Jul 13 06:26:29 PM PDT 24
Peak memory 209300 kb
Host smart-6a6cdcb1-e129-44c4-b99f-c158bf729770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952643002 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3952643002
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3725891853
Short name T925
Test name
Test status
Simulation time 29022654 ps
CPU time 1.2 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 209308 kb
Host smart-1980027e-0cf5-4d8e-8566-7c4c21c48e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725891853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3725891853
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1356903259
Short name T977
Test name
Test status
Simulation time 38885962 ps
CPU time 1.49 seconds
Started Jul 13 06:26:43 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 217632 kb
Host smart-831d330a-9615-4b55-9c4d-8e3d95df76ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356903259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1356903259
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4275810310
Short name T155
Test name
Test status
Simulation time 235382912 ps
CPU time 2.15 seconds
Started Jul 13 06:26:43 PM PDT 24
Finished Jul 13 06:26:46 PM PDT 24
Peak memory 221712 kb
Host smart-6ccac585-1959-4899-b034-eca07407a3af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275810310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4275810310
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1640529189
Short name T144
Test name
Test status
Simulation time 18403566 ps
CPU time 1.25 seconds
Started Jul 13 06:26:35 PM PDT 24
Finished Jul 13 06:26:37 PM PDT 24
Peak memory 217656 kb
Host smart-86848fbc-c702-4339-ad45-5a7e85dc7bc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640529189 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1640529189
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1653631102
Short name T924
Test name
Test status
Simulation time 33839823 ps
CPU time 0.99 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:35 PM PDT 24
Peak memory 208980 kb
Host smart-e2dd6864-0a1f-4aac-91ba-40d2bdadb689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653631102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1653631102
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.79375054
Short name T984
Test name
Test status
Simulation time 40584085 ps
CPU time 1.56 seconds
Started Jul 13 06:26:41 PM PDT 24
Finished Jul 13 06:26:43 PM PDT 24
Peak memory 208696 kb
Host smart-75ce9353-19ae-4682-b851-0f5fed50eeb1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79375054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_alert_test.79375054
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.445256444
Short name T902
Test name
Test status
Simulation time 406903351 ps
CPU time 9.16 seconds
Started Jul 13 06:26:40 PM PDT 24
Finished Jul 13 06:26:49 PM PDT 24
Peak memory 208904 kb
Host smart-e1747b26-cd08-4e60-8c11-4075c6d4bed0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445256444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.445256444
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4181471228
Short name T946
Test name
Test status
Simulation time 2483067745 ps
CPU time 12.77 seconds
Started Jul 13 06:26:42 PM PDT 24
Finished Jul 13 06:26:55 PM PDT 24
Peak memory 209244 kb
Host smart-0d72142a-8fb5-4e56-bf4d-0bf0bdce5440
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181471228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4181471228
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2775135293
Short name T889
Test name
Test status
Simulation time 107804680 ps
CPU time 2 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:37 PM PDT 24
Peak memory 217396 kb
Host smart-316a10cf-507a-43bb-ba05-5057cbdaa9d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775135293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2775135293
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1041166442
Short name T966
Test name
Test status
Simulation time 100189119 ps
CPU time 2.2 seconds
Started Jul 13 06:26:39 PM PDT 24
Finished Jul 13 06:26:41 PM PDT 24
Peak memory 220584 kb
Host smart-0081a2bc-f781-4f52-ac09-ef8cb78e0496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104116
6442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1041166442
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.200008458
Short name T161
Test name
Test status
Simulation time 175601122 ps
CPU time 2.17 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 209232 kb
Host smart-c6910aa3-1b94-45e7-b8c2-d0b4cac8a655
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200008458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.200008458
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1681353678
Short name T867
Test name
Test status
Simulation time 21202275 ps
CPU time 1.5 seconds
Started Jul 13 06:26:37 PM PDT 24
Finished Jul 13 06:26:39 PM PDT 24
Peak memory 209244 kb
Host smart-2fdec825-af4c-46b7-8e10-a9f951c64cb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681353678 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1681353678
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3633352542
Short name T945
Test name
Test status
Simulation time 33855103 ps
CPU time 1.16 seconds
Started Jul 13 06:26:37 PM PDT 24
Finished Jul 13 06:26:38 PM PDT 24
Peak memory 209236 kb
Host smart-283065aa-61aa-48c5-bcc9-0bd003fbd94c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633352542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3633352542
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.815213209
Short name T897
Test name
Test status
Simulation time 109563234 ps
CPU time 3.21 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:38 PM PDT 24
Peak memory 217428 kb
Host smart-717620dd-592f-484c-a41a-8ff92e1043ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815213209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.815213209
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2878418669
Short name T921
Test name
Test status
Simulation time 29043403 ps
CPU time 1.11 seconds
Started Jul 13 06:26:38 PM PDT 24
Finished Jul 13 06:26:39 PM PDT 24
Peak memory 217536 kb
Host smart-4ad442a8-a982-4326-b3d0-06e70ff81dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878418669 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2878418669
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1539730655
Short name T869
Test name
Test status
Simulation time 13803164 ps
CPU time 1.07 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 209252 kb
Host smart-e335f948-cc47-463f-a820-b4e8c1239fa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539730655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1539730655
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2545985600
Short name T865
Test name
Test status
Simulation time 36231378 ps
CPU time 1.11 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:36 PM PDT 24
Peak memory 208552 kb
Host smart-299d7d0f-fbc5-4624-8e87-3dd3bf7626a1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545985600 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2545985600
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3734217794
Short name T899
Test name
Test status
Simulation time 1496803257 ps
CPU time 8.4 seconds
Started Jul 13 06:26:34 PM PDT 24
Finished Jul 13 06:26:43 PM PDT 24
Peak memory 209196 kb
Host smart-5223e369-245a-4299-9de5-858531a8f488
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734217794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3734217794
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.507655206
Short name T879
Test name
Test status
Simulation time 2148576216 ps
CPU time 13.12 seconds
Started Jul 13 06:26:41 PM PDT 24
Finished Jul 13 06:26:55 PM PDT 24
Peak memory 209072 kb
Host smart-e80e4736-fe2a-424f-99ec-e51af036dd82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507655206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.507655206
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1103351388
Short name T880
Test name
Test status
Simulation time 75773215 ps
CPU time 1.49 seconds
Started Jul 13 06:26:41 PM PDT 24
Finished Jul 13 06:26:43 PM PDT 24
Peak memory 210340 kb
Host smart-d1aa7e84-b8bc-45ea-8059-1ba6bbf82074
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103351388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1103351388
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3269602657
Short name T941
Test name
Test status
Simulation time 633248746 ps
CPU time 1.61 seconds
Started Jul 13 06:26:36 PM PDT 24
Finished Jul 13 06:26:38 PM PDT 24
Peak memory 217924 kb
Host smart-bf1d02bf-b053-40fe-8540-e755a21a0ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326960
2657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3269602657
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1777997240
Short name T907
Test name
Test status
Simulation time 71667557 ps
CPU time 1.64 seconds
Started Jul 13 06:26:37 PM PDT 24
Finished Jul 13 06:26:39 PM PDT 24
Peak memory 209152 kb
Host smart-c0369d59-858c-4e86-bb7e-93559a7c6d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777997240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1777997240
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.63491423
Short name T875
Test name
Test status
Simulation time 17391393 ps
CPU time 1.11 seconds
Started Jul 13 06:26:35 PM PDT 24
Finished Jul 13 06:26:37 PM PDT 24
Peak memory 209244 kb
Host smart-bc3fecb0-8d8b-46d0-bf75-a24faffe0693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63491423 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.63491423
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3113104850
Short name T134
Test name
Test status
Simulation time 45511424 ps
CPU time 0.99 seconds
Started Jul 13 06:26:40 PM PDT 24
Finished Jul 13 06:26:41 PM PDT 24
Peak memory 209236 kb
Host smart-f39fe90a-8101-4d5a-b2b0-daa4cf1eb575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113104850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3113104850
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1975093730
Short name T934
Test name
Test status
Simulation time 258028820 ps
CPU time 2.53 seconds
Started Jul 13 06:26:38 PM PDT 24
Finished Jul 13 06:26:41 PM PDT 24
Peak memory 219928 kb
Host smart-beaa7024-c899-451d-90c2-d5f498a1b837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975093730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1975093730
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1567750676
Short name T982
Test name
Test status
Simulation time 117272869 ps
CPU time 1.72 seconds
Started Jul 13 06:26:44 PM PDT 24
Finished Jul 13 06:26:46 PM PDT 24
Peak memory 217572 kb
Host smart-8b012c38-c06c-4cdd-b2b7-23d412660e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567750676 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1567750676
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2681298176
Short name T219
Test name
Test status
Simulation time 19597501 ps
CPU time 1.05 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:26:47 PM PDT 24
Peak memory 209128 kb
Host smart-aacd4622-3780-4ff5-b76b-e007badbb36a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681298176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2681298176
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2256976417
Short name T864
Test name
Test status
Simulation time 28239867 ps
CPU time 0.99 seconds
Started Jul 13 06:26:42 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 209048 kb
Host smart-ca256ed9-f7db-46e1-8efc-85d18fd6af46
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256976417 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2256976417
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1678109862
Short name T891
Test name
Test status
Simulation time 297666553 ps
CPU time 3.33 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:26:49 PM PDT 24
Peak memory 208896 kb
Host smart-230c98c6-57cf-4f1f-a2c6-c9877fd6daf5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678109862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1678109862
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1159710752
Short name T163
Test name
Test status
Simulation time 697667838 ps
CPU time 18.46 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:27:04 PM PDT 24
Peak memory 208944 kb
Host smart-96112e30-4208-421f-bc59-0184f7b54022
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159710752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1159710752
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1611992100
Short name T948
Test name
Test status
Simulation time 127254465 ps
CPU time 1.35 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:26:47 PM PDT 24
Peak memory 210648 kb
Host smart-8478dd1c-773c-430d-9981-0b6d0b7e79cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611992100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1611992100
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3566781525
Short name T986
Test name
Test status
Simulation time 1016982834 ps
CPU time 3.48 seconds
Started Jul 13 06:26:42 PM PDT 24
Finished Jul 13 06:26:46 PM PDT 24
Peak memory 219148 kb
Host smart-99575d02-6365-440b-8f1f-66329c875afb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356678
1525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3566781525
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.713325433
Short name T863
Test name
Test status
Simulation time 127905437 ps
CPU time 1.21 seconds
Started Jul 13 06:26:44 PM PDT 24
Finished Jul 13 06:26:46 PM PDT 24
Peak memory 217388 kb
Host smart-318daa3e-dbfc-4645-b5d5-9ae5b2cea1f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713325433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.713325433
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1288982872
Short name T168
Test name
Test status
Simulation time 399168030 ps
CPU time 2.15 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:26:48 PM PDT 24
Peak memory 210948 kb
Host smart-b5906013-4a0a-457b-b9e6-d312bac5d5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288982872 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1288982872
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3117967490
Short name T871
Test name
Test status
Simulation time 25387935 ps
CPU time 1.07 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:26:46 PM PDT 24
Peak memory 209256 kb
Host smart-17a9b5a1-3322-4023-ba7f-c2e9a50cdbac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117967490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3117967490
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.459062063
Short name T988
Test name
Test status
Simulation time 520963016 ps
CPU time 5.41 seconds
Started Jul 13 06:26:42 PM PDT 24
Finished Jul 13 06:26:47 PM PDT 24
Peak memory 217444 kb
Host smart-0095b070-9828-4e26-a079-5d7a67ad4b07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459062063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.459062063
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.679948624
Short name T143
Test name
Test status
Simulation time 414993650 ps
CPU time 3.01 seconds
Started Jul 13 06:26:41 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 222260 kb
Host smart-4dcdad23-9646-432e-9617-1115d94a7750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679948624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.679948624
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3860782303
Short name T978
Test name
Test status
Simulation time 23868587 ps
CPU time 1.16 seconds
Started Jul 13 06:26:49 PM PDT 24
Finished Jul 13 06:26:51 PM PDT 24
Peak memory 217676 kb
Host smart-6c8c772b-c5c3-450a-b2e8-4ce01f5676ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860782303 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3860782303
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3884173608
Short name T215
Test name
Test status
Simulation time 42564654 ps
CPU time 0.93 seconds
Started Jul 13 06:26:48 PM PDT 24
Finished Jul 13 06:26:49 PM PDT 24
Peak memory 209048 kb
Host smart-60f800ae-4781-4274-a5b2-44124caca1b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884173608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3884173608
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3045641962
Short name T980
Test name
Test status
Simulation time 263994347 ps
CPU time 2.27 seconds
Started Jul 13 06:26:41 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 208764 kb
Host smart-cdc619f2-2495-4d1d-b8ac-9da0f27a473e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045641962 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3045641962
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2147300507
Short name T884
Test name
Test status
Simulation time 514338363 ps
CPU time 13.4 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:26:59 PM PDT 24
Peak memory 209184 kb
Host smart-19f44737-a1dc-4081-aa98-1a59cca0be22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147300507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2147300507
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3091715193
Short name T912
Test name
Test status
Simulation time 2079735706 ps
CPU time 10.98 seconds
Started Jul 13 06:26:42 PM PDT 24
Finished Jul 13 06:26:53 PM PDT 24
Peak memory 208956 kb
Host smart-cfa853d3-a3bc-4d43-a315-91347c268a0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091715193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3091715193
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4008567073
Short name T162
Test name
Test status
Simulation time 47537429 ps
CPU time 1.95 seconds
Started Jul 13 06:26:42 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 217480 kb
Host smart-ae43f7c0-7e32-46b5-a4df-eaef4d7b7d04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008567073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4008567073
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1347313507
Short name T910
Test name
Test status
Simulation time 523530941 ps
CPU time 2.44 seconds
Started Jul 13 06:26:45 PM PDT 24
Finished Jul 13 06:26:48 PM PDT 24
Peak memory 218456 kb
Host smart-e803efc8-871f-4f78-9745-9e5573b0e6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134731
3507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1347313507
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2801439230
Short name T965
Test name
Test status
Simulation time 71240567 ps
CPU time 1.07 seconds
Started Jul 13 06:26:43 PM PDT 24
Finished Jul 13 06:26:44 PM PDT 24
Peak memory 209224 kb
Host smart-d204921f-035f-4f14-ab2c-e503a31505db
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801439230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2801439230
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1980675166
Short name T919
Test name
Test status
Simulation time 31058696 ps
CPU time 1.63 seconds
Started Jul 13 06:26:43 PM PDT 24
Finished Jul 13 06:26:45 PM PDT 24
Peak memory 209292 kb
Host smart-e8438e77-d976-448b-ae2f-4a77a43427f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980675166 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1980675166
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1327587888
Short name T866
Test name
Test status
Simulation time 82488746 ps
CPU time 1.04 seconds
Started Jul 13 06:26:50 PM PDT 24
Finished Jul 13 06:26:51 PM PDT 24
Peak memory 209212 kb
Host smart-59d1d94d-04ba-43ca-962f-a6bcdac8fd1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327587888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1327587888
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2519890805
Short name T976
Test name
Test status
Simulation time 168728979 ps
CPU time 3.09 seconds
Started Jul 13 06:26:44 PM PDT 24
Finished Jul 13 06:26:47 PM PDT 24
Peak memory 217384 kb
Host smart-742b686f-feb3-4c86-af0e-aceecc5cd012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519890805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2519890805
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.738382566
Short name T877
Test name
Test status
Simulation time 48561337 ps
CPU time 1.18 seconds
Started Jul 13 06:26:55 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 221108 kb
Host smart-32d2de9c-2e22-4cee-b56a-325b9be2c122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738382566 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.738382566
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1304962631
Short name T886
Test name
Test status
Simulation time 67285408 ps
CPU time 0.98 seconds
Started Jul 13 06:26:54 PM PDT 24
Finished Jul 13 06:26:55 PM PDT 24
Peak memory 209088 kb
Host smart-ba6326d0-ac25-4975-8578-6baf247af238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304962631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1304962631
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1151344138
Short name T947
Test name
Test status
Simulation time 53109860 ps
CPU time 1.96 seconds
Started Jul 13 06:26:50 PM PDT 24
Finished Jul 13 06:26:52 PM PDT 24
Peak memory 208656 kb
Host smart-1a406faa-f78e-40ba-9cc9-52fe837fb8cf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151344138 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1151344138
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2019891092
Short name T159
Test name
Test status
Simulation time 443010832 ps
CPU time 11.82 seconds
Started Jul 13 06:26:48 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 209040 kb
Host smart-f426ebb2-ef13-48c4-bb2d-f335d7f83675
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019891092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2019891092
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.682795056
Short name T953
Test name
Test status
Simulation time 8562632437 ps
CPU time 8.54 seconds
Started Jul 13 06:26:48 PM PDT 24
Finished Jul 13 06:26:57 PM PDT 24
Peak memory 209148 kb
Host smart-43850fc3-ff9a-4f39-bb9f-003155705f67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682795056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.682795056
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1788248601
Short name T909
Test name
Test status
Simulation time 79661728 ps
CPU time 2.73 seconds
Started Jul 13 06:26:48 PM PDT 24
Finished Jul 13 06:26:51 PM PDT 24
Peak memory 211000 kb
Host smart-bd057c6a-f3e0-4989-a1d7-3fde8d2c8795
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788248601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1788248601
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3815061130
Short name T176
Test name
Test status
Simulation time 482674147 ps
CPU time 2.11 seconds
Started Jul 13 06:26:50 PM PDT 24
Finished Jul 13 06:26:52 PM PDT 24
Peak memory 217616 kb
Host smart-bc756fbd-5301-4a9a-a144-8875509b133c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381506
1130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3815061130
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.993404391
Short name T870
Test name
Test status
Simulation time 79515157 ps
CPU time 1.52 seconds
Started Jul 13 06:26:48 PM PDT 24
Finished Jul 13 06:26:50 PM PDT 24
Peak memory 217336 kb
Host smart-a0589b2c-aaa2-448e-8e7d-275c1ba97719
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993404391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.993404391
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1121081864
Short name T932
Test name
Test status
Simulation time 46726736 ps
CPU time 1.4 seconds
Started Jul 13 06:26:49 PM PDT 24
Finished Jul 13 06:26:51 PM PDT 24
Peak memory 209228 kb
Host smart-f06383ff-110f-45ee-8065-fd2edf64bcd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121081864 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1121081864
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3915572092
Short name T221
Test name
Test status
Simulation time 30526201 ps
CPU time 1.24 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:26:58 PM PDT 24
Peak memory 209296 kb
Host smart-be27c8b9-cfb6-425b-9e7b-638651028873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915572092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3915572092
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.157551598
Short name T961
Test name
Test status
Simulation time 217074729 ps
CPU time 1.95 seconds
Started Jul 13 06:26:57 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 217420 kb
Host smart-b70a9932-3b8e-4beb-9c59-48ad95718054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157551598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.157551598
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3501582022
Short name T151
Test name
Test status
Simulation time 159860785 ps
CPU time 2.22 seconds
Started Jul 13 06:26:56 PM PDT 24
Finished Jul 13 06:27:00 PM PDT 24
Peak memory 222096 kb
Host smart-e5cd7c53-76b7-4562-b595-17e5b221089a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501582022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3501582022
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2213217763
Short name T265
Test name
Test status
Simulation time 23021064 ps
CPU time 0.85 seconds
Started Jul 13 06:30:59 PM PDT 24
Finished Jul 13 06:31:01 PM PDT 24
Peak memory 208720 kb
Host smart-be88a363-a411-4bad-8a30-594f9349af2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213217763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2213217763
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1810827555
Short name T750
Test name
Test status
Simulation time 472619476 ps
CPU time 21.87 seconds
Started Jul 13 06:30:57 PM PDT 24
Finished Jul 13 06:31:20 PM PDT 24
Peak memory 218160 kb
Host smart-8a1dc2a2-6a06-4cc3-9df2-15a22d6fe63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810827555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1810827555
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.418773339
Short name T823
Test name
Test status
Simulation time 448244773 ps
CPU time 6.79 seconds
Started Jul 13 06:30:59 PM PDT 24
Finished Jul 13 06:31:07 PM PDT 24
Peak memory 217552 kb
Host smart-2d0160fa-8962-495a-893f-a67129dd0c45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418773339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.418773339
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1107422070
Short name T182
Test name
Test status
Simulation time 6973477222 ps
CPU time 58.81 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:56 PM PDT 24
Peak memory 218880 kb
Host smart-3befc5b8-4b9c-4f03-898f-cfb2fd73850e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107422070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1107422070
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.738506314
Short name T439
Test name
Test status
Simulation time 1566303974 ps
CPU time 11.5 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 217644 kb
Host smart-205a0dd4-7e1c-4628-a823-916926ade439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738506314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.738506314
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3857370950
Short name T273
Test name
Test status
Simulation time 1008892192 ps
CPU time 20.2 seconds
Started Jul 13 06:31:02 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 224280 kb
Host smart-3ae07cc0-6623-4379-8449-b1ab7ee759cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857370950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3857370950
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.981752032
Short name T803
Test name
Test status
Simulation time 4528699823 ps
CPU time 36.28 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:35 PM PDT 24
Peak memory 217732 kb
Host smart-759fc0e8-c732-4e99-a2eb-8e620bec07ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981752032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.981752032
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3633002110
Short name T579
Test name
Test status
Simulation time 610232230 ps
CPU time 4.16 seconds
Started Jul 13 06:31:02 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 217640 kb
Host smart-bf5d1ce6-6eb4-4760-b5b1-b1e1948ea913
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633002110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3633002110
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1617229685
Short name T810
Test name
Test status
Simulation time 6176040066 ps
CPU time 46.89 seconds
Started Jul 13 06:30:59 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 267824 kb
Host smart-d6f2a08e-d310-41d1-9846-f9681dfd4fb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617229685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1617229685
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1980444667
Short name T484
Test name
Test status
Simulation time 341875628 ps
CPU time 10.83 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 246664 kb
Host smart-2951e2a1-7644-4ba2-b120-a3cdeda168d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980444667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1980444667
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1742744436
Short name T660
Test name
Test status
Simulation time 58251960 ps
CPU time 2.21 seconds
Started Jul 13 06:31:02 PM PDT 24
Finished Jul 13 06:31:06 PM PDT 24
Peak memory 218136 kb
Host smart-30b1f774-65ec-4f4d-964d-69c049f908ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742744436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1742744436
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.516953241
Short name T733
Test name
Test status
Simulation time 2302467942 ps
CPU time 8.44 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:07 PM PDT 24
Peak memory 217732 kb
Host smart-55dc0cd5-21a1-4c69-bf65-ac7573c55f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516953241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.516953241
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.868782369
Short name T88
Test name
Test status
Simulation time 415675293 ps
CPU time 26.39 seconds
Started Jul 13 06:30:57 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 280436 kb
Host smart-29430df4-1c44-40da-ab4d-65ac74f0c615
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868782369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.868782369
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3235723533
Short name T247
Test name
Test status
Simulation time 864943469 ps
CPU time 22.38 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:20 PM PDT 24
Peak memory 225964 kb
Host smart-b249dba7-a37e-42d9-8f4a-c9e458006520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235723533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3235723533
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2799119968
Short name T367
Test name
Test status
Simulation time 1428608432 ps
CPU time 13.27 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:13 PM PDT 24
Peak memory 218176 kb
Host smart-2e9b5e28-abaa-483a-ab08-b50149c65a50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799119968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
799119968
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.4254251530
Short name T302
Test name
Test status
Simulation time 899030273 ps
CPU time 9.72 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:09 PM PDT 24
Peak memory 224712 kb
Host smart-5c5e29b6-e92d-4b88-a50e-f153bebf13d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254251530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4254251530
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1812814910
Short name T96
Test name
Test status
Simulation time 170258288 ps
CPU time 10.51 seconds
Started Jul 13 06:30:57 PM PDT 24
Finished Jul 13 06:31:09 PM PDT 24
Peak memory 217656 kb
Host smart-b1071667-6450-4c13-87d3-8ec7490dbcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812814910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1812814910
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1662358658
Short name T647
Test name
Test status
Simulation time 697945818 ps
CPU time 24.14 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:22 PM PDT 24
Peak memory 250916 kb
Host smart-94201f88-a6be-4ebf-88a1-258e9d3a893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662358658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1662358658
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1727291547
Short name T701
Test name
Test status
Simulation time 98657711 ps
CPU time 7.64 seconds
Started Jul 13 06:30:55 PM PDT 24
Finished Jul 13 06:31:03 PM PDT 24
Peak memory 250920 kb
Host smart-96057383-d92b-4e9a-a81e-d1f52bd9bde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727291547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1727291547
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2765880835
Short name T688
Test name
Test status
Simulation time 54373587104 ps
CPU time 265.97 seconds
Started Jul 13 06:31:01 PM PDT 24
Finished Jul 13 06:35:28 PM PDT 24
Peak memory 283688 kb
Host smart-cad9801b-1eb6-44a3-92a4-41baa8871917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765880835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2765880835
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2014164709
Short name T103
Test name
Test status
Simulation time 19037103046 ps
CPU time 596.59 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:40:54 PM PDT 24
Peak memory 276992 kb
Host smart-569c6c4f-e2df-4e27-b994-d339a9c91777
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2014164709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2014164709
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.784291005
Short name T770
Test name
Test status
Simulation time 26303071 ps
CPU time 0.9 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:00 PM PDT 24
Peak memory 211772 kb
Host smart-36fbe7ca-fdf5-4f2a-aedb-b81f8bad1942
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784291005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.784291005
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1336840868
Short name T312
Test name
Test status
Simulation time 15988596 ps
CPU time 0.87 seconds
Started Jul 13 06:31:04 PM PDT 24
Finished Jul 13 06:31:05 PM PDT 24
Peak memory 208880 kb
Host smart-ec2bbe4d-c026-4f90-a307-347cb043f7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336840868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1336840868
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2523144457
Short name T524
Test name
Test status
Simulation time 12419620 ps
CPU time 1 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:08 PM PDT 24
Peak memory 209092 kb
Host smart-46e3df93-33de-4005-83fc-e078690c8e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523144457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2523144457
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4269945178
Short name T505
Test name
Test status
Simulation time 742286216 ps
CPU time 15.17 seconds
Started Jul 13 06:30:58 PM PDT 24
Finished Jul 13 06:31:14 PM PDT 24
Peak memory 218100 kb
Host smart-b860c5fa-c6d8-48b3-9df7-2ffdf2321a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269945178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4269945178
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1325600289
Short name T25
Test name
Test status
Simulation time 393611532 ps
CPU time 10.59 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:17 PM PDT 24
Peak memory 217344 kb
Host smart-97f89238-3153-4a8e-82fa-4ee03353829a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325600289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1325600289
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.4134740321
Short name T297
Test name
Test status
Simulation time 6299635508 ps
CPU time 27.35 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:46 PM PDT 24
Peak memory 218808 kb
Host smart-37910c96-b699-4432-b848-34a0a39b5dd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134740321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.4134740321
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3815377851
Short name T459
Test name
Test status
Simulation time 3450705537 ps
CPU time 8.56 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:15 PM PDT 24
Peak memory 217772 kb
Host smart-c392a0a1-9e15-4c5d-a2df-5d1774b016a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815377851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
815377851
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.243561637
Short name T485
Test name
Test status
Simulation time 1375905176 ps
CPU time 11.1 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:18 PM PDT 24
Peak memory 218168 kb
Host smart-ad6d8ed6-cfdb-4644-acf7-3c4a8747d87d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243561637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.243561637
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2153602246
Short name T272
Test name
Test status
Simulation time 4112909443 ps
CPU time 28.84 seconds
Started Jul 13 06:31:09 PM PDT 24
Finished Jul 13 06:31:39 PM PDT 24
Peak memory 217688 kb
Host smart-19b9167d-8eb7-4070-a8a0-76943717359a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153602246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2153602246
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1911305857
Short name T67
Test name
Test status
Simulation time 185652938 ps
CPU time 5.3 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:12 PM PDT 24
Peak memory 217660 kb
Host smart-8bc42498-8dc1-43a3-bde4-f226de563b2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911305857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1911305857
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.232296685
Short name T110
Test name
Test status
Simulation time 6263804003 ps
CPU time 89.88 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:32:38 PM PDT 24
Peak memory 281516 kb
Host smart-d20a5b20-8f9f-4bd3-9d0a-f0448f0771b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232296685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.232296685
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1036594084
Short name T693
Test name
Test status
Simulation time 2107293312 ps
CPU time 11.4 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:33 PM PDT 24
Peak memory 245348 kb
Host smart-aa48137c-9307-4728-8ceb-5fa97614cbc8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036594084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1036594084
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1636251064
Short name T559
Test name
Test status
Simulation time 64905588 ps
CPU time 1.87 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:00 PM PDT 24
Peak memory 218152 kb
Host smart-6e3623b0-de06-4d0a-9e3b-d181b238f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636251064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1636251064
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.901883233
Short name T201
Test name
Test status
Simulation time 1133711779 ps
CPU time 10.18 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:32 PM PDT 24
Peak memory 217656 kb
Host smart-f0f56c20-3b87-45bf-b909-45769f56f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901883233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.901883233
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.394181803
Short name T263
Test name
Test status
Simulation time 618701077 ps
CPU time 15.2 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 218824 kb
Host smart-a752462c-67e4-4671-842b-32c483c40560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394181803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.394181803
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.266960330
Short name T310
Test name
Test status
Simulation time 1397190134 ps
CPU time 13.98 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:22 PM PDT 24
Peak memory 225968 kb
Host smart-ffb1deef-7d56-4c3d-b32d-feac3208872f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266960330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.266960330
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2421824585
Short name T686
Test name
Test status
Simulation time 743521543 ps
CPU time 10.16 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:19 PM PDT 24
Peak memory 218080 kb
Host smart-1300e161-ebd4-4115-8aef-163f15072beb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421824585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
421824585
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.957400626
Short name T670
Test name
Test status
Simulation time 366455030 ps
CPU time 9.72 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:18 PM PDT 24
Peak memory 218232 kb
Host smart-2356fb31-1b92-45b0-aea6-b91702a3364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957400626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.957400626
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2945841118
Short name T798
Test name
Test status
Simulation time 134125771 ps
CPU time 5.17 seconds
Started Jul 13 06:31:00 PM PDT 24
Finished Jul 13 06:31:06 PM PDT 24
Peak memory 217504 kb
Host smart-27a88094-367f-47c1-8982-727dbb755ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945841118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2945841118
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2504547701
Short name T400
Test name
Test status
Simulation time 7597177386 ps
CPU time 39.58 seconds
Started Jul 13 06:30:56 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 250924 kb
Host smart-b1ef63db-6d9d-4c66-ad90-1b6b360b88c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504547701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2504547701
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1275221847
Short name T631
Test name
Test status
Simulation time 250981185 ps
CPU time 8.45 seconds
Started Jul 13 06:31:01 PM PDT 24
Finished Jul 13 06:31:10 PM PDT 24
Peak memory 250856 kb
Host smart-1135fa9c-3c64-4559-9415-043f7685b7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275221847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1275221847
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3108869979
Short name T40
Test name
Test status
Simulation time 63125376684 ps
CPU time 134.74 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:33:24 PM PDT 24
Peak memory 279172 kb
Host smart-be7f0372-9b08-4ab7-af74-55f710b315c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108869979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3108869979
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3154185820
Short name T689
Test name
Test status
Simulation time 33260899202 ps
CPU time 173.26 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 267432 kb
Host smart-6b7c7f98-42dd-43f6-b19d-d0bb8a11dc80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3154185820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3154185820
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1131120222
Short name T683
Test name
Test status
Simulation time 16087171 ps
CPU time 0.91 seconds
Started Jul 13 06:31:03 PM PDT 24
Finished Jul 13 06:31:05 PM PDT 24
Peak memory 211820 kb
Host smart-b050c07f-ac42-4e8a-a9f2-4c1d044afc3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131120222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1131120222
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1730046616
Short name T363
Test name
Test status
Simulation time 53297690 ps
CPU time 0.88 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 208860 kb
Host smart-7681902e-bf4f-451b-acbe-c510e02cd9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730046616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1730046616
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2929824921
Short name T424
Test name
Test status
Simulation time 2173138200 ps
CPU time 17.05 seconds
Started Jul 13 06:31:53 PM PDT 24
Finished Jul 13 06:32:11 PM PDT 24
Peak memory 218164 kb
Host smart-09097609-3fcd-4eff-a21d-ab38735ff32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929824921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2929824921
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4029880003
Short name T28
Test name
Test status
Simulation time 452937565 ps
CPU time 6.03 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:32:00 PM PDT 24
Peak memory 217572 kb
Host smart-f472098c-d133-47d5-9677-063b52d00d9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029880003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4029880003
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1024619587
Short name T669
Test name
Test status
Simulation time 8143521211 ps
CPU time 47.97 seconds
Started Jul 13 06:31:50 PM PDT 24
Finished Jul 13 06:32:38 PM PDT 24
Peak memory 226036 kb
Host smart-2944782e-6de6-4f96-b1e4-29a7120ee2ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024619587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1024619587
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1411630562
Short name T756
Test name
Test status
Simulation time 688312291 ps
CPU time 4.29 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:01 PM PDT 24
Peak memory 218172 kb
Host smart-28d9ea24-0535-4568-a184-58b2120cbf15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411630562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1411630562
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2563039691
Short name T71
Test name
Test status
Simulation time 292360912 ps
CPU time 6.94 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:06 PM PDT 24
Peak memory 217664 kb
Host smart-8941bdf8-b48e-4ae2-816c-1ddaee57b461
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563039691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2563039691
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2259773894
Short name T106
Test name
Test status
Simulation time 2522618128 ps
CPU time 45.99 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:32:39 PM PDT 24
Peak memory 272968 kb
Host smart-1e0f59cb-d871-4dfd-8e43-3b1da03c3237
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259773894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2259773894
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1176689601
Short name T522
Test name
Test status
Simulation time 3111930693 ps
CPU time 24.93 seconds
Started Jul 13 06:31:57 PM PDT 24
Finished Jul 13 06:32:23 PM PDT 24
Peak memory 251276 kb
Host smart-d9761447-ace4-4ac9-972f-f15f8197b3c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176689601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1176689601
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.574271473
Short name T350
Test name
Test status
Simulation time 50696303 ps
CPU time 2.89 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:31:59 PM PDT 24
Peak memory 218100 kb
Host smart-bf1963ba-651e-4495-8bf2-4988d306621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574271473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.574271473
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2931045901
Short name T815
Test name
Test status
Simulation time 543426886 ps
CPU time 13.11 seconds
Started Jul 13 06:31:53 PM PDT 24
Finished Jul 13 06:32:08 PM PDT 24
Peak memory 225872 kb
Host smart-c98b4bef-a200-4e7e-858d-3ceae439e7b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931045901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2931045901
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2915055107
Short name T829
Test name
Test status
Simulation time 1150143732 ps
CPU time 9.25 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:32:05 PM PDT 24
Peak memory 225580 kb
Host smart-412effd1-b6c7-4376-b052-16688a401ce7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915055107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2915055107
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1432294112
Short name T809
Test name
Test status
Simulation time 172750531 ps
CPU time 6.13 seconds
Started Jul 13 06:31:56 PM PDT 24
Finished Jul 13 06:32:03 PM PDT 24
Peak memory 218172 kb
Host smart-2108c068-3a9a-4e6f-9f28-a5f0ddeb0599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432294112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1432294112
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2557274209
Short name T722
Test name
Test status
Simulation time 472528314 ps
CPU time 11.65 seconds
Started Jul 13 06:31:56 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 218236 kb
Host smart-75132511-ad67-44e9-b861-9021257b5682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557274209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2557274209
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3846210532
Short name T643
Test name
Test status
Simulation time 61730026 ps
CPU time 1.89 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:31:54 PM PDT 24
Peak memory 214108 kb
Host smart-7195d65e-dac5-4236-8495-c2d336f68604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846210532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3846210532
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.734396630
Short name T526
Test name
Test status
Simulation time 209118819 ps
CPU time 18.7 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:32:11 PM PDT 24
Peak memory 250916 kb
Host smart-e3695d7c-2d13-4675-aafa-02377aaa3ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734396630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.734396630
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3050416456
Short name T109
Test name
Test status
Simulation time 299766427 ps
CPU time 6.23 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:31:59 PM PDT 24
Peak memory 247104 kb
Host smart-5cc5d296-cbdf-4286-9503-9fb1f5df1996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050416456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3050416456
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4050471964
Short name T776
Test name
Test status
Simulation time 3444246628 ps
CPU time 105.96 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:33:43 PM PDT 24
Peak memory 242712 kb
Host smart-1ae3e2a6-3dbb-4c2f-b6ab-f15b3e152c9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050471964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4050471964
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3189710823
Short name T772
Test name
Test status
Simulation time 186034725099 ps
CPU time 918.89 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:47:10 PM PDT 24
Peak memory 464096 kb
Host smart-2241c16d-775c-4998-bef7-176de187454b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3189710823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3189710823
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3700605342
Short name T578
Test name
Test status
Simulation time 12869636 ps
CPU time 0.9 seconds
Started Jul 13 06:31:53 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 211896 kb
Host smart-558cc80e-e78f-426c-a424-b6a1501b7bb4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700605342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3700605342
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1099909532
Short name T69
Test name
Test status
Simulation time 15530931 ps
CPU time 1.07 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:31:53 PM PDT 24
Peak memory 208920 kb
Host smart-39c99d17-39b8-4622-b06b-36590ce49e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099909532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1099909532
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2274737727
Short name T708
Test name
Test status
Simulation time 1348463377 ps
CPU time 14.08 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:32:07 PM PDT 24
Peak memory 225972 kb
Host smart-022f5441-0bf7-4964-8d81-db389dcb4e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274737727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2274737727
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.4092892306
Short name T435
Test name
Test status
Simulation time 334082741 ps
CPU time 5.1 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:06 PM PDT 24
Peak memory 217324 kb
Host smart-44903180-a091-4dfa-bfc6-a0c539ae6bf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092892306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.4092892306
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1957131537
Short name T198
Test name
Test status
Simulation time 1553768748 ps
CPU time 51.15 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 218808 kb
Host smart-f04ec6a6-9fe2-4826-9155-21dcd1f91c36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957131537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1957131537
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.314982734
Short name T684
Test name
Test status
Simulation time 995114754 ps
CPU time 16.05 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 218156 kb
Host smart-2b14dc65-04e9-449b-be69-7e418aa02ac2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314982734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.314982734
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3149671330
Short name T680
Test name
Test status
Simulation time 283320154 ps
CPU time 5.2 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:31:57 PM PDT 24
Peak memory 217636 kb
Host smart-9495b32e-8e94-4d34-8bc4-c47b305cadb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149671330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3149671330
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.869248967
Short name T355
Test name
Test status
Simulation time 2053945248 ps
CPU time 38.8 seconds
Started Jul 13 06:31:53 PM PDT 24
Finished Jul 13 06:32:33 PM PDT 24
Peak memory 276664 kb
Host smart-37d1dd1e-ae77-4abe-a418-5a07286e1a1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869248967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.869248967
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3233129006
Short name T540
Test name
Test status
Simulation time 3001726405 ps
CPU time 27.54 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:24 PM PDT 24
Peak memory 250904 kb
Host smart-b431d873-5acf-4f55-b344-46ed39209210
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233129006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3233129006
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.497381085
Short name T278
Test name
Test status
Simulation time 109916755 ps
CPU time 3.82 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:31:58 PM PDT 24
Peak memory 218148 kb
Host smart-b7f62d75-4dc0-4db2-ac89-0b87683268ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497381085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.497381085
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3270211296
Short name T718
Test name
Test status
Simulation time 2425755084 ps
CPU time 15.8 seconds
Started Jul 13 06:31:56 PM PDT 24
Finished Jul 13 06:32:13 PM PDT 24
Peak memory 226048 kb
Host smart-e121541a-5113-4c64-99d2-30e29111e69d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270211296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3270211296
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2038736800
Short name T558
Test name
Test status
Simulation time 661270271 ps
CPU time 15.37 seconds
Started Jul 13 06:31:53 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 225896 kb
Host smart-35d6363f-39a3-408d-8664-ab7799a704be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038736800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2038736800
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.751280763
Short name T732
Test name
Test status
Simulation time 867504751 ps
CPU time 11.79 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:32:04 PM PDT 24
Peak memory 218192 kb
Host smart-ac207a3d-ab7a-4dcd-902d-0577a31024a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751280763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.751280763
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3922249489
Short name T700
Test name
Test status
Simulation time 4387996908 ps
CPU time 10.69 seconds
Started Jul 13 06:31:53 PM PDT 24
Finished Jul 13 06:32:05 PM PDT 24
Peak memory 225984 kb
Host smart-fe4d5fc3-84c8-4338-b977-6d4b25ff8e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922249489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3922249489
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3053806261
Short name T724
Test name
Test status
Simulation time 147200530 ps
CPU time 2.77 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:31:59 PM PDT 24
Peak memory 214732 kb
Host smart-d7f7d517-a929-484b-81f2-f48d711f0106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053806261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3053806261
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2599263409
Short name T494
Test name
Test status
Simulation time 366136370 ps
CPU time 24.96 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:25 PM PDT 24
Peak memory 250972 kb
Host smart-3588eea9-d2f7-4679-a169-7551bd9713ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599263409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2599263409
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1529789267
Short name T850
Test name
Test status
Simulation time 577922071 ps
CPU time 7.64 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:32:03 PM PDT 24
Peak memory 250924 kb
Host smart-5c772f81-702d-4b26-b4b1-e1ff97cfbee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529789267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1529789267
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2047209626
Short name T775
Test name
Test status
Simulation time 6204796656 ps
CPU time 120.74 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:33:56 PM PDT 24
Peak memory 275560 kb
Host smart-0d0c15e8-4566-48aa-9e1f-6db2c6d3d4a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047209626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2047209626
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3440624510
Short name T292
Test name
Test status
Simulation time 48352261 ps
CPU time 1.2 seconds
Started Jul 13 06:31:53 PM PDT 24
Finished Jul 13 06:31:56 PM PDT 24
Peak memory 217680 kb
Host smart-75753413-6946-4d4a-9f7d-928ea0608334
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440624510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3440624510
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3101836914
Short name T250
Test name
Test status
Simulation time 20783877 ps
CPU time 1.02 seconds
Started Jul 13 06:32:01 PM PDT 24
Finished Jul 13 06:32:03 PM PDT 24
Peak memory 208944 kb
Host smart-7d05d0a8-dbf6-448e-82e7-7dab36a4f532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101836914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3101836914
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.823693611
Short name T819
Test name
Test status
Simulation time 1295082051 ps
CPU time 15.3 seconds
Started Jul 13 06:31:56 PM PDT 24
Finished Jul 13 06:32:12 PM PDT 24
Peak memory 225968 kb
Host smart-8156d97c-b6a9-41e0-acb3-59a4233b3e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823693611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.823693611
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3410890186
Short name T677
Test name
Test status
Simulation time 629484235 ps
CPU time 4.31 seconds
Started Jul 13 06:31:57 PM PDT 24
Finished Jul 13 06:32:02 PM PDT 24
Peak memory 217100 kb
Host smart-8d041910-bbfb-49a1-80db-23834942469a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410890186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3410890186
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1742097014
Short name T105
Test name
Test status
Simulation time 1953619188 ps
CPU time 56.69 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:53 PM PDT 24
Peak memory 218816 kb
Host smart-888eff98-a22c-4a84-ac83-f6299ea16781
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742097014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1742097014
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3860474118
Short name T2
Test name
Test status
Simulation time 651188881 ps
CPU time 9.57 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:32:05 PM PDT 24
Peak memory 222996 kb
Host smart-38540be8-37e5-4bc9-932e-628316ebcda8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860474118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3860474118
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2072627963
Short name T620
Test name
Test status
Simulation time 4348389585 ps
CPU time 9.81 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 217696 kb
Host smart-63148c75-5edf-4226-b3eb-d6bf8807d95b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072627963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2072627963
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1245889763
Short name T245
Test name
Test status
Simulation time 2331331754 ps
CPU time 88.37 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 280824 kb
Host smart-cbd6b476-37e8-4926-a2d8-5869341488a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245889763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1245889763
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3584589636
Short name T404
Test name
Test status
Simulation time 1330453435 ps
CPU time 10.69 seconds
Started Jul 13 06:31:57 PM PDT 24
Finished Jul 13 06:32:08 PM PDT 24
Peak memory 250816 kb
Host smart-27a4575a-1d1e-4e0a-ad1c-3a2346e42d1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584589636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3584589636
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1704849836
Short name T180
Test name
Test status
Simulation time 276704993 ps
CPU time 4.08 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:00 PM PDT 24
Peak memory 218172 kb
Host smart-d765ef9a-ee44-4a79-99b2-95635db29fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704849836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1704849836
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1125212881
Short name T729
Test name
Test status
Simulation time 335110602 ps
CPU time 9.73 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:06 PM PDT 24
Peak memory 218176 kb
Host smart-b97d91aa-e1db-4782-9bd1-d76c2a381eab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125212881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1125212881
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2275553869
Short name T351
Test name
Test status
Simulation time 1879425556 ps
CPU time 13.91 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:32:10 PM PDT 24
Peak memory 225896 kb
Host smart-5ec5a08a-8080-4e17-819f-66da9c05b71e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275553869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2275553869
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3353661255
Short name T345
Test name
Test status
Simulation time 364266700 ps
CPU time 12.81 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:10 PM PDT 24
Peak memory 218108 kb
Host smart-f730e909-3fda-44db-9d8f-fd9cff920fef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353661255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3353661255
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3314697241
Short name T433
Test name
Test status
Simulation time 410090748 ps
CPU time 10.66 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:11 PM PDT 24
Peak memory 225296 kb
Host smart-a6c9055c-0af3-43e2-8a2a-72bdc29a16ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314697241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3314697241
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1724674541
Short name T857
Test name
Test status
Simulation time 724538985 ps
CPU time 2.22 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:01 PM PDT 24
Peak memory 217660 kb
Host smart-9ca81714-6e28-422a-914f-7883e89843dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724674541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1724674541
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2397097909
Short name T415
Test name
Test status
Simulation time 7224746081 ps
CPU time 40.47 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:38 PM PDT 24
Peak memory 250984 kb
Host smart-9925a886-532d-4209-ae2c-bc90e11b716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397097909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2397097909
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2249376164
Short name T790
Test name
Test status
Simulation time 64992140 ps
CPU time 6.48 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:05 PM PDT 24
Peak memory 247116 kb
Host smart-47595b0e-8758-4027-bcb4-2e0cc0bf83ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249376164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2249376164
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3779970246
Short name T81
Test name
Test status
Simulation time 2434010702 ps
CPU time 19.26 seconds
Started Jul 13 06:31:55 PM PDT 24
Finished Jul 13 06:32:16 PM PDT 24
Peak memory 245768 kb
Host smart-f52c1c24-2c67-4d35-83ee-4d60a0add9ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779970246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3779970246
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.884278689
Short name T379
Test name
Test status
Simulation time 22159150 ps
CPU time 0.91 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:31:57 PM PDT 24
Peak memory 211832 kb
Host smart-5426a443-fb6c-4fb2-a79d-febff25f5efd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884278689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.884278689
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3732400432
Short name T654
Test name
Test status
Simulation time 41537247 ps
CPU time 1 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:02 PM PDT 24
Peak memory 208932 kb
Host smart-f2173fa6-a600-4ac6-8cf2-ad8a5b47fd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732400432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3732400432
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1821461736
Short name T642
Test name
Test status
Simulation time 241624460 ps
CPU time 12.05 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:12 PM PDT 24
Peak memory 218124 kb
Host smart-1cb6e4c7-6074-4c9a-9e9b-075cabb87043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821461736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1821461736
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3137508182
Short name T603
Test name
Test status
Simulation time 497920516 ps
CPU time 3.35 seconds
Started Jul 13 06:32:01 PM PDT 24
Finished Jul 13 06:32:05 PM PDT 24
Peak memory 217036 kb
Host smart-31b38aa5-d3cd-4922-96dd-19529fb5b48f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137508182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3137508182
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2791482002
Short name T451
Test name
Test status
Simulation time 2012951383 ps
CPU time 57.68 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:57 PM PDT 24
Peak memory 218232 kb
Host smart-94a8bb11-7677-4066-938b-53d05b6e1770
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791482002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2791482002
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2921738041
Short name T349
Test name
Test status
Simulation time 8747294165 ps
CPU time 13.46 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:14 PM PDT 24
Peak memory 226040 kb
Host smart-febd7a38-09d2-4b6b-b73d-4ba8111f002f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921738041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2921738041
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2868159900
Short name T796
Test name
Test status
Simulation time 631742189 ps
CPU time 5.34 seconds
Started Jul 13 06:32:02 PM PDT 24
Finished Jul 13 06:32:08 PM PDT 24
Peak memory 217660 kb
Host smart-297dce8d-f47e-48e2-9742-e8eab52cfd2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868159900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2868159900
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.375988934
Short name T561
Test name
Test status
Simulation time 19473122124 ps
CPU time 91.51 seconds
Started Jul 13 06:32:02 PM PDT 24
Finished Jul 13 06:33:34 PM PDT 24
Peak memory 280332 kb
Host smart-a660a16f-2ecf-4208-a64a-58d1219289eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375988934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.375988934
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2742547433
Short name T291
Test name
Test status
Simulation time 646567954 ps
CPU time 11.91 seconds
Started Jul 13 06:32:01 PM PDT 24
Finished Jul 13 06:32:14 PM PDT 24
Peak memory 223052 kb
Host smart-e4e414de-2533-4ab0-8d10-dabb392b2328
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742547433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2742547433
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.992484854
Short name T616
Test name
Test status
Simulation time 535921973 ps
CPU time 2.81 seconds
Started Jul 13 06:32:07 PM PDT 24
Finished Jul 13 06:32:10 PM PDT 24
Peak memory 222408 kb
Host smart-90d29909-673d-49fe-a495-cc5fc441ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992484854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.992484854
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3014580924
Short name T442
Test name
Test status
Simulation time 1026441031 ps
CPU time 11.99 seconds
Started Jul 13 06:32:00 PM PDT 24
Finished Jul 13 06:32:13 PM PDT 24
Peak memory 218164 kb
Host smart-33dfb1ef-2d56-49bc-aac0-68342a0acc67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014580924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3014580924
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4209401942
Short name T82
Test name
Test status
Simulation time 762511548 ps
CPU time 9.67 seconds
Started Jul 13 06:32:06 PM PDT 24
Finished Jul 13 06:32:16 PM PDT 24
Peak memory 225976 kb
Host smart-491b46d5-944a-495a-a88e-db0560e10b61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209401942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4209401942
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.17048050
Short name T673
Test name
Test status
Simulation time 858119445 ps
CPU time 7.54 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:08 PM PDT 24
Peak memory 218188 kb
Host smart-07901cc1-5d38-4ad1-abb9-f1f1b93f3140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.17048050
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2853879761
Short name T795
Test name
Test status
Simulation time 1546617028 ps
CPU time 15.32 seconds
Started Jul 13 06:32:01 PM PDT 24
Finished Jul 13 06:32:17 PM PDT 24
Peak memory 225964 kb
Host smart-c464a487-3976-4fc1-9e8d-1abdc179abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853879761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2853879761
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2833152227
Short name T612
Test name
Test status
Simulation time 25292460 ps
CPU time 1.02 seconds
Started Jul 13 06:32:00 PM PDT 24
Finished Jul 13 06:32:03 PM PDT 24
Peak memory 212156 kb
Host smart-6308cb14-21aa-41b4-8f3a-da4dc328f32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833152227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2833152227
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.479875431
Short name T436
Test name
Test status
Simulation time 594157051 ps
CPU time 27.92 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:26 PM PDT 24
Peak memory 250924 kb
Host smart-2c46fa57-28aa-465d-a8d3-8fc058702999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479875431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.479875431
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.901527640
Short name T97
Test name
Test status
Simulation time 194619778 ps
CPU time 3.04 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:02 PM PDT 24
Peak memory 218080 kb
Host smart-a6c61475-f1d1-4cd7-8f76-3c5f0609e2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901527640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.901527640
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4120818185
Short name T859
Test name
Test status
Simulation time 23813237387 ps
CPU time 131.15 seconds
Started Jul 13 06:32:06 PM PDT 24
Finished Jul 13 06:34:18 PM PDT 24
Peak memory 330864 kb
Host smart-2fda0845-781e-42ce-aff6-8dfe5c49006d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120818185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4120818185
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3087906795
Short name T227
Test name
Test status
Simulation time 81153024218 ps
CPU time 686.28 seconds
Started Jul 13 06:32:02 PM PDT 24
Finished Jul 13 06:43:29 PM PDT 24
Peak memory 269768 kb
Host smart-199f17ce-ac58-4c79-94ce-d4bff9b3d5e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3087906795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3087906795
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.551191194
Short name T783
Test name
Test status
Simulation time 17622746 ps
CPU time 0.92 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:01 PM PDT 24
Peak memory 211868 kb
Host smart-837f06df-7574-46b1-b04f-d6de9a322949
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551191194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.551191194
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3241617276
Short name T595
Test name
Test status
Simulation time 34700382 ps
CPU time 0.97 seconds
Started Jul 13 06:32:00 PM PDT 24
Finished Jul 13 06:32:02 PM PDT 24
Peak memory 208828 kb
Host smart-8baaa83b-729d-4031-bca2-77a4cb583be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241617276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3241617276
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1923804007
Short name T564
Test name
Test status
Simulation time 718570969 ps
CPU time 18.52 seconds
Started Jul 13 06:32:06 PM PDT 24
Finished Jul 13 06:32:25 PM PDT 24
Peak memory 225984 kb
Host smart-a3ac2326-f477-4d0c-9c32-114e3c0884f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923804007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1923804007
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.420391933
Short name T29
Test name
Test status
Simulation time 1020077427 ps
CPU time 24.35 seconds
Started Jul 13 06:32:01 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 217488 kb
Host smart-d78fbdd8-c855-4b94-8fba-ff171e4a52c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420391933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.420391933
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2302678317
Short name T581
Test name
Test status
Simulation time 10738825538 ps
CPU time 44.82 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 218228 kb
Host smart-a86a1251-bbea-4beb-9be4-05a0c76c228a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302678317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2302678317
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2922637403
Short name T753
Test name
Test status
Simulation time 1041305286 ps
CPU time 8.48 seconds
Started Jul 13 06:32:07 PM PDT 24
Finished Jul 13 06:32:16 PM PDT 24
Peak memory 222928 kb
Host smart-bb4cc904-2f57-47de-95ad-27462238eee3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922637403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2922637403
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.937195382
Short name T751
Test name
Test status
Simulation time 247424503 ps
CPU time 2.44 seconds
Started Jul 13 06:32:06 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 217660 kb
Host smart-1610b8a0-03c2-45d8-9c8e-764e19369925
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937195382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
937195382
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.858644950
Short name T520
Test name
Test status
Simulation time 4808975326 ps
CPU time 55.92 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:55 PM PDT 24
Peak memory 275536 kb
Host smart-007041fb-4cc7-4986-a4c7-7ba304b715db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858644950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.858644950
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.690294783
Short name T388
Test name
Test status
Simulation time 1202187281 ps
CPU time 15.16 seconds
Started Jul 13 06:32:02 PM PDT 24
Finished Jul 13 06:32:18 PM PDT 24
Peak memory 250848 kb
Host smart-85c1977c-8779-4dea-a931-eb477ebe2765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690294783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.690294783
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2724744901
Short name T222
Test name
Test status
Simulation time 369541747 ps
CPU time 4.62 seconds
Started Jul 13 06:32:02 PM PDT 24
Finished Jul 13 06:32:08 PM PDT 24
Peak memory 218152 kb
Host smart-05505629-cf1a-47a8-a8f7-7509a736bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724744901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2724744901
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3385449636
Short name T191
Test name
Test status
Simulation time 4109807659 ps
CPU time 19.89 seconds
Started Jul 13 06:32:00 PM PDT 24
Finished Jul 13 06:32:21 PM PDT 24
Peak memory 226032 kb
Host smart-b67d9bea-dd43-47d7-8162-3b388fd7f344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385449636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3385449636
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4057644423
Short name T768
Test name
Test status
Simulation time 714106396 ps
CPU time 12.23 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:11 PM PDT 24
Peak memory 218176 kb
Host smart-4bcce65f-9475-450b-a082-b8848f5dfa1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057644423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4057644423
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1598827025
Short name T649
Test name
Test status
Simulation time 546505372 ps
CPU time 11.81 seconds
Started Jul 13 06:32:07 PM PDT 24
Finished Jul 13 06:32:19 PM PDT 24
Peak memory 224992 kb
Host smart-8cbd9107-96f1-4bb0-a25a-ca7d211a1c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598827025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1598827025
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1061935539
Short name T682
Test name
Test status
Simulation time 23303089 ps
CPU time 1.71 seconds
Started Jul 13 06:32:02 PM PDT 24
Finished Jul 13 06:32:04 PM PDT 24
Peak memory 217596 kb
Host smart-f7454f42-e187-4efb-8565-1c1319651b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061935539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1061935539
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3177119438
Short name T622
Test name
Test status
Simulation time 370142768 ps
CPU time 24.72 seconds
Started Jul 13 06:32:07 PM PDT 24
Finished Jul 13 06:32:32 PM PDT 24
Peak memory 250916 kb
Host smart-c555637f-fe92-4c84-a3d2-729a5c74a9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177119438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3177119438
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1912703128
Short name T681
Test name
Test status
Simulation time 431379021 ps
CPU time 8.48 seconds
Started Jul 13 06:32:02 PM PDT 24
Finished Jul 13 06:32:11 PM PDT 24
Peak memory 250264 kb
Host smart-8f13afe0-4e83-46af-a2fd-1009d1cc2356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912703128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1912703128
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2044950483
Short name T119
Test name
Test status
Simulation time 3627540983 ps
CPU time 112.85 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 226024 kb
Host smart-f67890e0-582d-4e4a-81f8-e7a48648679d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044950483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2044950483
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2534632858
Short name T91
Test name
Test status
Simulation time 23585293111 ps
CPU time 3838.97 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 07:35:59 PM PDT 24
Peak memory 644320 kb
Host smart-b158fbd5-9db9-4dbf-9905-eaf1a6301d9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2534632858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2534632858
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.334326396
Short name T431
Test name
Test status
Simulation time 129633458 ps
CPU time 0.9 seconds
Started Jul 13 06:32:01 PM PDT 24
Finished Jul 13 06:32:03 PM PDT 24
Peak memory 211844 kb
Host smart-fde11665-42fb-4f3b-a112-aaa9f2e0b979
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334326396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.334326396
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.734871646
Short name T625
Test name
Test status
Simulation time 110379581 ps
CPU time 1.32 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:13 PM PDT 24
Peak memory 208940 kb
Host smart-45f88f00-97aa-4f66-9c49-70674d65034f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734871646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.734871646
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4175712436
Short name T437
Test name
Test status
Simulation time 228194324 ps
CPU time 12.31 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:23 PM PDT 24
Peak memory 225936 kb
Host smart-d208bde9-1ee5-453d-a010-b979d399f22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175712436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4175712436
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1160922462
Short name T471
Test name
Test status
Simulation time 847737422 ps
CPU time 6.08 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:15 PM PDT 24
Peak memory 217044 kb
Host smart-5db6fe54-3f04-4b1a-8916-e9aeb699b96e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160922462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1160922462
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2952198902
Short name T311
Test name
Test status
Simulation time 2654048822 ps
CPU time 42.03 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:52 PM PDT 24
Peak memory 226036 kb
Host smart-886766c4-160c-46ac-b434-c242af3f8628
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952198902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2952198902
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.518800496
Short name T20
Test name
Test status
Simulation time 208890880 ps
CPU time 3.65 seconds
Started Jul 13 06:32:14 PM PDT 24
Finished Jul 13 06:32:18 PM PDT 24
Peak memory 218396 kb
Host smart-a5100890-a4df-42b0-a511-82b69ab077dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518800496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.518800496
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2082328040
Short name T832
Test name
Test status
Simulation time 432126237 ps
CPU time 7.21 seconds
Started Jul 13 06:32:16 PM PDT 24
Finished Jul 13 06:32:23 PM PDT 24
Peak memory 217664 kb
Host smart-6208806d-9ca4-4aa3-98c6-d1272fea1ff9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082328040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2082328040
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3950915295
Short name T838
Test name
Test status
Simulation time 1484711198 ps
CPU time 45.71 seconds
Started Jul 13 06:32:11 PM PDT 24
Finished Jul 13 06:32:58 PM PDT 24
Peak memory 267332 kb
Host smart-25bad569-41e7-4667-b30f-a0bb83700b2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950915295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3950915295
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2430800863
Short name T456
Test name
Test status
Simulation time 732438943 ps
CPU time 27.18 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:38 PM PDT 24
Peak memory 250908 kb
Host smart-2bce3745-1c92-44c4-ae7d-76800c22d6bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430800863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2430800863
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1045188576
Short name T714
Test name
Test status
Simulation time 74103152 ps
CPU time 1.9 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:13 PM PDT 24
Peak memory 218152 kb
Host smart-01e3e7b5-1252-4124-ba56-66f2853a8d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045188576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1045188576
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.299929260
Short name T742
Test name
Test status
Simulation time 1143601506 ps
CPU time 13.63 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:24 PM PDT 24
Peak memory 218892 kb
Host smart-dbce03ec-c0bd-4895-bdec-c754fef09fd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299929260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.299929260
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2745068512
Short name T322
Test name
Test status
Simulation time 1525883538 ps
CPU time 17.72 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 225960 kb
Host smart-5e4916f5-ace4-44b4-a767-2a96da3c24d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745068512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2745068512
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4278290361
Short name T53
Test name
Test status
Simulation time 780569849 ps
CPU time 8.9 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:19 PM PDT 24
Peak memory 218148 kb
Host smart-d094f5c8-3245-4cb8-af7c-0db57f0b653c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278290361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4278290361
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3685360944
Short name T644
Test name
Test status
Simulation time 403273480 ps
CPU time 7.01 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:19 PM PDT 24
Peak memory 225116 kb
Host smart-b5e33de4-47a0-459d-9e78-877d621151ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685360944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3685360944
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.280962171
Short name T466
Test name
Test status
Simulation time 171032622 ps
CPU time 4.79 seconds
Started Jul 13 06:32:00 PM PDT 24
Finished Jul 13 06:32:06 PM PDT 24
Peak memory 217616 kb
Host smart-abd3cf59-8076-41f1-a244-89ee5ce81a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280962171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.280962171
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2276860325
Short name T763
Test name
Test status
Simulation time 320622825 ps
CPU time 29.06 seconds
Started Jul 13 06:32:07 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 250856 kb
Host smart-d2cd5361-39c4-4b0f-9004-72d109fd7320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276860325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2276860325
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.88456164
Short name T316
Test name
Test status
Simulation time 210130409 ps
CPU time 6.73 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:17 PM PDT 24
Peak memory 246876 kb
Host smart-f957d778-5696-4910-95e5-ebd9fbdd229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88456164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.88456164
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.603744719
Short name T193
Test name
Test status
Simulation time 39901341 ps
CPU time 0.88 seconds
Started Jul 13 06:31:59 PM PDT 24
Finished Jul 13 06:32:01 PM PDT 24
Peak memory 212924 kb
Host smart-34490495-a046-449e-8719-0d338dc6493d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603744719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.603744719
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1637895211
Short name T671
Test name
Test status
Simulation time 21098244 ps
CPU time 1.22 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:12 PM PDT 24
Peak memory 208928 kb
Host smart-03e084f2-3c75-47ab-a5fd-80eef8a10cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637895211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1637895211
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.4150796752
Short name T717
Test name
Test status
Simulation time 9337491880 ps
CPU time 15.18 seconds
Started Jul 13 06:32:11 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 218564 kb
Host smart-8efaffe8-5d43-47f5-881c-be956a08a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150796752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.4150796752
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2962381504
Short name T5
Test name
Test status
Simulation time 190919199 ps
CPU time 1.6 seconds
Started Jul 13 06:32:13 PM PDT 24
Finished Jul 13 06:32:15 PM PDT 24
Peak memory 217008 kb
Host smart-a627c6c7-023c-4ff9-9904-66f245b493c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962381504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2962381504
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1635129049
Short name T378
Test name
Test status
Simulation time 9770713023 ps
CPU time 38.27 seconds
Started Jul 13 06:32:12 PM PDT 24
Finished Jul 13 06:32:51 PM PDT 24
Peak memory 218792 kb
Host smart-dfb45ca4-b91a-444f-9dc9-9b4e0bff1893
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635129049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1635129049
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4151418099
Short name T720
Test name
Test status
Simulation time 384763166 ps
CPU time 7.15 seconds
Started Jul 13 06:32:11 PM PDT 24
Finished Jul 13 06:32:19 PM PDT 24
Peak memory 218224 kb
Host smart-f7d36027-6f44-4794-9121-9fdfc63f4846
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151418099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4151418099
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1471573102
Short name T401
Test name
Test status
Simulation time 6079884572 ps
CPU time 6.06 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:17 PM PDT 24
Peak memory 217652 kb
Host smart-49cdde60-4087-42ee-b704-f0a264f52055
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471573102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1471573102
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3955062614
Short name T648
Test name
Test status
Simulation time 2671125881 ps
CPU time 40.95 seconds
Started Jul 13 06:32:13 PM PDT 24
Finished Jul 13 06:32:54 PM PDT 24
Peak memory 267360 kb
Host smart-ffcbb9f1-deb3-4f46-81d6-7a0a9c19f5d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955062614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3955062614
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.552789810
Short name T587
Test name
Test status
Simulation time 5822142260 ps
CPU time 20.28 seconds
Started Jul 13 06:32:17 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 250984 kb
Host smart-7cb9bdef-fb45-4c95-9dd0-172d8c9b6af1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552789810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.552789810
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.492602571
Short name T174
Test name
Test status
Simulation time 101194494 ps
CPU time 1.77 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:13 PM PDT 24
Peak memory 218152 kb
Host smart-138bdf46-aff8-4b97-b49f-9bc2fbd4d203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492602571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.492602571
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.374934990
Short name T501
Test name
Test status
Simulation time 3407595271 ps
CPU time 10.7 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:21 PM PDT 24
Peak memory 226032 kb
Host smart-4020730b-c114-4d89-92db-3bfc38dd0d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374934990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.374934990
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3641906999
Short name T31
Test name
Test status
Simulation time 1249017880 ps
CPU time 12.47 seconds
Started Jul 13 06:32:12 PM PDT 24
Finished Jul 13 06:32:25 PM PDT 24
Peak memory 218472 kb
Host smart-9e30c003-b26e-488e-aade-bf7b0e03913b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641906999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3641906999
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2639211953
Short name T10
Test name
Test status
Simulation time 294003874 ps
CPU time 12.36 seconds
Started Jul 13 06:32:14 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 226196 kb
Host smart-78dd427c-d2c1-4142-b4a8-b747eae99a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639211953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2639211953
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1107096858
Short name T172
Test name
Test status
Simulation time 774217393 ps
CPU time 3.6 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:15 PM PDT 24
Peak memory 214544 kb
Host smart-fb71b150-7e9e-4efa-99f1-49917d7e95ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107096858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1107096858
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2913497562
Short name T411
Test name
Test status
Simulation time 302933813 ps
CPU time 18.99 seconds
Started Jul 13 06:32:11 PM PDT 24
Finished Jul 13 06:32:31 PM PDT 24
Peak memory 250944 kb
Host smart-e1188689-aa1a-469c-87be-31b0082bb2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913497562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2913497562
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1467523225
Short name T632
Test name
Test status
Simulation time 454042004 ps
CPU time 10.51 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:20 PM PDT 24
Peak memory 250852 kb
Host smart-a426bb2c-625b-41af-9c4e-7986201a7216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467523225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1467523225
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1383213482
Short name T314
Test name
Test status
Simulation time 27312396601 ps
CPU time 231.36 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:36:03 PM PDT 24
Peak memory 280972 kb
Host smart-c443c90b-88d4-43a9-bb59-eceffc9f151d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383213482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1383213482
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.344572207
Short name T372
Test name
Test status
Simulation time 12544975 ps
CPU time 1.07 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:12 PM PDT 24
Peak memory 211772 kb
Host smart-ab32d17d-ff6a-4b46-a797-9ac2a23e884f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344572207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.344572207
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1719512082
Short name T65
Test name
Test status
Simulation time 33707315 ps
CPU time 0.92 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:21 PM PDT 24
Peak memory 208884 kb
Host smart-ebba375d-2f9c-492a-bc14-36273984f760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719512082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1719512082
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3890712547
Short name T639
Test name
Test status
Simulation time 587421898 ps
CPU time 9.24 seconds
Started Jul 13 06:32:12 PM PDT 24
Finished Jul 13 06:32:22 PM PDT 24
Peak memory 218092 kb
Host smart-368030f6-9a05-4ef6-a33f-9eaefb59086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890712547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3890712547
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1899161915
Short name T801
Test name
Test status
Simulation time 224488938 ps
CPU time 2 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:21 PM PDT 24
Peak memory 217028 kb
Host smart-f4d361cd-c066-49c9-9ed2-a746a45e6b41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899161915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1899161915
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2797741475
Short name T574
Test name
Test status
Simulation time 20985070905 ps
CPU time 54.78 seconds
Started Jul 13 06:32:20 PM PDT 24
Finished Jul 13 06:33:16 PM PDT 24
Peak memory 218712 kb
Host smart-656f59fd-92df-495a-99ba-ab27bc08a9d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797741475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2797741475
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1903589069
Short name T674
Test name
Test status
Simulation time 588225737 ps
CPU time 9.35 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:30 PM PDT 24
Peak memory 218184 kb
Host smart-6fa37f2e-3565-441a-b32d-bd636eff7673
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903589069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1903589069
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1622344035
Short name T61
Test name
Test status
Simulation time 399702733 ps
CPU time 10.86 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:22 PM PDT 24
Peak memory 217584 kb
Host smart-4b3f5b1c-f7b8-4c34-8a53-8d1711dccc07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622344035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1622344035
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1253565218
Short name T189
Test name
Test status
Simulation time 2058425507 ps
CPU time 47.41 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:33:06 PM PDT 24
Peak memory 251804 kb
Host smart-8147707d-b66e-4055-bb79-1a4b74daba63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253565218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1253565218
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.154955675
Short name T328
Test name
Test status
Simulation time 342199724 ps
CPU time 13.02 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:33 PM PDT 24
Peak memory 223364 kb
Host smart-35c34cde-8228-4701-b61e-d4036e8d4364
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154955675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.154955675
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.993883630
Short name T359
Test name
Test status
Simulation time 148773655 ps
CPU time 3.81 seconds
Started Jul 13 06:32:09 PM PDT 24
Finished Jul 13 06:32:13 PM PDT 24
Peak memory 218172 kb
Host smart-3734bf7a-1840-4cf2-820d-d1b166e368aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993883630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.993883630
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3173733428
Short name T309
Test name
Test status
Simulation time 220206072 ps
CPU time 10.41 seconds
Started Jul 13 06:32:26 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 225904 kb
Host smart-5a6cdfa0-e209-4767-9f87-8f79935ed571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173733428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3173733428
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3157140564
Short name T480
Test name
Test status
Simulation time 1132746723 ps
CPU time 10.62 seconds
Started Jul 13 06:32:26 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 218108 kb
Host smart-a1151249-3921-43aa-95ad-aab670d9fb27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157140564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3157140564
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2977171966
Short name T252
Test name
Test status
Simulation time 35199995 ps
CPU time 2.7 seconds
Started Jul 13 06:32:10 PM PDT 24
Finished Jul 13 06:32:14 PM PDT 24
Peak memory 214676 kb
Host smart-ec770019-06ea-4eba-90af-eb7f379caf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977171966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2977171966
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2597851169
Short name T389
Test name
Test status
Simulation time 315160105 ps
CPU time 23.15 seconds
Started Jul 13 06:32:16 PM PDT 24
Finished Jul 13 06:32:39 PM PDT 24
Peak memory 245340 kb
Host smart-318799d1-7a4a-484c-ac77-b1ed6784c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597851169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2597851169
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2805448871
Short name T260
Test name
Test status
Simulation time 76216621 ps
CPU time 6.84 seconds
Started Jul 13 06:32:11 PM PDT 24
Finished Jul 13 06:32:19 PM PDT 24
Peak memory 250356 kb
Host smart-e118631f-b42b-4940-956b-9d4df7afd1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805448871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2805448871
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1457433379
Short name T519
Test name
Test status
Simulation time 3467575635 ps
CPU time 41.24 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:33:01 PM PDT 24
Peak memory 251016 kb
Host smart-27424c0b-9b41-4c76-8e81-dc3f175b1a46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457433379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1457433379
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2234687942
Short name T102
Test name
Test status
Simulation time 41379389253 ps
CPU time 688.86 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:43:49 PM PDT 24
Peak memory 282660 kb
Host smart-cddef62b-e8e2-4f63-9039-41801c7131e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2234687942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2234687942
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.63926204
Short name T299
Test name
Test status
Simulation time 24389088 ps
CPU time 1.06 seconds
Started Jul 13 06:32:08 PM PDT 24
Finished Jul 13 06:32:10 PM PDT 24
Peak memory 211892 kb
Host smart-ceb4b5e4-5985-4948-84d7-1c2ef3a833da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63926204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_volatile_unlock_smoke.63926204
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.791666340
Short name T646
Test name
Test status
Simulation time 20227408 ps
CPU time 0.95 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:20 PM PDT 24
Peak memory 208852 kb
Host smart-6c4746fa-c17b-4ad1-947f-a6aef3e064cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791666340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.791666340
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.560460386
Short name T381
Test name
Test status
Simulation time 924353465 ps
CPU time 13.41 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:34 PM PDT 24
Peak memory 225968 kb
Host smart-581b84da-09c4-4545-9ad6-8696cab63d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560460386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.560460386
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1025696422
Short name T584
Test name
Test status
Simulation time 3034614350 ps
CPU time 8.42 seconds
Started Jul 13 06:32:20 PM PDT 24
Finished Jul 13 06:32:30 PM PDT 24
Peak memory 217664 kb
Host smart-36624843-ef9b-4609-885a-eda0017f1739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025696422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1025696422
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3319228201
Short name T636
Test name
Test status
Simulation time 9840396887 ps
CPU time 69.25 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 218908 kb
Host smart-285ec2e4-02d8-4161-abe4-ddcb877dda99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319228201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3319228201
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2329846398
Short name T196
Test name
Test status
Simulation time 508334277 ps
CPU time 15.3 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:35 PM PDT 24
Peak memory 218172 kb
Host smart-39b72456-f4e7-4244-9759-34cf4b0c304b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329846398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2329846398
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2107586322
Short name T793
Test name
Test status
Simulation time 1383924221 ps
CPU time 4 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:30 PM PDT 24
Peak memory 217572 kb
Host smart-d3a52c88-e20b-4286-806a-220c1138bc10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107586322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2107586322
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2362006663
Short name T444
Test name
Test status
Simulation time 3693949488 ps
CPU time 12.89 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:33 PM PDT 24
Peak memory 250992 kb
Host smart-c98681ae-ac7a-4b44-b841-7791a4dc1fde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362006663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2362006663
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3757950521
Short name T281
Test name
Test status
Simulation time 72325864 ps
CPU time 3.26 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:23 PM PDT 24
Peak memory 218200 kb
Host smart-e84999e4-0da4-4f0b-b21d-77b10c04dda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757950521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3757950521
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1519798293
Short name T469
Test name
Test status
Simulation time 939933940 ps
CPU time 14.93 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:34 PM PDT 24
Peak memory 225964 kb
Host smart-496a1016-0c36-4f60-9dd0-a94ccd9bf576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519798293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1519798293
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2698607229
Short name T192
Test name
Test status
Simulation time 1271106880 ps
CPU time 13.94 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:33 PM PDT 24
Peak memory 225912 kb
Host smart-4e79532e-eb95-463f-9a05-a13ce9e1024e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698607229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2698607229
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3149002502
Short name T668
Test name
Test status
Simulation time 337789892 ps
CPU time 9.91 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:30 PM PDT 24
Peak memory 218156 kb
Host smart-54b94be2-2d49-4db4-90c7-3b74d032efa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149002502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3149002502
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1428554333
Short name T374
Test name
Test status
Simulation time 3111579750 ps
CPU time 14.56 seconds
Started Jul 13 06:32:16 PM PDT 24
Finished Jul 13 06:32:31 PM PDT 24
Peak memory 226040 kb
Host smart-467ab0ac-7faa-465e-bb16-9ac16c63acdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428554333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1428554333
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3800208489
Short name T676
Test name
Test status
Simulation time 167674518 ps
CPU time 1.36 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:20 PM PDT 24
Peak memory 222868 kb
Host smart-014399c9-0a30-4eff-a88d-c4785052aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800208489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3800208489
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1691792524
Short name T395
Test name
Test status
Simulation time 720573132 ps
CPU time 17.01 seconds
Started Jul 13 06:32:17 PM PDT 24
Finished Jul 13 06:32:35 PM PDT 24
Peak memory 250888 kb
Host smart-fee1b3bb-4896-48ef-9e4e-d5e70b51f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691792524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1691792524
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1982394896
Short name T188
Test name
Test status
Simulation time 53909871 ps
CPU time 7.63 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 243136 kb
Host smart-84e1b0fb-8339-4b13-9bbf-f48057f60a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982394896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1982394896
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1445164500
Short name T699
Test name
Test status
Simulation time 1845915051 ps
CPU time 38.94 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:59 PM PDT 24
Peak memory 250928 kb
Host smart-33612115-bab2-460b-b6da-fd015443b994
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445164500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1445164500
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2225071011
Short name T296
Test name
Test status
Simulation time 11135006 ps
CPU time 1.07 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:21 PM PDT 24
Peak memory 211736 kb
Host smart-3d3f80cb-fb07-49a8-a57a-3dab132bc2de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225071011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2225071011
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1866354119
Short name T847
Test name
Test status
Simulation time 57003558 ps
CPU time 1.07 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:29 PM PDT 24
Peak memory 208912 kb
Host smart-2acf966d-2a1a-4c99-8780-a2426eb3939e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866354119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1866354119
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1918004891
Short name T702
Test name
Test status
Simulation time 1370278722 ps
CPU time 10.34 seconds
Started Jul 13 06:32:20 PM PDT 24
Finished Jul 13 06:32:32 PM PDT 24
Peak memory 218188 kb
Host smart-a2099774-babc-4cb9-b921-3b26f9ccc6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918004891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1918004891
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1276643524
Short name T440
Test name
Test status
Simulation time 299571950 ps
CPU time 7.92 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:34 PM PDT 24
Peak memory 217088 kb
Host smart-b416414a-3ece-4598-828a-78b1cfb33771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276643524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1276643524
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.470318970
Short name T496
Test name
Test status
Simulation time 4946068005 ps
CPU time 22.84 seconds
Started Jul 13 06:32:26 PM PDT 24
Finished Jul 13 06:32:50 PM PDT 24
Peak memory 218248 kb
Host smart-d0a1522c-ac6c-476a-bbac-90e3aa7cb654
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470318970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.470318970
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.662559940
Short name T577
Test name
Test status
Simulation time 1234891192 ps
CPU time 5.48 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:33 PM PDT 24
Peak memory 222984 kb
Host smart-6d3ced47-89ba-4a9b-9cfa-75879f97310f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662559940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.662559940
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2134676713
Short name T590
Test name
Test status
Simulation time 436172749 ps
CPU time 12.53 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:33 PM PDT 24
Peak memory 217672 kb
Host smart-e978ff81-1fb6-4dad-8f4b-069433e5c997
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134676713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2134676713
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2275570634
Short name T417
Test name
Test status
Simulation time 5311768298 ps
CPU time 67.57 seconds
Started Jul 13 06:32:17 PM PDT 24
Finished Jul 13 06:33:25 PM PDT 24
Peak memory 283416 kb
Host smart-f8cb6acf-e935-4f35-8d60-009ada4f57c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275570634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2275570634
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.755678421
Short name T734
Test name
Test status
Simulation time 320860940 ps
CPU time 11.77 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:31 PM PDT 24
Peak memory 250880 kb
Host smart-c9a951ec-4529-4ccc-a80f-60a05eb67990
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755678421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.755678421
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2810576128
Short name T365
Test name
Test status
Simulation time 149880983 ps
CPU time 2.01 seconds
Started Jul 13 06:32:18 PM PDT 24
Finished Jul 13 06:32:21 PM PDT 24
Peak memory 218104 kb
Host smart-19e722fe-96ab-44a7-bfe8-d9957476b598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810576128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2810576128
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3873197933
Short name T518
Test name
Test status
Simulation time 1439785545 ps
CPU time 10.87 seconds
Started Jul 13 06:32:29 PM PDT 24
Finished Jul 13 06:32:40 PM PDT 24
Peak memory 225992 kb
Host smart-b61c62aa-a714-4d08-8c57-38030c5083d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873197933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3873197933
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1174754316
Short name T362
Test name
Test status
Simulation time 3433385391 ps
CPU time 13.63 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:42 PM PDT 24
Peak memory 226032 kb
Host smart-fa7941f5-b2bc-4c2a-a1ab-9e3082889499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174754316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1174754316
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2316483838
Short name T434
Test name
Test status
Simulation time 1134565640 ps
CPU time 13.61 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:39 PM PDT 24
Peak memory 218172 kb
Host smart-065d6fcb-0bee-475a-a124-b1ed63f9d05a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316483838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2316483838
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3617020403
Short name T51
Test name
Test status
Simulation time 1141741683 ps
CPU time 12.22 seconds
Started Jul 13 06:32:19 PM PDT 24
Finished Jul 13 06:32:33 PM PDT 24
Peak memory 225976 kb
Host smart-33645231-25a2-4772-841a-233a0a946ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617020403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3617020403
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2545143743
Short name T745
Test name
Test status
Simulation time 137649180 ps
CPU time 2.21 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:28 PM PDT 24
Peak memory 217584 kb
Host smart-cb0f9b09-e2b4-4861-a59c-9d2a78ca2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545143743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2545143743
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1968470883
Short name T583
Test name
Test status
Simulation time 173862023 ps
CPU time 21.28 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 250840 kb
Host smart-74cb0957-a35e-46c8-a301-b546a7388cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968470883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1968470883
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1806920932
Short name T483
Test name
Test status
Simulation time 384733775 ps
CPU time 6.51 seconds
Started Jul 13 06:32:22 PM PDT 24
Finished Jul 13 06:32:29 PM PDT 24
Peak memory 246896 kb
Host smart-f6d264de-7c56-4350-93a3-560321c90a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806920932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1806920932
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1638994873
Short name T806
Test name
Test status
Simulation time 1017496387 ps
CPU time 43.31 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 250896 kb
Host smart-c6e46461-c6de-4145-ab83-2282597bd4c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638994873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1638994873
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2451659435
Short name T630
Test name
Test status
Simulation time 47175840 ps
CPU time 1.03 seconds
Started Jul 13 06:32:17 PM PDT 24
Finished Jul 13 06:32:18 PM PDT 24
Peak memory 211836 kb
Host smart-4d23f9e0-2a8e-4e51-b23a-0e99c7640409
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451659435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2451659435
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2729974951
Short name T447
Test name
Test status
Simulation time 42291865 ps
CPU time 0.85 seconds
Started Jul 13 06:31:09 PM PDT 24
Finished Jul 13 06:31:11 PM PDT 24
Peak memory 208756 kb
Host smart-008562d4-4da2-4af6-bb44-9326ca8666ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729974951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2729974951
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.454846821
Short name T692
Test name
Test status
Simulation time 16789899 ps
CPU time 0.81 seconds
Started Jul 13 06:31:08 PM PDT 24
Finished Jul 13 06:31:10 PM PDT 24
Peak memory 208912 kb
Host smart-302b7ccc-8b2c-4916-86bf-cad5949a70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454846821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.454846821
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3032337573
Short name T597
Test name
Test status
Simulation time 1899669589 ps
CPU time 9.78 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:28 PM PDT 24
Peak memory 225904 kb
Host smart-a7088f51-7786-41b3-90df-ddda16c95a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032337573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3032337573
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3604793863
Short name T541
Test name
Test status
Simulation time 1383125847 ps
CPU time 6.94 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:15 PM PDT 24
Peak memory 217144 kb
Host smart-c75f1a76-c604-43ee-9f5a-db6ca52c8b9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604793863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3604793863
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1686417472
Short name T330
Test name
Test status
Simulation time 4978798518 ps
CPU time 40.68 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:49 PM PDT 24
Peak memory 218820 kb
Host smart-38db6268-5f39-4ddb-8308-16ec86a8e346
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686417472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1686417472
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3896071757
Short name T353
Test name
Test status
Simulation time 416736164 ps
CPU time 3.27 seconds
Started Jul 13 06:31:14 PM PDT 24
Finished Jul 13 06:31:18 PM PDT 24
Peak memory 217644 kb
Host smart-f6c31b54-8ac2-4ce8-97d5-f3537da0ee8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896071757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
896071757
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1104663612
Short name T288
Test name
Test status
Simulation time 331828881 ps
CPU time 6.51 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:12 PM PDT 24
Peak memory 223020 kb
Host smart-accd5aec-dc4b-4fea-b029-d730f2ac73ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104663612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1104663612
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4098360551
Short name T185
Test name
Test status
Simulation time 6557351050 ps
CPU time 21.46 seconds
Started Jul 13 06:31:08 PM PDT 24
Finished Jul 13 06:31:31 PM PDT 24
Peak memory 217648 kb
Host smart-1bf49697-6191-409a-a2ef-1d0670ae41de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098360551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4098360551
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1163716698
Short name T760
Test name
Test status
Simulation time 76512576 ps
CPU time 1.88 seconds
Started Jul 13 06:31:08 PM PDT 24
Finished Jul 13 06:31:11 PM PDT 24
Peak memory 217664 kb
Host smart-1425be42-e31c-4095-90d7-5246ba80f787
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163716698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1163716698
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.104620743
Short name T343
Test name
Test status
Simulation time 1132866608 ps
CPU time 38.18 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:46 PM PDT 24
Peak memory 250848 kb
Host smart-ca2b6731-2088-4779-9cb6-f0214063aa1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104620743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.104620743
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.994553527
Short name T403
Test name
Test status
Simulation time 850779258 ps
CPU time 17.88 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 247416 kb
Host smart-6a2496f6-80c3-4098-801b-254d1dade316
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994553527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.994553527
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.328518179
Short name T739
Test name
Test status
Simulation time 112890939 ps
CPU time 1.63 seconds
Started Jul 13 06:31:18 PM PDT 24
Finished Jul 13 06:31:21 PM PDT 24
Peak memory 218164 kb
Host smart-3f745c90-46f7-4230-b0be-ada2eb2584a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328518179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.328518179
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1513490442
Short name T476
Test name
Test status
Simulation time 301327302 ps
CPU time 19.96 seconds
Started Jul 13 06:31:08 PM PDT 24
Finished Jul 13 06:31:30 PM PDT 24
Peak memory 214636 kb
Host smart-a5015c86-03f3-4b9e-a482-c88024d0adb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513490442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1513490442
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3471695018
Short name T50
Test name
Test status
Simulation time 117073155 ps
CPU time 24.92 seconds
Started Jul 13 06:31:04 PM PDT 24
Finished Jul 13 06:31:30 PM PDT 24
Peak memory 282436 kb
Host smart-87ee7826-e3b7-4441-a3c6-6ee51a79e5c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471695018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3471695018
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2889292839
Short name T332
Test name
Test status
Simulation time 596996914 ps
CPU time 14.28 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:22 PM PDT 24
Peak memory 225972 kb
Host smart-5c047eb6-2339-4d9c-b617-447be0bd433c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889292839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2889292839
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1734817177
Short name T357
Test name
Test status
Simulation time 3659269982 ps
CPU time 12.91 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:22 PM PDT 24
Peak memory 226040 kb
Host smart-97fa6b42-4173-4e19-9aa0-3b91592d68cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734817177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
734817177
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.4002545122
Short name T236
Test name
Test status
Simulation time 1190172586 ps
CPU time 12.71 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:19 PM PDT 24
Peak memory 218300 kb
Host smart-417830f6-f0e1-4ef3-b55a-dea82be429d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002545122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.4002545122
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3975297493
Short name T628
Test name
Test status
Simulation time 25717734 ps
CPU time 1.42 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:20 PM PDT 24
Peak memory 213684 kb
Host smart-656142f8-3d1b-4ba7-aace-dedfc964960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975297493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3975297493
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.823740796
Short name T633
Test name
Test status
Simulation time 1133101137 ps
CPU time 29.26 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 250792 kb
Host smart-c734f64f-79d9-4ab5-b605-d0b2046cf060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823740796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.823740796
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1897034004
Short name T489
Test name
Test status
Simulation time 64976380 ps
CPU time 3.71 seconds
Started Jul 13 06:31:08 PM PDT 24
Finished Jul 13 06:31:14 PM PDT 24
Peak memory 222324 kb
Host smart-959dcf9e-6155-4365-bb3e-fcee17238183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897034004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1897034004
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1222562884
Short name T547
Test name
Test status
Simulation time 15590811419 ps
CPU time 80.37 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:32:39 PM PDT 24
Peak memory 219168 kb
Host smart-5acdaffc-ebef-4810-9c66-fdd634a2ff49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222562884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1222562884
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4253987439
Short name T594
Test name
Test status
Simulation time 48711001 ps
CPU time 0.86 seconds
Started Jul 13 06:31:08 PM PDT 24
Finished Jul 13 06:31:10 PM PDT 24
Peak memory 211812 kb
Host smart-af2cc9e6-444e-4f70-ad81-e03b1b44f4b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253987439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4253987439
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3149928325
Short name T727
Test name
Test status
Simulation time 29518362 ps
CPU time 1.34 seconds
Started Jul 13 06:32:32 PM PDT 24
Finished Jul 13 06:32:34 PM PDT 24
Peak memory 208984 kb
Host smart-36bb30de-a438-42b6-b139-f084548b8338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149928325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3149928325
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.105652629
Short name T672
Test name
Test status
Simulation time 362803527 ps
CPU time 11.73 seconds
Started Jul 13 06:32:35 PM PDT 24
Finished Jul 13 06:32:48 PM PDT 24
Peak memory 226276 kb
Host smart-4b1a9850-baf5-46be-85b4-f99dd6d9fd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105652629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.105652629
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.29348644
Short name T450
Test name
Test status
Simulation time 69522137 ps
CPU time 1.5 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:28 PM PDT 24
Peak memory 217020 kb
Host smart-78fbcf7a-8fd8-40c9-8de3-3326028989a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29348644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.29348644
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1114130748
Short name T441
Test name
Test status
Simulation time 77457674 ps
CPU time 3.42 seconds
Started Jul 13 06:32:32 PM PDT 24
Finished Jul 13 06:32:36 PM PDT 24
Peak memory 218016 kb
Host smart-846ab306-5d7a-4455-951f-fea5d748100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114130748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1114130748
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.820254781
Short name T386
Test name
Test status
Simulation time 751534351 ps
CPU time 14.86 seconds
Started Jul 13 06:32:30 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 226188 kb
Host smart-5cc1d2d1-c5f0-4bac-83ea-1d0bc8108a1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820254781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.820254781
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.611174890
Short name T566
Test name
Test status
Simulation time 603001672 ps
CPU time 8.68 seconds
Started Jul 13 06:32:28 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 218140 kb
Host smart-1a299f91-8c6d-4d57-9f90-fc7af656ed43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611174890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.611174890
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4116486769
Short name T645
Test name
Test status
Simulation time 852982681 ps
CPU time 8.42 seconds
Started Jul 13 06:32:28 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 224996 kb
Host smart-788fe4d7-61f9-408e-9977-27c9d19d5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116486769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4116486769
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3793568607
Short name T344
Test name
Test status
Simulation time 27144012 ps
CPU time 2.1 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:30 PM PDT 24
Peak memory 214176 kb
Host smart-fcdab783-f587-4168-b4e4-a3a4a9682f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793568607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3793568607
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.52016945
Short name T785
Test name
Test status
Simulation time 1152451419 ps
CPU time 32.76 seconds
Started Jul 13 06:32:28 PM PDT 24
Finished Jul 13 06:33:01 PM PDT 24
Peak memory 250720 kb
Host smart-688efee5-25ea-430b-be16-bfa1c665ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52016945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.52016945
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3836898090
Short name T608
Test name
Test status
Simulation time 535987168 ps
CPU time 8.62 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:42 PM PDT 24
Peak memory 250844 kb
Host smart-314744ec-0da6-4414-b252-abe7a2bc9a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836898090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3836898090
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1467640010
Short name T698
Test name
Test status
Simulation time 9009290484 ps
CPU time 87.83 seconds
Started Jul 13 06:32:24 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 267304 kb
Host smart-99fbb561-3be2-43d6-a76b-ad62df339089
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467640010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1467640010
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.791654530
Short name T128
Test name
Test status
Simulation time 42882903196 ps
CPU time 211.42 seconds
Started Jul 13 06:32:26 PM PDT 24
Finished Jul 13 06:35:58 PM PDT 24
Peak memory 283768 kb
Host smart-f5efb998-3d84-4f89-b476-f4942ca56c0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=791654530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.791654530
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3939551298
Short name T841
Test name
Test status
Simulation time 15951472 ps
CPU time 0.88 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 211836 kb
Host smart-e9b8815c-3dbb-4675-ac8f-f0aa8a050825
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939551298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3939551298
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1556638780
Short name T858
Test name
Test status
Simulation time 17212558 ps
CPU time 0.83 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:29 PM PDT 24
Peak memory 208672 kb
Host smart-8b4d2489-2503-4b3e-a53a-c87c5097641d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556638780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1556638780
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1903223307
Short name T244
Test name
Test status
Simulation time 1209851292 ps
CPU time 13.87 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:42 PM PDT 24
Peak memory 226008 kb
Host smart-2be0ac73-99e6-42e0-9444-6e7964bc3d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903223307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1903223307
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3267319873
Short name T8
Test name
Test status
Simulation time 457176793 ps
CPU time 5.67 seconds
Started Jul 13 06:32:26 PM PDT 24
Finished Jul 13 06:32:32 PM PDT 24
Peak memory 217356 kb
Host smart-9cb37b1e-1da6-4fca-80a3-9e5c42ad2565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267319873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3267319873
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1327152908
Short name T479
Test name
Test status
Simulation time 469730753 ps
CPU time 2.13 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 221992 kb
Host smart-7d400acc-5191-4829-9a8f-442650a77ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327152908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1327152908
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3297495396
Short name T461
Test name
Test status
Simulation time 1216103837 ps
CPU time 7.63 seconds
Started Jul 13 06:32:26 PM PDT 24
Finished Jul 13 06:32:35 PM PDT 24
Peak memory 218164 kb
Host smart-718ec936-ae5e-4fc0-ba4c-9ca968f80ca8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297495396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3297495396
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3309817504
Short name T512
Test name
Test status
Simulation time 1042979857 ps
CPU time 6.2 seconds
Started Jul 13 06:32:28 PM PDT 24
Finished Jul 13 06:32:35 PM PDT 24
Peak memory 218204 kb
Host smart-315f43ab-240e-4d31-abd3-f33022433ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309817504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3309817504
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3758048251
Short name T824
Test name
Test status
Simulation time 268491526 ps
CPU time 13.17 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:39 PM PDT 24
Peak memory 225328 kb
Host smart-d9f2a71d-6444-413e-96a9-a88ec97d30ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758048251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3758048251
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3994688340
Short name T611
Test name
Test status
Simulation time 96811721 ps
CPU time 2.04 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:35 PM PDT 24
Peak memory 214248 kb
Host smart-6f73201c-17a2-410c-9dbf-d497b4333324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994688340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3994688340
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.962994705
Short name T321
Test name
Test status
Simulation time 262155309 ps
CPU time 31.04 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:59 PM PDT 24
Peak memory 250820 kb
Host smart-edecbffc-b701-411d-8847-2c4f49fd65e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962994705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.962994705
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1637669344
Short name T248
Test name
Test status
Simulation time 78206634 ps
CPU time 8.71 seconds
Started Jul 13 06:32:26 PM PDT 24
Finished Jul 13 06:32:36 PM PDT 24
Peak memory 250796 kb
Host smart-f2273862-4299-4c4d-ab69-71ad42520cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637669344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1637669344
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1718810003
Short name T79
Test name
Test status
Simulation time 6568089770 ps
CPU time 58.21 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:33:27 PM PDT 24
Peak memory 267792 kb
Host smart-310c8651-de16-46cd-8d8c-dfb94fcfd2fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718810003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1718810003
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2551786899
Short name T774
Test name
Test status
Simulation time 65945857 ps
CPU time 1.15 seconds
Started Jul 13 06:32:25 PM PDT 24
Finished Jul 13 06:32:27 PM PDT 24
Peak memory 217788 kb
Host smart-26844bf9-ef4f-4b37-a3a9-e5675f7fbf9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551786899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2551786899
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1174719925
Short name T499
Test name
Test status
Simulation time 255874465 ps
CPU time 1.25 seconds
Started Jul 13 06:32:35 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 208960 kb
Host smart-ad14a91f-5e9c-4f17-ba6d-b4ee4e9a84d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174719925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1174719925
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3290285743
Short name T515
Test name
Test status
Simulation time 350316106 ps
CPU time 16.22 seconds
Started Jul 13 06:32:37 PM PDT 24
Finished Jul 13 06:32:54 PM PDT 24
Peak memory 218012 kb
Host smart-79a5ced7-e81f-4d31-9a64-632ba5b00512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290285743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3290285743
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.577803256
Short name T500
Test name
Test status
Simulation time 10888275206 ps
CPU time 18.65 seconds
Started Jul 13 06:32:34 PM PDT 24
Finished Jul 13 06:32:53 PM PDT 24
Peak memory 217680 kb
Host smart-754e5e5f-d151-4055-be69-5b1f380c8a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577803256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.577803256
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.132790907
Short name T337
Test name
Test status
Simulation time 46307678 ps
CPU time 2.37 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 222188 kb
Host smart-09fd7be6-51eb-41eb-883c-45e9de6a85bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132790907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.132790907
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2941953303
Short name T585
Test name
Test status
Simulation time 355363890 ps
CPU time 16.34 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:51 PM PDT 24
Peak memory 218412 kb
Host smart-a79c49ad-6133-4beb-9218-fbc9b7edbb82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941953303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2941953303
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3069202781
Short name T287
Test name
Test status
Simulation time 1425049748 ps
CPU time 13.76 seconds
Started Jul 13 06:32:37 PM PDT 24
Finished Jul 13 06:32:51 PM PDT 24
Peak memory 225812 kb
Host smart-6d9366e1-c46e-4bfc-9844-3840095cd29f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069202781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3069202781
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1198099884
Short name T552
Test name
Test status
Simulation time 348514430 ps
CPU time 11.95 seconds
Started Jul 13 06:32:34 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 218172 kb
Host smart-3170ce4b-20da-4bf0-9789-afad73cad1ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198099884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1198099884
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1474594155
Short name T685
Test name
Test status
Simulation time 255923763 ps
CPU time 8.57 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:42 PM PDT 24
Peak memory 225248 kb
Host smart-0e9c1e94-c6b8-4b65-bccf-374a03f75223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474594155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1474594155
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3238959985
Short name T72
Test name
Test status
Simulation time 164893970 ps
CPU time 1.94 seconds
Started Jul 13 06:32:36 PM PDT 24
Finished Jul 13 06:32:38 PM PDT 24
Peak memory 214172 kb
Host smart-1dd51db2-c208-49d4-b705-4028c0699b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238959985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3238959985
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.369903086
Short name T551
Test name
Test status
Simulation time 331259709 ps
CPU time 39.18 seconds
Started Jul 13 06:32:35 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 250924 kb
Host smart-c9420a61-0f0c-4552-b2da-7181fbb74b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369903086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.369903086
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3770466305
Short name T360
Test name
Test status
Simulation time 1125249620 ps
CPU time 8.47 seconds
Started Jul 13 06:32:36 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 243268 kb
Host smart-3e9a7db8-fb43-4304-b94d-2e5f0638dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770466305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3770466305
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1274584423
Short name T749
Test name
Test status
Simulation time 112199337615 ps
CPU time 176.6 seconds
Started Jul 13 06:32:35 PM PDT 24
Finished Jul 13 06:35:33 PM PDT 24
Peak memory 283712 kb
Host smart-41e0ab0c-1ecc-47d3-930f-968dde827043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274584423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1274584423
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2403855406
Short name T438
Test name
Test status
Simulation time 14483595 ps
CPU time 0.93 seconds
Started Jul 13 06:32:36 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 211812 kb
Host smart-54f5dcc0-521c-4e99-b010-07ebc0d24e4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403855406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2403855406
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3351456462
Short name T178
Test name
Test status
Simulation time 59358029 ps
CPU time 0.92 seconds
Started Jul 13 06:32:32 PM PDT 24
Finished Jul 13 06:32:34 PM PDT 24
Peak memory 208860 kb
Host smart-6ab8b028-a683-44f5-8690-3f8999d74aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351456462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3351456462
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.147139447
Short name T173
Test name
Test status
Simulation time 370681152 ps
CPU time 15.78 seconds
Started Jul 13 06:32:34 PM PDT 24
Finished Jul 13 06:32:51 PM PDT 24
Peak memory 218164 kb
Host smart-8209d121-13df-46a5-a904-12853aaaae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147139447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.147139447
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1504782323
Short name T341
Test name
Test status
Simulation time 152329389 ps
CPU time 2.38 seconds
Started Jul 13 06:32:34 PM PDT 24
Finished Jul 13 06:32:38 PM PDT 24
Peak memory 217008 kb
Host smart-7d11648a-1879-4718-9bac-46edc0936548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504782323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1504782323
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.315137372
Short name T418
Test name
Test status
Simulation time 47459233 ps
CPU time 2.78 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:37 PM PDT 24
Peak memory 222152 kb
Host smart-a79abbd4-f4c3-4d8e-a217-1c93f007e0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315137372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.315137372
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.321278822
Short name T107
Test name
Test status
Simulation time 919266546 ps
CPU time 15.35 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:50 PM PDT 24
Peak memory 226032 kb
Host smart-384afd60-d845-4a23-bf75-28d0cc612e91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321278822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.321278822
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1480716906
Short name T687
Test name
Test status
Simulation time 996656738 ps
CPU time 7.87 seconds
Started Jul 13 06:32:37 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 225596 kb
Host smart-ff05ab65-644e-4452-ae7b-fe3500d78172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480716906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1480716906
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3252776213
Short name T270
Test name
Test status
Simulation time 1154020708 ps
CPU time 11.83 seconds
Started Jul 13 06:32:34 PM PDT 24
Finished Jul 13 06:32:46 PM PDT 24
Peak memory 218204 kb
Host smart-85d7f559-a8ce-4d55-8689-21655651f393
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252776213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3252776213
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2331839237
Short name T637
Test name
Test status
Simulation time 821170403 ps
CPU time 14.33 seconds
Started Jul 13 06:32:38 PM PDT 24
Finished Jul 13 06:32:53 PM PDT 24
Peak memory 225904 kb
Host smart-21f6d209-5946-4bf6-a31b-e0611b31881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331839237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2331839237
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3478370714
Short name T259
Test name
Test status
Simulation time 779803478 ps
CPU time 8.62 seconds
Started Jul 13 06:32:36 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 217728 kb
Host smart-2cb9bfdb-911a-4ee6-8adc-d526884229b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478370714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3478370714
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1083303447
Short name T271
Test name
Test status
Simulation time 1615308700 ps
CPU time 26.37 seconds
Started Jul 13 06:32:35 PM PDT 24
Finished Jul 13 06:33:02 PM PDT 24
Peak memory 250916 kb
Host smart-edaede87-f45c-422c-b977-22a7a3aed7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083303447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1083303447
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1748703284
Short name T268
Test name
Test status
Simulation time 45284421 ps
CPU time 6.23 seconds
Started Jul 13 06:32:35 PM PDT 24
Finished Jul 13 06:32:42 PM PDT 24
Peak memory 246948 kb
Host smart-8e9a284e-30e7-4003-beae-781c640ebd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748703284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1748703284
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1061627137
Short name T618
Test name
Test status
Simulation time 2130393911 ps
CPU time 37.62 seconds
Started Jul 13 06:32:34 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 225972 kb
Host smart-645c100b-e982-4e4e-9838-044bdb530cdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061627137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1061627137
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3954049057
Short name T679
Test name
Test status
Simulation time 33440123 ps
CPU time 0.93 seconds
Started Jul 13 06:32:34 PM PDT 24
Finished Jul 13 06:32:36 PM PDT 24
Peak memory 211812 kb
Host smart-813ee8cb-d898-47e8-941e-62dbeb4a9b03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954049057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3954049057
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3869329735
Short name T305
Test name
Test status
Simulation time 24545063 ps
CPU time 0.89 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 208756 kb
Host smart-54e99090-91c2-4dfe-8dad-30e10aafc6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869329735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3869329735
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2803620432
Short name T549
Test name
Test status
Simulation time 44773263 ps
CPU time 1.79 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:32:48 PM PDT 24
Peak memory 217036 kb
Host smart-6cae1570-0535-4944-a46c-5a8269b21fb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803620432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2803620432
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.874149843
Short name T762
Test name
Test status
Simulation time 71113441 ps
CPU time 3.82 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 222312 kb
Host smart-f21443ea-d2cc-4700-9b23-568c97eaf88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874149843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.874149843
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.4261019958
Short name T548
Test name
Test status
Simulation time 193775458 ps
CPU time 10.04 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:55 PM PDT 24
Peak memory 226088 kb
Host smart-bfe5b74c-6ed3-41ff-b872-6c927bffdd3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261019958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4261019958
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1358542371
Short name T368
Test name
Test status
Simulation time 1428786200 ps
CPU time 8.22 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:53 PM PDT 24
Peak memory 225972 kb
Host smart-ede80bb8-3ce4-4d90-8c95-1f2ad9749e53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358542371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1358542371
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1943799553
Short name T657
Test name
Test status
Simulation time 1429312260 ps
CPU time 13.92 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:33:02 PM PDT 24
Peak memory 218172 kb
Host smart-e2548ac7-0c67-4a30-8a19-c56cf66476c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943799553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1943799553
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.843241036
Short name T323
Test name
Test status
Simulation time 489899091 ps
CPU time 9.79 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:32:58 PM PDT 24
Peak memory 224704 kb
Host smart-1c3d33ef-c9ea-4d8c-8814-8efebab93622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843241036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.843241036
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3245209788
Short name T849
Test name
Test status
Simulation time 51918082 ps
CPU time 3.86 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:38 PM PDT 24
Peak memory 215020 kb
Host smart-bb3f865a-0dc3-459c-bb2c-db26effd6dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245209788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3245209788
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3574148619
Short name T802
Test name
Test status
Simulation time 741156649 ps
CPU time 15.93 seconds
Started Jul 13 06:32:35 PM PDT 24
Finished Jul 13 06:32:52 PM PDT 24
Peak memory 250920 kb
Host smart-de025035-e183-41e5-aa8f-89794373f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574148619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3574148619
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2452691891
Short name T473
Test name
Test status
Simulation time 105454007 ps
CPU time 6.71 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:32:53 PM PDT 24
Peak memory 250388 kb
Host smart-2aa23d3b-7e14-4da0-8e94-08d64968dc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452691891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2452691891
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.104477243
Short name T382
Test name
Test status
Simulation time 7056946900 ps
CPU time 122.13 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:34:49 PM PDT 24
Peak memory 252804 kb
Host smart-c5832e95-0c93-47ea-a470-e4a74d472de1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104477243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.104477243
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4056730160
Short name T573
Test name
Test status
Simulation time 13066876 ps
CPU time 0.96 seconds
Started Jul 13 06:32:33 PM PDT 24
Finished Jul 13 06:32:35 PM PDT 24
Peak memory 211876 kb
Host smart-d5acb64e-a492-406c-a1ac-6ee2a9f128c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056730160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.4056730160
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.865868699
Short name T744
Test name
Test status
Simulation time 25782644 ps
CPU time 1.04 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 208840 kb
Host smart-f8f92736-51f7-4bce-a56a-ff24c6e74c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865868699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.865868699
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2223580548
Short name T423
Test name
Test status
Simulation time 307932104 ps
CPU time 11.35 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:57 PM PDT 24
Peak memory 226040 kb
Host smart-475f9847-853f-4954-9362-8ba31e5db6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223580548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2223580548
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2970569687
Short name T738
Test name
Test status
Simulation time 206157952 ps
CPU time 5.68 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:49 PM PDT 24
Peak memory 217148 kb
Host smart-c33af56d-12ae-468f-a961-cfa908c759eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970569687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2970569687
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2665854344
Short name T373
Test name
Test status
Simulation time 168862702 ps
CPU time 3.28 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:32:52 PM PDT 24
Peak memory 222604 kb
Host smart-9ea25dda-d81c-48da-8d22-5245d7b88d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665854344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2665854344
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2547772751
Short name T303
Test name
Test status
Simulation time 181373507 ps
CPU time 8.87 seconds
Started Jul 13 06:32:42 PM PDT 24
Finished Jul 13 06:32:52 PM PDT 24
Peak memory 218216 kb
Host smart-2f6dff85-5f9b-4665-bfbd-141fd7101c06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547772751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2547772751
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3450090090
Short name T506
Test name
Test status
Simulation time 1768663637 ps
CPU time 12.28 seconds
Started Jul 13 06:32:49 PM PDT 24
Finished Jul 13 06:33:02 PM PDT 24
Peak memory 225980 kb
Host smart-9bb0ee26-ac8d-4f3a-866e-c7ba321b3818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450090090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3450090090
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3797161062
Short name T545
Test name
Test status
Simulation time 286683295 ps
CPU time 9.08 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:32:55 PM PDT 24
Peak memory 218160 kb
Host smart-dcc99fff-6ef5-407e-850f-6370cf4bf010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797161062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3797161062
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2721340703
Short name T560
Test name
Test status
Simulation time 389660241 ps
CPU time 14.16 seconds
Started Jul 13 06:32:46 PM PDT 24
Finished Jul 13 06:33:02 PM PDT 24
Peak memory 218244 kb
Host smart-6d4cde73-9de9-450c-9a5a-ffd3e822d5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721340703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2721340703
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.476633748
Short name T11
Test name
Test status
Simulation time 197026517 ps
CPU time 2.93 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:48 PM PDT 24
Peak memory 217664 kb
Host smart-00410799-72d4-415a-9fc9-0dedda485a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476633748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.476633748
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3691059284
Short name T283
Test name
Test status
Simulation time 2925108132 ps
CPU time 30.7 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 250916 kb
Host smart-0d986883-803c-4ed4-a3c4-a1e28737b325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691059284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3691059284
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.382435011
Short name T817
Test name
Test status
Simulation time 339725366 ps
CPU time 3.49 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:48 PM PDT 24
Peak memory 222580 kb
Host smart-7d6e9299-8e4e-4b21-9811-faaa366daa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382435011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.382435011
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1575702856
Short name T54
Test name
Test status
Simulation time 2626819277 ps
CPU time 64.44 seconds
Started Jul 13 06:32:42 PM PDT 24
Finished Jul 13 06:33:47 PM PDT 24
Peak memory 220572 kb
Host smart-87c5050c-797e-42df-a601-ecb3ae20958b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575702856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1575702856
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.617995838
Short name T315
Test name
Test status
Simulation time 19526262 ps
CPU time 0.84 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:32:49 PM PDT 24
Peak memory 208724 kb
Host smart-7643d2bb-726e-4ede-931f-465e56614a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617995838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.617995838
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1100881380
Short name T307
Test name
Test status
Simulation time 2818596448 ps
CPU time 8.24 seconds
Started Jul 13 06:32:42 PM PDT 24
Finished Jul 13 06:32:51 PM PDT 24
Peak memory 218140 kb
Host smart-5b81b1dd-1957-4f8e-b335-7c770fbc397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100881380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1100881380
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.316482968
Short name T38
Test name
Test status
Simulation time 69560874 ps
CPU time 3.99 seconds
Started Jul 13 06:32:42 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 222752 kb
Host smart-7ca96090-5736-4d8b-922a-f0555941aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316482968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.316482968
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2391521393
Short name T246
Test name
Test status
Simulation time 1613150699 ps
CPU time 18.05 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:33:01 PM PDT 24
Peak memory 225920 kb
Host smart-d9b3c0f6-11ca-495a-bad2-5fd31fa5f99d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391521393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2391521393
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3882587504
Short name T9
Test name
Test status
Simulation time 2098594628 ps
CPU time 15 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:33:01 PM PDT 24
Peak memory 218172 kb
Host smart-2218f508-9a18-4d3d-9280-f9b97efb30de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882587504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3882587504
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2330080784
Short name T290
Test name
Test status
Simulation time 305685901 ps
CPU time 7.86 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:53 PM PDT 24
Peak memory 224860 kb
Host smart-feedee2a-1f87-4682-b9a7-2e7281a32223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330080784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2330080784
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2563805170
Short name T80
Test name
Test status
Simulation time 694111338 ps
CPU time 2.3 seconds
Started Jul 13 06:32:46 PM PDT 24
Finished Jul 13 06:32:49 PM PDT 24
Peak memory 217664 kb
Host smart-212969b5-9598-4dd8-a6bd-d14539f2de63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563805170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2563805170
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.4094693632
Short name T503
Test name
Test status
Simulation time 297743233 ps
CPU time 38.89 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:33:27 PM PDT 24
Peak memory 251036 kb
Host smart-b7c82d70-1921-407a-89f1-31e997f3b465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094693632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4094693632
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3408219209
Short name T112
Test name
Test status
Simulation time 85455289 ps
CPU time 6.64 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:50 PM PDT 24
Peak memory 250912 kb
Host smart-5a5a0eac-9c1f-4112-83a4-7fa60e451ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408219209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3408219209
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1098058757
Short name T44
Test name
Test status
Simulation time 74329364187 ps
CPU time 740.57 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:45:06 PM PDT 24
Peak memory 268380 kb
Host smart-af2f6736-3f45-42dd-a14d-20137c6708be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098058757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1098058757
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3413127993
Short name T755
Test name
Test status
Simulation time 23933813 ps
CPU time 1.07 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 211812 kb
Host smart-f3eff86b-7769-4c6d-a67e-46cfc95addec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413127993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3413127993
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2750893789
Short name T383
Test name
Test status
Simulation time 17651302 ps
CPU time 0.97 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:00 PM PDT 24
Peak memory 208924 kb
Host smart-2ff0325d-3693-4e68-aa39-c3865e08dfc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750893789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2750893789
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1239018556
Short name T32
Test name
Test status
Simulation time 1044849311 ps
CPU time 24.12 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:33:10 PM PDT 24
Peak memory 225976 kb
Host smart-4149f49c-d246-40c7-b0ac-4e3506cb4e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239018556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1239018556
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3149926158
Short name T7
Test name
Test status
Simulation time 612442826 ps
CPU time 6 seconds
Started Jul 13 06:32:44 PM PDT 24
Finished Jul 13 06:32:52 PM PDT 24
Peak memory 217356 kb
Host smart-ce0206b7-bb59-4a78-916f-545711943139
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149926158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3149926158
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1646456425
Short name T261
Test name
Test status
Simulation time 445176619 ps
CPU time 3.6 seconds
Started Jul 13 06:32:42 PM PDT 24
Finished Jul 13 06:32:46 PM PDT 24
Peak memory 222720 kb
Host smart-7cddc396-c292-48e3-82cf-1823682f8ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646456425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1646456425
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1833540880
Short name T510
Test name
Test status
Simulation time 928777238 ps
CPU time 12.46 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:32:59 PM PDT 24
Peak memory 225976 kb
Host smart-3b09cc8b-c8fc-43dc-8026-939776106579
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833540880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1833540880
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2904595968
Short name T257
Test name
Test status
Simulation time 1272204421 ps
CPU time 11.21 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:32:58 PM PDT 24
Peak memory 225992 kb
Host smart-d11c6016-d689-42b8-b3d8-7f93a9cc8b7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904595968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2904595968
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3128160031
Short name T47
Test name
Test status
Simulation time 256794366 ps
CPU time 10.95 seconds
Started Jul 13 06:32:45 PM PDT 24
Finished Jul 13 06:32:57 PM PDT 24
Peak memory 225968 kb
Host smart-e6d3a433-5e01-401c-87ab-69f3ecd2cecc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128160031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3128160031
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.636028661
Short name T177
Test name
Test status
Simulation time 1531538032 ps
CPU time 9.81 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:32:58 PM PDT 24
Peak memory 225008 kb
Host smart-63a9781e-e301-4232-ac60-93600dbd0a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636028661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.636028661
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1188143931
Short name T629
Test name
Test status
Simulation time 112421507 ps
CPU time 3.99 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:48 PM PDT 24
Peak memory 217672 kb
Host smart-02f25038-bd71-4e41-bd7e-e274f8215ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188143931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1188143931
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2064766186
Short name T301
Test name
Test status
Simulation time 171380017 ps
CPU time 22.86 seconds
Started Jul 13 06:32:46 PM PDT 24
Finished Jul 13 06:33:10 PM PDT 24
Peak memory 250980 kb
Host smart-9c52af67-c5dd-49aa-ae33-e9b473b1713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064766186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2064766186
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1196504144
Short name T565
Test name
Test status
Simulation time 123770134 ps
CPU time 7.45 seconds
Started Jul 13 06:32:47 PM PDT 24
Finished Jul 13 06:32:56 PM PDT 24
Peak memory 250492 kb
Host smart-d18677ea-a0e8-4a7e-9408-c14f9c193d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196504144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1196504144
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1156949015
Short name T449
Test name
Test status
Simulation time 30977062644 ps
CPU time 323.73 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:38:24 PM PDT 24
Peak memory 276596 kb
Host smart-19bbdefa-285b-4e7d-a9e4-b4186db380ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156949015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1156949015
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3208859320
Short name T43
Test name
Test status
Simulation time 63808955280 ps
CPU time 536.57 seconds
Started Jul 13 06:32:54 PM PDT 24
Finished Jul 13 06:41:51 PM PDT 24
Peak memory 677088 kb
Host smart-185aead5-46b8-4c0a-91ff-510a9ce1e322
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3208859320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3208859320
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3921921049
Short name T563
Test name
Test status
Simulation time 15877069 ps
CPU time 1.01 seconds
Started Jul 13 06:32:43 PM PDT 24
Finished Jul 13 06:32:45 PM PDT 24
Peak memory 211852 kb
Host smart-904caaeb-e770-425d-b51d-de868f8e1463
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921921049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3921921049
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2931631918
Short name T399
Test name
Test status
Simulation time 65324123 ps
CPU time 1.1 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:32:59 PM PDT 24
Peak memory 208936 kb
Host smart-029ec116-dd9b-4943-9e2e-b497c4b8896d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931631918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2931631918
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1173682360
Short name T428
Test name
Test status
Simulation time 576529828 ps
CPU time 8.43 seconds
Started Jul 13 06:33:02 PM PDT 24
Finished Jul 13 06:33:11 PM PDT 24
Peak memory 218056 kb
Host smart-331a5b42-2eac-4d6b-ae2c-844f88c1face
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173682360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1173682360
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3474670387
Short name T393
Test name
Test status
Simulation time 2048147316 ps
CPU time 4.76 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:33:01 PM PDT 24
Peak memory 217136 kb
Host smart-737da532-3e4e-4599-b467-a1610298767d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474670387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3474670387
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.724979319
Short name T408
Test name
Test status
Simulation time 126109133 ps
CPU time 2.98 seconds
Started Jul 13 06:32:59 PM PDT 24
Finished Jul 13 06:33:03 PM PDT 24
Peak memory 218116 kb
Host smart-2b6163b8-1bcb-402f-b0b2-53a28851af2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724979319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.724979319
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3033242658
Short name T114
Test name
Test status
Simulation time 276693689 ps
CPU time 12.62 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 225956 kb
Host smart-296821cc-773d-4afd-bea0-f6c2ff39dbd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033242658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3033242658
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.4268873303
Short name T406
Test name
Test status
Simulation time 233583815 ps
CPU time 9.56 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 218180 kb
Host smart-b394a49e-b14b-4cac-9e44-ec9c33c76ea6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268873303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
4268873303
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3045479082
Short name T120
Test name
Test status
Simulation time 242211460 ps
CPU time 3.36 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:33:00 PM PDT 24
Peak memory 217604 kb
Host smart-b7e2ef03-95ed-4ed9-a28c-27856bd017a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045479082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3045479082
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1125950556
Short name T623
Test name
Test status
Simulation time 694904789 ps
CPU time 30.27 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 250864 kb
Host smart-376c9e28-35db-4300-b949-c537d45a4619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125950556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1125950556
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1633617221
Short name T171
Test name
Test status
Simulation time 77096612 ps
CPU time 6.33 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:05 PM PDT 24
Peak memory 246228 kb
Host smart-424558fb-61a4-44ca-b2a6-2ee96bceb974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633617221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1633617221
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.4163723116
Short name T596
Test name
Test status
Simulation time 16052223445 ps
CPU time 147.44 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:35:25 PM PDT 24
Peak memory 251120 kb
Host smart-f077f4df-294e-4740-af59-84a1a1be0bf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163723116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.4163723116
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4189489386
Short name T225
Test name
Test status
Simulation time 66837308 ps
CPU time 0.88 seconds
Started Jul 13 06:33:02 PM PDT 24
Finished Jul 13 06:33:04 PM PDT 24
Peak memory 211772 kb
Host smart-2dd285da-d6a9-45da-b178-20f8adc199a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189489386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.4189489386
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1117519904
Short name T626
Test name
Test status
Simulation time 120853152 ps
CPU time 1.05 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:32:59 PM PDT 24
Peak memory 208944 kb
Host smart-be367bed-677b-4f43-b333-2ecf16393196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117519904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1117519904
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2427015741
Short name T470
Test name
Test status
Simulation time 1558222686 ps
CPU time 15.49 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 225976 kb
Host smart-31867819-c66b-4e53-8574-3fe556b90f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427015741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2427015741
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1709770566
Short name T23
Test name
Test status
Simulation time 423861963 ps
CPU time 7.33 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:07 PM PDT 24
Peak memory 217496 kb
Host smart-a6fe7f9d-c3cb-476e-9a73-e5ad7b3990e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709770566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1709770566
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1512945932
Short name T786
Test name
Test status
Simulation time 41874819 ps
CPU time 2.54 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:02 PM PDT 24
Peak memory 218160 kb
Host smart-0d753f47-6685-426b-8a48-dcf70da7c78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512945932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1512945932
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3362944199
Short name T409
Test name
Test status
Simulation time 5152997702 ps
CPU time 18.34 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 226028 kb
Host smart-ce1501af-b04e-4ad2-8949-46f298714020
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362944199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3362944199
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3342873543
Short name T736
Test name
Test status
Simulation time 1111296108 ps
CPU time 8.73 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:33:05 PM PDT 24
Peak memory 225952 kb
Host smart-bf2e13d8-0e3c-415b-a016-f909ffe54fa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342873543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3342873543
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1843080419
Short name T498
Test name
Test status
Simulation time 1444278730 ps
CPU time 7.19 seconds
Started Jul 13 06:33:00 PM PDT 24
Finished Jul 13 06:33:08 PM PDT 24
Peak memory 218180 kb
Host smart-97bcef17-85aa-4d10-9a19-885436277d1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843080419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1843080419
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1695161103
Short name T493
Test name
Test status
Simulation time 1673448385 ps
CPU time 9.63 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 218236 kb
Host smart-04ff1172-e994-4625-84f1-e077544a24a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695161103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1695161103
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2388357190
Short name T319
Test name
Test status
Simulation time 192391415 ps
CPU time 2.79 seconds
Started Jul 13 06:32:59 PM PDT 24
Finished Jul 13 06:33:03 PM PDT 24
Peak memory 214544 kb
Host smart-6e63d4d5-55e8-421d-a86b-19ac0e136dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388357190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2388357190
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2665569103
Short name T397
Test name
Test status
Simulation time 158293162 ps
CPU time 23.98 seconds
Started Jul 13 06:32:59 PM PDT 24
Finished Jul 13 06:33:24 PM PDT 24
Peak memory 250856 kb
Host smart-db67125b-cbee-408d-92f7-52269c7d42d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665569103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2665569103
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2718252037
Short name T376
Test name
Test status
Simulation time 154635950 ps
CPU time 8.44 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:07 PM PDT 24
Peak memory 242724 kb
Host smart-6a383145-f421-46f7-a77a-2635b885c689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718252037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2718252037
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2731535693
Short name T266
Test name
Test status
Simulation time 66248035494 ps
CPU time 420.56 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:39:59 PM PDT 24
Peak memory 267316 kb
Host smart-6355281c-9e29-4f63-bbe2-109d6abe354b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731535693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2731535693
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3176738106
Short name T532
Test name
Test status
Simulation time 42339234926 ps
CPU time 2565.42 seconds
Started Jul 13 06:33:00 PM PDT 24
Finished Jul 13 07:15:47 PM PDT 24
Peak memory 1553528 kb
Host smart-ba5ff4f3-bd05-41da-aa13-560c21a8fb5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3176738106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3176738106
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1841794168
Short name T621
Test name
Test status
Simulation time 33201424 ps
CPU time 0.83 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:32:59 PM PDT 24
Peak memory 211756 kb
Host smart-ca099ad1-41bf-482b-94e3-570d90c00d6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841794168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1841794168
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.822998245
Short name T462
Test name
Test status
Simulation time 75890599 ps
CPU time 0.84 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:18 PM PDT 24
Peak memory 208988 kb
Host smart-9896b593-e9a8-4aa0-8647-71e686f33b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822998245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.822998245
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1745761015
Short name T230
Test name
Test status
Simulation time 62568131 ps
CPU time 0.83 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:07 PM PDT 24
Peak memory 208992 kb
Host smart-dd9a711b-4d2e-4ffa-8189-66cf5fcd14b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745761015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1745761015
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2439838561
Short name T822
Test name
Test status
Simulation time 839743554 ps
CPU time 8.45 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:16 PM PDT 24
Peak memory 218388 kb
Host smart-ebcfaa94-cf62-4fe5-8501-4a174a20c014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439838561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2439838561
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.718580253
Short name T667
Test name
Test status
Simulation time 804029034 ps
CPU time 3.04 seconds
Started Jul 13 06:31:18 PM PDT 24
Finished Jul 13 06:31:22 PM PDT 24
Peak memory 217108 kb
Host smart-c9b080e0-5767-4041-8626-2e75f7e5118f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718580253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.718580253
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2837278303
Short name T21
Test name
Test status
Simulation time 2607476124 ps
CPU time 40.91 seconds
Started Jul 13 06:31:14 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 226028 kb
Host smart-6975bd80-1619-43db-b9fe-00a4ad583b60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837278303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2837278303
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2781655195
Short name T487
Test name
Test status
Simulation time 1676921388 ps
CPU time 21.79 seconds
Started Jul 13 06:31:15 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 217724 kb
Host smart-bd36a5fa-643e-4185-8049-ed5c0887f13c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781655195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
781655195
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2534282412
Short name T361
Test name
Test status
Simulation time 2035770238 ps
CPU time 8.26 seconds
Started Jul 13 06:31:15 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 224072 kb
Host smart-2e43b139-540b-49d5-a52e-eb17c7a01aaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534282412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2534282412
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2193960319
Short name T100
Test name
Test status
Simulation time 8918863204 ps
CPU time 24 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:31:44 PM PDT 24
Peak memory 217704 kb
Host smart-78db1df0-c491-4f2b-99bb-e7b6e13b48b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193960319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2193960319
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4010868300
Short name T18
Test name
Test status
Simulation time 244767480 ps
CPU time 2.59 seconds
Started Jul 13 06:31:05 PM PDT 24
Finished Jul 13 06:31:09 PM PDT 24
Peak memory 217616 kb
Host smart-43dfe2c1-6226-4acd-92aa-4ec4a3ea7f32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010868300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4010868300
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2356054606
Short name T661
Test name
Test status
Simulation time 9698907908 ps
CPU time 54.81 seconds
Started Jul 13 06:31:14 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 280148 kb
Host smart-276ed9e9-5580-4fb6-9e8b-7eca211c2365
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356054606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2356054606
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.693043325
Short name T238
Test name
Test status
Simulation time 45225803 ps
CPU time 2.04 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:11 PM PDT 24
Peak memory 218156 kb
Host smart-0383f098-8e3a-4986-85fd-5399a4a56663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693043325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.693043325
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.48593015
Short name T820
Test name
Test status
Simulation time 1532212301 ps
CPU time 10.59 seconds
Started Jul 13 06:31:09 PM PDT 24
Finished Jul 13 06:31:20 PM PDT 24
Peak memory 214728 kb
Host smart-1710920c-539b-4403-91cb-b93dcbdbfcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48593015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.48593015
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.572341160
Short name T111
Test name
Test status
Simulation time 132162787 ps
CPU time 27.12 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:48 PM PDT 24
Peak memory 281980 kb
Host smart-6eb292c5-144c-4145-80fa-dde5cb6f1ac0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572341160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.572341160
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1917157655
Short name T653
Test name
Test status
Simulation time 981542212 ps
CPU time 10.08 seconds
Started Jul 13 06:31:15 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 225956 kb
Host smart-4ab8a29b-97e3-4bca-b59b-75125e5acead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917157655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1917157655
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2989118425
Short name T488
Test name
Test status
Simulation time 803270690 ps
CPU time 8.46 seconds
Started Jul 13 06:31:22 PM PDT 24
Finished Jul 13 06:31:31 PM PDT 24
Peak memory 225976 kb
Host smart-ef593b65-b338-4385-8013-fcfe7c7fc6c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989118425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2989118425
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1142247380
Short name T308
Test name
Test status
Simulation time 901995055 ps
CPU time 8.19 seconds
Started Jul 13 06:31:14 PM PDT 24
Finished Jul 13 06:31:23 PM PDT 24
Peak memory 218164 kb
Host smart-bac926b0-91aa-4c74-a5aa-aed61d4e92ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142247380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
142247380
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2038540281
Short name T778
Test name
Test status
Simulation time 224106738 ps
CPU time 9.68 seconds
Started Jul 13 06:31:11 PM PDT 24
Finished Jul 13 06:31:21 PM PDT 24
Peak memory 225972 kb
Host smart-249761f6-3662-4524-805b-9bdec16ccece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038540281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2038540281
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2914567246
Short name T76
Test name
Test status
Simulation time 149132126 ps
CPU time 2.3 seconds
Started Jul 13 06:31:08 PM PDT 24
Finished Jul 13 06:31:12 PM PDT 24
Peak memory 214420 kb
Host smart-f7aba5f9-b0ce-4c3e-b901-ea030b9a2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914567246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2914567246
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2928428870
Short name T199
Test name
Test status
Simulation time 877239047 ps
CPU time 29.52 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 250920 kb
Host smart-bd32f33d-ec96-4509-a7b9-c3bd1be76258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928428870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2928428870
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1597737464
Short name T258
Test name
Test status
Simulation time 79938225 ps
CPU time 8.41 seconds
Started Jul 13 06:31:06 PM PDT 24
Finished Jul 13 06:31:16 PM PDT 24
Peak memory 250856 kb
Host smart-1e733a4f-5363-4864-882e-a3550f8efcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597737464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1597737464
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.360944995
Short name T513
Test name
Test status
Simulation time 30063024405 ps
CPU time 224.58 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:35:02 PM PDT 24
Peak memory 278400 kb
Host smart-68fedb3e-373f-414c-b0c3-a966f786329d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360944995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.360944995
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1873603977
Short name T36
Test name
Test status
Simulation time 14039560 ps
CPU time 0.96 seconds
Started Jul 13 06:31:07 PM PDT 24
Finished Jul 13 06:31:10 PM PDT 24
Peak memory 211908 kb
Host smart-4ed8ce32-157d-4976-b099-cac21a0eef41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873603977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1873603977
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3431826342
Short name T419
Test name
Test status
Simulation time 52826835 ps
CPU time 1.07 seconds
Started Jul 13 06:32:55 PM PDT 24
Finished Jul 13 06:32:56 PM PDT 24
Peak memory 208900 kb
Host smart-4804711d-a900-41fa-a27c-532fbfa7f43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431826342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3431826342
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2843904134
Short name T98
Test name
Test status
Simulation time 318157770 ps
CPU time 11.12 seconds
Started Jul 13 06:32:55 PM PDT 24
Finished Jul 13 06:33:06 PM PDT 24
Peak memory 225888 kb
Host smart-cd57a397-d0a3-48c5-96d8-a1f28192f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843904134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2843904134
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3710554444
Short name T6
Test name
Test status
Simulation time 364150194 ps
CPU time 2.49 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:02 PM PDT 24
Peak memory 217004 kb
Host smart-336ac565-ed9a-428b-82de-3e9d366865cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710554444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3710554444
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2984634781
Short name T765
Test name
Test status
Simulation time 94336778 ps
CPU time 4.37 seconds
Started Jul 13 06:32:55 PM PDT 24
Finished Jul 13 06:32:59 PM PDT 24
Peak memory 222636 kb
Host smart-7a84b22c-49d5-48a1-9bc4-ebe568eb83f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984634781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2984634781
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2614944577
Short name T42
Test name
Test status
Simulation time 1136341682 ps
CPU time 17.95 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:16 PM PDT 24
Peak memory 225976 kb
Host smart-d3852e2f-9f9a-47ee-b526-beab2f43da50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614944577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2614944577
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3519880959
Short name T586
Test name
Test status
Simulation time 210866627 ps
CPU time 9.29 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 226200 kb
Host smart-835c1729-27dc-4e55-b465-5c361b747263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519880959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3519880959
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2073314065
Short name T811
Test name
Test status
Simulation time 4589765481 ps
CPU time 9.59 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 218180 kb
Host smart-fc4087d2-c075-4657-b6ec-14a2ca473db9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073314065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2073314065
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1590079195
Short name T627
Test name
Test status
Simulation time 375213657 ps
CPU time 8.69 seconds
Started Jul 13 06:33:00 PM PDT 24
Finished Jul 13 06:33:10 PM PDT 24
Peak memory 225980 kb
Host smart-c68822d3-3f52-47e1-81c2-60d9a80a6453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590079195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1590079195
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2088540724
Short name T511
Test name
Test status
Simulation time 151537152 ps
CPU time 2.72 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:03 PM PDT 24
Peak memory 217648 kb
Host smart-89b843ae-b9c1-4543-a679-cc7b7f4efc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088540724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2088540724
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.4048440760
Short name T197
Test name
Test status
Simulation time 1308246200 ps
CPU time 29.25 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:33:27 PM PDT 24
Peak memory 250956 kb
Host smart-080131d7-e12e-40d3-ba17-6d32597f7943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048440760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4048440760
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.704052997
Short name T85
Test name
Test status
Simulation time 400150944 ps
CPU time 8.03 seconds
Started Jul 13 06:33:00 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 247404 kb
Host smart-d4ae9e1c-d75a-4adc-a4eb-e9a8f23c6b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704052997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.704052997
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2516782414
Short name T22
Test name
Test status
Simulation time 15017474969 ps
CPU time 291.83 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:37:49 PM PDT 24
Peak memory 267252 kb
Host smart-c50e7009-1939-4c85-8446-d39dfb834af1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516782414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2516782414
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3764881510
Short name T228
Test name
Test status
Simulation time 13057946 ps
CPU time 0.89 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:32:57 PM PDT 24
Peak memory 211900 kb
Host smart-a999fdb9-9eeb-4996-b712-520bb63e6cc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764881510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3764881510
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1357719972
Short name T457
Test name
Test status
Simulation time 60251985 ps
CPU time 0.94 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:33:06 PM PDT 24
Peak memory 208572 kb
Host smart-58370e77-7f2d-48b4-bb6d-0b5868120671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357719972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1357719972
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.696988622
Short name T99
Test name
Test status
Simulation time 377043437 ps
CPU time 12.54 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:10 PM PDT 24
Peak memory 218088 kb
Host smart-ec7d13bd-9bab-4470-9254-78fbfd86dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696988622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.696988622
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.301198967
Short name T525
Test name
Test status
Simulation time 1194114211 ps
CPU time 8.8 seconds
Started Jul 13 06:33:02 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 217376 kb
Host smart-e15940f9-7f60-45e1-b88f-cefa84604f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301198967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.301198967
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.812790852
Short name T862
Test name
Test status
Simulation time 104734146 ps
CPU time 1.85 seconds
Started Jul 13 06:32:58 PM PDT 24
Finished Jul 13 06:33:02 PM PDT 24
Peak memory 222100 kb
Host smart-09d2cda6-25a0-4b2b-8a7e-92756123e594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812790852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.812790852
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4233522822
Short name T30
Test name
Test status
Simulation time 562316767 ps
CPU time 10.46 seconds
Started Jul 13 06:33:03 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 225980 kb
Host smart-084712bb-5448-4cf3-a044-cfd919899e1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233522822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4233522822
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1305676020
Short name T794
Test name
Test status
Simulation time 343572516 ps
CPU time 14.78 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 225968 kb
Host smart-cdc46c45-9ce7-41a7-a064-b0f180e79fe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305676020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1305676020
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3623643648
Short name T243
Test name
Test status
Simulation time 2041015313 ps
CPU time 15.33 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:18 PM PDT 24
Peak memory 225976 kb
Host smart-42123df7-bf64-422b-bd6c-156ec7654da6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623643648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3623643648
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3603435628
Short name T831
Test name
Test status
Simulation time 37758485 ps
CPU time 2.08 seconds
Started Jul 13 06:32:57 PM PDT 24
Finished Jul 13 06:33:01 PM PDT 24
Peak memory 213388 kb
Host smart-0155deba-f09b-4103-9ffb-edb084b9a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603435628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3603435628
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4163198825
Short name T588
Test name
Test status
Simulation time 589173884 ps
CPU time 18.28 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 251008 kb
Host smart-cc79f9c5-67bd-4053-9893-032d3b17b39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163198825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4163198825
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3306919060
Short name T276
Test name
Test status
Simulation time 51365206 ps
CPU time 7.77 seconds
Started Jul 13 06:32:55 PM PDT 24
Finished Jul 13 06:33:03 PM PDT 24
Peak memory 250928 kb
Host smart-fd2aca30-1878-4ed1-9766-f4e3f19cba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306919060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3306919060
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3015533042
Short name T830
Test name
Test status
Simulation time 5502798784 ps
CPU time 58.71 seconds
Started Jul 13 06:33:00 PM PDT 24
Finished Jul 13 06:34:00 PM PDT 24
Peak memory 250940 kb
Host smart-eb7c6688-f819-4335-accc-68b4cfc37cfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015533042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3015533042
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2769068672
Short name T537
Test name
Test status
Simulation time 44289877 ps
CPU time 0.92 seconds
Started Jul 13 06:32:56 PM PDT 24
Finished Jul 13 06:32:58 PM PDT 24
Peak memory 211792 kb
Host smart-cb8134de-cfd6-4a9d-8ff7-3082ed60a72f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769068672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2769068672
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1287724342
Short name T606
Test name
Test status
Simulation time 17107722 ps
CPU time 0.89 seconds
Started Jul 13 06:33:03 PM PDT 24
Finished Jul 13 06:33:05 PM PDT 24
Peak memory 208880 kb
Host smart-34e3ca95-71b5-487b-997b-04bf2b13595c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287724342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1287724342
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1019015761
Short name T190
Test name
Test status
Simulation time 771354820 ps
CPU time 14.59 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:33:19 PM PDT 24
Peak memory 218160 kb
Host smart-80b50e89-ee4a-4e80-a712-a11172b9df32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019015761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1019015761
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3507748783
Short name T370
Test name
Test status
Simulation time 267595351 ps
CPU time 8.47 seconds
Started Jul 13 06:33:03 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 217400 kb
Host smart-a164cd64-5ff7-4522-93e8-37b4f6dbf68d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507748783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3507748783
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3072657791
Short name T835
Test name
Test status
Simulation time 350487757 ps
CPU time 2.82 seconds
Started Jul 13 06:33:00 PM PDT 24
Finished Jul 13 06:33:04 PM PDT 24
Peak memory 218156 kb
Host smart-c99a171d-376a-466f-a446-c0da3130a48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072657791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3072657791
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.405862792
Short name T57
Test name
Test status
Simulation time 1426660456 ps
CPU time 12.42 seconds
Started Jul 13 06:33:03 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 225968 kb
Host smart-9d95d6e4-930f-41df-bc04-d04623d23651
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405862792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.405862792
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.235744215
Short name T454
Test name
Test status
Simulation time 1478457866 ps
CPU time 11.89 seconds
Started Jul 13 06:33:06 PM PDT 24
Finished Jul 13 06:33:19 PM PDT 24
Peak memory 225984 kb
Host smart-7648abf9-7e8f-4749-bbac-573a7a579821
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235744215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.235744215
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3564342573
Short name T352
Test name
Test status
Simulation time 534898890 ps
CPU time 9.94 seconds
Started Jul 13 06:33:05 PM PDT 24
Finished Jul 13 06:33:16 PM PDT 24
Peak memory 218184 kb
Host smart-afb770ea-ecfd-4f2d-ac4e-4c1ba5abdebb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564342573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3564342573
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3085106816
Short name T599
Test name
Test status
Simulation time 303294531 ps
CPU time 11.09 seconds
Started Jul 13 06:33:00 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 218300 kb
Host smart-1748c75f-710a-40fe-b02e-8c0ea5c36c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085106816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3085106816
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3454018281
Short name T613
Test name
Test status
Simulation time 294287810 ps
CPU time 3.82 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:33:08 PM PDT 24
Peak memory 218016 kb
Host smart-820040cf-cc61-48b0-a020-c2373ac04b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454018281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3454018281
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3397739655
Short name T788
Test name
Test status
Simulation time 2153509724 ps
CPU time 27.39 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:30 PM PDT 24
Peak memory 250988 kb
Host smart-94240ac7-5e3f-4408-a12a-4810f392c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397739655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3397739655
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2903903777
Short name T582
Test name
Test status
Simulation time 301603718 ps
CPU time 6.91 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 250936 kb
Host smart-45b01f2a-a9ca-4d72-ba23-84a6c468786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903903777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2903903777
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2777960331
Short name T122
Test name
Test status
Simulation time 4528827892 ps
CPU time 119.73 seconds
Started Jul 13 06:33:06 PM PDT 24
Finished Jul 13 06:35:06 PM PDT 24
Peak memory 272428 kb
Host smart-0cc8267d-5a77-4a93-9762-a89ff96817e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777960331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2777960331
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3416521699
Short name T167
Test name
Test status
Simulation time 28454008561 ps
CPU time 1031.59 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:50:16 PM PDT 24
Peak memory 595156 kb
Host smart-eb264f2f-c47d-4c35-bcd6-9b590a669c57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3416521699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.3416521699
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1197691824
Short name T690
Test name
Test status
Simulation time 25508398 ps
CPU time 0.87 seconds
Started Jul 13 06:33:06 PM PDT 24
Finished Jul 13 06:33:08 PM PDT 24
Peak memory 211880 kb
Host smart-f789b246-1539-4c8d-bc81-7ae73f16e889
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197691824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1197691824
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2297821195
Short name T338
Test name
Test status
Simulation time 28642457 ps
CPU time 1.1 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:04 PM PDT 24
Peak memory 208916 kb
Host smart-43d46213-fffd-4981-8a70-41dbb72edfca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297821195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2297821195
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1470899778
Short name T773
Test name
Test status
Simulation time 5392380460 ps
CPU time 13.63 seconds
Started Jul 13 06:33:02 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 218820 kb
Host smart-9b63cbb6-0e99-4cd2-8fd2-5a10a27fb074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470899778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1470899778
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4189927316
Short name T412
Test name
Test status
Simulation time 752833460 ps
CPU time 2.3 seconds
Started Jul 13 06:33:06 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 217048 kb
Host smart-35cbc952-4702-45e6-9eff-58b8dba51ebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189927316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.4189927316
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2123014821
Short name T33
Test name
Test status
Simulation time 24042356 ps
CPU time 1.63 seconds
Started Jul 13 06:33:02 PM PDT 24
Finished Jul 13 06:33:05 PM PDT 24
Peak memory 221764 kb
Host smart-733b105d-8bf3-4a8e-9592-6766ffdd2976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123014821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2123014821
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.279491233
Short name T737
Test name
Test status
Simulation time 754588996 ps
CPU time 12.43 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 218600 kb
Host smart-618bd6cb-0d3d-4871-93aa-e658fe0cef1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279491233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.279491233
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3372477282
Short name T860
Test name
Test status
Simulation time 339513996 ps
CPU time 13.85 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 225784 kb
Host smart-1de0d05a-8ca8-4c52-af8d-4ab3f9e75992
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372477282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3372477282
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.225756053
Short name T711
Test name
Test status
Simulation time 962340819 ps
CPU time 10.2 seconds
Started Jul 13 06:33:06 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 218112 kb
Host smart-c8393345-d4b9-4bbd-8255-c092ac304b86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225756053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.225756053
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.572032032
Short name T730
Test name
Test status
Simulation time 1524270995 ps
CPU time 11.52 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:33:16 PM PDT 24
Peak memory 226036 kb
Host smart-40f101e3-1cd4-4055-9a1a-94c3662f8666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572032032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.572032032
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1347829386
Short name T427
Test name
Test status
Simulation time 163048432 ps
CPU time 1.99 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:04 PM PDT 24
Peak memory 214008 kb
Host smart-39238c98-e14d-4ef2-8422-24a0ec1af94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347829386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1347829386
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1060702342
Short name T179
Test name
Test status
Simulation time 268846033 ps
CPU time 33.74 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:36 PM PDT 24
Peak memory 250904 kb
Host smart-8c7eb397-afef-4af4-a7d1-0501d613df0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060702342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1060702342
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3081042497
Short name T84
Test name
Test status
Simulation time 176511209 ps
CPU time 9.08 seconds
Started Jul 13 06:33:06 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 250844 kb
Host smart-c1a73d6c-a3c8-44ab-b6d6-078a69654878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081042497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3081042497
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1288647280
Short name T576
Test name
Test status
Simulation time 8768411302 ps
CPU time 237.65 seconds
Started Jul 13 06:33:02 PM PDT 24
Finished Jul 13 06:37:01 PM PDT 24
Peak memory 283728 kb
Host smart-b2535b0a-b785-4a8f-96c3-cfc32d8d80dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288647280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1288647280
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1551269165
Short name T728
Test name
Test status
Simulation time 74698891 ps
CPU time 0.86 seconds
Started Jul 13 06:33:03 PM PDT 24
Finished Jul 13 06:33:05 PM PDT 24
Peak memory 211848 kb
Host smart-ba77af3a-1fb2-4aea-977d-a3a53531b178
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551269165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1551269165
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.928127948
Short name T662
Test name
Test status
Simulation time 45666827 ps
CPU time 0.97 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:13 PM PDT 24
Peak memory 209000 kb
Host smart-adc87baf-437f-4636-b53c-f67dd240e233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928127948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.928127948
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2042234350
Short name T539
Test name
Test status
Simulation time 881048250 ps
CPU time 9.43 seconds
Started Jul 13 06:33:09 PM PDT 24
Finished Jul 13 06:33:19 PM PDT 24
Peak memory 225984 kb
Host smart-1cb3a36f-164b-4aa6-8ac9-933453d9af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042234350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2042234350
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2862652907
Short name T385
Test name
Test status
Simulation time 149541017 ps
CPU time 4.86 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:18 PM PDT 24
Peak memory 217656 kb
Host smart-23b5ad57-4a41-43d8-a1c8-dcaae82fb600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862652907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2862652907
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.906372248
Short name T624
Test name
Test status
Simulation time 281941932 ps
CPU time 3.95 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 218144 kb
Host smart-3fffb4a9-3db2-452c-a402-e31c4b9b032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906372248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.906372248
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1160657428
Short name T318
Test name
Test status
Simulation time 1227101739 ps
CPU time 16.57 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 218816 kb
Host smart-a2a3cd8f-340b-425a-8438-eaac8291b48f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160657428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1160657428
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3254260137
Short name T491
Test name
Test status
Simulation time 860980996 ps
CPU time 11.41 seconds
Started Jul 13 06:33:10 PM PDT 24
Finished Jul 13 06:33:22 PM PDT 24
Peak memory 225916 kb
Host smart-f6164710-2d2f-49df-b76a-ae45ed7f6e58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254260137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3254260137
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1882277264
Short name T517
Test name
Test status
Simulation time 323536053 ps
CPU time 11.65 seconds
Started Jul 13 06:33:12 PM PDT 24
Finished Jul 13 06:33:25 PM PDT 24
Peak memory 218160 kb
Host smart-8b950460-2c90-49f7-a961-be72bc023edf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882277264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1882277264
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3436201658
Short name T605
Test name
Test status
Simulation time 2600323499 ps
CPU time 10.52 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:22 PM PDT 24
Peak memory 218360 kb
Host smart-50e6d158-8449-4891-9870-b2d5c30a9fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436201658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3436201658
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4091265653
Short name T754
Test name
Test status
Simulation time 13780059 ps
CPU time 1.23 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:04 PM PDT 24
Peak memory 212032 kb
Host smart-eca105db-a403-483b-ab23-76666ebb2a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091265653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4091265653
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.4263392332
Short name T83
Test name
Test status
Simulation time 311525385 ps
CPU time 27.48 seconds
Started Jul 13 06:33:03 PM PDT 24
Finished Jul 13 06:33:31 PM PDT 24
Peak memory 250916 kb
Host smart-aa08afc6-25a4-48e9-9968-494877778d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263392332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4263392332
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3171545389
Short name T814
Test name
Test status
Simulation time 76213328 ps
CPU time 6.76 seconds
Started Jul 13 06:33:01 PM PDT 24
Finished Jul 13 06:33:09 PM PDT 24
Peak memory 250860 kb
Host smart-6175bf1c-d2d8-4f3e-be50-1bfb12dd2c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171545389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3171545389
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3479437333
Short name T224
Test name
Test status
Simulation time 26757250432 ps
CPU time 241.66 seconds
Started Jul 13 06:33:13 PM PDT 24
Finished Jul 13 06:37:15 PM PDT 24
Peak memory 252596 kb
Host smart-17f10914-5304-4c6b-b394-af4f5a270538
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479437333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3479437333
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1854714436
Short name T166
Test name
Test status
Simulation time 141589478856 ps
CPU time 459.17 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:40:52 PM PDT 24
Peak memory 514576 kb
Host smart-3c727cce-d6fb-4d53-836b-800d36b9326f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1854714436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1854714436
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3948899043
Short name T731
Test name
Test status
Simulation time 30219448 ps
CPU time 0.89 seconds
Started Jul 13 06:33:04 PM PDT 24
Finished Jul 13 06:33:06 PM PDT 24
Peak memory 211808 kb
Host smart-d20d538b-1993-4fae-9084-890bfad2f011
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948899043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3948899043
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2886739653
Short name T807
Test name
Test status
Simulation time 55636485 ps
CPU time 0.8 seconds
Started Jul 13 06:33:09 PM PDT 24
Finished Jul 13 06:33:11 PM PDT 24
Peak memory 208944 kb
Host smart-62332f48-491c-4e9f-b34c-c5dfc379ec45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886739653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2886739653
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1991233418
Short name T468
Test name
Test status
Simulation time 2010829942 ps
CPU time 14.2 seconds
Started Jul 13 06:33:09 PM PDT 24
Finished Jul 13 06:33:24 PM PDT 24
Peak memory 225984 kb
Host smart-804e2fb7-13f7-400a-b0ee-f39631c5215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991233418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1991233418
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.865541711
Short name T607
Test name
Test status
Simulation time 481778650 ps
CPU time 6.97 seconds
Started Jul 13 06:33:10 PM PDT 24
Finished Jul 13 06:33:18 PM PDT 24
Peak memory 217212 kb
Host smart-376b0609-b8bc-4394-b3f1-2948a0354287
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865541711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.865541711
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1610929930
Short name T792
Test name
Test status
Simulation time 31094178 ps
CPU time 1.45 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:14 PM PDT 24
Peak memory 218172 kb
Host smart-65d97132-83b1-4c69-9f11-e99889b329d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610929930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1610929930
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1259137258
Short name T767
Test name
Test status
Simulation time 726561122 ps
CPU time 13.97 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:26 PM PDT 24
Peak memory 225968 kb
Host smart-d6632093-1e37-495d-9692-bab14771a866
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259137258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1259137258
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4058806051
Short name T443
Test name
Test status
Simulation time 363208839 ps
CPU time 10.59 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:23 PM PDT 24
Peak memory 225984 kb
Host smart-6dc5a8a7-b4b0-4eaa-8e20-48fa6d8a587c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058806051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4058806051
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1110316353
Short name T398
Test name
Test status
Simulation time 1442280590 ps
CPU time 10.51 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:23 PM PDT 24
Peak memory 218100 kb
Host smart-a569fbbd-b215-455b-b8d9-61515b1406c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110316353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1110316353
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.476633928
Short name T465
Test name
Test status
Simulation time 306707986 ps
CPU time 8.27 seconds
Started Jul 13 06:33:12 PM PDT 24
Finished Jul 13 06:33:21 PM PDT 24
Peak memory 224744 kb
Host smart-ff16c52f-c37e-4dc6-96fe-917ee3260abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476633928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.476633928
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1315313115
Short name T721
Test name
Test status
Simulation time 52116392 ps
CPU time 2.88 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:15 PM PDT 24
Peak memory 217592 kb
Host smart-151dcb06-4edd-4403-814a-5a1c046e14b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315313115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1315313115
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.327972176
Short name T504
Test name
Test status
Simulation time 332222062 ps
CPU time 29.22 seconds
Started Jul 13 06:33:10 PM PDT 24
Finished Jul 13 06:33:40 PM PDT 24
Peak memory 250912 kb
Host smart-1912d17c-b0cf-4641-85dd-92cf2fa89bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327972176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.327972176
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.692747293
Short name T818
Test name
Test status
Simulation time 312707368 ps
CPU time 6.52 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:19 PM PDT 24
Peak memory 250536 kb
Host smart-c737598f-31fa-415b-a94f-6b941591180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692747293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.692747293
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.31694933
Short name T535
Test name
Test status
Simulation time 11829284082 ps
CPU time 163.3 seconds
Started Jul 13 06:33:12 PM PDT 24
Finished Jul 13 06:35:57 PM PDT 24
Peak memory 267364 kb
Host smart-b7feebdd-8e41-46b9-a404-d554d311a177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31694933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.lc_ctrl_stress_all.31694933
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1081317744
Short name T164
Test name
Test status
Simulation time 26424596414 ps
CPU time 153.47 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:35:46 PM PDT 24
Peak memory 269340 kb
Host smart-54ce9d8d-0bfc-4e1c-9bf1-18107ab2ae37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1081317744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1081317744
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1950300408
Short name T536
Test name
Test status
Simulation time 54297544 ps
CPU time 0.9 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:14 PM PDT 24
Peak memory 211896 kb
Host smart-aa639327-a6cd-4474-a6e3-478fbe5ef2d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950300408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1950300408
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2632212430
Short name T570
Test name
Test status
Simulation time 31471758 ps
CPU time 0.85 seconds
Started Jul 13 06:33:17 PM PDT 24
Finished Jul 13 06:33:19 PM PDT 24
Peak memory 208924 kb
Host smart-054a77fe-62fa-42ba-a30c-5c816705e15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632212430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2632212430
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.776998403
Short name T94
Test name
Test status
Simulation time 211351861 ps
CPU time 10.19 seconds
Started Jul 13 06:33:13 PM PDT 24
Finished Jul 13 06:33:24 PM PDT 24
Peak memory 218084 kb
Host smart-787e2851-d1fe-4f5d-8c24-f1289f1912a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776998403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.776998403
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2426041531
Short name T748
Test name
Test status
Simulation time 411219708 ps
CPU time 3.27 seconds
Started Jul 13 06:33:09 PM PDT 24
Finished Jul 13 06:33:13 PM PDT 24
Peak memory 217020 kb
Host smart-556dcd3b-c38d-474c-a63c-7db73814b4ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426041531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2426041531
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1132083016
Short name T482
Test name
Test status
Simulation time 88891344 ps
CPU time 1.84 seconds
Started Jul 13 06:33:09 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 221976 kb
Host smart-f38eb350-f162-4278-92fd-e10b0493b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132083016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1132083016
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4033605726
Short name T851
Test name
Test status
Simulation time 1819879225 ps
CPU time 10.73 seconds
Started Jul 13 06:33:12 PM PDT 24
Finished Jul 13 06:33:24 PM PDT 24
Peak memory 226032 kb
Host smart-f74d0855-776e-40b9-b84e-c0aa3b380ac7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033605726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4033605726
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2046436756
Short name T390
Test name
Test status
Simulation time 1287332873 ps
CPU time 16.59 seconds
Started Jul 13 06:33:12 PM PDT 24
Finished Jul 13 06:33:30 PM PDT 24
Peak memory 225968 kb
Host smart-64953c8c-f8d1-4b03-accf-f55898a306fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046436756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2046436756
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.118924516
Short name T384
Test name
Test status
Simulation time 226571389 ps
CPU time 9.59 seconds
Started Jul 13 06:33:10 PM PDT 24
Finished Jul 13 06:33:21 PM PDT 24
Peak memory 226000 kb
Host smart-37e00110-ec3d-4fb2-85ca-c48a9f37ed7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118924516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.118924516
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4011723769
Short name T237
Test name
Test status
Simulation time 2247672496 ps
CPU time 11.68 seconds
Started Jul 13 06:33:13 PM PDT 24
Finished Jul 13 06:33:25 PM PDT 24
Peak memory 225968 kb
Host smart-65915acf-72c2-4587-bf91-78bc6bced139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011723769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4011723769
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1220921360
Short name T75
Test name
Test status
Simulation time 122169885 ps
CPU time 1.57 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:13 PM PDT 24
Peak memory 217652 kb
Host smart-d124fc3c-87f1-4bb3-b13c-8a432efa3540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220921360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1220921360
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3131034165
Short name T821
Test name
Test status
Simulation time 538166506 ps
CPU time 22.35 seconds
Started Jul 13 06:33:08 PM PDT 24
Finished Jul 13 06:33:31 PM PDT 24
Peak memory 250940 kb
Host smart-85bf403a-1f78-4073-9cd0-f1beb936f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131034165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3131034165
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3850764056
Short name T478
Test name
Test status
Simulation time 67190618 ps
CPU time 3.53 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:16 PM PDT 24
Peak memory 218156 kb
Host smart-e108556f-1da4-4ba0-9923-a9921c6f9df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850764056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3850764056
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.146495050
Short name T366
Test name
Test status
Simulation time 1093226254 ps
CPU time 57.66 seconds
Started Jul 13 06:33:13 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 275872 kb
Host smart-6e643199-aec3-40fb-a25e-319c6b4a61ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146495050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.146495050
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2580668782
Short name T445
Test name
Test status
Simulation time 36255622 ps
CPU time 0.91 seconds
Started Jul 13 06:33:11 PM PDT 24
Finished Jul 13 06:33:13 PM PDT 24
Peak memory 211820 kb
Host smart-c3722ab0-636f-4b48-8db8-042dcd14fa22
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580668782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2580668782
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1079490865
Short name T89
Test name
Test status
Simulation time 56477941 ps
CPU time 0.94 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:23 PM PDT 24
Peak memory 208916 kb
Host smart-18def98f-c4f1-49bc-b71b-234bc8298aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079490865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1079490865
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1373587026
Short name T527
Test name
Test status
Simulation time 1805363565 ps
CPU time 14.66 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:36 PM PDT 24
Peak memory 218152 kb
Host smart-f46c978f-afb8-46a0-a46c-b33ef0d41766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373587026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1373587026
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2843521827
Short name T508
Test name
Test status
Simulation time 655840121 ps
CPU time 9.91 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:30 PM PDT 24
Peak memory 217132 kb
Host smart-daabbdc3-8225-48dc-94cd-776ecee562bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843521827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2843521827
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1815106564
Short name T609
Test name
Test status
Simulation time 89086016 ps
CPU time 1.89 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:23 PM PDT 24
Peak memory 222052 kb
Host smart-fd89790b-d6f6-4a63-8372-fa293982ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815106564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1815106564
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.45384768
Short name T293
Test name
Test status
Simulation time 767161141 ps
CPU time 14.67 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:36 PM PDT 24
Peak memory 218948 kb
Host smart-0995f2c1-9510-45d6-8f11-8fffe1612c0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45384768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.45384768
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3301007680
Short name T347
Test name
Test status
Simulation time 1581997184 ps
CPU time 15.77 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:37 PM PDT 24
Peak memory 225968 kb
Host smart-02f66321-b4d1-4346-8173-85166161de15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301007680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3301007680
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1867559278
Short name T635
Test name
Test status
Simulation time 1141237602 ps
CPU time 11.24 seconds
Started Jul 13 06:33:18 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 225908 kb
Host smart-c90c477e-f28f-4358-9f90-4b6888d2c6c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867559278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1867559278
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3861234470
Short name T448
Test name
Test status
Simulation time 2091474452 ps
CPU time 7.91 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 218232 kb
Host smart-bf47c315-ed92-4706-a675-d1c6434760cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861234470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3861234470
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2806676287
Short name T298
Test name
Test status
Simulation time 40742274 ps
CPU time 1.26 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:22 PM PDT 24
Peak memory 217580 kb
Host smart-6523953a-a73d-44c7-905e-a0b4809f2964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806676287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2806676287
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1976125395
Short name T108
Test name
Test status
Simulation time 1148605697 ps
CPU time 30.12 seconds
Started Jul 13 06:33:21 PM PDT 24
Finished Jul 13 06:33:52 PM PDT 24
Peak memory 251220 kb
Host smart-652d601f-a13e-4e7b-a4bf-c0e06442c57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976125395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1976125395
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3331774766
Short name T304
Test name
Test status
Simulation time 66595603 ps
CPU time 7.1 seconds
Started Jul 13 06:33:18 PM PDT 24
Finished Jul 13 06:33:26 PM PDT 24
Peak memory 246896 kb
Host smart-df0edd73-7cc7-46ac-8498-77e2339d88d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331774766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3331774766
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2800003169
Short name T295
Test name
Test status
Simulation time 7489670184 ps
CPU time 166.21 seconds
Started Jul 13 06:33:18 PM PDT 24
Finished Jul 13 06:36:04 PM PDT 24
Peak memory 266932 kb
Host smart-eba78483-0bd9-477e-9a17-1106a1dd76d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800003169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2800003169
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2776479578
Short name T769
Test name
Test status
Simulation time 12996090 ps
CPU time 1.07 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:21 PM PDT 24
Peak memory 211788 kb
Host smart-a69526a7-e231-4e88-98db-57f516b500fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776479578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2776479578
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3709043377
Short name T556
Test name
Test status
Simulation time 77590847 ps
CPU time 1.18 seconds
Started Jul 13 06:33:26 PM PDT 24
Finished Jul 13 06:33:28 PM PDT 24
Peak memory 208916 kb
Host smart-0cb55ea2-94a0-457b-bf1c-6182a798da6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709043377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3709043377
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1264921830
Short name T41
Test name
Test status
Simulation time 645482751 ps
CPU time 15.49 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:35 PM PDT 24
Peak memory 218092 kb
Host smart-45c257f8-e946-48d3-bf57-91524591248f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264921830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1264921830
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1742732468
Short name T726
Test name
Test status
Simulation time 324511859 ps
CPU time 4.69 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:25 PM PDT 24
Peak memory 217388 kb
Host smart-c41e74e9-f165-427c-8253-fdaf26974b1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742732468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1742732468
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1118505504
Short name T267
Test name
Test status
Simulation time 91253704 ps
CPU time 2.4 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:24 PM PDT 24
Peak memory 218152 kb
Host smart-3a87b929-de08-4245-8a64-b05dde744d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118505504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1118505504
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4152997404
Short name T761
Test name
Test status
Simulation time 344838327 ps
CPU time 15.79 seconds
Started Jul 13 06:33:18 PM PDT 24
Finished Jul 13 06:33:35 PM PDT 24
Peak memory 218196 kb
Host smart-9e660ea8-5c2d-4ddf-9a9f-cb4f3fadcb0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152997404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4152997404
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3041102998
Short name T289
Test name
Test status
Simulation time 493714443 ps
CPU time 10.79 seconds
Started Jul 13 06:33:18 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 225976 kb
Host smart-db679946-2da8-4144-86db-a506b418ed05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041102998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3041102998
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.640343095
Short name T391
Test name
Test status
Simulation time 296675312 ps
CPU time 9.89 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 218108 kb
Host smart-b31c50c1-0492-41c3-addc-2c670119118b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640343095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.640343095
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1115277873
Short name T380
Test name
Test status
Simulation time 1295723569 ps
CPU time 13.49 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:35 PM PDT 24
Peak memory 225908 kb
Host smart-75c80d16-8db6-4f4d-bfbc-5c5944e276d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115277873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1115277873
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3466311644
Short name T854
Test name
Test status
Simulation time 45063057 ps
CPU time 0.99 seconds
Started Jul 13 06:33:18 PM PDT 24
Finished Jul 13 06:33:19 PM PDT 24
Peak memory 212100 kb
Host smart-2a219845-963f-434a-a359-b401f09117f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466311644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3466311644
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2050005371
Short name T416
Test name
Test status
Simulation time 361271835 ps
CPU time 36.9 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:57 PM PDT 24
Peak memory 250920 kb
Host smart-3a316833-c962-4e87-95a1-3b538bf64541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050005371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2050005371
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.754459712
Short name T475
Test name
Test status
Simulation time 51056919 ps
CPU time 7.68 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:36 PM PDT 24
Peak memory 242784 kb
Host smart-f476c765-f74e-4d18-a623-6c213f918c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754459712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.754459712
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.251020187
Short name T781
Test name
Test status
Simulation time 2929174182 ps
CPU time 85.88 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:34:46 PM PDT 24
Peak memory 283704 kb
Host smart-d03e728c-d96b-4dc3-ab24-0a6bd234613d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251020187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.251020187
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2174871556
Short name T165
Test name
Test status
Simulation time 76850323670 ps
CPU time 598.48 seconds
Started Jul 13 06:33:28 PM PDT 24
Finished Jul 13 06:43:28 PM PDT 24
Peak memory 373304 kb
Host smart-a4864ac6-996c-4060-bca5-fe8cd3ed0a7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2174871556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2174871556
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4136018756
Short name T771
Test name
Test status
Simulation time 45957520 ps
CPU time 0.9 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:21 PM PDT 24
Peak memory 211804 kb
Host smart-a88e130e-9a44-4e22-bd45-31180994b729
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136018756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4136018756
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3682769785
Short name T264
Test name
Test status
Simulation time 40342942 ps
CPU time 0.84 seconds
Started Jul 13 06:33:21 PM PDT 24
Finished Jul 13 06:33:23 PM PDT 24
Peak memory 208956 kb
Host smart-f09ec5ae-8905-4ae2-975d-8ad369ad441c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682769785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3682769785
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1284741630
Short name T239
Test name
Test status
Simulation time 2419946035 ps
CPU time 15.58 seconds
Started Jul 13 06:33:24 PM PDT 24
Finished Jul 13 06:33:41 PM PDT 24
Peak memory 218820 kb
Host smart-9471ab93-401a-4ca8-9176-c049838e2bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284741630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1284741630
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2055929522
Short name T402
Test name
Test status
Simulation time 4877715317 ps
CPU time 28.51 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:49 PM PDT 24
Peak memory 217716 kb
Host smart-72d3f2d4-d666-431d-ac14-60851fb89c31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055929522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2055929522
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3536061277
Short name T453
Test name
Test status
Simulation time 302475396 ps
CPU time 2.82 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:24 PM PDT 24
Peak memory 218152 kb
Host smart-ccc0c280-51d4-4ddd-9cdd-b4e2f4d99841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536061277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3536061277
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.211582059
Short name T844
Test name
Test status
Simulation time 193450908 ps
CPU time 9.17 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 225900 kb
Host smart-c52660d7-2fdc-4d2e-a49e-44fe53c0712a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211582059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.211582059
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2084701300
Short name T240
Test name
Test status
Simulation time 309917274 ps
CPU time 8.13 seconds
Started Jul 13 06:33:24 PM PDT 24
Finished Jul 13 06:33:33 PM PDT 24
Peak memory 218104 kb
Host smart-3e7a9f1f-c895-414a-a182-ed156eb8c245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084701300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2084701300
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2117605752
Short name T554
Test name
Test status
Simulation time 1720599547 ps
CPU time 14.4 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:35 PM PDT 24
Peak memory 218196 kb
Host smart-b46fbed0-e44d-4786-aeb6-1ac47a59dde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117605752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2117605752
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2927117472
Short name T805
Test name
Test status
Simulation time 115464901 ps
CPU time 1.77 seconds
Started Jul 13 06:33:24 PM PDT 24
Finished Jul 13 06:33:27 PM PDT 24
Peak memory 217584 kb
Host smart-9a082928-7300-436e-bcfa-32586a282dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927117472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2927117472
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2196908475
Short name T455
Test name
Test status
Simulation time 458858697 ps
CPU time 25.86 seconds
Started Jul 13 06:33:21 PM PDT 24
Finished Jul 13 06:33:48 PM PDT 24
Peak memory 250704 kb
Host smart-67367208-be89-4b05-bc2a-78d998c644ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196908475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2196908475
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.703457156
Short name T86
Test name
Test status
Simulation time 64763812 ps
CPU time 6.2 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:27 PM PDT 24
Peak memory 246180 kb
Host smart-c583936c-079b-45c0-a0d7-e5bee00b139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703457156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.703457156
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2598802381
Short name T204
Test name
Test status
Simulation time 5631317116 ps
CPU time 194.54 seconds
Started Jul 13 06:33:21 PM PDT 24
Finished Jul 13 06:36:37 PM PDT 24
Peak memory 267188 kb
Host smart-d97bbcda-6de0-4cb0-9266-3ba1fd727f20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598802381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2598802381
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3488823387
Short name T789
Test name
Test status
Simulation time 7792753172 ps
CPU time 269.42 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:37:58 PM PDT 24
Peak memory 276448 kb
Host smart-2334c593-8a95-4b3e-887c-701a2be82302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3488823387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3488823387
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3420124279
Short name T509
Test name
Test status
Simulation time 11243684 ps
CPU time 1.04 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:23 PM PDT 24
Peak memory 211712 kb
Host smart-96dce410-4670-462c-8ccb-21793af17431
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420124279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3420124279
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.427024841
Short name T410
Test name
Test status
Simulation time 63334272 ps
CPU time 1.12 seconds
Started Jul 13 06:31:13 PM PDT 24
Finished Jul 13 06:31:15 PM PDT 24
Peak memory 208900 kb
Host smart-75440ed4-2649-49b6-9661-19aac73b3783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427024841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.427024841
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3528027111
Short name T115
Test name
Test status
Simulation time 577710391 ps
CPU time 10.66 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:28 PM PDT 24
Peak memory 226272 kb
Host smart-83d0b281-cf45-4252-809b-bcf92fdc2e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528027111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3528027111
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2065781041
Short name T183
Test name
Test status
Simulation time 748858705 ps
CPU time 19.91 seconds
Started Jul 13 06:31:15 PM PDT 24
Finished Jul 13 06:31:35 PM PDT 24
Peak memory 217420 kb
Host smart-8b93c539-0de3-4d13-802a-7cc651303dbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065781041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2065781041
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.447732833
Short name T571
Test name
Test status
Simulation time 6490470484 ps
CPU time 32.33 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:49 PM PDT 24
Peak memory 218868 kb
Host smart-1fcae538-d3d5-46a2-a7bf-bc77b621c98c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447732833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.447732833
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1816006239
Short name T326
Test name
Test status
Simulation time 170230414 ps
CPU time 5.3 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:28 PM PDT 24
Peak memory 217580 kb
Host smart-561530e3-c56a-421d-af0b-b66fc1490531
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816006239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
816006239
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.433922317
Short name T405
Test name
Test status
Simulation time 786982806 ps
CPU time 5.66 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:28 PM PDT 24
Peak memory 218164 kb
Host smart-5421e370-52bc-4496-8e8c-c19b1bfeb7dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433922317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.433922317
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1325186340
Short name T77
Test name
Test status
Simulation time 739435229 ps
CPU time 13.03 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:34 PM PDT 24
Peak memory 217664 kb
Host smart-22a7fed4-b25c-4029-9007-eae4455bc6dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325186340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1325186340
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3076110426
Short name T113
Test name
Test status
Simulation time 148352846 ps
CPU time 4.01 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:22 PM PDT 24
Peak memory 217876 kb
Host smart-ff3b8417-e212-4ad3-a023-2cba967dcac7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076110426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3076110426
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1029783576
Short name T740
Test name
Test status
Simulation time 9052765196 ps
CPU time 90.69 seconds
Started Jul 13 06:31:18 PM PDT 24
Finished Jul 13 06:32:50 PM PDT 24
Peak memory 267480 kb
Host smart-58cb6c3b-9265-47b8-9ac8-060a5e624105
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029783576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1029783576
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.6187328
Short name T502
Test name
Test status
Simulation time 3363756493 ps
CPU time 19.29 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:37 PM PDT 24
Peak memory 250872 kb
Host smart-2c26df39-1e77-4944-8b45-3a07c32d26b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6187328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_post_trans.6187328
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3738985533
Short name T826
Test name
Test status
Simulation time 363933340 ps
CPU time 3.57 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 218084 kb
Host smart-8b87abc7-0c6d-4ece-9863-60ca24bd61f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738985533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3738985533
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1440954829
Short name T74
Test name
Test status
Simulation time 773663867 ps
CPU time 22.17 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:40 PM PDT 24
Peak memory 217944 kb
Host smart-89f15748-3fdc-491b-a16d-7399eff59eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440954829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1440954829
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1019787031
Short name T87
Test name
Test status
Simulation time 299492388 ps
CPU time 24.61 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:46 PM PDT 24
Peak memory 284284 kb
Host smart-73be9809-3c7c-4140-9c04-9ff38d0eb2cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019787031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1019787031
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.4144327053
Short name T827
Test name
Test status
Simulation time 717150052 ps
CPU time 13.87 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:31:34 PM PDT 24
Peak memory 225972 kb
Host smart-124ea440-5911-4b5c-977b-08f79824f35d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144327053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.4144327053
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3549751204
Short name T837
Test name
Test status
Simulation time 207176808 ps
CPU time 10.33 seconds
Started Jul 13 06:31:18 PM PDT 24
Finished Jul 13 06:31:30 PM PDT 24
Peak memory 218132 kb
Host smart-727ab4fe-e85f-40c0-8501-ef2327627ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549751204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3549751204
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2250025167
Short name T836
Test name
Test status
Simulation time 3042976449 ps
CPU time 10.6 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:32 PM PDT 24
Peak memory 225884 kb
Host smart-713362c7-6e31-4820-8030-4091a47b7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250025167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2250025167
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2640531907
Short name T375
Test name
Test status
Simulation time 205648042 ps
CPU time 2.74 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 217580 kb
Host smart-b5660193-343a-4252-bef5-48037e8d872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640531907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2640531907
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1028351802
Short name T325
Test name
Test status
Simulation time 721487182 ps
CPU time 29.36 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:52 PM PDT 24
Peak memory 250920 kb
Host smart-6cc11267-9fe4-4393-becb-4eb1dd81e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028351802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1028351802
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.68082761
Short name T528
Test name
Test status
Simulation time 343570479 ps
CPU time 6.42 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 247136 kb
Host smart-7659e74a-626d-4aea-896a-844a01e5f7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68082761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.68082761
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.67459788
Short name T705
Test name
Test status
Simulation time 80631981 ps
CPU time 0.94 seconds
Started Jul 13 06:31:15 PM PDT 24
Finished Jul 13 06:31:17 PM PDT 24
Peak memory 211768 kb
Host smart-79f628ac-e902-4e41-b8de-5eed4462928d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67459788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_volatile_unlock_smoke.67459788
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1950153360
Short name T592
Test name
Test status
Simulation time 32413389 ps
CPU time 0.89 seconds
Started Jul 13 06:33:26 PM PDT 24
Finished Jul 13 06:33:28 PM PDT 24
Peak memory 208664 kb
Host smart-0756f489-6304-4f5a-a9c4-4132036c0715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950153360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1950153360
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1220374072
Short name T855
Test name
Test status
Simulation time 800230160 ps
CPU time 12.34 seconds
Started Jul 13 06:33:19 PM PDT 24
Finished Jul 13 06:33:33 PM PDT 24
Peak memory 225916 kb
Host smart-29f99dd3-6518-44a3-93f0-9bb011362f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220374072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1220374072
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.229356551
Short name T813
Test name
Test status
Simulation time 977419986 ps
CPU time 6.22 seconds
Started Jul 13 06:33:28 PM PDT 24
Finished Jul 13 06:33:35 PM PDT 24
Peak memory 217356 kb
Host smart-1ffcc9cf-5db0-455d-b9a6-a3d98e4f7fd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229356551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.229356551
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1535604872
Short name T658
Test name
Test status
Simulation time 158484854 ps
CPU time 1.66 seconds
Started Jul 13 06:33:24 PM PDT 24
Finished Jul 13 06:33:27 PM PDT 24
Peak memory 218084 kb
Host smart-874eaaa6-4e75-424d-9657-eadf543188e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535604872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1535604872
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2662483675
Short name T710
Test name
Test status
Simulation time 1534686303 ps
CPU time 12.14 seconds
Started Jul 13 06:33:25 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 225908 kb
Host smart-347dff09-786e-471b-b84e-484997e1a349
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662483675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2662483675
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2971696259
Short name T181
Test name
Test status
Simulation time 338875993 ps
CPU time 8.12 seconds
Started Jul 13 06:33:38 PM PDT 24
Finished Jul 13 06:33:48 PM PDT 24
Peak memory 218116 kb
Host smart-4b3d089e-db1c-4f14-b2c0-0bd378cc0494
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971696259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2971696259
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.739931256
Short name T533
Test name
Test status
Simulation time 430487946 ps
CPU time 11.99 seconds
Started Jul 13 06:33:31 PM PDT 24
Finished Jul 13 06:33:44 PM PDT 24
Peak memory 218224 kb
Host smart-2476a6eb-ab75-4ce3-b98d-4b1530fd4c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739931256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.739931256
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3468700789
Short name T553
Test name
Test status
Simulation time 19828554 ps
CPU time 1.18 seconds
Started Jul 13 06:33:18 PM PDT 24
Finished Jul 13 06:33:20 PM PDT 24
Peak memory 213628 kb
Host smart-1c31e688-6085-4c08-b167-1fc3e5c42468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468700789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3468700789
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.501890401
Short name T852
Test name
Test status
Simulation time 426060033 ps
CPU time 22.1 seconds
Started Jul 13 06:33:21 PM PDT 24
Finished Jul 13 06:33:44 PM PDT 24
Peak memory 250844 kb
Host smart-dfc8a38c-e972-4392-81f8-7d9d3dc16a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501890401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.501890401
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1549121614
Short name T35
Test name
Test status
Simulation time 250556262 ps
CPU time 10.2 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:31 PM PDT 24
Peak memory 250984 kb
Host smart-4fce6f0a-4f99-4aaf-a062-53c484d9da1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549121614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1549121614
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3975357475
Short name T589
Test name
Test status
Simulation time 6730975513 ps
CPU time 220.96 seconds
Started Jul 13 06:33:30 PM PDT 24
Finished Jul 13 06:37:11 PM PDT 24
Peak memory 253328 kb
Host smart-89d9cfb3-46b1-4add-93a5-23426e2c421e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975357475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3975357475
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1638326308
Short name T186
Test name
Test status
Simulation time 27632309567 ps
CPU time 287.31 seconds
Started Jul 13 06:33:40 PM PDT 24
Finished Jul 13 06:38:28 PM PDT 24
Peak memory 283800 kb
Host smart-cc06565e-24d5-46a5-be97-87f8136f6ff7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1638326308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1638326308
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.387756
Short name T329
Test name
Test status
Simulation time 24627813 ps
CPU time 0.9 seconds
Started Jul 13 06:33:20 PM PDT 24
Finished Jul 13 06:33:22 PM PDT 24
Peak memory 211856 kb
Host smart-7dc10f41-b2ea-49ec-8d9f-67176d76e530
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volat
ile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_
volatile_unlock_smoke.387756
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1385638313
Short name T371
Test name
Test status
Simulation time 32945313 ps
CPU time 0.89 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:31 PM PDT 24
Peak memory 208852 kb
Host smart-0c45cc90-5e34-487b-9abe-dd447f730197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385638313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1385638313
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2210743778
Short name T713
Test name
Test status
Simulation time 538581582 ps
CPU time 16 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:44 PM PDT 24
Peak memory 225988 kb
Host smart-1286d4ed-d5f1-4301-97c0-4d213398f30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210743778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2210743778
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2704845226
Short name T497
Test name
Test status
Simulation time 282973661 ps
CPU time 4.06 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:34 PM PDT 24
Peak memory 216876 kb
Host smart-f36de7cb-3ffd-42aa-a5aa-ec2131333c08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704845226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2704845226
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.380645651
Short name T282
Test name
Test status
Simulation time 261100858 ps
CPU time 3.58 seconds
Started Jul 13 06:33:38 PM PDT 24
Finished Jul 13 06:33:43 PM PDT 24
Peak memory 222176 kb
Host smart-e4e3fe12-4066-44ed-b375-4ea220c57dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380645651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.380645651
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3401407699
Short name T56
Test name
Test status
Simulation time 281987491 ps
CPU time 9.4 seconds
Started Jul 13 06:33:26 PM PDT 24
Finished Jul 13 06:33:37 PM PDT 24
Peak memory 225988 kb
Host smart-96c8749a-18a7-43a0-abd5-8ce4a6591d19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401407699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3401407699
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2181749959
Short name T336
Test name
Test status
Simulation time 1694790784 ps
CPU time 12.1 seconds
Started Jul 13 06:33:25 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 225968 kb
Host smart-92d1c0a9-b673-43ad-a784-10a1e362bd8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181749959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2181749959
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2692967774
Short name T712
Test name
Test status
Simulation time 270000468 ps
CPU time 7.24 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:35 PM PDT 24
Peak memory 218208 kb
Host smart-2a1eb376-42d3-4a0d-8fb6-2ead94ffa804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692967774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2692967774
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2066661139
Short name T377
Test name
Test status
Simulation time 226506482 ps
CPU time 9.05 seconds
Started Jul 13 06:33:28 PM PDT 24
Finished Jul 13 06:33:39 PM PDT 24
Peak memory 218156 kb
Host smart-a5f5efae-7827-4b45-8389-407dfe176bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066661139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2066661139
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.584416927
Short name T782
Test name
Test status
Simulation time 318152291 ps
CPU time 6.71 seconds
Started Jul 13 06:33:26 PM PDT 24
Finished Jul 13 06:33:33 PM PDT 24
Peak memory 217664 kb
Host smart-fcc3a952-4324-4561-a52f-5babbb1c39f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584416927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.584416927
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3060741187
Short name T845
Test name
Test status
Simulation time 1360432155 ps
CPU time 24.17 seconds
Started Jul 13 06:33:28 PM PDT 24
Finished Jul 13 06:33:54 PM PDT 24
Peak memory 250896 kb
Host smart-5477e272-0f85-4cc4-bd99-d4bb2c7a66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060741187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3060741187
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1591163250
Short name T446
Test name
Test status
Simulation time 295595777 ps
CPU time 7.65 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:36 PM PDT 24
Peak memory 250944 kb
Host smart-1142b0d0-7797-45c9-875b-8ac7a1ce3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591163250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1591163250
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.252976112
Short name T568
Test name
Test status
Simulation time 8926195667 ps
CPU time 92.49 seconds
Started Jul 13 06:33:30 PM PDT 24
Finished Jul 13 06:35:03 PM PDT 24
Peak memory 226264 kb
Host smart-6ce53f88-19e0-404f-a8de-8823c01d1dca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252976112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.252976112
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1249289660
Short name T846
Test name
Test status
Simulation time 12878733 ps
CPU time 0.95 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 211816 kb
Host smart-32ba7d28-abb6-46a6-924f-b7478718f4e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249289660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1249289660
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3544862306
Short name T90
Test name
Test status
Simulation time 16586970 ps
CPU time 1.1 seconds
Started Jul 13 06:33:25 PM PDT 24
Finished Jul 13 06:33:27 PM PDT 24
Peak memory 208832 kb
Host smart-04e50ea2-2735-4bb1-a25e-227cc1c90065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544862306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3544862306
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2976894533
Short name T546
Test name
Test status
Simulation time 3517565810 ps
CPU time 20.99 seconds
Started Jul 13 06:33:28 PM PDT 24
Finished Jul 13 06:33:50 PM PDT 24
Peak memory 218900 kb
Host smart-ff23bfbf-fcdc-4b72-a93c-854f9aa9fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976894533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2976894533
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1762660962
Short name T861
Test name
Test status
Simulation time 971228194 ps
CPU time 6.17 seconds
Started Jul 13 06:33:26 PM PDT 24
Finished Jul 13 06:33:33 PM PDT 24
Peak memory 217624 kb
Host smart-0126d8c9-da9b-4135-9556-d1b9815241a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762660962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1762660962
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2479665418
Short name T241
Test name
Test status
Simulation time 68752521 ps
CPU time 1.54 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:32 PM PDT 24
Peak memory 218152 kb
Host smart-0c942ff7-cf2a-4b5b-90fc-bce8f5fef7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479665418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2479665418
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2246894315
Short name T432
Test name
Test status
Simulation time 1859255821 ps
CPU time 16.72 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:45 PM PDT 24
Peak memory 225960 kb
Host smart-11cfc166-df0d-435e-8448-645a853b7dee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246894315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2246894315
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3752741380
Short name T601
Test name
Test status
Simulation time 388535657 ps
CPU time 8.47 seconds
Started Jul 13 06:33:25 PM PDT 24
Finished Jul 13 06:33:34 PM PDT 24
Peak memory 218160 kb
Host smart-f9a3e2a0-ee76-46f6-bbfc-9305f209892e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752741380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3752741380
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2798521803
Short name T317
Test name
Test status
Simulation time 364733627 ps
CPU time 10.66 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:39 PM PDT 24
Peak memory 224600 kb
Host smart-f907c90d-0ea0-416e-a95a-78235d8362f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798521803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2798521803
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.333410365
Short name T59
Test name
Test status
Simulation time 220118722 ps
CPU time 6.27 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:34 PM PDT 24
Peak memory 217652 kb
Host smart-fefd0d26-4b67-470b-b177-01c569ebc97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333410365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.333410365
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2875552287
Short name T458
Test name
Test status
Simulation time 1038120815 ps
CPU time 33.22 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 250836 kb
Host smart-9b72e37d-e567-481b-ae68-04f911b74bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875552287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2875552287
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3721004844
Short name T759
Test name
Test status
Simulation time 207466662 ps
CPU time 7.89 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 247120 kb
Host smart-68416f53-237d-4628-b2c0-210fc4f66ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721004844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3721004844
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2951867987
Short name T474
Test name
Test status
Simulation time 17281760190 ps
CPU time 69.88 seconds
Started Jul 13 06:33:31 PM PDT 24
Finished Jul 13 06:34:42 PM PDT 24
Peak memory 226024 kb
Host smart-1b154ff9-85df-41e8-acce-e744520ab8eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951867987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2951867987
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.959079765
Short name T14
Test name
Test status
Simulation time 59667976495 ps
CPU time 339.51 seconds
Started Jul 13 06:33:30 PM PDT 24
Finished Jul 13 06:39:10 PM PDT 24
Peak memory 496728 kb
Host smart-de1a43a3-8311-4146-a28a-7349719158a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=959079765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.959079765
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.557681098
Short name T746
Test name
Test status
Simulation time 16316685 ps
CPU time 1.04 seconds
Started Jul 13 06:33:27 PM PDT 24
Finished Jul 13 06:33:29 PM PDT 24
Peak memory 213056 kb
Host smart-748caf3f-7960-4b37-b77a-88fd8f6850f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557681098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.557681098
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3652753829
Short name T655
Test name
Test status
Simulation time 43543087 ps
CPU time 0.95 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:40 PM PDT 24
Peak memory 208928 kb
Host smart-476c1dea-6c25-4d60-b2e5-96b162390274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652753829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3652753829
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4264568352
Short name T694
Test name
Test status
Simulation time 285737742 ps
CPU time 14.09 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:44 PM PDT 24
Peak memory 218092 kb
Host smart-cb13a2d5-fa03-4416-b29f-0601232fdba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264568352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4264568352
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.769175315
Short name T780
Test name
Test status
Simulation time 168034327 ps
CPU time 2.57 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:33 PM PDT 24
Peak memory 216972 kb
Host smart-18736914-b54d-43d7-8229-4ddda041ad63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769175315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.769175315
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.36409063
Short name T704
Test name
Test status
Simulation time 60615771 ps
CPU time 3.13 seconds
Started Jul 13 06:33:40 PM PDT 24
Finished Jul 13 06:33:44 PM PDT 24
Peak memory 222304 kb
Host smart-f4f14afb-bda3-48ff-92fd-77f70e2b32fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36409063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.36409063
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.200513085
Short name T779
Test name
Test status
Simulation time 1104926325 ps
CPU time 13.15 seconds
Started Jul 13 06:33:39 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 225900 kb
Host smart-9c261771-5024-4514-965f-fdca7aa66f1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200513085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.200513085
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.445192271
Short name T557
Test name
Test status
Simulation time 2998479238 ps
CPU time 12.85 seconds
Started Jul 13 06:33:38 PM PDT 24
Finished Jul 13 06:33:52 PM PDT 24
Peak memory 226044 kb
Host smart-a7203a35-afcd-455a-b9f8-0567bcd19a30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445192271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.445192271
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2637132055
Short name T615
Test name
Test status
Simulation time 1453247244 ps
CPU time 13.34 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:50 PM PDT 24
Peak memory 218168 kb
Host smart-15745e87-0b2f-4704-9b78-e6fc6776118a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637132055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2637132055
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2280183573
Short name T251
Test name
Test status
Simulation time 233067218 ps
CPU time 7.84 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 218268 kb
Host smart-931b434c-ea0f-481a-9320-87f52b24eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280183573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2280183573
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2610479772
Short name T346
Test name
Test status
Simulation time 127685643 ps
CPU time 2.4 seconds
Started Jul 13 06:33:39 PM PDT 24
Finished Jul 13 06:33:42 PM PDT 24
Peak memory 217580 kb
Host smart-1c909462-0ebc-4280-8628-2bb80732a311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610479772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2610479772
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.66437304
Short name T95
Test name
Test status
Simulation time 235071210 ps
CPU time 25.72 seconds
Started Jul 13 06:33:26 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 250916 kb
Host smart-cb43daf3-a51b-4566-81db-19e214d1844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66437304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.66437304
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1950406310
Short name T804
Test name
Test status
Simulation time 278413685 ps
CPU time 6.95 seconds
Started Jul 13 06:33:31 PM PDT 24
Finished Jul 13 06:33:39 PM PDT 24
Peak memory 250476 kb
Host smart-4cecd43d-24df-475b-b82b-ab0cff03f83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950406310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1950406310
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1806497499
Short name T856
Test name
Test status
Simulation time 5845177054 ps
CPU time 52.23 seconds
Started Jul 13 06:33:38 PM PDT 24
Finished Jul 13 06:34:32 PM PDT 24
Peak memory 242776 kb
Host smart-097ca4fd-a0eb-479f-8080-38e44affcd01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806497499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1806497499
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2786035903
Short name T274
Test name
Test status
Simulation time 40394568 ps
CPU time 0.96 seconds
Started Jul 13 06:33:29 PM PDT 24
Finished Jul 13 06:33:31 PM PDT 24
Peak memory 211872 kb
Host smart-f695a6f7-34f7-4417-8964-e29c453eff86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786035903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2786035903
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.540333242
Short name T354
Test name
Test status
Simulation time 176971803 ps
CPU time 8.11 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:46 PM PDT 24
Peak memory 226004 kb
Host smart-04f1b7c2-5511-41cc-8ef4-1d3733be48ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540333242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.540333242
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1545091289
Short name T27
Test name
Test status
Simulation time 1745749489 ps
CPU time 9.44 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:49 PM PDT 24
Peak memory 217244 kb
Host smart-f5844868-b670-4c9d-91ee-1a60ecb606c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545091289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1545091289
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2470892970
Short name T758
Test name
Test status
Simulation time 125297988 ps
CPU time 2.54 seconds
Started Jul 13 06:33:35 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 218168 kb
Host smart-4a195eaf-77a9-4282-a61b-713364773c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470892970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2470892970
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1603293322
Short name T569
Test name
Test status
Simulation time 1144426140 ps
CPU time 18.21 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:55 PM PDT 24
Peak memory 225944 kb
Host smart-60d9ee1b-88ee-44f4-b13e-b5695bbe272c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603293322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1603293322
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2105601203
Short name T187
Test name
Test status
Simulation time 956533106 ps
CPU time 9.58 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:47 PM PDT 24
Peak memory 225968 kb
Host smart-2a781450-b7ea-4591-9b14-40e56d9bfc18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105601203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2105601203
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.45428632
Short name T641
Test name
Test status
Simulation time 1805212767 ps
CPU time 15.31 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 218104 kb
Host smart-8d40e216-9753-4168-9d53-5cb5c7ff1432
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45428632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.45428632
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2607308297
Short name T614
Test name
Test status
Simulation time 420215358 ps
CPU time 6.25 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:45 PM PDT 24
Peak memory 224768 kb
Host smart-2e9912d8-7119-4532-a7bf-e6783b9a811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607308297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2607308297
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3534806206
Short name T364
Test name
Test status
Simulation time 38505333 ps
CPU time 2.97 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:42 PM PDT 24
Peak memory 214548 kb
Host smart-957acdc5-f107-44e5-9886-29f4df757d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534806206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3534806206
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2920980493
Short name T333
Test name
Test status
Simulation time 179804074 ps
CPU time 18.15 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:58 PM PDT 24
Peak memory 250768 kb
Host smart-95affe25-956f-4d3c-9613-cf0afacc97b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920980493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2920980493
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.130973539
Short name T604
Test name
Test status
Simulation time 640841051 ps
CPU time 6.21 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:45 PM PDT 24
Peak memory 247108 kb
Host smart-e2022c62-3b77-4891-94bc-a77ea2ffb676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130973539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.130973539
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3327488929
Short name T68
Test name
Test status
Simulation time 4111825344 ps
CPU time 129.6 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:35:48 PM PDT 24
Peak memory 251024 kb
Host smart-afd36c64-2e13-4311-96b8-63430ac73f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327488929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3327488929
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1676556493
Short name T853
Test name
Test status
Simulation time 74413267 ps
CPU time 0.9 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:39 PM PDT 24
Peak memory 212908 kb
Host smart-d274d46e-e47c-43a6-aafb-52439ac333b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676556493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1676556493
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.179743199
Short name T808
Test name
Test status
Simulation time 23162369 ps
CPU time 0.95 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:39 PM PDT 24
Peak memory 208836 kb
Host smart-ae6aa33d-0eed-443b-a22a-f587592e9062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179743199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.179743199
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.581266192
Short name T464
Test name
Test status
Simulation time 902905265 ps
CPU time 9.07 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:49 PM PDT 24
Peak memory 218128 kb
Host smart-889e6591-3e0c-43e7-b019-448f6138c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581266192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.581266192
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.948057661
Short name T555
Test name
Test status
Simulation time 97402823 ps
CPU time 1.87 seconds
Started Jul 13 06:33:35 PM PDT 24
Finished Jul 13 06:33:37 PM PDT 24
Peak memory 216948 kb
Host smart-f0c6154d-cd86-474d-9e44-80ac27db31fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948057661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.948057661
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3002266581
Short name T741
Test name
Test status
Simulation time 41130881 ps
CPU time 2.11 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:39 PM PDT 24
Peak memory 218172 kb
Host smart-e21cccb1-8722-4157-9ab4-8bd66e39fcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002266581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3002266581
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3297934452
Short name T392
Test name
Test status
Simulation time 1436440125 ps
CPU time 16.7 seconds
Started Jul 13 06:33:35 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 218764 kb
Host smart-12dca0aa-1170-4036-9446-283a8ac491b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297934452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3297934452
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.962657732
Short name T425
Test name
Test status
Simulation time 497505498 ps
CPU time 7.86 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:47 PM PDT 24
Peak memory 225976 kb
Host smart-605aabf8-e407-40d1-8927-5662ccaba2e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962657732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.962657732
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.537495295
Short name T825
Test name
Test status
Simulation time 1966112989 ps
CPU time 14.26 seconds
Started Jul 13 06:33:38 PM PDT 24
Finished Jul 13 06:33:54 PM PDT 24
Peak memory 225464 kb
Host smart-722f1e19-cf21-4c9a-8a9b-4001961044ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537495295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.537495295
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3953435197
Short name T52
Test name
Test status
Simulation time 874501189 ps
CPU time 8.78 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:46 PM PDT 24
Peak memory 225932 kb
Host smart-dcb14d80-fe8c-4652-ba3a-f8a36f103d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953435197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3953435197
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.219507786
Short name T387
Test name
Test status
Simulation time 156550573 ps
CPU time 4.12 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:43 PM PDT 24
Peak memory 217648 kb
Host smart-9e772131-d557-49ed-86ee-881e4e24635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219507786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.219507786
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3674794087
Short name T572
Test name
Test status
Simulation time 291905952 ps
CPU time 24.89 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:34:04 PM PDT 24
Peak memory 250908 kb
Host smart-f9a8ec9f-2fa4-4ba3-9897-9ed81c40ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674794087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3674794087
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.448202447
Short name T784
Test name
Test status
Simulation time 116952438 ps
CPU time 5.48 seconds
Started Jul 13 06:33:35 PM PDT 24
Finished Jul 13 06:33:41 PM PDT 24
Peak memory 226344 kb
Host smart-1c5f47a3-db16-4880-be13-823f0440a251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448202447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.448202447
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1854882684
Short name T486
Test name
Test status
Simulation time 4485193611 ps
CPU time 36.89 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:34:14 PM PDT 24
Peak memory 251004 kb
Host smart-9d1c5064-a664-46a3-99ca-425a4f5d39ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854882684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1854882684
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1916531880
Short name T799
Test name
Test status
Simulation time 13750946 ps
CPU time 1.06 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:33:41 PM PDT 24
Peak memory 211828 kb
Host smart-743ee1a4-9263-4d70-a44f-a3f6a6575e57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916531880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1916531880
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.781067488
Short name T420
Test name
Test status
Simulation time 67878296 ps
CPU time 0.92 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:33:52 PM PDT 24
Peak memory 208988 kb
Host smart-57c3d370-754a-46ba-81a7-1df63997bb83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781067488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.781067488
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1773416332
Short name T550
Test name
Test status
Simulation time 1611696311 ps
CPU time 15.48 seconds
Started Jul 13 06:33:51 PM PDT 24
Finished Jul 13 06:34:08 PM PDT 24
Peak memory 225940 kb
Host smart-8647f5b0-b291-45d1-b7fc-4d8ea8139d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773416332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1773416332
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2488934984
Short name T342
Test name
Test status
Simulation time 54522351 ps
CPU time 2.06 seconds
Started Jul 13 06:33:46 PM PDT 24
Finished Jul 13 06:33:49 PM PDT 24
Peak memory 216904 kb
Host smart-e19d7ef3-9f79-41db-9ea6-97606924703e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488934984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2488934984
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2342000559
Short name T521
Test name
Test status
Simulation time 190702694 ps
CPU time 4.67 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:33:54 PM PDT 24
Peak memory 218168 kb
Host smart-0b9518a5-45b3-48cd-9bb9-c4b6bc16bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342000559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2342000559
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3270838643
Short name T839
Test name
Test status
Simulation time 836636805 ps
CPU time 11.6 seconds
Started Jul 13 06:33:47 PM PDT 24
Finished Jul 13 06:33:59 PM PDT 24
Peak memory 225896 kb
Host smart-e59bbaa6-37d9-4480-9f7a-9afea0342f27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270838643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3270838643
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2599318556
Short name T651
Test name
Test status
Simulation time 801703982 ps
CPU time 10.84 seconds
Started Jul 13 06:33:52 PM PDT 24
Finished Jul 13 06:34:04 PM PDT 24
Peak memory 218172 kb
Host smart-3873f458-15fa-47c0-a3e1-9db3dee2ffd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599318556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2599318556
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3892522318
Short name T117
Test name
Test status
Simulation time 226662128 ps
CPU time 10.21 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 225908 kb
Host smart-bf28a8ca-7cca-4e80-8556-fe8b1f0cdc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892522318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3892522318
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2318248532
Short name T320
Test name
Test status
Simulation time 223027360 ps
CPU time 3.63 seconds
Started Jul 13 06:33:41 PM PDT 24
Finished Jul 13 06:33:45 PM PDT 24
Peak memory 217580 kb
Host smart-fd37dcba-2d94-487e-aa7f-fa0ec58d986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318248532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2318248532
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3186588564
Short name T253
Test name
Test status
Simulation time 1373128410 ps
CPU time 37.58 seconds
Started Jul 13 06:33:37 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 250912 kb
Host smart-34b65fcc-9229-46b8-9be2-84aa90701891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186588564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3186588564
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2433962884
Short name T598
Test name
Test status
Simulation time 63031160 ps
CPU time 6.54 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:33:55 PM PDT 24
Peak memory 242724 kb
Host smart-dfdefab5-5946-4c4e-90c9-eb0832df9129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433962884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2433962884
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1608209172
Short name T223
Test name
Test status
Simulation time 69609942028 ps
CPU time 146.51 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:36:16 PM PDT 24
Peak memory 276620 kb
Host smart-17c59b4a-6201-4c4b-8300-fa4b98b6691a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608209172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1608209172
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1238197903
Short name T429
Test name
Test status
Simulation time 14622510 ps
CPU time 0.94 seconds
Started Jul 13 06:33:36 PM PDT 24
Finished Jul 13 06:33:38 PM PDT 24
Peak memory 211824 kb
Host smart-e5701113-93e5-4735-afb4-dc2d71af3089
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238197903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1238197903
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3663358606
Short name T725
Test name
Test status
Simulation time 20750571 ps
CPU time 1.23 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:33:51 PM PDT 24
Peak memory 208908 kb
Host smart-fa192260-e155-42a4-8cfb-7d8baf5f4211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663358606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3663358606
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2901421809
Short name T17
Test name
Test status
Simulation time 541697330 ps
CPU time 17.18 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:34:09 PM PDT 24
Peak memory 218168 kb
Host smart-812fbe1c-6224-4e55-b3a7-bfb245d23ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901421809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2901421809
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2254773161
Short name T640
Test name
Test status
Simulation time 698078293 ps
CPU time 10 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 217388 kb
Host smart-c7bd2338-6779-43fa-b282-b89e12608cc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254773161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2254773161
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2607288991
Short name T706
Test name
Test status
Simulation time 92185095 ps
CPU time 3.12 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:33:54 PM PDT 24
Peak memory 222552 kb
Host smart-e7f4e691-e1e2-4385-9301-444995b82334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607288991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2607288991
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3962352158
Short name T816
Test name
Test status
Simulation time 293629650 ps
CPU time 15.54 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 225968 kb
Host smart-0df6a67b-acb5-4d99-9615-b6d64f721e65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962352158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3962352158
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3076395007
Short name T507
Test name
Test status
Simulation time 751792930 ps
CPU time 11.29 seconds
Started Jul 13 06:33:51 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 226004 kb
Host smart-85ad94e6-bc74-4c0e-bbdb-420a81d60c8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076395007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3076395007
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2897733970
Short name T421
Test name
Test status
Simulation time 1799946523 ps
CPU time 9.64 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:33:59 PM PDT 24
Peak memory 218488 kb
Host smart-03ce018d-cffb-4264-be44-14eff6111e92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897733970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2897733970
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4169593243
Short name T703
Test name
Test status
Simulation time 271554099 ps
CPU time 11.43 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 225932 kb
Host smart-94bb8b65-28bf-4af2-8b2d-d330363606ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169593243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4169593243
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2347993842
Short name T777
Test name
Test status
Simulation time 608125455 ps
CPU time 3.12 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 217660 kb
Host smart-a325436e-6faa-4c4f-8a4e-f1d800f96c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347993842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2347993842
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.413562604
Short name T842
Test name
Test status
Simulation time 863617708 ps
CPU time 32.45 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:34:22 PM PDT 24
Peak memory 250764 kb
Host smart-1e95118c-1856-43fa-9072-da6f7f66d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413562604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.413562604
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1334058539
Short name T580
Test name
Test status
Simulation time 605819293 ps
CPU time 9.67 seconds
Started Jul 13 06:33:47 PM PDT 24
Finished Jul 13 06:33:57 PM PDT 24
Peak memory 250916 kb
Host smart-62015ad6-86ee-4522-b69e-028120fdf8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334058539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1334058539
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1093924077
Short name T752
Test name
Test status
Simulation time 10790272637 ps
CPU time 165.64 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:36:37 PM PDT 24
Peak memory 250968 kb
Host smart-b6b3941e-6c12-4c6f-bbd2-5e7847276cfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093924077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1093924077
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2970682711
Short name T73
Test name
Test status
Simulation time 29367152462 ps
CPU time 580.61 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:43:31 PM PDT 24
Peak memory 294632 kb
Host smart-2707b2a7-1ae5-4b59-9086-1459c399dd4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2970682711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2970682711
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3565379340
Short name T394
Test name
Test status
Simulation time 15716970 ps
CPU time 0.95 seconds
Started Jul 13 06:33:51 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 217592 kb
Host smart-21781b18-4046-41d7-b615-627dfccdd5d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565379340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3565379340
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2710984105
Short name T66
Test name
Test status
Simulation time 16499254 ps
CPU time 1.12 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:33:52 PM PDT 24
Peak memory 208900 kb
Host smart-c6f37d70-4ad5-42c1-b860-01fc3ffd4ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710984105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2710984105
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2940143785
Short name T716
Test name
Test status
Simulation time 626398467 ps
CPU time 9.89 seconds
Started Jul 13 06:33:52 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 218096 kb
Host smart-9cd00412-6211-4cab-9777-90ac69ff7616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940143785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2940143785
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1722430356
Short name T723
Test name
Test status
Simulation time 1002820504 ps
CPU time 14.59 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:34:06 PM PDT 24
Peak memory 217396 kb
Host smart-733d0929-bcb1-4676-be4b-ea2ab31af13c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722430356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1722430356
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.490108426
Short name T715
Test name
Test status
Simulation time 117215178 ps
CPU time 2.93 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:33:54 PM PDT 24
Peak memory 218168 kb
Host smart-460ad2cd-34c2-41c2-95d8-c3f24246741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490108426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.490108426
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1629040509
Short name T531
Test name
Test status
Simulation time 2645555396 ps
CPU time 13.22 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 225964 kb
Host smart-cba650cc-ae93-4d85-85b8-6c74c048c079
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629040509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1629040509
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1796139507
Short name T696
Test name
Test status
Simulation time 2507713772 ps
CPU time 12.23 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 225968 kb
Host smart-2009743b-4276-4cc9-bcf0-3489fcc9f917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796139507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1796139507
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2129075199
Short name T285
Test name
Test status
Simulation time 3161400215 ps
CPU time 12.74 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 218236 kb
Host smart-b704c6ed-c671-497f-9acb-76003bda7a62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129075199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2129075199
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3700091702
Short name T3
Test name
Test status
Simulation time 1764145383 ps
CPU time 10.15 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:34:01 PM PDT 24
Peak memory 224952 kb
Host smart-31536288-9228-42ad-9665-5df7e0c8f293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700091702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3700091702
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1791279658
Short name T591
Test name
Test status
Simulation time 49687353 ps
CPU time 2.11 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:33:52 PM PDT 24
Peak memory 214596 kb
Host smart-9ec627b6-677c-43fb-a759-a42cb0baee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791279658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1791279658
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.453755971
Short name T530
Test name
Test status
Simulation time 266223133 ps
CPU time 34.17 seconds
Started Jul 13 06:33:50 PM PDT 24
Finished Jul 13 06:34:25 PM PDT 24
Peak memory 250920 kb
Host smart-bd5c4723-ec44-4f22-b5ec-1003ebb40487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453755971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.453755971
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.585962782
Short name T492
Test name
Test status
Simulation time 118935079 ps
CPU time 6.47 seconds
Started Jul 13 06:33:52 PM PDT 24
Finished Jul 13 06:33:59 PM PDT 24
Peak memory 247004 kb
Host smart-03490c0a-e3b0-419a-862e-acbe2dcbfc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585962782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.585962782
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3385685198
Short name T833
Test name
Test status
Simulation time 21050219635 ps
CPU time 538.57 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:42:49 PM PDT 24
Peak memory 226028 kb
Host smart-635c6705-380d-4a30-aaa6-eacfc558e057
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385685198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3385685198
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3180598504
Short name T650
Test name
Test status
Simulation time 14822646 ps
CPU time 0.92 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:33:50 PM PDT 24
Peak memory 211868 kb
Host smart-ec7c4373-1940-4fc9-a34c-3fc94e0240fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180598504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3180598504
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.722595806
Short name T477
Test name
Test status
Simulation time 60383590 ps
CPU time 1.15 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 209036 kb
Host smart-3069c87a-a8e8-4fa5-b3e4-2283f4aa0661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722595806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.722595806
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.592066235
Short name T664
Test name
Test status
Simulation time 188852640 ps
CPU time 8.4 seconds
Started Jul 13 06:33:56 PM PDT 24
Finished Jul 13 06:34:05 PM PDT 24
Peak memory 218100 kb
Host smart-c060f6de-8e76-4f24-9474-fa416c2975bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592066235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.592066235
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2121699316
Short name T848
Test name
Test status
Simulation time 679413290 ps
CPU time 4 seconds
Started Jul 13 06:33:57 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 217132 kb
Host smart-df6e98be-12d4-4ac9-ba64-d4d232bd4a42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121699316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2121699316
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2247413194
Short name T652
Test name
Test status
Simulation time 87549378 ps
CPU time 2.61 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:02 PM PDT 24
Peak memory 218180 kb
Host smart-7edd3fdd-64ef-4317-93c8-2b39541c87fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247413194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2247413194
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1087023550
Short name T523
Test name
Test status
Simulation time 1297803614 ps
CPU time 12.43 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:34:14 PM PDT 24
Peak memory 225900 kb
Host smart-3403e0c0-1af6-4cf4-bb0b-c14c9d9f1e59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087023550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1087023550
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1064656948
Short name T659
Test name
Test status
Simulation time 702857898 ps
CPU time 12.49 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:17 PM PDT 24
Peak memory 218044 kb
Host smart-b5c8f0bf-1239-457b-aa35-13b9b54ab706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064656948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1064656948
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.235248677
Short name T638
Test name
Test status
Simulation time 312136589 ps
CPU time 11.43 seconds
Started Jul 13 06:33:58 PM PDT 24
Finished Jul 13 06:34:11 PM PDT 24
Peak memory 218284 kb
Host smart-fd22b86f-ee97-46b2-ae51-6241b3b286fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235248677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.235248677
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4252818439
Short name T286
Test name
Test status
Simulation time 420911765 ps
CPU time 2.29 seconds
Started Jul 13 06:33:49 PM PDT 24
Finished Jul 13 06:33:53 PM PDT 24
Peak memory 214200 kb
Host smart-c9c386d9-0aaa-42b0-8827-b22dba103c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252818439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4252818439
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2970688214
Short name T665
Test name
Test status
Simulation time 230940419 ps
CPU time 22.28 seconds
Started Jul 13 06:33:48 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 250920 kb
Host smart-13861cf2-1ecc-4dff-acb4-9cac83b460e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970688214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2970688214
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1872267788
Short name T396
Test name
Test status
Simulation time 329661828 ps
CPU time 7.41 seconds
Started Jul 13 06:34:03 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 246672 kb
Host smart-78d41c38-15d2-4909-a072-e58cfda0005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872267788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1872267788
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.914523216
Short name T46
Test name
Test status
Simulation time 15432251364 ps
CPU time 113.12 seconds
Started Jul 13 06:33:59 PM PDT 24
Finished Jul 13 06:35:55 PM PDT 24
Peak memory 270956 kb
Host smart-fa57c51b-69eb-4fdd-8ee7-311c70e29a9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914523216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.914523216
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.481003234
Short name T697
Test name
Test status
Simulation time 11713203 ps
CPU time 1 seconds
Started Jul 13 06:33:47 PM PDT 24
Finished Jul 13 06:33:49 PM PDT 24
Peak memory 211796 kb
Host smart-e4d8db08-0568-49e8-95af-c4da9c139307
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481003234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.481003234
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2488892358
Short name T34
Test name
Test status
Simulation time 32222253 ps
CPU time 0.95 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:23 PM PDT 24
Peak memory 208856 kb
Host smart-6c6748af-4d6a-43f0-a172-9767b8b1e508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488892358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2488892358
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1270939096
Short name T407
Test name
Test status
Simulation time 370799449 ps
CPU time 8.34 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:27 PM PDT 24
Peak memory 218004 kb
Host smart-e3ad7d57-86f2-4c63-aade-720956729a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270939096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1270939096
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3787685286
Short name T747
Test name
Test status
Simulation time 150480386 ps
CPU time 2.44 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:20 PM PDT 24
Peak memory 217012 kb
Host smart-5f710992-abb1-4305-9a7b-9245cdd85652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787685286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3787685286
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1062568510
Short name T735
Test name
Test status
Simulation time 14670672824 ps
CPU time 47.03 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:32:07 PM PDT 24
Peak memory 218900 kb
Host smart-9e75f4bb-87b8-4ef5-b80e-6e594b6b5b55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062568510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1062568510
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.375674422
Short name T62
Test name
Test status
Simulation time 94834897 ps
CPU time 3.01 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:31:23 PM PDT 24
Peak memory 217696 kb
Host smart-8b72f3b9-43ae-4b73-9e82-ee9b4f112769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375674422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.375674422
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1993095162
Short name T275
Test name
Test status
Simulation time 373575930 ps
CPU time 3.57 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 218172 kb
Host smart-2c37c7ae-4f33-4494-9847-4d7f4074899e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993095162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1993095162
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.310618455
Short name T194
Test name
Test status
Simulation time 4838134231 ps
CPU time 18.31 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 217676 kb
Host smart-96e3d8fe-740f-4a2c-a5ff-eef782960749
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310618455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.310618455
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.4029549955
Short name T675
Test name
Test status
Simulation time 4583944797 ps
CPU time 9.47 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:31 PM PDT 24
Peak memory 217744 kb
Host smart-9d5aa477-440c-46e6-897f-36271730722e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029549955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
4029549955
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.415710114
Short name T538
Test name
Test status
Simulation time 915298252 ps
CPU time 41.49 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:58 PM PDT 24
Peak memory 250896 kb
Host smart-82597a6b-5292-472f-b47e-4909263a7df7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415710114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.415710114
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2147012412
Short name T334
Test name
Test status
Simulation time 966429086 ps
CPU time 16.59 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:39 PM PDT 24
Peak memory 223144 kb
Host smart-91162025-2887-4961-aee6-88eeb1c04e27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147012412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2147012412
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2336824260
Short name T269
Test name
Test status
Simulation time 265504346 ps
CPU time 5.61 seconds
Started Jul 13 06:31:20 PM PDT 24
Finished Jul 13 06:31:27 PM PDT 24
Peak memory 218152 kb
Host smart-dfdfc102-526d-4ed8-b258-5c654282dcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336824260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2336824260
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.774201659
Short name T202
Test name
Test status
Simulation time 321900812 ps
CPU time 11.78 seconds
Started Jul 13 06:31:18 PM PDT 24
Finished Jul 13 06:31:31 PM PDT 24
Peak memory 214688 kb
Host smart-ee3e0bb0-04c3-460f-8e47-a475c1292d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774201659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.774201659
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3176146291
Short name T593
Test name
Test status
Simulation time 1153364923 ps
CPU time 9.91 seconds
Started Jul 13 06:31:18 PM PDT 24
Finished Jul 13 06:31:29 PM PDT 24
Peak memory 218212 kb
Host smart-109dc990-7e5f-4c2b-8102-806c24a1dfca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176146291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3176146291
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.484356936
Short name T249
Test name
Test status
Simulation time 250929500 ps
CPU time 11.95 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:29 PM PDT 24
Peak memory 225912 kb
Host smart-27fad1fd-209e-4ab7-881a-9b94cb050919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484356936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.484356936
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3474468471
Short name T294
Test name
Test status
Simulation time 2043070186 ps
CPU time 9.21 seconds
Started Jul 13 06:31:18 PM PDT 24
Finished Jul 13 06:31:29 PM PDT 24
Peak memory 218208 kb
Host smart-859070ad-e7b8-4e32-b92a-3dd13700ff67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474468471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
474468471
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.70381339
Short name T235
Test name
Test status
Simulation time 985320071 ps
CPU time 18.5 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:41 PM PDT 24
Peak memory 225912 kb
Host smart-268cbdea-ac3d-4dea-b5b0-fff388338047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70381339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.70381339
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1419096579
Short name T495
Test name
Test status
Simulation time 30897997 ps
CPU time 1.68 seconds
Started Jul 13 06:31:16 PM PDT 24
Finished Jul 13 06:31:19 PM PDT 24
Peak memory 217648 kb
Host smart-e6ba088c-3b16-4dc5-b7cc-6af3f6722a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419096579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1419096579
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3278234945
Short name T695
Test name
Test status
Simulation time 386111428 ps
CPU time 28.42 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:51 PM PDT 24
Peak memory 250852 kb
Host smart-24962228-0cc4-4ad5-8f8e-7169c0748a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278234945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3278234945
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2101917246
Short name T766
Test name
Test status
Simulation time 1037191728 ps
CPU time 5.89 seconds
Started Jul 13 06:31:17 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 247092 kb
Host smart-2343134c-a83b-4e05-ad45-35628e2240f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101917246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2101917246
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2934470475
Short name T843
Test name
Test status
Simulation time 2462834087 ps
CPU time 89.07 seconds
Started Jul 13 06:31:19 PM PDT 24
Finished Jul 13 06:32:49 PM PDT 24
Peak memory 250592 kb
Host smart-32e7a030-de6a-4996-8848-ba2f56f580c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934470475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2934470475
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.842921088
Short name T481
Test name
Test status
Simulation time 39264250 ps
CPU time 0.89 seconds
Started Jul 13 06:31:14 PM PDT 24
Finished Jul 13 06:31:16 PM PDT 24
Peak memory 211920 kb
Host smart-9d8967a3-8971-46c5-93b6-0b3857fe2454
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842921088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.842921088
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1886788668
Short name T797
Test name
Test status
Simulation time 14467206 ps
CPU time 0.83 seconds
Started Jul 13 06:31:31 PM PDT 24
Finished Jul 13 06:31:33 PM PDT 24
Peak memory 208732 kb
Host smart-63f5d209-29a3-4868-8698-1f0c93888375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886788668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1886788668
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3262607437
Short name T226
Test name
Test status
Simulation time 38895469 ps
CPU time 0.88 seconds
Started Jul 13 06:31:31 PM PDT 24
Finished Jul 13 06:31:33 PM PDT 24
Peak memory 208964 kb
Host smart-7c8a7ce4-74b0-4421-87e4-eeb3834c785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262607437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3262607437
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4255495988
Short name T256
Test name
Test status
Simulation time 440650807 ps
CPU time 13.66 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:36 PM PDT 24
Peak memory 218156 kb
Host smart-a06dfd81-1657-4b61-b3a6-f1d15cd6ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255495988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4255495988
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.503447553
Short name T104
Test name
Test status
Simulation time 1425138566 ps
CPU time 8.92 seconds
Started Jul 13 06:31:32 PM PDT 24
Finished Jul 13 06:31:41 PM PDT 24
Peak memory 217056 kb
Host smart-5dd88972-fae9-49db-a8e6-a616caede587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503447553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.503447553
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4203587324
Short name T534
Test name
Test status
Simulation time 3559135482 ps
CPU time 30.88 seconds
Started Jul 13 06:31:29 PM PDT 24
Finished Jul 13 06:32:00 PM PDT 24
Peak memory 225952 kb
Host smart-f8c83d04-3ba9-441e-9362-ca3cc3a157d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203587324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4203587324
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.623065497
Short name T284
Test name
Test status
Simulation time 599687254 ps
CPU time 4.37 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:36 PM PDT 24
Peak memory 217736 kb
Host smart-4e4c9a7f-0cb2-4c18-be5b-510b3c10fb2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623065497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.623065497
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2452267990
Short name T324
Test name
Test status
Simulation time 86371210 ps
CPU time 2.28 seconds
Started Jul 13 06:31:33 PM PDT 24
Finished Jul 13 06:31:35 PM PDT 24
Peak memory 218476 kb
Host smart-24a523c0-1926-44c0-8911-740ea61f9711
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452267990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2452267990
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3903507285
Short name T339
Test name
Test status
Simulation time 1230066497 ps
CPU time 18.93 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:49 PM PDT 24
Peak memory 217752 kb
Host smart-26f2ab90-2c9f-4ae8-99dc-33647a39a273
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903507285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3903507285
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4192956499
Short name T64
Test name
Test status
Simulation time 261169367 ps
CPU time 3.4 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:35 PM PDT 24
Peak memory 217596 kb
Host smart-260fee79-5022-4a0b-aace-b2ce3cdbca62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192956499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4192956499
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.174585663
Short name T663
Test name
Test status
Simulation time 5880003682 ps
CPU time 43.2 seconds
Started Jul 13 06:31:31 PM PDT 24
Finished Jul 13 06:32:15 PM PDT 24
Peak memory 276604 kb
Host smart-2afc0902-284c-492c-aaa0-0af99d007673
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174585663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.174585663
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2899873593
Short name T452
Test name
Test status
Simulation time 3409038657 ps
CPU time 14.26 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:45 PM PDT 24
Peak memory 250972 kb
Host smart-e793972e-6871-40e4-ba35-c04a172a50b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899873593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2899873593
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2400135487
Short name T656
Test name
Test status
Simulation time 32059377 ps
CPU time 2.23 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:25 PM PDT 24
Peak memory 222100 kb
Host smart-47c4e21c-bb8a-4ff2-b396-d037958a2159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400135487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2400135487
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.715192280
Short name T300
Test name
Test status
Simulation time 598566253 ps
CPU time 17.14 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:49 PM PDT 24
Peak memory 217656 kb
Host smart-5a55a8dc-4617-42be-a5be-cccf364d36e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715192280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.715192280
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1030819828
Short name T743
Test name
Test status
Simulation time 803677311 ps
CPU time 13.43 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:44 PM PDT 24
Peak memory 226040 kb
Host smart-f16379f8-48b5-4ff6-84b1-344c30230535
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030819828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1030819828
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2363653199
Short name T544
Test name
Test status
Simulation time 930906981 ps
CPU time 8.03 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:39 PM PDT 24
Peak memory 225968 kb
Host smart-afc41c3a-4e39-4627-ab73-aecbd4d20ab5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363653199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2363653199
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1055514968
Short name T575
Test name
Test status
Simulation time 225060094 ps
CPU time 7.9 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:39 PM PDT 24
Peak memory 218104 kb
Host smart-eec93862-33b3-40ea-b178-5c393d2921b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055514968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
055514968
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3815079192
Short name T617
Test name
Test status
Simulation time 339579421 ps
CPU time 8.27 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:31 PM PDT 24
Peak memory 225888 kb
Host smart-ae896ee2-7628-4d1e-96b7-c268c23f89d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815079192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3815079192
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2725222072
Short name T37
Test name
Test status
Simulation time 41043838 ps
CPU time 1.64 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 213956 kb
Host smart-e9c7ee2f-40d5-4acd-934e-c1244d8453c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725222072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2725222072
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3829484627
Short name T828
Test name
Test status
Simulation time 1101086982 ps
CPU time 26.09 seconds
Started Jul 13 06:32:20 PM PDT 24
Finished Jul 13 06:32:47 PM PDT 24
Peak memory 249912 kb
Host smart-fb8c3fdb-e4a9-4c58-b50c-1d686edc4802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829484627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3829484627
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3291040330
Short name T812
Test name
Test status
Simulation time 92237931 ps
CPU time 3.56 seconds
Started Jul 13 06:31:22 PM PDT 24
Finished Jul 13 06:31:26 PM PDT 24
Peak memory 222472 kb
Host smart-4bf08073-18b5-4bb6-94fa-326fcef6ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291040330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3291040330
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1575566173
Short name T70
Test name
Test status
Simulation time 75103274062 ps
CPU time 101.76 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:33:12 PM PDT 24
Peak memory 242784 kb
Host smart-37d7bb98-19ea-46de-ab5f-326db3ca8309
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575566173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1575566173
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2151349766
Short name T567
Test name
Test status
Simulation time 13133836 ps
CPU time 0.9 seconds
Started Jul 13 06:31:21 PM PDT 24
Finished Jul 13 06:31:24 PM PDT 24
Peak memory 211832 kb
Host smart-9c2afdc5-eb23-47f8-acb7-8af8a78f379e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151349766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2151349766
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1556310655
Short name T514
Test name
Test status
Simulation time 21366418 ps
CPU time 1.22 seconds
Started Jul 13 06:31:45 PM PDT 24
Finished Jul 13 06:31:48 PM PDT 24
Peak memory 208928 kb
Host smart-3df2626c-740e-4406-8882-a568690c75b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556310655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1556310655
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.375745978
Short name T542
Test name
Test status
Simulation time 309135296 ps
CPU time 11.04 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:42 PM PDT 24
Peak memory 225972 kb
Host smart-632ddc59-67e1-4d1b-946e-4d2cd4a8d84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375745978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.375745978
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4046259217
Short name T26
Test name
Test status
Simulation time 1614238360 ps
CPU time 10.83 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:31:56 PM PDT 24
Peak memory 217128 kb
Host smart-cddbb539-693e-431d-b024-94474912b2d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046259217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4046259217
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.25957566
Short name T707
Test name
Test status
Simulation time 873291818 ps
CPU time 30.37 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:32:14 PM PDT 24
Peak memory 218180 kb
Host smart-76fd47e2-e3ad-4c85-a8a1-17494f614e35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25957566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_erro
rs.25957566
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1975584369
Short name T490
Test name
Test status
Simulation time 1973725294 ps
CPU time 12.12 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 217396 kb
Host smart-150e7c11-25e2-40d1-b62f-bd0ab8dc0c75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975584369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
975584369
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.891119927
Short name T757
Test name
Test status
Simulation time 170255455 ps
CPU time 2.25 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 218172 kb
Host smart-139bd9a2-1a1c-415d-ae31-cd9a2040330a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891119927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.891119927
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.282620427
Short name T63
Test name
Test status
Simulation time 4994981023 ps
CPU time 34.19 seconds
Started Jul 13 06:31:45 PM PDT 24
Finished Jul 13 06:32:20 PM PDT 24
Peak memory 217704 kb
Host smart-6b9ad5df-7fa3-43b1-bbf9-742d4a6ad2eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282620427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.282620427
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.18400104
Short name T255
Test name
Test status
Simulation time 122383811 ps
CPU time 2.3 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:31:48 PM PDT 24
Peak memory 217676 kb
Host smart-95f812e4-458c-4f92-929c-d9d9d4e141b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18400104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.18400104
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2621832649
Short name T195
Test name
Test status
Simulation time 2579497989 ps
CPU time 62.99 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:32:49 PM PDT 24
Peak memory 275572 kb
Host smart-7d7615a6-914b-4d7d-8b1b-a7ae516152b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621832649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2621832649
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2273959739
Short name T184
Test name
Test status
Simulation time 676243009 ps
CPU time 15.26 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:32:00 PM PDT 24
Peak memory 245992 kb
Host smart-d9727e97-7a57-4024-91bb-123640aaa342
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273959739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2273959739
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3768649730
Short name T340
Test name
Test status
Simulation time 181915809 ps
CPU time 3.28 seconds
Started Jul 13 06:31:31 PM PDT 24
Finished Jul 13 06:31:35 PM PDT 24
Peak memory 222448 kb
Host smart-3e5ed1d4-b80b-4500-a15e-a529d8805000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768649730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3768649730
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1300816401
Short name T200
Test name
Test status
Simulation time 504310853 ps
CPU time 8.54 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:39 PM PDT 24
Peak memory 214768 kb
Host smart-ce8342d4-dd18-496e-a26c-814fde8d43a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300816401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1300816401
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.774979829
Short name T422
Test name
Test status
Simulation time 1081793890 ps
CPU time 12.37 seconds
Started Jul 13 06:31:41 PM PDT 24
Finished Jul 13 06:31:54 PM PDT 24
Peak memory 225984 kb
Host smart-6b197ce8-8cac-4e13-a347-e44fd9ba771c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774979829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.774979829
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2113312067
Short name T602
Test name
Test status
Simulation time 1302968299 ps
CPU time 21.81 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:32:06 PM PDT 24
Peak memory 225976 kb
Host smart-ad9e0b52-9456-4ae6-a298-57ae2fdd4fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113312067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2113312067
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1686113984
Short name T356
Test name
Test status
Simulation time 2056437444 ps
CPU time 10.87 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:31:54 PM PDT 24
Peak memory 218168 kb
Host smart-85c0e9e2-6512-42be-ba81-ecd6dd96c2b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686113984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
686113984
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1394951228
Short name T791
Test name
Test status
Simulation time 1690931894 ps
CPU time 15.66 seconds
Started Jul 13 06:31:31 PM PDT 24
Finished Jul 13 06:31:48 PM PDT 24
Peak memory 224968 kb
Host smart-51396a27-48ef-4997-838d-0a9ba2af5c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394951228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1394951228
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.259134065
Short name T93
Test name
Test status
Simulation time 53924863 ps
CPU time 1.47 seconds
Started Jul 13 06:32:27 PM PDT 24
Finished Jul 13 06:32:29 PM PDT 24
Peak memory 217208 kb
Host smart-a01b6d9a-0cc3-4c96-9f52-f6ecd3fa94dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259134065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.259134065
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2477652619
Short name T678
Test name
Test status
Simulation time 725958602 ps
CPU time 23.04 seconds
Started Jul 13 06:31:29 PM PDT 24
Finished Jul 13 06:31:52 PM PDT 24
Peak memory 245748 kb
Host smart-c25f234d-1096-4fc2-b65b-993bef7e5a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477652619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2477652619
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.684231279
Short name T331
Test name
Test status
Simulation time 49273933 ps
CPU time 8.09 seconds
Started Jul 13 06:31:30 PM PDT 24
Finished Jul 13 06:31:38 PM PDT 24
Peak memory 250916 kb
Host smart-997784e4-60d2-4d2e-aedc-6e345097d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684231279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.684231279
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3368460810
Short name T369
Test name
Test status
Simulation time 1287410213 ps
CPU time 47.77 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:32:30 PM PDT 24
Peak memory 246652 kb
Host smart-74f60cbf-4870-429b-8569-695757b84fea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368460810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3368460810
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3121965066
Short name T242
Test name
Test status
Simulation time 44170109 ps
CPU time 1.01 seconds
Started Jul 13 06:31:32 PM PDT 24
Finished Jul 13 06:31:33 PM PDT 24
Peak memory 211904 kb
Host smart-4a9f77c2-39bc-4306-b481-37902dc19341
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121965066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3121965066
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1626054297
Short name T719
Test name
Test status
Simulation time 16287069 ps
CPU time 1.16 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:31:44 PM PDT 24
Peak memory 208892 kb
Host smart-7ecc5c5f-2e09-42a7-a039-926ba456f9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626054297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1626054297
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1156282994
Short name T840
Test name
Test status
Simulation time 1142711006 ps
CPU time 11.72 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:31:58 PM PDT 24
Peak memory 225940 kb
Host smart-751b7c63-2bef-46a7-90cf-dd3ad6a6b45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156282994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1156282994
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.674146071
Short name T634
Test name
Test status
Simulation time 730634276 ps
CPU time 2.76 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:31:49 PM PDT 24
Peak memory 217240 kb
Host smart-f5db7a88-4679-4561-89a4-b5e1591d775d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674146071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.674146071
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.511552880
Short name T691
Test name
Test status
Simulation time 747694955 ps
CPU time 18.3 seconds
Started Jul 13 06:31:45 PM PDT 24
Finished Jul 13 06:32:04 PM PDT 24
Peak memory 217664 kb
Host smart-88e70551-98df-4f7d-9713-c84a72162d21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511552880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.511552880
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3962248071
Short name T280
Test name
Test status
Simulation time 842937809 ps
CPU time 6.68 seconds
Started Jul 13 06:31:45 PM PDT 24
Finished Jul 13 06:31:53 PM PDT 24
Peak memory 218124 kb
Host smart-f689706a-811e-43e0-805f-6faca74c2599
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962248071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3962248071
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.944075839
Short name T262
Test name
Test status
Simulation time 4908556664 ps
CPU time 21.93 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:32:08 PM PDT 24
Peak memory 217756 kb
Host smart-e86be830-e03a-4eb0-a953-1e262265ee0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944075839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.944075839
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2110851081
Short name T116
Test name
Test status
Simulation time 166577482 ps
CPU time 6 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:31:49 PM PDT 24
Peak memory 217644 kb
Host smart-a47652db-c83f-41eb-a4f0-0e7dd89b785c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110851081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2110851081
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2980590518
Short name T709
Test name
Test status
Simulation time 3820786324 ps
CPU time 68.79 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:32:55 PM PDT 24
Peak memory 283752 kb
Host smart-09d4089b-7732-4e21-82ed-eb5f439297f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980590518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2980590518
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2899977812
Short name T600
Test name
Test status
Simulation time 17554995772 ps
CPU time 34.5 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:32:20 PM PDT 24
Peak memory 251020 kb
Host smart-089336f8-b3fa-4c8b-931a-a6d55023c4aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899977812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2899977812
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4014822061
Short name T313
Test name
Test status
Simulation time 209797749 ps
CPU time 2.49 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 218164 kb
Host smart-f8dc0fd3-6314-4e49-a84f-e5c1136ba600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014822061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4014822061
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.947872914
Short name T203
Test name
Test status
Simulation time 1127827426 ps
CPU time 18.29 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:32:03 PM PDT 24
Peak memory 214600 kb
Host smart-bf8396e1-01e3-4eb4-8219-7e8f3b84b52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947872914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.947872914
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2577017472
Short name T327
Test name
Test status
Simulation time 359441543 ps
CPU time 11.95 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:31:57 PM PDT 24
Peak memory 225996 kb
Host smart-5967fde7-3523-41c2-92af-b9f95b306c6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577017472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2577017472
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.651648515
Short name T562
Test name
Test status
Simulation time 3057210566 ps
CPU time 14.57 seconds
Started Jul 13 06:31:45 PM PDT 24
Finished Jul 13 06:32:01 PM PDT 24
Peak memory 218236 kb
Host smart-8ecc8fd5-94fa-4480-895a-811745e9e87f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651648515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.651648515
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.4004998610
Short name T58
Test name
Test status
Simulation time 169911106 ps
CPU time 2.47 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 214548 kb
Host smart-1a8a9e2a-4a2f-43b0-8171-3b07b5f699a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004998610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4004998610
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1845718904
Short name T335
Test name
Test status
Simulation time 294107543 ps
CPU time 32.47 seconds
Started Jul 13 06:31:42 PM PDT 24
Finished Jul 13 06:32:15 PM PDT 24
Peak memory 250940 kb
Host smart-65e9e816-b563-432a-863f-d46441d34a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845718904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1845718904
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.207097300
Short name T348
Test name
Test status
Simulation time 750484141 ps
CPU time 7.54 seconds
Started Jul 13 06:31:46 PM PDT 24
Finished Jul 13 06:31:54 PM PDT 24
Peak memory 250856 kb
Host smart-d07bf7f8-6000-4611-b5cd-8081d97db746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207097300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.207097300
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1075259722
Short name T529
Test name
Test status
Simulation time 4978686822 ps
CPU time 137.71 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:34:03 PM PDT 24
Peak memory 248508 kb
Host smart-ed0222b1-e50d-46e0-96ad-60f4478b8040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075259722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1075259722
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3279522412
Short name T124
Test name
Test status
Simulation time 40524908841 ps
CPU time 545.28 seconds
Started Jul 13 06:31:47 PM PDT 24
Finished Jul 13 06:40:53 PM PDT 24
Peak memory 316892 kb
Host smart-52149b2a-9338-47c6-a8ca-4239a9fea76b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3279522412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3279522412
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2898867653
Short name T118
Test name
Test status
Simulation time 43455378 ps
CPU time 0.83 seconds
Started Jul 13 06:31:45 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 211820 kb
Host smart-460f3c6c-12c4-4972-8a8d-371d88aa047d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898867653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2898867653
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3323186614
Short name T787
Test name
Test status
Simulation time 65518531 ps
CPU time 1.17 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 208940 kb
Host smart-a674b5ea-e46f-4fb8-8369-edfd1ddfab88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323186614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3323186614
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2126690321
Short name T463
Test name
Test status
Simulation time 32594232 ps
CPU time 0.84 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 208912 kb
Host smart-3a55fb7c-9ad7-44e2-b7cb-8c7c5077f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126690321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2126690321
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1821333750
Short name T610
Test name
Test status
Simulation time 1218238857 ps
CPU time 14.16 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:32:07 PM PDT 24
Peak memory 218036 kb
Host smart-cff1db46-4750-4dd7-aedb-ca98a116e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821333750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1821333750
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.508739489
Short name T834
Test name
Test status
Simulation time 112825576 ps
CPU time 1.8 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:31:54 PM PDT 24
Peak memory 217016 kb
Host smart-e087ff0e-e4ef-4029-8b4f-d1e05fd69b96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508739489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.508739489
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.892893461
Short name T472
Test name
Test status
Simulation time 4918268875 ps
CPU time 49.63 seconds
Started Jul 13 06:31:58 PM PDT 24
Finished Jul 13 06:32:49 PM PDT 24
Peak memory 226036 kb
Host smart-f76de227-e467-416e-b728-00121647bd5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892893461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.892893461
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1957204729
Short name T666
Test name
Test status
Simulation time 598815171 ps
CPU time 15.42 seconds
Started Jul 13 06:31:56 PM PDT 24
Finished Jul 13 06:32:12 PM PDT 24
Peak memory 217968 kb
Host smart-35a5aba6-9aad-4a56-ba51-68d52f753ae9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957204729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
957204729
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.396787136
Short name T764
Test name
Test status
Simulation time 118066226 ps
CPU time 4.34 seconds
Started Jul 13 06:31:50 PM PDT 24
Finished Jul 13 06:31:54 PM PDT 24
Peak memory 221612 kb
Host smart-8a03175c-7401-4c0c-b111-cda7522cea1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396787136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.396787136
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2998935565
Short name T78
Test name
Test status
Simulation time 2307197276 ps
CPU time 34.01 seconds
Started Jul 13 06:31:56 PM PDT 24
Finished Jul 13 06:32:31 PM PDT 24
Peak memory 217720 kb
Host smart-e456d903-7867-45fd-892c-ab40c883f237
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998935565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2998935565
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2148299679
Short name T460
Test name
Test status
Simulation time 184496713 ps
CPU time 4.03 seconds
Started Jul 13 06:31:50 PM PDT 24
Finished Jul 13 06:31:55 PM PDT 24
Peak memory 217808 kb
Host smart-87fbe4a2-7771-431c-a9a0-93891fec2152
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148299679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2148299679
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1742414539
Short name T254
Test name
Test status
Simulation time 7909287794 ps
CPU time 41.82 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:32:35 PM PDT 24
Peak memory 270452 kb
Host smart-5ca0ae21-e4a5-4021-89d1-749d8fba7843
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742414539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1742414539
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3866928949
Short name T543
Test name
Test status
Simulation time 2434585442 ps
CPU time 18.12 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:32:11 PM PDT 24
Peak memory 250968 kb
Host smart-7ae2c909-ab1d-4ad6-a224-febdc8c089fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866928949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3866928949
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2127929184
Short name T619
Test name
Test status
Simulation time 142314401 ps
CPU time 2.58 seconds
Started Jul 13 06:31:50 PM PDT 24
Finished Jul 13 06:31:53 PM PDT 24
Peak memory 218108 kb
Host smart-e2abc44d-eb06-4460-9637-bf3403e9d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127929184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2127929184
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3769815034
Short name T358
Test name
Test status
Simulation time 335585132 ps
CPU time 5.36 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:32:01 PM PDT 24
Peak memory 214488 kb
Host smart-3082aff6-bae6-440e-9034-4b1fbdd98fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769815034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3769815034
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3844045555
Short name T426
Test name
Test status
Simulation time 509596464 ps
CPU time 15.44 seconds
Started Jul 13 06:31:51 PM PDT 24
Finished Jul 13 06:32:06 PM PDT 24
Peak memory 225984 kb
Host smart-16a6ce3e-8fce-4730-9e94-7302fa2268c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844045555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3844045555
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.4028907343
Short name T413
Test name
Test status
Simulation time 2020192785 ps
CPU time 12.32 seconds
Started Jul 13 06:31:56 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 225908 kb
Host smart-12b50256-5861-48c4-901b-de31972a7007
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028907343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.4028907343
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3586786328
Short name T279
Test name
Test status
Simulation time 497482919 ps
CPU time 11.27 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:32:04 PM PDT 24
Peak memory 218132 kb
Host smart-6f8c72dc-4936-4329-bb2d-99c40dfbb26f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586786328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
586786328
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2850808098
Short name T467
Test name
Test status
Simulation time 932093024 ps
CPU time 10.49 seconds
Started Jul 13 06:31:57 PM PDT 24
Finished Jul 13 06:32:09 PM PDT 24
Peak memory 218224 kb
Host smart-8fa23c81-abc6-4810-bb61-d889cf9588bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850808098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2850808098
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.156812528
Short name T414
Test name
Test status
Simulation time 71668356 ps
CPU time 1.47 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 217584 kb
Host smart-125fb21d-7e63-4edf-9ede-1c44871f6319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156812528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.156812528
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1550239691
Short name T430
Test name
Test status
Simulation time 5199111697 ps
CPU time 26.03 seconds
Started Jul 13 06:31:43 PM PDT 24
Finished Jul 13 06:32:10 PM PDT 24
Peak memory 250976 kb
Host smart-f9c4a9e5-de1f-46c9-855f-3c60f9d7c412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550239691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1550239691
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.153797933
Short name T800
Test name
Test status
Simulation time 84013341 ps
CPU time 8.64 seconds
Started Jul 13 06:31:54 PM PDT 24
Finished Jul 13 06:32:04 PM PDT 24
Peak memory 243092 kb
Host smart-c1edc09f-3e55-44c3-9f3b-1b990e0d8dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153797933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.153797933
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3586901109
Short name T55
Test name
Test status
Simulation time 8321886633 ps
CPU time 126.6 seconds
Started Jul 13 06:31:52 PM PDT 24
Finished Jul 13 06:33:59 PM PDT 24
Peak memory 258916 kb
Host smart-269fd7be-cc62-4d16-b742-c7754b7d210a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586901109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3586901109
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.68892410
Short name T306
Test name
Test status
Simulation time 29539107 ps
CPU time 0.96 seconds
Started Jul 13 06:31:44 PM PDT 24
Finished Jul 13 06:31:47 PM PDT 24
Peak memory 211816 kb
Host smart-a79b0500-8109-4e29-ac43-13ead2c06a6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68892410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_volatile_unlock_smoke.68892410
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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