Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1797715	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2024001

1

T2

713

T3

5

T4

260

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3474420	1			T2	722		T3	41		T4	165
values[0x0]	172915	1			T2	210		T3	5		T4	85
values[0x1]	174381	1			T2	206		T3	3		T4	115

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1429128	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2392588

1

T2

806

T3

22

T4

292

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11387	1			T9	4		T12	6		T13	131
valid_sources[0x01]	20962	1			T9	3		T12	1		T13	159
valid_sources[0x02]	11348	1			T9	3		T12	5		T13	105
valid_sources[0x03]	11392	1			T10	2		T13	88		T21	4
valid_sources[0x04]	11445	1			T9	3		T12	1		T13	94
valid_sources[0x05]	12254	1			T9	1		T12	4		T13	142
valid_sources[0x06]	11695	1			T9	4		T12	1		T13	100
valid_sources[0x07]	12549	1			T9	3		T10	1		T12	2
valid_sources[0x08]	13690	1			T2	126		T12	3		T13	110
valid_sources[0x09]	11627	1			T13	109		T21	1		T22	5
valid_sources[0x0a]	17367	1			T9	10		T12	3		T13	120
valid_sources[0x0b]	11776	1			T8	1		T9	7		T12	7
valid_sources[0x0c]	13046	1			T9	14		T12	6		T13	73
valid_sources[0x0d]	11484	1			T8	15		T9	6		T12	6
valid_sources[0x0e]	11362	1			T9	2		T12	6		T13	114
valid_sources[0x0f]	11847	1			T9	11		T10	1		T12	2
valid_sources[0x10]	11407	1			T13	108		T22	8		T82	3
valid_sources[0x11]	13070	1			T9	5		T10	2		T12	2
valid_sources[0x12]	16213	1			T9	4		T12	3		T13	117
valid_sources[0x13]	13593	1			T2	3		T8	6		T9	6
valid_sources[0x14]	12811	1			T9	5		T12	1		T13	109
valid_sources[0x15]	11181	1			T9	1		T10	3		T13	81
valid_sources[0x16]	15205	1			T8	1		T9	22		T12	4
valid_sources[0x17]	11637	1			T8	8		T9	3		T12	1
valid_sources[0x18]	11412	1			T9	3		T12	3		T13	90
valid_sources[0x19]	13306	1			T12	2		T13	146		T22	5
valid_sources[0x1a]	11263	1			T9	2		T12	4		T13	127
valid_sources[0x1b]	11723	1			T2	24		T9	7		T12	1
valid_sources[0x1c]	11783	1			T12	6		T13	108		T21	1
valid_sources[0x1d]	12909	1			T9	3		T12	5		T13	130
valid_sources[0x1e]	11591	1			T8	8		T9	7		T12	1
valid_sources[0x1f]	41130	1			T9	4		T11	1		T12	8
valid_sources[0x20]	55294	1			T4	365		T12	3		T13	104
valid_sources[0x21]	11489	1			T9	4		T10	1		T11	1
valid_sources[0x22]	11662	1			T9	8		T12	4		T13	115
valid_sources[0x23]	13497	1			T2	94		T8	17		T9	12
valid_sources[0x24]	13683	1			T9	14		T12	4		T13	111
valid_sources[0x25]	11615	1			T12	5		T13	110		T6	9
valid_sources[0x26]	25184	1			T8	1		T9	2		T12	3
valid_sources[0x27]	11066	1			T9	10		T12	4		T13	148
valid_sources[0x28]	11530	1			T12	1		T13	111		T21	2
valid_sources[0x29]	20002	1			T12	1		T13	150		T21	1
valid_sources[0x2a]	11249	1			T9	3		T12	1		T13	131
valid_sources[0x2b]	13294	1			T9	4		T11	1		T12	8
valid_sources[0x2c]	11088	1			T12	8		T13	106		T21	1
valid_sources[0x2d]	11366	1			T8	2		T9	6		T12	4
valid_sources[0x2e]	16878	1			T2	62		T8	4		T12	2
valid_sources[0x2f]	11310	1			T9	7		T10	1		T12	3
valid_sources[0x30]	11576	1			T10	2		T12	9		T13	124
valid_sources[0x31]	15101	1			T9	1		T12	3		T13	90
valid_sources[0x32]	11207	1			T12	1		T13	113		T22	2
valid_sources[0x33]	11406	1			T8	10		T9	9		T12	9
valid_sources[0x34]	11679	1			T9	10		T12	6		T13	125
valid_sources[0x35]	15487	1			T9	20		T12	1		T13	106
valid_sources[0x36]	11495	1			T9	13		T13	121		T22	3
valid_sources[0x37]	11516	1			T2	33		T12	1		T13	88
valid_sources[0x38]	15599	1			T9	1		T12	4		T13	106
valid_sources[0x39]	11643	1			T2	29		T8	1		T9	8
valid_sources[0x3a]	11159	1			T8	7		T9	1		T12	3
valid_sources[0x3b]	72585	1			T9	7		T12	4		T13	126
valid_sources[0x3c]	11795	1			T9	13		T12	7		T13	100
valid_sources[0x3d]	13008	1			T12	2		T13	117		T21	2
valid_sources[0x3e]	11286	1			T9	9		T10	1		T12	3
valid_sources[0x3f]	15669	1			T12	1		T13	104		T22	2
valid_sources[0x40]	12329	1			T8	2		T12	9		T13	101
valid_sources[0x41]	11192	1			T2	18		T9	3		T12	5
valid_sources[0x42]	11917	1			T8	3		T9	20		T12	1
valid_sources[0x43]	11375	1			T2	20		T8	9		T5	4
valid_sources[0x44]	11761	1			T2	85		T9	3		T12	1
valid_sources[0x45]	11502	1			T13	129		T21	3		T22	5
valid_sources[0x46]	16034	1			T9	3		T12	8		T13	109
valid_sources[0x47]	11528	1			T2	1		T9	4		T12	4
valid_sources[0x48]	11903	1			T9	3		T12	3		T13	128
valid_sources[0x49]	11463	1			T9	12		T10	2		T12	3
valid_sources[0x4a]	11394	1			T8	14		T9	3		T11	3
valid_sources[0x4b]	11829	1			T9	3		T12	3		T13	140
valid_sources[0x4c]	11758	1			T9	13		T12	5		T13	105
valid_sources[0x4d]	13868	1			T10	1		T12	5		T13	85
valid_sources[0x4e]	13658	1			T9	4		T12	2		T13	125
valid_sources[0x4f]	13625	1			T2	15		T9	17		T12	4
valid_sources[0x50]	11514	1			T9	11		T10	1		T12	7
valid_sources[0x51]	11391	1			T10	1		T12	1		T13	94
valid_sources[0x52]	11408	1			T9	26		T10	1		T11	1
valid_sources[0x53]	12611	1			T9	1		T10	1		T12	3
valid_sources[0x54]	11562	1			T8	7		T10	1		T12	3
valid_sources[0x55]	11743	1			T9	9		T12	8		T13	108
valid_sources[0x56]	11395	1			T2	1		T9	19		T12	2
valid_sources[0x57]	11646	1			T9	7		T12	1		T13	114
valid_sources[0x58]	15904	1			T9	7		T12	4		T13	140
valid_sources[0x59]	11598	1			T8	4		T12	4		T13	145
valid_sources[0x5a]	12603	1			T5	1		T9	3		T12	1
valid_sources[0x5b]	11766	1			T12	1		T13	94		T21	4
valid_sources[0x5c]	11982	1			T9	4		T12	1		T13	77
valid_sources[0x5d]	135592	1			T2	14		T9	14		T12	1
valid_sources[0x5e]	13626	1			T8	1		T12	9		T13	147
valid_sources[0x5f]	11363	1			T9	3		T12	2		T13	85
valid_sources[0x60]	14308	1			T12	6		T13	102		T21	1
valid_sources[0x61]	11529	1			T10	1		T12	1		T13	137
valid_sources[0x62]	13064	1			T2	12		T9	9		T12	4
valid_sources[0x63]	11309	1			T9	1		T12	3		T13	98
valid_sources[0x64]	11728	1			T9	2		T12	2		T13	110
valid_sources[0x65]	12259	1			T2	7		T10	1		T12	2
valid_sources[0x66]	11939	1			T12	3		T13	80		T22	5
valid_sources[0x67]	11385	1			T9	4		T12	2		T13	119
valid_sources[0x68]	12684	1			T9	1		T10	1		T12	1
valid_sources[0x69]	11083	1			T9	1		T12	4		T13	74
valid_sources[0x6a]	18130	1			T8	6		T9	5		T12	6
valid_sources[0x6b]	11179	1			T9	20		T12	5		T13	103
valid_sources[0x6c]	12380	1			T9	28		T12	4		T13	76
valid_sources[0x6d]	12430	1			T12	2		T13	99		T6	5
valid_sources[0x6e]	30414	1			T9	24		T12	2		T13	79
valid_sources[0x6f]	17054	1			T10	3		T12	6		T13	106
valid_sources[0x70]	11586	1			T8	10		T9	1		T12	1
valid_sources[0x71]	108309	1			T9	11		T12	2		T13	82
valid_sources[0x72]	11293	1			T9	6		T12	2		T13	128
valid_sources[0x73]	11512	1			T8	3		T9	6		T12	4
valid_sources[0x74]	15152	1			T8	6		T9	19		T12	4
valid_sources[0x75]	13641	1			T8	19		T9	4		T12	16
valid_sources[0x76]	19481	1			T9	8		T12	4		T13	141
valid_sources[0x77]	11485	1			T2	71		T8	1		T9	1
valid_sources[0x78]	11653	1			T2	21		T9	3		T12	6
valid_sources[0x79]	11688	1			T8	1		T9	3		T10	1
valid_sources[0x7a]	11458	1			T9	2		T11	1		T12	7
valid_sources[0x7b]	11218	1			T8	19		T9	18		T12	5
valid_sources[0x7c]	11795	1			T8	2		T9	2		T10	1
valid_sources[0x7d]	13017	1			T9	9		T13	70		T21	2
valid_sources[0x7e]	11163	1			T10	1		T12	3		T13	94
valid_sources[0x7f]	11765	1			T9	5		T10	2		T12	1
valid_sources[0x80]	11726	1			T8	1		T9	4		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1724260

1

T2

357

T4

83

T8

73

values[0x0]

all_enables

biggest_size

150084

1

T2

179

T3

4

T4

77

values[0x1]

all_enables

biggest_size

149657

1

T2

177

T3

1

T4

100