Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	103541185	15312	0	0
claim_transition_if_regwen_rd_A	103541185	2049	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103541185	15312	0	0
T43	0	2	0	0
T44	0	1	0	0
T69	200162	3	0	0
T75	8616	0	0	0
T91	0	1	0	0
T92	0	1	0	0
T97	0	1	0	0
T119	25985	0	0	0
T120	0	13	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	7	0	0
T160	1560	0	0	0
T161	5812	0	0	0
T162	17600	0	0	0
T163	5578	0	0	0
T164	37015	0	0	0
T165	143161	0	0	0
T166	1518	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103541185	2049	0	0
T29	35580	0	0	0
T43	0	14	0	0
T51	39577	0	0	0
T70	4854	0	0	0
T74	0	5	0	0
T91	852131	6	0	0
T125	0	16	0	0
T126	0	63	0	0
T152	0	18	0	0
T154	0	7	0	0
T167	0	1	0	0
T168	0	7	0	0
T169	0	7	0	0
T170	951	0	0	0
T171	31105	0	0	0
T172	161075	0	0	0
T173	6509	0	0	0
T174	9035	0	0	0
T175	47895	0	0	0