Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48222 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1762 |
1 |
|
|
T5 |
10 |
|
T17 |
6 |
|
T18 |
6 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49277 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
707 |
1 |
|
|
T20 |
20 |
|
T52 |
14 |
|
T73 |
10 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48257 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1727 |
1 |
|
|
T4 |
28 |
|
T26 |
17 |
|
T27 |
11 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48299 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1685 |
1 |
|
|
T4 |
30 |
|
T26 |
8 |
|
T27 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48285 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1699 |
1 |
|
|
T4 |
28 |
|
T12 |
1 |
|
T26 |
8 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
45604 |
1 |
|
|
T2 |
77 |
|
T3 |
74 |
|
T4 |
249 |
no_err_inj |
4380 |
1 |
|
|
T1 |
1 |
|
T4 |
38 |
|
T12 |
4 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48279 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1705 |
1 |
|
|
T5 |
8 |
|
T17 |
8 |
|
T18 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49354 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
630 |
1 |
|
|
T20 |
19 |
|
T52 |
11 |
|
T73 |
13 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36324 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
13660 |
1 |
|
|
T4 |
159 |
|
T5 |
94 |
|
T6 |
4 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48308 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1676 |
1 |
|
|
T4 |
22 |
|
T12 |
1 |
|
T26 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48226 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1758 |
1 |
|
|
T4 |
30 |
|
T26 |
7 |
|
T27 |
5 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48286 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1698 |
1 |
|
|
T4 |
27 |
|
T12 |
1 |
|
T26 |
6 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48253 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1731 |
1 |
|
|
T5 |
9 |
|
T17 |
12 |
|
T18 |
16 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48065 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1919 |
1 |
|
|
T4 |
11 |
|
T15 |
19 |
|
T16 |
11 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49329 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
655 |
1 |
|
|
T20 |
15 |
|
T52 |
19 |
|
T73 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49352 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
632 |
1 |
|
|
T20 |
25 |
|
T52 |
19 |
|
T73 |
11 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49333 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
651 |
1 |
|
|
T20 |
18 |
|
T52 |
15 |
|
T73 |
17 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47427 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
2557 |
1 |
|
|
T4 |
13 |
|
T12 |
12 |
|
T29 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46097 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T4 |
287 |
auto[1] |
3887 |
1 |
|
|
T3 |
74 |
|
T25 |
100 |
|
T58 |
59 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48341 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1643 |
1 |
|
|
T4 |
24 |
|
T26 |
8 |
|
T27 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48330 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1654 |
1 |
|
|
T4 |
24 |
|
T12 |
2 |
|
T26 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48265 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1719 |
1 |
|
|
T4 |
25 |
|
T12 |
3 |
|
T26 |
10 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48214 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1770 |
1 |
|
|
T5 |
14 |
|
T17 |
15 |
|
T18 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44760 |
1 |
|
|
T1 |
1 |
|
T3 |
74 |
|
T4 |
287 |
auto[1] |
5224 |
1 |
|
|
T2 |
77 |
|
T5 |
17 |
|
T23 |
86 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46144 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
3840 |
1 |
|
|
T21 |
61 |
|
T57 |
99 |
|
T72 |
82 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49984 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48261 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1723 |
1 |
|
|
T5 |
12 |
|
T17 |
12 |
|
T18 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48208 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1776 |
1 |
|
|
T5 |
14 |
|
T17 |
11 |
|
T18 |
13 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48251 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[1] |
1733 |
1 |
|
|
T5 |
10 |
|
T17 |
18 |
|
T18 |
12 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
44325 |
1 |
|
|
T2 |
77 |
|
T3 |
74 |
|
T4 |
242 |
auto[0] |
no_err_inj |
3102 |
1 |
|
|
T1 |
1 |
|
T4 |
32 |
|
T14 |
16 |
auto[1] |
err_inj |
1279 |
1 |
|
|
T4 |
7 |
|
T12 |
8 |
|
T29 |
4 |
auto[1] |
no_err_inj |
1278 |
1 |
|
|
T4 |
6 |
|
T12 |
4 |
|
T29 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45909 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1518 |
1 |
|
|
T4 |
23 |
|
T26 |
12 |
|
T27 |
10 |
auto[1] |
auto[0] |
2421 |
1 |
|
|
T4 |
12 |
|
T12 |
10 |
|
T29 |
11 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T4 |
1 |
|
T12 |
2 |
|
T251 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45815 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1612 |
1 |
|
|
T4 |
28 |
|
T26 |
7 |
|
T27 |
5 |
auto[1] |
auto[0] |
2411 |
1 |
|
|
T4 |
11 |
|
T12 |
12 |
|
T29 |
10 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T4 |
2 |
|
T29 |
1 |
|
T252 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45866 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1561 |
1 |
|
|
T4 |
25 |
|
T26 |
10 |
|
T27 |
5 |
auto[1] |
auto[0] |
2399 |
1 |
|
|
T4 |
13 |
|
T12 |
9 |
|
T29 |
11 |
auto[1] |
auto[1] |
158 |
1 |
|
|
T12 |
3 |
|
T252 |
1 |
|
T43 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45886 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1541 |
1 |
|
|
T4 |
29 |
|
T26 |
8 |
|
T27 |
9 |
auto[1] |
auto[0] |
2413 |
1 |
|
|
T4 |
12 |
|
T12 |
12 |
|
T29 |
10 |
auto[1] |
auto[1] |
144 |
1 |
|
|
T4 |
1 |
|
T29 |
1 |
|
T252 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45865 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1562 |
1 |
|
|
T4 |
27 |
|
T26 |
8 |
|
T27 |
10 |
auto[1] |
auto[0] |
2420 |
1 |
|
|
T4 |
12 |
|
T12 |
11 |
|
T29 |
11 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T4 |
1 |
|
T12 |
1 |
|
T252 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45855 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1572 |
1 |
|
|
T4 |
28 |
|
T26 |
17 |
|
T27 |
11 |
auto[1] |
auto[0] |
2402 |
1 |
|
|
T4 |
13 |
|
T12 |
12 |
|
T29 |
11 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T251 |
3 |
|
T107 |
1 |
|
T253 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35148 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1176 |
1 |
|
|
T17 |
6 |
|
T18 |
6 |
|
T63 |
5 |
auto[1] |
auto[0] |
13074 |
1 |
|
|
T4 |
159 |
|
T5 |
84 |
|
T6 |
4 |
auto[1] |
auto[1] |
586 |
1 |
|
|
T5 |
10 |
|
T31 |
11 |
|
T101 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35210 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1114 |
1 |
|
|
T17 |
8 |
|
T18 |
6 |
|
T63 |
6 |
auto[1] |
auto[0] |
13069 |
1 |
|
|
T4 |
159 |
|
T5 |
86 |
|
T6 |
4 |
auto[1] |
auto[1] |
591 |
1 |
|
|
T5 |
8 |
|
T31 |
6 |
|
T101 |
4 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35179 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1145 |
1 |
|
|
T15 |
19 |
|
T16 |
11 |
|
T254 |
18 |
auto[1] |
auto[0] |
12886 |
1 |
|
|
T4 |
148 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
774 |
1 |
|
|
T4 |
11 |
|
T32 |
4 |
|
T43 |
10 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35184 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1140 |
1 |
|
|
T17 |
12 |
|
T18 |
16 |
|
T63 |
9 |
auto[1] |
auto[0] |
13069 |
1 |
|
|
T4 |
159 |
|
T5 |
85 |
|
T6 |
4 |
auto[1] |
auto[1] |
591 |
1 |
|
|
T5 |
9 |
|
T31 |
7 |
|
T101 |
8 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31699 |
1 |
|
|
T1 |
1 |
|
T3 |
74 |
|
T4 |
128 |
auto[0] |
auto[1] |
4625 |
1 |
|
|
T2 |
77 |
|
T23 |
86 |
|
T17 |
9 |
auto[1] |
auto[0] |
13061 |
1 |
|
|
T4 |
159 |
|
T5 |
77 |
|
T6 |
4 |
auto[1] |
auto[1] |
599 |
1 |
|
|
T5 |
17 |
|
T31 |
7 |
|
T101 |
4 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35371 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
953 |
1 |
|
|
T4 |
9 |
|
T12 |
2 |
|
T26 |
12 |
auto[1] |
auto[0] |
12959 |
1 |
|
|
T4 |
144 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
701 |
1 |
|
|
T4 |
15 |
|
T27 |
10 |
|
T251 |
2 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35369 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
955 |
1 |
|
|
T4 |
9 |
|
T26 |
8 |
|
T97 |
3 |
auto[1] |
auto[0] |
12972 |
1 |
|
|
T4 |
144 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
688 |
1 |
|
|
T4 |
15 |
|
T27 |
9 |
|
T252 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35282 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1042 |
1 |
|
|
T4 |
12 |
|
T26 |
7 |
|
T97 |
11 |
auto[1] |
auto[0] |
12944 |
1 |
|
|
T4 |
141 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
716 |
1 |
|
|
T4 |
18 |
|
T27 |
5 |
|
T29 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35360 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
964 |
1 |
|
|
T4 |
5 |
|
T12 |
1 |
|
T26 |
9 |
auto[1] |
auto[0] |
12948 |
1 |
|
|
T4 |
142 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
712 |
1 |
|
|
T4 |
17 |
|
T27 |
12 |
|
T29 |
2 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35307 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1017 |
1 |
|
|
T4 |
13 |
|
T26 |
8 |
|
T97 |
11 |
auto[1] |
auto[0] |
12992 |
1 |
|
|
T4 |
142 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
668 |
1 |
|
|
T4 |
17 |
|
T27 |
9 |
|
T29 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35338 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
986 |
1 |
|
|
T4 |
12 |
|
T26 |
17 |
|
T97 |
13 |
auto[1] |
auto[0] |
12919 |
1 |
|
|
T4 |
143 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
741 |
1 |
|
|
T4 |
16 |
|
T27 |
11 |
|
T251 |
3 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35140 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1184 |
1 |
|
|
T17 |
18 |
|
T18 |
12 |
|
T63 |
9 |
auto[1] |
auto[0] |
13111 |
1 |
|
|
T4 |
159 |
|
T5 |
84 |
|
T6 |
4 |
auto[1] |
auto[1] |
549 |
1 |
|
|
T5 |
10 |
|
T31 |
6 |
|
T101 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35155 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1169 |
1 |
|
|
T17 |
11 |
|
T18 |
13 |
|
T63 |
8 |
auto[1] |
auto[0] |
13053 |
1 |
|
|
T4 |
159 |
|
T5 |
80 |
|
T6 |
4 |
auto[1] |
auto[1] |
607 |
1 |
|
|
T5 |
14 |
|
T31 |
6 |
|
T101 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34979 |
1 |
|
|
T1 |
1 |
|
T2 |
77 |
|
T3 |
74 |
auto[0] |
auto[1] |
1345 |
1 |
|
|
T12 |
12 |
|
T255 |
15 |
|
T123 |
11 |
auto[1] |
auto[0] |
12448 |
1 |
|
|
T4 |
146 |
|
T5 |
94 |
|
T6 |
4 |
auto[1] |
auto[1] |
1212 |
1 |
|
|
T4 |
13 |
|
T29 |
11 |
|
T252 |
14 |