Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94156198

1

T1

859

T2

43790

T3

21102

auto[1]

1334910

1

T3

10044

T4

9745

T12

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94165580

1

T1

859

T2

43790

T3

18920

auto[1]

1325528

1

T3

12226

T4

9634

T12

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6872852	1			T1	97		T2	7140		T3	6736
auto[IdleSt]	19977901	1			T1	56		T2	8197		T3	7699
auto[ClkMuxSt]	33711	1			T1	1		T2	77		T3	62
auto[CntIncrSt]	33397	1			T1	1		T2	77		T3	62
auto[CntProgSt]	1421509	1			T1	9		T2	3381		T3	118
auto[TransCheckSt]	26216	1			T1	1		T2	77		T3	50
auto[TokenHashSt]	36450996	1			T1	35		T2	10497		T3	318
auto[FlashRmaSt]	32349	1			T1	1		T3	70		T4	76
auto[TokenCheck0St]	11983	1			T1	1		T3	22		T4	38
auto[TokenCheck1St]	8801	1			T1	1		T3	21		T4	38
auto[TransProgSt]	340484	1			T1	10		T3	32		T4	618
auto[PostTransSt]	11982370	1			T1	646		T2	14344		T3	12
auto[ScrapSt]	161295	1			T3	3		T14	46		T25	3
auto[EscalateSt]	6542267	1			T3	15941		T4	65717		T12	653
auto[InvalidSt]	11593146	1			T4	158696		T12	385		T26	9536

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1831	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11593146	1			T4	158696		T12	385		T26	9536
EscalateSt	6542267	1			T3	15941		T4	65717		T12	653
ScrapSt	161295	1			T3	3		T14	46		T25	3
PostTransSt	11982370	1			T1	646		T2	14344		T3	12
TransProgSt	340484	1			T1	10		T3	32		T4	618
TokenCheck1St	8801	1			T1	1		T3	21		T4	38
TokenCheck0St	11983	1			T1	1		T3	22		T4	38
FlashRmaSt	32349	1			T1	1		T3	70		T4	76
TokenHashSt	36450996	1			T1	35		T2	10497		T3	318
TransCheckSt	26216	1			T1	1		T2	77		T3	50
CntProgSt	1421509	1			T1	9		T2	3381		T3	118
CntIncrSt	33397	1			T1	1		T2	77		T3	62
ClkMuxSt	33711	1			T1	1		T2	77		T3	62
IdleSt	19977901	1			T1	56		T2	8197		T3	7699
ResetSt	6872852	1			T1	97		T2	7140		T3	6736
arcs[ResetSt=>IdleSt]	50330	1			T1	1		T2	78		T3	67
arcs[IdleSt=>ScrapSt]	247	1			T3	1		T14	1		T25	1
arcs[IdleSt=>ClkMuxSt]	33461	1			T1	1		T2	77		T3	62
arcs[ClkMuxSt=>CntIncrSt]	33397	1			T1	1		T2	77		T3	62
arcs[CntIncrSt=>PostTransSt]	1777	1			T5	14		T17	11		T18	13
arcs[CntIncrSt=>CntProgSt]	31555	1			T1	1		T2	77		T3	60
arcs[CntProgSt=>PostTransSt]	4360	1			T4	11		T5	10		T15	19
arcs[CntProgSt=>TransCheckSt]	26216	1			T1	1		T2	77		T3	50
arcs[TransCheckSt=>PostTransSt]	3626	1			T5	10		T17	18		T21	28
arcs[TransCheckSt=>TokenHashSt]	22434	1			T1	1		T2	77		T3	44
arcs[TokenHashSt=>PostTransSt]	9614	1			T2	77		T5	43		T23	86
arcs[TokenHashSt=>FlashRmaSt]	12089	1			T1	1		T3	25		T4	38
arcs[FlashRmaSt=>TokenCheck0St]	11983	1			T1	1		T3	22		T4	38
arcs[TokenCheck0St=>PostTransSt]	3149	1			T5	7		T17	8		T20	19
arcs[TokenCheck0St=>TokenCheck1St]	8801	1			T1	1		T3	21		T4	38
arcs[TokenCheck1St=>PostTransSt]	629	1			T21	4		T63	1		T57	18
arcs[TransProgSt=>PostTransSt]	7263	1			T1	1		T3	9		T4	38
arcs[IdleSt=>EscalateSt]	252	1			T3	3		T25	12		T58	4
arcs[ClkMuxSt=>EscalateSt]	64	1			T25	1		T58	2		T59	3
arcs[CntIncrSt=>EscalateSt]	65	1			T3	2		T25	2		T58	1
arcs[CntProgSt=>EscalateSt]	979	1			T3	10		T25	9		T58	13
arcs[TransCheckSt=>EscalateSt]	156	1			T3	6		T25	4		T58	4
arcs[TokenHashSt=>EscalateSt]	731	1			T3	19		T25	26		T58	13
arcs[FlashRmaSt=>EscalateSt]	106	1			T3	3		T25	2		T58	2
arcs[TokenCheck0St=>EscalateSt]	33	1			T3	1		T59	2		T62	1
arcs[TokenCheck1St=>EscalateSt]	149	1			T3	4		T25	9		T58	2
arcs[TransProgSt=>EscalateSt]	760	1			T3	8		T25	9		T58	10
arcs[PostTransSt=>EscalateSt]	4676	1			T3	9		T4	11		T5	10
arcs[InvalidSt=>EscalateSt]	12491	1			T4	186		T12	4		T26	69

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6872688	1			T1	97		T2	7140		T3	6730
auto[0]	auto[IdleSt]	19977722	1			T1	56		T2	8197		T3	7697
auto[0]	auto[ClkMuxSt]	33665	1			T1	1		T2	77		T3	62
auto[0]	auto[CntIncrSt]	33358	1			T1	1		T2	77		T3	62
auto[0]	auto[CntProgSt]	1420863	1			T1	9		T2	3381		T3	113
auto[0]	auto[TransCheckSt]	26103	1			T1	1		T2	77		T3	47
auto[0]	auto[TokenHashSt]	36450499	1			T1	35		T2	10497		T3	305
auto[0]	auto[FlashRmaSt]	32283	1			T1	1		T3	67		T4	76
auto[0]	auto[TokenCheck0St]	11963	1			T1	1		T3	21		T4	38
auto[0]	auto[TokenCheck1St]	8710	1			T1	1		T3	18		T4	38
auto[0]	auto[TransProgSt]	340002	1			T1	10		T3	27		T4	618
auto[0]	auto[PostTransSt]	11979958	1			T1	646		T2	14344		T3	8
auto[0]	auto[ScrapSt]	161264	1			T3	3		T14	46		T25	3
auto[0]	auto[EscalateSt]	5218489	1			T3	5942		T4	56071		T12	457
auto[0]	auto[InvalidSt]	11586800	1			T4	158601		T12	383		T26	9500
auto[1]	auto[ResetSt]	164	1			T3	6		T25	4		T58	2
auto[1]	auto[IdleSt]	179	1			T3	2		T25	5		T58	3
auto[1]	auto[ClkMuxSt]	46	1			T25	1		T58	2		T59	1
auto[1]	auto[CntIncrSt]	39	1			T25	1		T58	1		T59	1
auto[1]	auto[CntProgSt]	646	1			T3	5		T25	4		T58	8
auto[1]	auto[TransCheckSt]	113	1			T3	3		T25	4		T58	4
auto[1]	auto[TokenHashSt]	497	1			T3	13		T25	15		T58	8
auto[1]	auto[FlashRmaSt]	66	1			T3	3		T25	2		T58	2
auto[1]	auto[TokenCheck0St]	20	1			T3	1		T59	1		T249	1
auto[1]	auto[TokenCheck1St]	91	1			T3	3		T25	3		T58	2
auto[1]	auto[TransProgSt]	482	1			T3	5		T25	5		T58	6
auto[1]	auto[PostTransSt]	2412	1			T3	4		T4	4		T5	5
auto[1]	auto[ScrapSt]	31	1			T59	1		T250	1		T62	5
auto[1]	auto[EscalateSt]	1323778	1			T3	9999		T4	9646		T12	196
auto[1]	auto[InvalidSt]	6346	1			T4	95		T12	2		T26	36

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6872673	1			T1	97		T2	7140		T3	6730
auto[0]	auto[IdleSt]	19977730	1			T1	56		T2	8197		T3	7697
auto[0]	auto[ClkMuxSt]	33675	1			T1	1		T2	77		T3	62
auto[0]	auto[CntIncrSt]	33354	1			T1	1		T2	77		T3	60
auto[0]	auto[CntProgSt]	1420856	1			T1	9		T2	3381		T3	110
auto[0]	auto[TransCheckSt]	26111	1			T1	1		T2	77		T3	46
auto[0]	auto[TokenHashSt]	36450509	1			T1	35		T2	10497		T3	304
auto[0]	auto[FlashRmaSt]	32277	1			T1	1		T3	69		T4	76
auto[0]	auto[TokenCheck0St]	11958	1			T1	1		T3	21		T4	38
auto[0]	auto[TokenCheck1St]	8692	1			T1	1		T3	18		T4	38
auto[0]	auto[TransProgSt]	339941	1			T1	10		T3	25		T4	618
auto[0]	auto[PostTransSt]	11980015	1			T1	646		T2	14344		T3	4
auto[0]	auto[ScrapSt]	161262	1			T3	2		T14	46		T25	2
auto[0]	auto[EscalateSt]	5227695	1			T3	3772		T4	56181		T12	457
auto[0]	auto[InvalidSt]	11587001	1			T4	158605		T12	383		T26	9503
auto[1]	auto[ResetSt]	179	1			T3	6		T25	3		T58	2
auto[1]	auto[IdleSt]	171	1			T3	2		T25	11		T58	3
auto[1]	auto[ClkMuxSt]	36	1			T25	1		T58	2		T59	2
auto[1]	auto[CntIncrSt]	43	1			T3	2		T25	1		T58	1
auto[1]	auto[CntProgSt]	653	1			T3	8		T25	7		T58	9
auto[1]	auto[TransCheckSt]	105	1			T3	4		T25	2		T58	1
auto[1]	auto[TokenHashSt]	487	1			T3	14		T25	16		T58	7
auto[1]	auto[FlashRmaSt]	72	1			T3	1		T25	2		T58	2
auto[1]	auto[TokenCheck0St]	25	1			T3	1		T59	1		T62	1
auto[1]	auto[TokenCheck1St]	109	1			T3	3		T25	7		T62	3
auto[1]	auto[TransProgSt]	543	1			T3	7		T25	6		T58	6
auto[1]	auto[PostTransSt]	2355	1			T3	8		T4	7		T5	5
auto[1]	auto[ScrapSt]	33	1			T3	1		T25	1		T59	1
auto[1]	auto[EscalateSt]	1314572	1			T3	12169		T4	9536		T12	196
auto[1]	auto[InvalidSt]	6145	1			T4	91		T12	2		T26	33