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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.92 97.97 96.03 93.40 97.62 98.73 98.76 95.94


Total test records in report: 992
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T134 /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1701901532 Jul 15 06:32:08 PM PDT 24 Jul 15 06:41:18 PM PDT 24 62500898526 ps
T814 /workspace/coverage/default/36.lc_ctrl_sec_mubi.3844458741 Jul 15 06:31:51 PM PDT 24 Jul 15 06:32:09 PM PDT 24 385792843 ps
T815 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.480516499 Jul 15 06:29:37 PM PDT 24 Jul 15 06:29:38 PM PDT 24 94261752 ps
T816 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2615574131 Jul 15 06:30:22 PM PDT 24 Jul 15 06:30:36 PM PDT 24 1918920180 ps
T817 /workspace/coverage/default/30.lc_ctrl_stress_all.3510248168 Jul 15 06:31:37 PM PDT 24 Jul 15 06:35:18 PM PDT 24 7093490107 ps
T818 /workspace/coverage/default/38.lc_ctrl_sec_token_digest.76530601 Jul 15 06:31:56 PM PDT 24 Jul 15 06:32:07 PM PDT 24 328973414 ps
T819 /workspace/coverage/default/3.lc_ctrl_jtag_priority.3712116816 Jul 15 06:29:42 PM PDT 24 Jul 15 06:29:45 PM PDT 24 85157457 ps
T820 /workspace/coverage/default/14.lc_ctrl_jtag_errors.2542733779 Jul 15 06:30:44 PM PDT 24 Jul 15 06:31:15 PM PDT 24 22161300203 ps
T821 /workspace/coverage/default/45.lc_ctrl_prog_failure.2852363043 Jul 15 06:32:13 PM PDT 24 Jul 15 06:32:16 PM PDT 24 140382949 ps
T822 /workspace/coverage/default/7.lc_ctrl_alert_test.1629798437 Jul 15 06:30:14 PM PDT 24 Jul 15 06:30:16 PM PDT 24 105976985 ps
T823 /workspace/coverage/default/41.lc_ctrl_security_escalation.110169520 Jul 15 06:32:11 PM PDT 24 Jul 15 06:32:25 PM PDT 24 1047023173 ps
T824 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3712090587 Jul 15 06:30:50 PM PDT 24 Jul 15 06:30:51 PM PDT 24 42241434 ps
T825 /workspace/coverage/default/23.lc_ctrl_stress_all.663926645 Jul 15 06:31:22 PM PDT 24 Jul 15 06:32:45 PM PDT 24 5531453789 ps
T826 /workspace/coverage/default/48.lc_ctrl_sec_mubi.3008677933 Jul 15 06:32:27 PM PDT 24 Jul 15 06:32:35 PM PDT 24 469085442 ps
T827 /workspace/coverage/default/4.lc_ctrl_alert_test.3776021491 Jul 15 06:29:57 PM PDT 24 Jul 15 06:29:59 PM PDT 24 17913741 ps
T828 /workspace/coverage/default/1.lc_ctrl_jtag_errors.2067700626 Jul 15 06:29:26 PM PDT 24 Jul 15 06:30:08 PM PDT 24 5474179431 ps
T186 /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3907376932 Jul 15 06:31:58 PM PDT 24 Jul 15 06:39:52 PM PDT 24 97825951402 ps
T829 /workspace/coverage/default/26.lc_ctrl_jtag_access.1571056053 Jul 15 06:31:23 PM PDT 24 Jul 15 06:31:33 PM PDT 24 742824827 ps
T830 /workspace/coverage/default/35.lc_ctrl_state_failure.395783412 Jul 15 06:31:43 PM PDT 24 Jul 15 06:32:17 PM PDT 24 5023595111 ps
T831 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1159431821 Jul 15 06:29:53 PM PDT 24 Jul 15 06:30:01 PM PDT 24 1250731468 ps
T832 /workspace/coverage/default/39.lc_ctrl_stress_all.1376682789 Jul 15 06:32:02 PM PDT 24 Jul 15 06:33:37 PM PDT 24 15285689288 ps
T833 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.993324555 Jul 15 06:29:25 PM PDT 24 Jul 15 06:29:48 PM PDT 24 1913454893 ps
T834 /workspace/coverage/default/12.lc_ctrl_jtag_errors.1777412199 Jul 15 06:30:31 PM PDT 24 Jul 15 06:30:55 PM PDT 24 9636938883 ps
T835 /workspace/coverage/default/27.lc_ctrl_alert_test.2372598422 Jul 15 06:31:37 PM PDT 24 Jul 15 06:31:39 PM PDT 24 22843492 ps
T836 /workspace/coverage/default/48.lc_ctrl_jtag_access.2037542231 Jul 15 06:32:25 PM PDT 24 Jul 15 06:32:42 PM PDT 24 648079064 ps
T837 /workspace/coverage/default/5.lc_ctrl_security_escalation.1033757725 Jul 15 06:29:53 PM PDT 24 Jul 15 06:30:05 PM PDT 24 841791484 ps
T838 /workspace/coverage/default/15.lc_ctrl_security_escalation.1925637283 Jul 15 06:30:51 PM PDT 24 Jul 15 06:31:00 PM PDT 24 194921370 ps
T839 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2940442184 Jul 15 06:31:19 PM PDT 24 Jul 15 06:31:33 PM PDT 24 324926432 ps
T840 /workspace/coverage/default/35.lc_ctrl_sec_mubi.4006578116 Jul 15 06:31:51 PM PDT 24 Jul 15 06:32:10 PM PDT 24 1602475179 ps
T841 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2717826352 Jul 15 06:31:21 PM PDT 24 Jul 15 06:31:36 PM PDT 24 378861795 ps
T842 /workspace/coverage/default/16.lc_ctrl_smoke.1316098575 Jul 15 06:30:50 PM PDT 24 Jul 15 06:30:53 PM PDT 24 39203265 ps
T843 /workspace/coverage/default/26.lc_ctrl_stress_all.649825695 Jul 15 06:31:22 PM PDT 24 Jul 15 06:36:16 PM PDT 24 17894377346 ps
T844 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.761257777 Jul 15 06:29:21 PM PDT 24 Jul 15 06:29:56 PM PDT 24 1309211069 ps
T845 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1253390135 Jul 15 06:30:16 PM PDT 24 Jul 15 06:30:26 PM PDT 24 581254082 ps
T846 /workspace/coverage/default/16.lc_ctrl_errors.2652240460 Jul 15 06:30:53 PM PDT 24 Jul 15 06:31:11 PM PDT 24 478419768 ps
T847 /workspace/coverage/default/25.lc_ctrl_jtag_access.3406850538 Jul 15 06:31:21 PM PDT 24 Jul 15 06:31:29 PM PDT 24 4496749881 ps
T848 /workspace/coverage/default/1.lc_ctrl_security_escalation.4143067748 Jul 15 06:29:25 PM PDT 24 Jul 15 06:29:36 PM PDT 24 624968936 ps
T849 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3468449341 Jul 15 06:29:31 PM PDT 24 Jul 15 06:29:45 PM PDT 24 6965932751 ps
T850 /workspace/coverage/default/8.lc_ctrl_stress_all.70549733 Jul 15 06:30:23 PM PDT 24 Jul 15 06:36:58 PM PDT 24 26297947945 ps
T851 /workspace/coverage/default/17.lc_ctrl_state_post_trans.2180449747 Jul 15 06:30:56 PM PDT 24 Jul 15 06:31:00 PM PDT 24 42261626 ps
T852 /workspace/coverage/default/19.lc_ctrl_sec_mubi.3436422557 Jul 15 06:31:08 PM PDT 24 Jul 15 06:31:22 PM PDT 24 1137847369 ps
T853 /workspace/coverage/default/43.lc_ctrl_sec_mubi.2396416979 Jul 15 06:32:06 PM PDT 24 Jul 15 06:32:22 PM PDT 24 1100947744 ps
T854 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2502523706 Jul 15 06:30:01 PM PDT 24 Jul 15 06:30:27 PM PDT 24 8459055818 ps
T855 /workspace/coverage/default/17.lc_ctrl_state_failure.1104323579 Jul 15 06:30:57 PM PDT 24 Jul 15 06:31:25 PM PDT 24 2554142153 ps
T856 /workspace/coverage/default/41.lc_ctrl_alert_test.3294672178 Jul 15 06:32:08 PM PDT 24 Jul 15 06:32:10 PM PDT 24 48202475 ps
T857 /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.152759983 Jul 15 06:30:24 PM PDT 24 Jul 15 06:30:49 PM PDT 24 1622425996 ps
T858 /workspace/coverage/default/14.lc_ctrl_state_failure.3831882923 Jul 15 06:30:45 PM PDT 24 Jul 15 06:31:17 PM PDT 24 901258217 ps
T859 /workspace/coverage/default/33.lc_ctrl_state_post_trans.2644133245 Jul 15 06:31:45 PM PDT 24 Jul 15 06:31:53 PM PDT 24 74425742 ps
T860 /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1394541317 Jul 15 06:30:55 PM PDT 24 Jul 15 06:32:09 PM PDT 24 2025141303 ps
T861 /workspace/coverage/default/44.lc_ctrl_stress_all.1066241345 Jul 15 06:32:16 PM PDT 24 Jul 15 06:32:46 PM PDT 24 1910595791 ps
T862 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2581897263 Jul 15 06:31:05 PM PDT 24 Jul 15 06:31:19 PM PDT 24 1809176168 ps
T863 /workspace/coverage/default/13.lc_ctrl_security_escalation.3765096881 Jul 15 06:30:42 PM PDT 24 Jul 15 06:30:50 PM PDT 24 588845233 ps
T864 /workspace/coverage/default/19.lc_ctrl_smoke.504181362 Jul 15 06:31:07 PM PDT 24 Jul 15 06:31:11 PM PDT 24 213283903 ps
T865 /workspace/coverage/default/5.lc_ctrl_jtag_access.3389228592 Jul 15 06:30:05 PM PDT 24 Jul 15 06:30:24 PM PDT 24 3626351890 ps
T866 /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2586470268 Jul 15 06:30:51 PM PDT 24 Jul 15 06:31:03 PM PDT 24 2541021059 ps
T867 /workspace/coverage/default/34.lc_ctrl_smoke.4237781433 Jul 15 06:31:45 PM PDT 24 Jul 15 06:31:48 PM PDT 24 173240948 ps
T868 /workspace/coverage/default/19.lc_ctrl_jtag_access.2292772497 Jul 15 06:31:06 PM PDT 24 Jul 15 06:31:20 PM PDT 24 896868148 ps
T140 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4171516211 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:57 PM PDT 24 140292537 ps
T141 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2993293731 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:57 PM PDT 24 30458297 ps
T142 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.474001501 Jul 15 07:24:52 PM PDT 24 Jul 15 07:25:29 PM PDT 24 118356435 ps
T167 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.95518308 Jul 15 07:24:37 PM PDT 24 Jul 15 07:25:14 PM PDT 24 78843473 ps
T168 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2164795961 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:52 PM PDT 24 118910443 ps
T869 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.544853516 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:03 PM PDT 24 37363966 ps
T135 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.508512332 Jul 15 07:24:41 PM PDT 24 Jul 15 07:25:16 PM PDT 24 27808353 ps
T136 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4222775969 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:54 PM PDT 24 321801438 ps
T199 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.790331654 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:29 PM PDT 24 101002366 ps
T224 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1088035098 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:57 PM PDT 24 71345648 ps
T131 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1236275301 Jul 15 07:24:13 PM PDT 24 Jul 15 07:24:53 PM PDT 24 170090748 ps
T132 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2429257524 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:25 PM PDT 24 311988754 ps
T133 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2654218040 Jul 15 07:24:05 PM PDT 24 Jul 15 07:24:50 PM PDT 24 256290429 ps
T870 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1907725569 Jul 15 07:24:42 PM PDT 24 Jul 15 07:25:16 PM PDT 24 30134055 ps
T155 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.580173638 Jul 15 07:24:31 PM PDT 24 Jul 15 07:25:10 PM PDT 24 179032751 ps
T237 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2414202667 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:14 PM PDT 24 37597473 ps
T166 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2139345364 Jul 15 07:24:32 PM PDT 24 Jul 15 07:25:08 PM PDT 24 443099225 ps
T169 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2004193756 Jul 15 07:24:42 PM PDT 24 Jul 15 07:25:33 PM PDT 24 3668425962 ps
T187 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1344816887 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:03 PM PDT 24 109402686 ps
T137 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1863884476 Jul 15 07:24:37 PM PDT 24 Jul 15 07:25:15 PM PDT 24 114940124 ps
T188 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3685846651 Jul 15 07:24:44 PM PDT 24 Jul 15 07:25:21 PM PDT 24 56882011 ps
T164 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.747969345 Jul 15 07:24:29 PM PDT 24 Jul 15 07:25:10 PM PDT 24 1610287318 ps
T871 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.484448856 Jul 15 07:24:13 PM PDT 24 Jul 15 07:24:52 PM PDT 24 99211508 ps
T138 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1946899899 Jul 15 07:24:45 PM PDT 24 Jul 15 07:25:23 PM PDT 24 222567094 ps
T872 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1962613580 Jul 15 07:24:41 PM PDT 24 Jul 15 07:25:16 PM PDT 24 17755028 ps
T238 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.542080781 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:27 PM PDT 24 30005271 ps
T873 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2116339903 Jul 15 07:24:29 PM PDT 24 Jul 15 07:25:06 PM PDT 24 223559292 ps
T225 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.557595767 Jul 15 07:24:11 PM PDT 24 Jul 15 07:24:51 PM PDT 24 13405145 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1213890933 Jul 15 07:24:28 PM PDT 24 Jul 15 07:25:05 PM PDT 24 28186616 ps
T139 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.120993882 Jul 15 07:24:51 PM PDT 24 Jul 15 07:25:30 PM PDT 24 30925304 ps
T239 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3046013584 Jul 15 07:24:55 PM PDT 24 Jul 15 07:25:33 PM PDT 24 11578225 ps
T875 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.560221209 Jul 15 07:24:28 PM PDT 24 Jul 15 07:25:08 PM PDT 24 296035883 ps
T152 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4153876678 Jul 15 07:24:45 PM PDT 24 Jul 15 07:25:24 PM PDT 24 76045062 ps
T876 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2809026794 Jul 15 07:24:07 PM PDT 24 Jul 15 07:24:51 PM PDT 24 145598868 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.627210723 Jul 15 07:24:25 PM PDT 24 Jul 15 07:25:25 PM PDT 24 1158663314 ps
T156 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.214484446 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:27 PM PDT 24 39501381 ps
T153 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3713132942 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:59 PM PDT 24 293324382 ps
T149 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3340805502 Jul 15 07:24:48 PM PDT 24 Jul 15 07:25:28 PM PDT 24 296409812 ps
T878 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.356546355 Jul 15 07:24:25 PM PDT 24 Jul 15 07:25:03 PM PDT 24 151097151 ps
T240 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2579033232 Jul 15 07:24:40 PM PDT 24 Jul 15 07:25:16 PM PDT 24 95979125 ps
T879 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1408234533 Jul 15 07:24:32 PM PDT 24 Jul 15 07:25:08 PM PDT 24 38617387 ps
T241 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2946232967 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:23 PM PDT 24 54721476 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3269793996 Jul 15 07:24:28 PM PDT 24 Jul 15 07:25:06 PM PDT 24 44924798 ps
T162 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3181842129 Jul 15 07:24:30 PM PDT 24 Jul 15 07:25:07 PM PDT 24 61696075 ps
T189 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1849806349 Jul 15 07:24:17 PM PDT 24 Jul 15 07:24:54 PM PDT 24 80001335 ps
T242 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.948809559 Jul 15 07:24:40 PM PDT 24 Jul 15 07:25:16 PM PDT 24 127996430 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3456609207 Jul 15 07:24:26 PM PDT 24 Jul 15 07:25:52 PM PDT 24 9737761331 ps
T148 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.84718260 Jul 15 07:24:51 PM PDT 24 Jul 15 07:25:30 PM PDT 24 52062283 ps
T882 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.709623246 Jul 15 07:24:13 PM PDT 24 Jul 15 07:24:59 PM PDT 24 3470411145 ps
T150 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2988173713 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:07 PM PDT 24 286390724 ps
T165 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.780637571 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:15 PM PDT 24 359134488 ps
T226 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2888926078 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:56 PM PDT 24 42165641 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3665472332 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:52 PM PDT 24 65613085 ps
T151 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2150254409 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:54 PM PDT 24 47331139 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2588996888 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:57 PM PDT 24 206928598 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3898262587 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:15 PM PDT 24 79735730 ps
T886 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1231732932 Jul 15 07:24:45 PM PDT 24 Jul 15 07:25:22 PM PDT 24 25401103 ps
T887 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2786141972 Jul 15 07:24:51 PM PDT 24 Jul 15 07:25:29 PM PDT 24 36867193 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4077169332 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:04 PM PDT 24 41525344 ps
T143 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1689626729 Jul 15 07:24:49 PM PDT 24 Jul 15 07:25:28 PM PDT 24 49206676 ps
T889 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.818271586 Jul 15 07:24:41 PM PDT 24 Jul 15 07:25:16 PM PDT 24 98061896 ps
T890 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3624680624 Jul 15 07:24:52 PM PDT 24 Jul 15 07:25:32 PM PDT 24 568693883 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.694701550 Jul 15 07:24:11 PM PDT 24 Jul 15 07:24:53 PM PDT 24 61782331 ps
T892 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.836834326 Jul 15 07:24:45 PM PDT 24 Jul 15 07:25:23 PM PDT 24 31061486 ps
T893 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3414585165 Jul 15 07:24:51 PM PDT 24 Jul 15 07:25:28 PM PDT 24 30432290 ps
T894 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2261180447 Jul 15 07:24:51 PM PDT 24 Jul 15 07:25:30 PM PDT 24 80777930 ps
T895 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.930593421 Jul 15 07:24:40 PM PDT 24 Jul 15 07:25:20 PM PDT 24 617084399 ps
T896 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2825666963 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:29 PM PDT 24 51740161 ps
T897 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4172185773 Jul 15 07:24:28 PM PDT 24 Jul 15 07:25:12 PM PDT 24 838140596 ps
T898 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1217502795 Jul 15 07:24:31 PM PDT 24 Jul 15 07:25:06 PM PDT 24 764986363 ps
T227 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4022872439 Jul 15 07:24:14 PM PDT 24 Jul 15 07:24:52 PM PDT 24 42135699 ps
T899 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4094716721 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:29 PM PDT 24 38611177 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.605249664 Jul 15 07:24:21 PM PDT 24 Jul 15 07:25:03 PM PDT 24 245303571 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2749248110 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:58 PM PDT 24 77630830 ps
T158 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3114505664 Jul 15 07:24:45 PM PDT 24 Jul 15 07:25:23 PM PDT 24 257103469 ps
T902 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3337775651 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:23 PM PDT 24 81054057 ps
T154 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2795660308 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:16 PM PDT 24 440646355 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2972008440 Jul 15 07:24:30 PM PDT 24 Jul 15 07:25:06 PM PDT 24 17061404 ps
T904 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.56577561 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:15 PM PDT 24 189412141 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4227145106 Jul 15 07:24:05 PM PDT 24 Jul 15 07:24:48 PM PDT 24 36357824 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3003090962 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:04 PM PDT 24 41834725 ps
T907 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3278177706 Jul 15 07:24:40 PM PDT 24 Jul 15 07:25:16 PM PDT 24 90881404 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.595421824 Jul 15 07:24:20 PM PDT 24 Jul 15 07:25:08 PM PDT 24 2637685075 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2001458967 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:59 PM PDT 24 166949571 ps
T163 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1133720238 Jul 15 07:24:44 PM PDT 24 Jul 15 07:25:20 PM PDT 24 221201541 ps
T910 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3003112936 Jul 15 07:24:43 PM PDT 24 Jul 15 07:25:20 PM PDT 24 41536644 ps
T911 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1152231332 Jul 15 07:24:18 PM PDT 24 Jul 15 07:24:59 PM PDT 24 1240946300 ps
T144 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2090622949 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:30 PM PDT 24 118510698 ps
T912 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1211151115 Jul 15 07:24:56 PM PDT 24 Jul 15 07:25:35 PM PDT 24 48720834 ps
T913 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1642723860 Jul 15 07:24:42 PM PDT 24 Jul 15 07:25:16 PM PDT 24 49457927 ps
T914 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2128185046 Jul 15 07:24:52 PM PDT 24 Jul 15 07:25:31 PM PDT 24 21938982 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3964818692 Jul 15 07:24:16 PM PDT 24 Jul 15 07:24:54 PM PDT 24 43328660 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1783911682 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:52 PM PDT 24 30526244 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.759638727 Jul 15 07:24:25 PM PDT 24 Jul 15 07:25:03 PM PDT 24 47618718 ps
T228 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2401939083 Jul 15 07:24:47 PM PDT 24 Jul 15 07:25:26 PM PDT 24 15803615 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.459606546 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:12 PM PDT 24 6721534707 ps
T919 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1079199851 Jul 15 07:24:43 PM PDT 24 Jul 15 07:25:19 PM PDT 24 27557586 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3322699055 Jul 15 07:24:21 PM PDT 24 Jul 15 07:24:59 PM PDT 24 27701101 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3709119939 Jul 15 07:24:41 PM PDT 24 Jul 15 07:25:16 PM PDT 24 33697717 ps
T922 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.592232636 Jul 15 07:24:48 PM PDT 24 Jul 15 07:25:26 PM PDT 24 22932852 ps
T159 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.390389154 Jul 15 07:24:31 PM PDT 24 Jul 15 07:25:09 PM PDT 24 291099421 ps
T923 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1735780195 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:14 PM PDT 24 59049248 ps
T924 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3934580375 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:56 PM PDT 24 98064665 ps
T147 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1484011873 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:31 PM PDT 24 122692629 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3392630669 Jul 15 07:24:39 PM PDT 24 Jul 15 07:25:18 PM PDT 24 2101301544 ps
T926 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3296921213 Jul 15 07:24:51 PM PDT 24 Jul 15 07:25:29 PM PDT 24 24060774 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1829198526 Jul 15 07:24:26 PM PDT 24 Jul 15 07:25:03 PM PDT 24 106484706 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.472959115 Jul 15 07:24:20 PM PDT 24 Jul 15 07:25:08 PM PDT 24 1018544785 ps
T929 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4069786951 Jul 15 07:24:13 PM PDT 24 Jul 15 07:24:52 PM PDT 24 700420676 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2291050581 Jul 15 07:24:19 PM PDT 24 Jul 15 07:25:12 PM PDT 24 763888856 ps
T931 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.376182841 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:27 PM PDT 24 48752549 ps
T229 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3887595390 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:52 PM PDT 24 124876322 ps
T932 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1721372767 Jul 15 07:24:36 PM PDT 24 Jul 15 07:25:11 PM PDT 24 19892535 ps
T230 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2954400307 Jul 15 07:24:43 PM PDT 24 Jul 15 07:25:18 PM PDT 24 49275064 ps
T933 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1289725166 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:23 PM PDT 24 35168131 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2671150482 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:57 PM PDT 24 39542743 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1750192191 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:04 PM PDT 24 41789790 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.433918413 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:56 PM PDT 24 25925704 ps
T937 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.859143548 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:14 PM PDT 24 50463063 ps
T938 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3266079690 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:56 PM PDT 24 13755982 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.422788618 Jul 15 07:24:29 PM PDT 24 Jul 15 07:25:15 PM PDT 24 2032285733 ps
T940 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.330913777 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:14 PM PDT 24 28727077 ps
T941 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1903718918 Jul 15 07:24:37 PM PDT 24 Jul 15 07:25:13 PM PDT 24 84591208 ps
T231 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.782525988 Jul 15 07:24:30 PM PDT 24 Jul 15 07:25:06 PM PDT 24 164143296 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3644386783 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:57 PM PDT 24 148647380 ps
T232 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3202369367 Jul 15 07:24:25 PM PDT 24 Jul 15 07:25:03 PM PDT 24 13792806 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2755006628 Jul 15 07:24:23 PM PDT 24 Jul 15 07:25:02 PM PDT 24 240551131 ps
T944 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1418596118 Jul 15 07:24:30 PM PDT 24 Jul 15 07:25:07 PM PDT 24 285539433 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3844523038 Jul 15 07:24:25 PM PDT 24 Jul 15 07:25:04 PM PDT 24 203746233 ps
T946 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1765418220 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:22 PM PDT 24 12885232 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.362737898 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:14 PM PDT 24 32022927 ps
T948 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1942629785 Jul 15 07:24:28 PM PDT 24 Jul 15 07:25:04 PM PDT 24 73418287 ps
T949 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.777449399 Jul 15 07:24:34 PM PDT 24 Jul 15 07:25:09 PM PDT 24 34088251 ps
T950 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4094954412 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:58 PM PDT 24 229263214 ps
T951 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.331178708 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:25 PM PDT 24 400348254 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.77265945 Jul 15 07:24:26 PM PDT 24 Jul 15 07:25:05 PM PDT 24 422938608 ps
T145 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2665804701 Jul 15 07:24:37 PM PDT 24 Jul 15 07:25:16 PM PDT 24 378883107 ps
T157 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3987205437 Jul 15 07:24:22 PM PDT 24 Jul 15 07:25:00 PM PDT 24 63248011 ps
T953 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3641850732 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:23 PM PDT 24 14693777 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2045880220 Jul 15 07:24:26 PM PDT 24 Jul 15 07:25:04 PM PDT 24 65224089 ps
T955 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3446212965 Jul 15 07:24:32 PM PDT 24 Jul 15 07:25:10 PM PDT 24 74249256 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1143523324 Jul 15 07:24:06 PM PDT 24 Jul 15 07:24:50 PM PDT 24 323502867 ps
T233 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.320853881 Jul 15 07:24:25 PM PDT 24 Jul 15 07:25:03 PM PDT 24 21045556 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.754992838 Jul 15 07:24:08 PM PDT 24 Jul 15 07:24:53 PM PDT 24 5823434344 ps
T958 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.683517621 Jul 15 07:24:28 PM PDT 24 Jul 15 07:25:07 PM PDT 24 68932049 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.67789326 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:57 PM PDT 24 35819546 ps
T960 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2098087756 Jul 15 07:24:05 PM PDT 24 Jul 15 07:24:49 PM PDT 24 244288186 ps
T961 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1554199081 Jul 15 07:24:11 PM PDT 24 Jul 15 07:25:00 PM PDT 24 352071057 ps
T962 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3000539048 Jul 15 07:24:44 PM PDT 24 Jul 15 07:25:23 PM PDT 24 375777246 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.194275654 Jul 15 07:24:38 PM PDT 24 Jul 15 07:25:21 PM PDT 24 977675029 ps
T146 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2059332147 Jul 15 07:24:23 PM PDT 24 Jul 15 07:25:01 PM PDT 24 405724102 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1057373947 Jul 15 07:24:06 PM PDT 24 Jul 15 07:24:53 PM PDT 24 626633692 ps
T235 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.291628735 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:57 PM PDT 24 21189344 ps
T965 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.762474651 Jul 15 07:24:21 PM PDT 24 Jul 15 07:25:00 PM PDT 24 252283571 ps
T966 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.641453759 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:23 PM PDT 24 52132664 ps
T967 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097741049 Jul 15 07:24:31 PM PDT 24 Jul 15 07:25:09 PM PDT 24 573329756 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2406863693 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:56 PM PDT 24 55358045 ps
T969 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1204047811 Jul 15 07:24:11 PM PDT 24 Jul 15 07:24:52 PM PDT 24 24886636 ps
T161 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1299083421 Jul 15 07:24:51 PM PDT 24 Jul 15 07:25:30 PM PDT 24 46912336 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2950278942 Jul 15 07:24:20 PM PDT 24 Jul 15 07:24:58 PM PDT 24 79524861 ps
T971 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2266165011 Jul 15 07:24:26 PM PDT 24 Jul 15 07:25:04 PM PDT 24 117397175 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.900188482 Jul 15 07:24:19 PM PDT 24 Jul 15 07:24:59 PM PDT 24 139623339 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3362583007 Jul 15 07:24:26 PM PDT 24 Jul 15 07:25:08 PM PDT 24 282161501 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.49289001 Jul 15 07:24:21 PM PDT 24 Jul 15 07:25:01 PM PDT 24 483261530 ps
T975 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3195403698 Jul 15 07:24:50 PM PDT 24 Jul 15 07:25:27 PM PDT 24 20644224 ps
T234 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1091058556 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:52 PM PDT 24 22252120 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1066156396 Jul 15 07:24:32 PM PDT 24 Jul 15 07:25:13 PM PDT 24 333629984 ps
T977 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.447719931 Jul 15 07:24:03 PM PDT 24 Jul 15 07:24:48 PM PDT 24 31401702 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3291313472 Jul 15 07:24:39 PM PDT 24 Jul 15 07:25:33 PM PDT 24 868299441 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1649781570 Jul 15 07:24:36 PM PDT 24 Jul 15 07:25:13 PM PDT 24 390276129 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1247498513 Jul 15 07:24:14 PM PDT 24 Jul 15 07:24:52 PM PDT 24 28690184 ps
T981 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.457098737 Jul 15 07:24:45 PM PDT 24 Jul 15 07:25:22 PM PDT 24 31790476 ps
T982 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1638434093 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:52 PM PDT 24 40994988 ps
T983 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.132642 Jul 15 07:24:27 PM PDT 24 Jul 15 07:25:04 PM PDT 24 99000960 ps
T160 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1931239359 Jul 15 07:24:46 PM PDT 24 Jul 15 07:25:25 PM PDT 24 98040241 ps
T984 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1504007170 Jul 15 07:24:31 PM PDT 24 Jul 15 07:25:06 PM PDT 24 81327170 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.599727049 Jul 15 07:24:41 PM PDT 24 Jul 15 07:25:17 PM PDT 24 103404573 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3976584123 Jul 15 07:24:39 PM PDT 24 Jul 15 07:25:19 PM PDT 24 957490653 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.79458782 Jul 15 07:24:12 PM PDT 24 Jul 15 07:24:52 PM PDT 24 21760545 ps
T236 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3984844237 Jul 15 07:24:48 PM PDT 24 Jul 15 07:25:27 PM PDT 24 20120332 ps
T988 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.694433376 Jul 15 07:24:39 PM PDT 24 Jul 15 07:25:16 PM PDT 24 703233187 ps
T989 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2200930990 Jul 15 07:24:11 PM PDT 24 Jul 15 07:24:51 PM PDT 24 15199546 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.461624428 Jul 15 07:24:07 PM PDT 24 Jul 15 07:24:52 PM PDT 24 119814537 ps
T991 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2164450973 Jul 15 07:24:26 PM PDT 24 Jul 15 07:25:16 PM PDT 24 2401537468 ps
T992 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2559601895 Jul 15 07:24:41 PM PDT 24 Jul 15 07:25:16 PM PDT 24 15071106 ps

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3919503100
Short name T4
Test name
Test status
Simulation time 7882456945 ps
CPU time 113.9 seconds
Started Jul 15 06:29:34 PM PDT 24
Finished Jul 15 06:31:28 PM PDT 24
Peak memory 278904 kb
Host smart-9718e8ca-da5c-4efa-ab61-09e18901d689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919503100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3919503100
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.838957569
Short name T3
Test name
Test status
Simulation time 311483873 ps
CPU time 11.95 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:32:04 PM PDT 24
Peak memory 225936 kb
Host smart-a12b889c-5b28-47ee-9980-b69500bca706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838957569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.838957569
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.492059279
Short name T20
Test name
Test status
Simulation time 421147224 ps
CPU time 18.38 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:40 PM PDT 24
Peak memory 219908 kb
Host smart-d2980e9c-6b05-4e5c-917e-c7b76fe0134a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492059279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.492059279
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3658000548
Short name T5
Test name
Test status
Simulation time 3656551625 ps
CPU time 104.01 seconds
Started Jul 15 06:29:39 PM PDT 24
Finished Jul 15 06:31:24 PM PDT 24
Peak memory 219316 kb
Host smart-989e93a5-b514-4be2-929a-1883f1cebcd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658000548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3658000548
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4222775969
Short name T136
Test name
Test status
Simulation time 321801438 ps
CPU time 3.19 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:54 PM PDT 24
Peak memory 218692 kb
Host smart-158e4a6d-f23d-4c92-9629-7c86b07111e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422277
5969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4222775969
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.520236630
Short name T7
Test name
Test status
Simulation time 212006855 ps
CPU time 1.35 seconds
Started Jul 15 06:30:45 PM PDT 24
Finished Jul 15 06:30:47 PM PDT 24
Peak memory 217472 kb
Host smart-7151c916-960a-4000-8432-9da08447df78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520236630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.520236630
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1608593052
Short name T60
Test name
Test status
Simulation time 473164414 ps
CPU time 25.79 seconds
Started Jul 15 06:29:46 PM PDT 24
Finished Jul 15 06:30:12 PM PDT 24
Peak memory 281628 kb
Host smart-47625817-b541-4690-af70-f12179c482c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608593052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1608593052
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3674552842
Short name T67
Test name
Test status
Simulation time 15202175742 ps
CPU time 506.17 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:40:04 PM PDT 24
Peak memory 281320 kb
Host smart-5297142e-8044-42d5-a647-4859bc53e4bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3674552842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3674552842
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2327601275
Short name T21
Test name
Test status
Simulation time 798714186 ps
CPU time 8.96 seconds
Started Jul 15 06:32:22 PM PDT 24
Finished Jul 15 06:32:32 PM PDT 24
Peak memory 218112 kb
Host smart-d37d0ff6-e4d9-4f9d-b810-beb2cb8931d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327601275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2327601275
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1546228314
Short name T25
Test name
Test status
Simulation time 396330847 ps
CPU time 11.29 seconds
Started Jul 15 06:31:01 PM PDT 24
Finished Jul 15 06:31:13 PM PDT 24
Peak memory 225872 kb
Host smart-0db83ba0-6bca-4097-b671-4e313b0c446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546228314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1546228314
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2429257524
Short name T132
Test name
Test status
Simulation time 311988754 ps
CPU time 2.98 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:25 PM PDT 24
Peak memory 222408 kb
Host smart-a5ba6a25-07b3-41a9-9996-05bb98f92356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429257524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2429257524
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.210591196
Short name T171
Test name
Test status
Simulation time 48647743748 ps
CPU time 254.36 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:34:17 PM PDT 24
Peak memory 279148 kb
Host smart-155884a2-8aac-4595-bbf6-e9410c5ea625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=210591196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.210591196
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.106817483
Short name T97
Test name
Test status
Simulation time 306557202 ps
CPU time 29.17 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 250900 kb
Host smart-959d7d09-4b73-480f-849e-7c5df263236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106817483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.106817483
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4022872439
Short name T227
Test name
Test status
Simulation time 42135699 ps
CPU time 1.01 seconds
Started Jul 15 07:24:14 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 209416 kb
Host smart-b56e9f4d-132f-4f4e-b0a9-d0ac3b982636
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022872439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4022872439
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3770611432
Short name T102
Test name
Test status
Simulation time 18730242 ps
CPU time 0.93 seconds
Started Jul 15 06:30:40 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 209044 kb
Host smart-f3e7337d-b03f-411b-990a-aa78681b69ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770611432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3770611432
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3535794363
Short name T49
Test name
Test status
Simulation time 661879620 ps
CPU time 14.7 seconds
Started Jul 15 06:30:49 PM PDT 24
Finished Jul 15 06:31:04 PM PDT 24
Peak memory 218164 kb
Host smart-315da073-780b-4ced-b142-50a30b33679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535794363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3535794363
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3570349256
Short name T55
Test name
Test status
Simulation time 160400076113 ps
CPU time 890.34 seconds
Started Jul 15 06:31:52 PM PDT 24
Finished Jul 15 06:46:43 PM PDT 24
Peak memory 545396 kb
Host smart-34086ae1-31c8-4b15-a794-e1f53cc70270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3570349256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3570349256
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2988173713
Short name T150
Test name
Test status
Simulation time 286390724 ps
CPU time 4.88 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:07 PM PDT 24
Peak memory 217488 kb
Host smart-441e6568-c8cd-4393-862c-c6a3e45fe57b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988173713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2988173713
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3713132942
Short name T153
Test name
Test status
Simulation time 293324382 ps
CPU time 3.39 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:59 PM PDT 24
Peak memory 217516 kb
Host smart-cca90e69-93e1-4ab3-a10d-e31b7c62801c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713132942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3713132942
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.577526016
Short name T123
Test name
Test status
Simulation time 264068777 ps
CPU time 7.13 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:32:06 PM PDT 24
Peak memory 250936 kb
Host smart-7b3053c6-5190-4e45-a9d5-3b363951355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577526016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.577526016
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3987205437
Short name T157
Test name
Test status
Simulation time 63248011 ps
CPU time 2.09 seconds
Started Jul 15 07:24:22 PM PDT 24
Finished Jul 15 07:25:00 PM PDT 24
Peak memory 221956 kb
Host smart-98214ae1-a841-4c7d-8e16-fa1c1080ff29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987205437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3987205437
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3010012101
Short name T185
Test name
Test status
Simulation time 115471501043 ps
CPU time 727.95 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:43:48 PM PDT 24
Peak memory 693412 kb
Host smart-c22529e3-333b-4b88-9797-1f3fbb8828f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3010012101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3010012101
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3527767470
Short name T39
Test name
Test status
Simulation time 3119438025 ps
CPU time 8.77 seconds
Started Jul 15 06:29:19 PM PDT 24
Finished Jul 15 06:29:29 PM PDT 24
Peak memory 217592 kb
Host smart-8be02641-74a7-4d54-b842-be6f7b34c113
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527767470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3527767470
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3104369676
Short name T2
Test name
Test status
Simulation time 951971319 ps
CPU time 12.19 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:29 PM PDT 24
Peak memory 225984 kb
Host smart-791db25b-42c7-4e8b-8297-5d0a2bb44d90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104369676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3104369676
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1931239359
Short name T160
Test name
Test status
Simulation time 98040241 ps
CPU time 3.81 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:25 PM PDT 24
Peak memory 217500 kb
Host smart-afea8474-f780-46a5-9bdb-75672db5f292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931239359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1931239359
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3340805502
Short name T149
Test name
Test status
Simulation time 296409812 ps
CPU time 2.77 seconds
Started Jul 15 07:24:48 PM PDT 24
Finished Jul 15 07:25:28 PM PDT 24
Peak memory 222016 kb
Host smart-cd7d9ae9-b74b-4166-bc38-dd69404c245a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340805502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3340805502
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.557595767
Short name T225
Test name
Test status
Simulation time 13405145 ps
CPU time 0.88 seconds
Started Jul 15 07:24:11 PM PDT 24
Finished Jul 15 07:24:51 PM PDT 24
Peak memory 209332 kb
Host smart-eb3bb70a-df7d-4bd0-ae2b-b32ed9c92cbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557595767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.557595767
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1585622410
Short name T108
Test name
Test status
Simulation time 10570301418 ps
CPU time 195.88 seconds
Started Jul 15 06:30:56 PM PDT 24
Finished Jul 15 06:34:13 PM PDT 24
Peak memory 277904 kb
Host smart-995d107d-da7f-4194-ad51-38b93d56fd1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1585622410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1585622410
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2251924383
Short name T15
Test name
Test status
Simulation time 105966326 ps
CPU time 4.83 seconds
Started Jul 15 06:32:17 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 218168 kb
Host smart-00e74bb1-401d-48ad-957d-c8ae7d8566ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251924383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2251924383
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2059332147
Short name T146
Test name
Test status
Simulation time 405724102 ps
CPU time 3 seconds
Started Jul 15 07:24:23 PM PDT 24
Finished Jul 15 07:25:01 PM PDT 24
Peak memory 222636 kb
Host smart-7881ded7-9237-4ff6-afd4-af83fd7295fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059332147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2059332147
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2795660308
Short name T154
Test name
Test status
Simulation time 440646355 ps
CPU time 2.95 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 222388 kb
Host smart-78b1c299-139f-4678-9d68-b58131a06933
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795660308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2795660308
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2090622949
Short name T144
Test name
Test status
Simulation time 118510698 ps
CPU time 4.18 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:30 PM PDT 24
Peak memory 217668 kb
Host smart-81eff258-123f-48e9-ba33-58106bc3a755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090622949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2090622949
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4246003802
Short name T265
Test name
Test status
Simulation time 47154887 ps
CPU time 0.89 seconds
Started Jul 15 06:29:21 PM PDT 24
Finished Jul 15 06:29:22 PM PDT 24
Peak memory 211828 kb
Host smart-6fd24214-4cb5-4266-a8ad-8cfb0d8cae1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246003802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.4246003802
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.589087315
Short name T278
Test name
Test status
Simulation time 373093788 ps
CPU time 9.64 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:38 PM PDT 24
Peak memory 224792 kb
Host smart-8dc04d91-6620-440b-a9e6-ba79d9e649e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589087315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.589087315
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2137240279
Short name T243
Test name
Test status
Simulation time 10591352 ps
CPU time 0.93 seconds
Started Jul 15 06:29:44 PM PDT 24
Finished Jul 15 06:29:45 PM PDT 24
Peak memory 209172 kb
Host smart-c15b75ad-2187-4d8f-b19c-640a6cb5e44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137240279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2137240279
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3011781656
Short name T245
Test name
Test status
Simulation time 12289375 ps
CPU time 0.99 seconds
Started Jul 15 06:29:47 PM PDT 24
Finished Jul 15 06:29:49 PM PDT 24
Peak memory 209168 kb
Host smart-ef5b349b-3cd8-4d78-bf93-96c979565384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011781656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3011781656
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3199006122
Short name T124
Test name
Test status
Simulation time 553759354 ps
CPU time 25.53 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:54 PM PDT 24
Peak memory 250868 kb
Host smart-df01bf60-d8eb-4651-acec-77482bdf6c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199006122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3199006122
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1236275301
Short name T131
Test name
Test status
Simulation time 170090748 ps
CPU time 1.87 seconds
Started Jul 15 07:24:13 PM PDT 24
Finished Jul 15 07:24:53 PM PDT 24
Peak memory 222260 kb
Host smart-4f846364-306a-4c81-af15-b7b63fb2c059
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236275301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1236275301
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3181842129
Short name T162
Test name
Test status
Simulation time 61696075 ps
CPU time 1.94 seconds
Started Jul 15 07:24:30 PM PDT 24
Finished Jul 15 07:25:07 PM PDT 24
Peak memory 222036 kb
Host smart-e2eccac8-b0e7-4797-8cd2-bb7e3e23ba3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181842129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3181842129
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.390389154
Short name T159
Test name
Test status
Simulation time 291099421 ps
CPU time 3.84 seconds
Started Jul 15 07:24:31 PM PDT 24
Finished Jul 15 07:25:09 PM PDT 24
Peak memory 217580 kb
Host smart-b6dcc1e1-d223-4d67-a658-6e9c43bac65d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390389154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.390389154
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2665804701
Short name T145
Test name
Test status
Simulation time 378883107 ps
CPU time 3.76 seconds
Started Jul 15 07:24:37 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 217624 kb
Host smart-a2b4ae24-98f2-4c1c-80ce-5b61c650b663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665804701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2665804701
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3247995683
Short name T56
Test name
Test status
Simulation time 24937123954 ps
CPU time 280.72 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:37:02 PM PDT 24
Peak memory 224348 kb
Host smart-85318693-5b80-4b9f-a670-821af5e71303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247995683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3247995683
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2821167605
Short name T119
Test name
Test status
Simulation time 206315996 ps
CPU time 33.34 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:59 PM PDT 24
Peak memory 269492 kb
Host smart-da762cea-f800-4702-8d57-eb0c708a29bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821167605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2821167605
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1091058556
Short name T234
Test name
Test status
Simulation time 22252120 ps
CPU time 1.12 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 209428 kb
Host smart-02e8b6fd-3be3-4781-aa3f-00b590c12b60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091058556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1091058556
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1638434093
Short name T982
Test name
Test status
Simulation time 40994988 ps
CPU time 1.88 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 209096 kb
Host smart-3ab3e95a-f416-482e-a7a2-0feefa4f47fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638434093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1638434093
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.447719931
Short name T977
Test name
Test status
Simulation time 31401702 ps
CPU time 1.07 seconds
Started Jul 15 07:24:03 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 218164 kb
Host smart-d9a95bcb-9fc1-4c78-96a4-3606dc8adc6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447719931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.447719931
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3665472332
Short name T883
Test name
Test status
Simulation time 65613085 ps
CPU time 0.96 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 217652 kb
Host smart-3982d25f-29e3-4ec0-bf18-1e46f4e7cd29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665472332 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3665472332
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.694701550
Short name T891
Test name
Test status
Simulation time 61782331 ps
CPU time 2.14 seconds
Started Jul 15 07:24:11 PM PDT 24
Finished Jul 15 07:24:53 PM PDT 24
Peak memory 209188 kb
Host smart-3b3bf5ac-82c9-4ab6-b2e7-67c83d849258
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694701550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.694701550
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.754992838
Short name T957
Test name
Test status
Simulation time 5823434344 ps
CPU time 5.55 seconds
Started Jul 15 07:24:08 PM PDT 24
Finished Jul 15 07:24:53 PM PDT 24
Peak memory 217348 kb
Host smart-c5f52c9b-13c4-4718-b0ff-0cb418272ce4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754992838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.754992838
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1057373947
Short name T964
Test name
Test status
Simulation time 626633692 ps
CPU time 5.73 seconds
Started Jul 15 07:24:06 PM PDT 24
Finished Jul 15 07:24:53 PM PDT 24
Peak memory 208832 kb
Host smart-4679c0a1-84c0-4935-802d-e4539914c7b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057373947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1057373947
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2098087756
Short name T960
Test name
Test status
Simulation time 244288186 ps
CPU time 2.19 seconds
Started Jul 15 07:24:05 PM PDT 24
Finished Jul 15 07:24:49 PM PDT 24
Peak memory 210720 kb
Host smart-04b8715d-e7af-4e38-8bcf-a8dbadbdcbf8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098087756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2098087756
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.461624428
Short name T990
Test name
Test status
Simulation time 119814537 ps
CPU time 4.1 seconds
Started Jul 15 07:24:07 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 219296 kb
Host smart-ec692861-f6c4-4353-8818-44cac270ed9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461624
428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.461624428
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2809026794
Short name T876
Test name
Test status
Simulation time 145598868 ps
CPU time 3.81 seconds
Started Jul 15 07:24:07 PM PDT 24
Finished Jul 15 07:24:51 PM PDT 24
Peak memory 209240 kb
Host smart-42c8411f-cdfe-491c-9ba2-3b1129c9eafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809026794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2809026794
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4227145106
Short name T905
Test name
Test status
Simulation time 36357824 ps
CPU time 1.3 seconds
Started Jul 15 07:24:05 PM PDT 24
Finished Jul 15 07:24:48 PM PDT 24
Peak memory 211396 kb
Host smart-2be9b4fa-6d62-4914-abe5-e4d8d04f35d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227145106 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4227145106
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1204047811
Short name T969
Test name
Test status
Simulation time 24886636 ps
CPU time 1.31 seconds
Started Jul 15 07:24:11 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 217568 kb
Host smart-ccf0ef51-abba-423b-8e54-148d7e27889a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204047811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1204047811
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1143523324
Short name T956
Test name
Test status
Simulation time 323502867 ps
CPU time 2.91 seconds
Started Jul 15 07:24:06 PM PDT 24
Finished Jul 15 07:24:50 PM PDT 24
Peak memory 217504 kb
Host smart-dc6ee3a2-a0c8-465f-bf34-67cd71da16cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143523324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1143523324
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2654218040
Short name T133
Test name
Test status
Simulation time 256290429 ps
CPU time 2.56 seconds
Started Jul 15 07:24:05 PM PDT 24
Finished Jul 15 07:24:50 PM PDT 24
Peak memory 217560 kb
Host smart-095c88bf-93bd-4fd4-b2c9-eb1b4fba40c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654218040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2654218040
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.79458782
Short name T987
Test name
Test status
Simulation time 21760545 ps
CPU time 1.41 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 217312 kb
Host smart-d5ef3f74-aa24-4dfc-8e0b-33a39772201e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79458782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash.79458782
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3887595390
Short name T229
Test name
Test status
Simulation time 124876322 ps
CPU time 1.09 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 211448 kb
Host smart-4c886990-4693-47fe-9cb9-2c9dd905df7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887595390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3887595390
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3266079690
Short name T938
Test name
Test status
Simulation time 13755982 ps
CPU time 1.09 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:56 PM PDT 24
Peak memory 218632 kb
Host smart-b88f599a-040f-4bab-99f3-6c80d13d77ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266079690 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3266079690
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2200930990
Short name T989
Test name
Test status
Simulation time 15199546 ps
CPU time 1.05 seconds
Started Jul 15 07:24:11 PM PDT 24
Finished Jul 15 07:24:51 PM PDT 24
Peak memory 209304 kb
Host smart-751fe499-1894-43ba-8f1a-6161eade13b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200930990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2200930990
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2164795961
Short name T168
Test name
Test status
Simulation time 118910443 ps
CPU time 1.46 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 209108 kb
Host smart-e2b22d20-6efc-44e6-8f29-bd779c95125a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164795961 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2164795961
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.709623246
Short name T882
Test name
Test status
Simulation time 3470411145 ps
CPU time 7.95 seconds
Started Jul 15 07:24:13 PM PDT 24
Finished Jul 15 07:24:59 PM PDT 24
Peak memory 209356 kb
Host smart-07ec005f-ea57-43ba-8c20-a4ad44fa267e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709623246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.709623246
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1554199081
Short name T961
Test name
Test status
Simulation time 352071057 ps
CPU time 9.46 seconds
Started Jul 15 07:24:11 PM PDT 24
Finished Jul 15 07:25:00 PM PDT 24
Peak memory 209092 kb
Host smart-62f5dd25-fdfa-4407-a772-59b200e9d6ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554199081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1554199081
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.484448856
Short name T871
Test name
Test status
Simulation time 99211508 ps
CPU time 1.53 seconds
Started Jul 15 07:24:13 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 210768 kb
Host smart-8586c5a0-a83f-4d68-b98b-726c35a694f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484448856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.484448856
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4069786951
Short name T929
Test name
Test status
Simulation time 700420676 ps
CPU time 1.34 seconds
Started Jul 15 07:24:13 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 217452 kb
Host smart-261a4838-24f8-4949-9d9c-2d2b26235f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069786951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4069786951
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1783911682
Short name T916
Test name
Test status
Simulation time 30526244 ps
CPU time 1.45 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 209364 kb
Host smart-b785ebe3-de3d-4ab3-92ec-09c9799056ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783911682 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1783911682
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1247498513
Short name T980
Test name
Test status
Simulation time 28690184 ps
CPU time 1.11 seconds
Started Jul 15 07:24:14 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 209340 kb
Host smart-0860c009-8d68-4332-b0f4-559c8bcbf288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247498513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1247498513
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2150254409
Short name T151
Test name
Test status
Simulation time 47331139 ps
CPU time 3.31 seconds
Started Jul 15 07:24:12 PM PDT 24
Finished Jul 15 07:24:54 PM PDT 24
Peak memory 217508 kb
Host smart-9ad07931-1c95-4056-b8e4-50b0dcf98c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150254409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2150254409
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1642723860
Short name T913
Test name
Test status
Simulation time 49457927 ps
CPU time 0.9 seconds
Started Jul 15 07:24:42 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 219568 kb
Host smart-1c9f7784-7946-40af-82ee-3229d35133f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642723860 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1642723860
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3414585165
Short name T893
Test name
Test status
Simulation time 30432290 ps
CPU time 0.86 seconds
Started Jul 15 07:24:51 PM PDT 24
Finished Jul 15 07:25:28 PM PDT 24
Peak memory 209208 kb
Host smart-b69603b1-891e-4b99-b279-f6c770762c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414585165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3414585165
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.836834326
Short name T892
Test name
Test status
Simulation time 31061486 ps
CPU time 1.5 seconds
Started Jul 15 07:24:45 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 209340 kb
Host smart-6f56e4ef-f21b-44c6-b1b5-9eb0450efee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836834326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.836834326
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.930593421
Short name T895
Test name
Test status
Simulation time 617084399 ps
CPU time 5.58 seconds
Started Jul 15 07:24:40 PM PDT 24
Finished Jul 15 07:25:20 PM PDT 24
Peak memory 217500 kb
Host smart-cf4542bb-7f61-4e00-99fc-b5b0c2d4c332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930593421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.930593421
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4153876678
Short name T152
Test name
Test status
Simulation time 76045062 ps
CPU time 2.53 seconds
Started Jul 15 07:24:45 PM PDT 24
Finished Jul 15 07:25:24 PM PDT 24
Peak memory 217528 kb
Host smart-a2149d19-f27f-452a-9c8b-76bff97bd2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153876678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4153876678
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.592232636
Short name T922
Test name
Test status
Simulation time 22932852 ps
CPU time 1.47 seconds
Started Jul 15 07:24:48 PM PDT 24
Finished Jul 15 07:25:26 PM PDT 24
Peak memory 217596 kb
Host smart-0fe99417-d5b2-4890-a3cb-a4e11d5aea14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592232636 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.592232636
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3685846651
Short name T188
Test name
Test status
Simulation time 56882011 ps
CPU time 0.89 seconds
Started Jul 15 07:24:44 PM PDT 24
Finished Jul 15 07:25:21 PM PDT 24
Peak memory 209268 kb
Host smart-4ba7ccbe-fdea-43c5-b577-4cd3c2f0af50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685846651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3685846651
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1079199851
Short name T919
Test name
Test status
Simulation time 27557586 ps
CPU time 1.44 seconds
Started Jul 15 07:24:43 PM PDT 24
Finished Jul 15 07:25:19 PM PDT 24
Peak memory 217560 kb
Host smart-5b264c23-1c27-4cc9-9cca-04ca787e1f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079199851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1079199851
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3003112936
Short name T910
Test name
Test status
Simulation time 41536644 ps
CPU time 3.03 seconds
Started Jul 15 07:24:43 PM PDT 24
Finished Jul 15 07:25:20 PM PDT 24
Peak memory 217684 kb
Host smart-6c0f54cc-f876-4a7c-9843-ad684b75086a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003112936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3003112936
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1133720238
Short name T163
Test name
Test status
Simulation time 221201541 ps
CPU time 1.9 seconds
Started Jul 15 07:24:44 PM PDT 24
Finished Jul 15 07:25:20 PM PDT 24
Peak memory 221776 kb
Host smart-a9829b94-97ad-4c91-86d0-3fc2a35391dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133720238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1133720238
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.790331654
Short name T199
Test name
Test status
Simulation time 101002366 ps
CPU time 1.14 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:29 PM PDT 24
Peak memory 222028 kb
Host smart-499fba3c-afc7-4faf-974a-e99e3e051d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790331654 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.790331654
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1765418220
Short name T946
Test name
Test status
Simulation time 12885232 ps
CPU time 0.91 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:22 PM PDT 24
Peak memory 209304 kb
Host smart-16e0e532-c97c-40a0-b507-2c5a5873464b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765418220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1765418220
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4094716721
Short name T899
Test name
Test status
Simulation time 38611177 ps
CPU time 1.26 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:29 PM PDT 24
Peak memory 211548 kb
Host smart-b5d171e4-3dea-46dd-aaa9-3dd1c884be78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094716721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4094716721
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3000539048
Short name T962
Test name
Test status
Simulation time 375777246 ps
CPU time 2.47 seconds
Started Jul 15 07:24:44 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 217460 kb
Host smart-b77ac2cb-3083-4f03-a4e9-be21b53335f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000539048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3000539048
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.641453759
Short name T966
Test name
Test status
Simulation time 52132664 ps
CPU time 1.16 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 217640 kb
Host smart-27e9824d-52d9-4bde-8e3d-0380322868dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641453759 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.641453759
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2954400307
Short name T230
Test name
Test status
Simulation time 49275064 ps
CPU time 0.9 seconds
Started Jul 15 07:24:43 PM PDT 24
Finished Jul 15 07:25:18 PM PDT 24
Peak memory 209352 kb
Host smart-a49bfc44-312f-4353-b0f0-92d544a651f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954400307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2954400307
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2946232967
Short name T241
Test name
Test status
Simulation time 54721476 ps
CPU time 1.1 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 209236 kb
Host smart-ea949b72-f901-482c-abb7-3650eeea37ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946232967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2946232967
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2261180447
Short name T894
Test name
Test status
Simulation time 80777930 ps
CPU time 2.3 seconds
Started Jul 15 07:24:51 PM PDT 24
Finished Jul 15 07:25:30 PM PDT 24
Peak memory 217504 kb
Host smart-cb5289cc-11ee-46c1-ae56-6b42b9110809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261180447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2261180447
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1484011873
Short name T147
Test name
Test status
Simulation time 122692629 ps
CPU time 3.78 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:31 PM PDT 24
Peak memory 217672 kb
Host smart-75af7be5-ccca-488d-801c-1fb03290059c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484011873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1484011873
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3641850732
Short name T953
Test name
Test status
Simulation time 14693777 ps
CPU time 1.1 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 219364 kb
Host smart-3e905f56-7e98-45b1-b445-c79c7ac71260
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641850732 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3641850732
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1231732932
Short name T886
Test name
Test status
Simulation time 25401103 ps
CPU time 0.9 seconds
Started Jul 15 07:24:45 PM PDT 24
Finished Jul 15 07:25:22 PM PDT 24
Peak memory 209348 kb
Host smart-11d7ace6-c363-4d5c-9efa-f99a6f43c9d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231732932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1231732932
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3296921213
Short name T926
Test name
Test status
Simulation time 24060774 ps
CPU time 1.08 seconds
Started Jul 15 07:24:51 PM PDT 24
Finished Jul 15 07:25:29 PM PDT 24
Peak memory 209392 kb
Host smart-a4315744-3deb-4150-a493-ef09fbb05768
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296921213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3296921213
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.84718260
Short name T148
Test name
Test status
Simulation time 52062283 ps
CPU time 1.77 seconds
Started Jul 15 07:24:51 PM PDT 24
Finished Jul 15 07:25:30 PM PDT 24
Peak memory 217700 kb
Host smart-77eb915d-53f7-4233-9636-45dc50b08505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84718260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.84718260
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3337775651
Short name T902
Test name
Test status
Simulation time 81054057 ps
CPU time 1.08 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 218808 kb
Host smart-8cba322e-38f5-4575-ada1-cd361a16130a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337775651 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3337775651
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2559601895
Short name T992
Test name
Test status
Simulation time 15071106 ps
CPU time 1.07 seconds
Started Jul 15 07:24:41 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 209124 kb
Host smart-e4a947a2-aaf6-4439-9833-c1d2df7ab0bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559601895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2559601895
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1289725166
Short name T933
Test name
Test status
Simulation time 35168131 ps
CPU time 1.45 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 211212 kb
Host smart-e9dd350c-aa2e-44eb-8fa6-3bf3c4f89619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289725166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1289725166
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.331178708
Short name T951
Test name
Test status
Simulation time 400348254 ps
CPU time 3.24 seconds
Started Jul 15 07:24:46 PM PDT 24
Finished Jul 15 07:25:25 PM PDT 24
Peak memory 217456 kb
Host smart-6f50f9ac-dcb2-4325-8c26-17edc9081193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331178708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.331178708
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3114505664
Short name T158
Test name
Test status
Simulation time 257103469 ps
CPU time 2.12 seconds
Started Jul 15 07:24:45 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 221688 kb
Host smart-661c5eb6-fbde-466c-bdb4-8615363ab21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114505664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3114505664
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.457098737
Short name T981
Test name
Test status
Simulation time 31790476 ps
CPU time 1.1 seconds
Started Jul 15 07:24:45 PM PDT 24
Finished Jul 15 07:25:22 PM PDT 24
Peak memory 217696 kb
Host smart-0ddd3160-b32a-4728-ad03-8c24f0fd9559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457098737 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.457098737
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.542080781
Short name T238
Test name
Test status
Simulation time 30005271 ps
CPU time 0.95 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:27 PM PDT 24
Peak memory 209336 kb
Host smart-478a7002-6cd7-4eda-8ed4-123de0d06329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542080781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.542080781
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2825666963
Short name T896
Test name
Test status
Simulation time 51740161 ps
CPU time 1.43 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:29 PM PDT 24
Peak memory 209404 kb
Host smart-38ad6fe8-a9bb-4692-9ad2-6c83e66c6a25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825666963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2825666963
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.120993882
Short name T139
Test name
Test status
Simulation time 30925304 ps
CPU time 1.76 seconds
Started Jul 15 07:24:51 PM PDT 24
Finished Jul 15 07:25:30 PM PDT 24
Peak memory 217488 kb
Host smart-80e63cfd-fd46-43f4-a687-815738914135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120993882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.120993882
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1299083421
Short name T161
Test name
Test status
Simulation time 46912336 ps
CPU time 2.12 seconds
Started Jul 15 07:24:51 PM PDT 24
Finished Jul 15 07:25:30 PM PDT 24
Peak memory 217548 kb
Host smart-50247632-9b90-4307-abd6-4a9b87125c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299083421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1299083421
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.376182841
Short name T931
Test name
Test status
Simulation time 48752549 ps
CPU time 1.16 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:27 PM PDT 24
Peak memory 221976 kb
Host smart-02f57842-93ca-4236-9abf-4f64dcaab1aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376182841 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.376182841
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2401939083
Short name T228
Test name
Test status
Simulation time 15803615 ps
CPU time 1.08 seconds
Started Jul 15 07:24:47 PM PDT 24
Finished Jul 15 07:25:26 PM PDT 24
Peak memory 209076 kb
Host smart-88183238-b33e-474a-a377-1217811f92ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401939083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2401939083
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3195403698
Short name T975
Test name
Test status
Simulation time 20644224 ps
CPU time 1 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:27 PM PDT 24
Peak memory 209436 kb
Host smart-521b9208-8b3c-485b-a0a7-bc0c5d23edee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195403698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3195403698
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1946899899
Short name T138
Test name
Test status
Simulation time 222567094 ps
CPU time 2.09 seconds
Started Jul 15 07:24:45 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 218568 kb
Host smart-e4dabbdb-d1a9-4d48-a6e3-4a7abc0710a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946899899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1946899899
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.214484446
Short name T156
Test name
Test status
Simulation time 39501381 ps
CPU time 1.18 seconds
Started Jul 15 07:24:50 PM PDT 24
Finished Jul 15 07:25:27 PM PDT 24
Peak memory 217660 kb
Host smart-2f3d1ae1-cb8d-4b27-87aa-707dcc2f06bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214484446 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.214484446
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3984844237
Short name T236
Test name
Test status
Simulation time 20120332 ps
CPU time 0.83 seconds
Started Jul 15 07:24:48 PM PDT 24
Finished Jul 15 07:25:27 PM PDT 24
Peak memory 209284 kb
Host smart-75413b37-94dc-4dce-9e78-4cf209311d61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984844237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3984844237
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.474001501
Short name T142
Test name
Test status
Simulation time 118356435 ps
CPU time 1 seconds
Started Jul 15 07:24:52 PM PDT 24
Finished Jul 15 07:25:29 PM PDT 24
Peak memory 209320 kb
Host smart-61da69ae-2d5e-4567-98ab-690179894e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474001501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.474001501
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3624680624
Short name T890
Test name
Test status
Simulation time 568693883 ps
CPU time 2.02 seconds
Started Jul 15 07:24:52 PM PDT 24
Finished Jul 15 07:25:32 PM PDT 24
Peak memory 217484 kb
Host smart-4759e00b-c2fc-4061-8122-bda60c52d4c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624680624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3624680624
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1211151115
Short name T912
Test name
Test status
Simulation time 48720834 ps
CPU time 0.99 seconds
Started Jul 15 07:24:56 PM PDT 24
Finished Jul 15 07:25:35 PM PDT 24
Peak memory 217584 kb
Host smart-47a9a13e-09f5-459f-b4ef-c963eaea9ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211151115 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1211151115
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3046013584
Short name T239
Test name
Test status
Simulation time 11578225 ps
CPU time 0.95 seconds
Started Jul 15 07:24:55 PM PDT 24
Finished Jul 15 07:25:33 PM PDT 24
Peak memory 209368 kb
Host smart-ab16910e-51b3-4026-84b8-0065fd439614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046013584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3046013584
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2786141972
Short name T887
Test name
Test status
Simulation time 36867193 ps
CPU time 1.25 seconds
Started Jul 15 07:24:51 PM PDT 24
Finished Jul 15 07:25:29 PM PDT 24
Peak memory 209344 kb
Host smart-a4b991e8-5915-4178-a8c8-be6ec1919db4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786141972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2786141972
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2128185046
Short name T914
Test name
Test status
Simulation time 21938982 ps
CPU time 1.42 seconds
Started Jul 15 07:24:52 PM PDT 24
Finished Jul 15 07:25:31 PM PDT 24
Peak memory 218604 kb
Host smart-fbd0ddc8-e2f4-47b6-ae3d-4eab14fcd379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128185046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2128185046
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1689626729
Short name T143
Test name
Test status
Simulation time 49206676 ps
CPU time 2.4 seconds
Started Jul 15 07:24:49 PM PDT 24
Finished Jul 15 07:25:28 PM PDT 24
Peak memory 217500 kb
Host smart-5030563f-ebac-4dc9-b71e-e0fd4082f314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689626729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1689626729
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.291628735
Short name T235
Test name
Test status
Simulation time 21189344 ps
CPU time 1.15 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 209440 kb
Host smart-b6b0b3ed-1de9-4a51-8fe6-46035f0e7d4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291628735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.291628735
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3644386783
Short name T942
Test name
Test status
Simulation time 148647380 ps
CPU time 1.4 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 217348 kb
Host smart-ff0d864d-21d2-4ed4-8a20-446da70dd2e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644386783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3644386783
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3934580375
Short name T924
Test name
Test status
Simulation time 98064665 ps
CPU time 0.88 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:56 PM PDT 24
Peak memory 209792 kb
Host smart-12865b52-a9b9-4216-aac1-8acf605bebb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934580375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3934580375
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1849806349
Short name T189
Test name
Test status
Simulation time 80001335 ps
CPU time 1.66 seconds
Started Jul 15 07:24:17 PM PDT 24
Finished Jul 15 07:24:54 PM PDT 24
Peak memory 217600 kb
Host smart-b4ea2231-411e-4eaa-a0e8-413038b2c185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849806349 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1849806349
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2993293731
Short name T141
Test name
Test status
Simulation time 30458297 ps
CPU time 1.11 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 217320 kb
Host smart-742f175b-ee98-449e-8fda-58fcb62146b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993293731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2993293731
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2406863693
Short name T968
Test name
Test status
Simulation time 55358045 ps
CPU time 1.05 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:56 PM PDT 24
Peak memory 208704 kb
Host smart-37ba0fce-5b87-4a45-8316-ae42a7789bef
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406863693 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2406863693
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.472959115
Short name T928
Test name
Test status
Simulation time 1018544785 ps
CPU time 12.22 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:25:08 PM PDT 24
Peak memory 217036 kb
Host smart-73154649-c4d9-4431-8df7-da88afcff1f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472959115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.472959115
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.595421824
Short name T908
Test name
Test status
Simulation time 2637685075 ps
CPU time 12.12 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:25:08 PM PDT 24
Peak memory 217380 kb
Host smart-d6697439-bea4-4c08-affa-5e0c429c426e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595421824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.595421824
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.900188482
Short name T972
Test name
Test status
Simulation time 139623339 ps
CPU time 3.69 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:59 PM PDT 24
Peak memory 210772 kb
Host smart-306612ac-2368-4ccb-99a7-241d9070778f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900188482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.900188482
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2950278942
Short name T970
Test name
Test status
Simulation time 79524861 ps
CPU time 2.6 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:58 PM PDT 24
Peak memory 218188 kb
Host smart-897d9ad0-c179-4ce1-8eed-8567c3609fd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295027
8942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2950278942
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2588996888
Short name T884
Test name
Test status
Simulation time 206928598 ps
CPU time 1.58 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 209252 kb
Host smart-18886bb3-1d7f-4eb8-b2af-3a3c19355b6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588996888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2588996888
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.762474651
Short name T965
Test name
Test status
Simulation time 252283571 ps
CPU time 1.81 seconds
Started Jul 15 07:24:21 PM PDT 24
Finished Jul 15 07:25:00 PM PDT 24
Peak memory 217604 kb
Host smart-7f3c167b-bd31-434e-8ab0-d497ab1432b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762474651 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.762474651
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.433918413
Short name T936
Test name
Test status
Simulation time 25925704 ps
CPU time 1.02 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:56 PM PDT 24
Peak memory 209228 kb
Host smart-0d615e4c-d521-4fe7-a0df-89d679bf325b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433918413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.433918413
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.605249664
Short name T900
Test name
Test status
Simulation time 245303571 ps
CPU time 5.12 seconds
Started Jul 15 07:24:21 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 217692 kb
Host smart-1e45dbcd-2ad2-4982-b4d1-e74664596d33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605249664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.605249664
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.67789326
Short name T959
Test name
Test status
Simulation time 35819546 ps
CPU time 1.8 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 209224 kb
Host smart-8077470b-1d53-4472-939f-1241589eaed5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67789326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing.67789326
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2671150482
Short name T934
Test name
Test status
Simulation time 39542743 ps
CPU time 1.26 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 208856 kb
Host smart-2bbe79e9-ebe9-4f86-8c03-02158e518d38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671150482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2671150482
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1088035098
Short name T224
Test name
Test status
Simulation time 71345648 ps
CPU time 1.02 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 217876 kb
Host smart-7ccab830-f2e9-43ea-a600-6567795b0b21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088035098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1088035098
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3322699055
Short name T920
Test name
Test status
Simulation time 27701101 ps
CPU time 1.3 seconds
Started Jul 15 07:24:21 PM PDT 24
Finished Jul 15 07:24:59 PM PDT 24
Peak memory 218816 kb
Host smart-d027f7fd-bafd-47ae-99c7-7a610ac903a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322699055 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3322699055
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2888926078
Short name T226
Test name
Test status
Simulation time 42165641 ps
CPU time 0.97 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:56 PM PDT 24
Peak memory 209360 kb
Host smart-897cf3f4-db10-4ec7-a803-6a1e75f1aaee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888926078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2888926078
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1152231332
Short name T911
Test name
Test status
Simulation time 1240946300 ps
CPU time 3.29 seconds
Started Jul 15 07:24:18 PM PDT 24
Finished Jul 15 07:24:59 PM PDT 24
Peak memory 209212 kb
Host smart-3835b5f4-5bd5-4d0b-b58d-16f3740e122a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152231332 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1152231332
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.49289001
Short name T974
Test name
Test status
Simulation time 483261530 ps
CPU time 2.97 seconds
Started Jul 15 07:24:21 PM PDT 24
Finished Jul 15 07:25:01 PM PDT 24
Peak memory 209048 kb
Host smart-e700a462-0d9e-4573-885c-493869b1d846
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49289001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_aliasing.49289001
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2291050581
Short name T930
Test name
Test status
Simulation time 763888856 ps
CPU time 17.13 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:25:12 PM PDT 24
Peak memory 217188 kb
Host smart-d37c4b8e-68de-49bc-a034-fa54c7f1016b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291050581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2291050581
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2755006628
Short name T943
Test name
Test status
Simulation time 240551131 ps
CPU time 3.5 seconds
Started Jul 15 07:24:23 PM PDT 24
Finished Jul 15 07:25:02 PM PDT 24
Peak memory 217468 kb
Host smart-854242bc-f5e2-4a99-8bad-3a83b0118539
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755006628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2755006628
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2001458967
Short name T909
Test name
Test status
Simulation time 166949571 ps
CPU time 4.06 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:59 PM PDT 24
Peak memory 219116 kb
Host smart-711e15f5-4055-45f0-8698-09f954d4b3e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200145
8967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2001458967
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2749248110
Short name T901
Test name
Test status
Simulation time 77630830 ps
CPU time 2.56 seconds
Started Jul 15 07:24:19 PM PDT 24
Finished Jul 15 07:24:58 PM PDT 24
Peak memory 217388 kb
Host smart-2f7620a4-89fc-4a46-a465-8bf8fd894bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749248110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2749248110
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3964818692
Short name T915
Test name
Test status
Simulation time 43328660 ps
CPU time 1.25 seconds
Started Jul 15 07:24:16 PM PDT 24
Finished Jul 15 07:24:54 PM PDT 24
Peak memory 209436 kb
Host smart-5f62cc24-7002-4b93-b87a-d5f054f06fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964818692 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3964818692
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4171516211
Short name T140
Test name
Test status
Simulation time 140292537 ps
CPU time 1.3 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:57 PM PDT 24
Peak memory 211320 kb
Host smart-c9c925af-7c0d-4f8e-bf75-6c258e8a00b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171516211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.4171516211
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4094954412
Short name T950
Test name
Test status
Simulation time 229263214 ps
CPU time 1.89 seconds
Started Jul 15 07:24:20 PM PDT 24
Finished Jul 15 07:24:58 PM PDT 24
Peak memory 217488 kb
Host smart-f7d99654-9054-4ecd-9561-cf9d7e000a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094954412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4094954412
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.320853881
Short name T233
Test name
Test status
Simulation time 21045556 ps
CPU time 1.35 seconds
Started Jul 15 07:24:25 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 209236 kb
Host smart-fc7f12ad-8a16-4f30-8a85-19be9c1f45af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320853881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.320853881
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.683517621
Short name T958
Test name
Test status
Simulation time 68932049 ps
CPU time 2.52 seconds
Started Jul 15 07:24:28 PM PDT 24
Finished Jul 15 07:25:07 PM PDT 24
Peak memory 208900 kb
Host smart-778dc475-41d2-459b-85b2-52c4f27252d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683517621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.683517621
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1213890933
Short name T874
Test name
Test status
Simulation time 28186616 ps
CPU time 0.97 seconds
Started Jul 15 07:24:28 PM PDT 24
Finished Jul 15 07:25:05 PM PDT 24
Peak memory 209764 kb
Host smart-84e2fba4-38f6-4356-8234-1d845f06fd28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213890933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1213890933
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2045880220
Short name T954
Test name
Test status
Simulation time 65224089 ps
CPU time 1.29 seconds
Started Jul 15 07:24:26 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 222552 kb
Host smart-f27deb3c-63d4-4e36-bb67-bd249949b9ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045880220 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2045880220
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3202369367
Short name T232
Test name
Test status
Simulation time 13792806 ps
CPU time 1.06 seconds
Started Jul 15 07:24:25 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 209248 kb
Host smart-2665ff27-2033-449d-855b-64d13cecb70d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202369367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3202369367
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.132642
Short name T983
Test name
Test status
Simulation time 99000960 ps
CPU time 1.77 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 208792 kb
Host smart-1a57bf01-2958-428b-8b54-ab0a7184d3e2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.lc_ctrl_jtag_alert_test.132642
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.627210723
Short name T877
Test name
Test status
Simulation time 1158663314 ps
CPU time 24.22 seconds
Started Jul 15 07:24:25 PM PDT 24
Finished Jul 15 07:25:25 PM PDT 24
Peak memory 209048 kb
Host smart-24342a97-4356-480d-8c30-62c7b1121160
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627210723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.627210723
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3456609207
Short name T881
Test name
Test status
Simulation time 9737761331 ps
CPU time 50.41 seconds
Started Jul 15 07:24:26 PM PDT 24
Finished Jul 15 07:25:52 PM PDT 24
Peak memory 209332 kb
Host smart-e31294d2-0d65-40b2-86a7-34f57ab54f58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456609207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3456609207
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3362583007
Short name T973
Test name
Test status
Simulation time 282161501 ps
CPU time 6.53 seconds
Started Jul 15 07:24:26 PM PDT 24
Finished Jul 15 07:25:08 PM PDT 24
Peak memory 217504 kb
Host smart-c01506de-9c21-41c6-91d5-d89495939217
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362583007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3362583007
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3844523038
Short name T945
Test name
Test status
Simulation time 203746233 ps
CPU time 2.64 seconds
Started Jul 15 07:24:25 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 218616 kb
Host smart-41597ecd-da52-4745-bfb4-e2375f816b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384452
3038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3844523038
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.356546355
Short name T878
Test name
Test status
Simulation time 151097151 ps
CPU time 2.35 seconds
Started Jul 15 07:24:25 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 209220 kb
Host smart-0d7d1e1a-259b-4b25-a851-5166290c90e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356546355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.356546355
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1829198526
Short name T927
Test name
Test status
Simulation time 106484706 ps
CPU time 1.42 seconds
Started Jul 15 07:24:26 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 209312 kb
Host smart-e6348974-567d-4964-a5f0-d9a3e9bfc061
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829198526 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1829198526
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4077169332
Short name T888
Test name
Test status
Simulation time 41525344 ps
CPU time 1.26 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 209384 kb
Host smart-69d2f4e3-6709-4f2c-af3d-2d2dec51cd7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077169332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.4077169332
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1942629785
Short name T948
Test name
Test status
Simulation time 73418287 ps
CPU time 1.39 seconds
Started Jul 15 07:24:28 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 218628 kb
Host smart-79eb336f-e55a-4458-b428-ccd7a3106c8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942629785 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1942629785
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.544853516
Short name T869
Test name
Test status
Simulation time 37363966 ps
CPU time 0.86 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 209288 kb
Host smart-dd4dd7ed-051e-4cb4-a80c-3a746b2bbe5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544853516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.544853516
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3269793996
Short name T880
Test name
Test status
Simulation time 44924798 ps
CPU time 1.7 seconds
Started Jul 15 07:24:28 PM PDT 24
Finished Jul 15 07:25:06 PM PDT 24
Peak memory 209164 kb
Host smart-77872604-6839-4453-884b-887617f056ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269793996 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3269793996
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2164450973
Short name T991
Test name
Test status
Simulation time 2401537468 ps
CPU time 13.95 seconds
Started Jul 15 07:24:26 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 217432 kb
Host smart-92ea6cc7-577b-4cc7-b49f-c66bea79b1e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164450973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2164450973
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.459606546
Short name T918
Test name
Test status
Simulation time 6721534707 ps
CPU time 9.92 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:12 PM PDT 24
Peak memory 209404 kb
Host smart-330103ac-d2c0-4628-a1f3-8eb6e5bd2d93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459606546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.459606546
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1418596118
Short name T944
Test name
Test status
Simulation time 285539433 ps
CPU time 2.14 seconds
Started Jul 15 07:24:30 PM PDT 24
Finished Jul 15 07:25:07 PM PDT 24
Peak memory 210972 kb
Host smart-7a1330e6-2ecf-4132-bfdd-f24f86df9d1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418596118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1418596118
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2266165011
Short name T971
Test name
Test status
Simulation time 117397175 ps
CPU time 2.13 seconds
Started Jul 15 07:24:26 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 218732 kb
Host smart-04a2a245-f216-462e-966c-23e4a6164714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226616
5011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2266165011
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1750192191
Short name T935
Test name
Test status
Simulation time 41789790 ps
CPU time 1.73 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 209220 kb
Host smart-569c30d2-9e1c-4f44-9502-8f94992efea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750192191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1750192191
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1344816887
Short name T187
Test name
Test status
Simulation time 109402686 ps
CPU time 1.1 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 209368 kb
Host smart-0e6aa1c5-a5f3-4946-b6ea-d712db0ff247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344816887 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1344816887
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.759638727
Short name T917
Test name
Test status
Simulation time 47618718 ps
CPU time 1.44 seconds
Started Jul 15 07:24:25 PM PDT 24
Finished Jul 15 07:25:03 PM PDT 24
Peak memory 209356 kb
Host smart-3546f6b3-3b10-4d1e-bfbd-4a0c7db490ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759638727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.759638727
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.77265945
Short name T952
Test name
Test status
Simulation time 422938608 ps
CPU time 3.22 seconds
Started Jul 15 07:24:26 PM PDT 24
Finished Jul 15 07:25:05 PM PDT 24
Peak memory 217448 kb
Host smart-84d8eae2-2d4b-4d73-9bd5-7ee6677629ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77265945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.77265945
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1408234533
Short name T879
Test name
Test status
Simulation time 38617387 ps
CPU time 1.22 seconds
Started Jul 15 07:24:32 PM PDT 24
Finished Jul 15 07:25:08 PM PDT 24
Peak memory 217660 kb
Host smart-bd1f7c50-c86a-46cd-9ab8-60385a7d9461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408234533 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1408234533
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.782525988
Short name T231
Test name
Test status
Simulation time 164143296 ps
CPU time 1.05 seconds
Started Jul 15 07:24:30 PM PDT 24
Finished Jul 15 07:25:06 PM PDT 24
Peak memory 209356 kb
Host smart-26baa4b1-5575-4c4b-a58c-33261b8d4f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782525988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.782525988
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.777449399
Short name T949
Test name
Test status
Simulation time 34088251 ps
CPU time 1.01 seconds
Started Jul 15 07:24:34 PM PDT 24
Finished Jul 15 07:25:09 PM PDT 24
Peak memory 209124 kb
Host smart-2a6c04fe-69e0-4668-a5c8-53e065456d9b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777449399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.777449399
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.560221209
Short name T875
Test name
Test status
Simulation time 296035883 ps
CPU time 3.99 seconds
Started Jul 15 07:24:28 PM PDT 24
Finished Jul 15 07:25:08 PM PDT 24
Peak memory 217012 kb
Host smart-dde8c56a-66d6-4d5a-817b-cece9d271019
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560221209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.560221209
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4172185773
Short name T897
Test name
Test status
Simulation time 838140596 ps
CPU time 8.16 seconds
Started Jul 15 07:24:28 PM PDT 24
Finished Jul 15 07:25:12 PM PDT 24
Peak memory 217016 kb
Host smart-971bab23-9362-43ce-9b64-b791ed26c3ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172185773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4172185773
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2116339903
Short name T873
Test name
Test status
Simulation time 223559292 ps
CPU time 1.31 seconds
Started Jul 15 07:24:29 PM PDT 24
Finished Jul 15 07:25:06 PM PDT 24
Peak memory 217456 kb
Host smart-23e176b6-d0dc-4315-bf80-49da9d4a6e1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116339903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2116339903
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097741049
Short name T967
Test name
Test status
Simulation time 573329756 ps
CPU time 2.67 seconds
Started Jul 15 07:24:31 PM PDT 24
Finished Jul 15 07:25:09 PM PDT 24
Peak memory 219200 kb
Host smart-09bdf487-e539-44f4-be6f-13c56d8f098f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209774
1049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2097741049
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1217502795
Short name T898
Test name
Test status
Simulation time 764986363 ps
CPU time 1.23 seconds
Started Jul 15 07:24:31 PM PDT 24
Finished Jul 15 07:25:06 PM PDT 24
Peak memory 209240 kb
Host smart-363530c2-6617-4372-b807-43d926259c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217502795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1217502795
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3003090962
Short name T906
Test name
Test status
Simulation time 41834725 ps
CPU time 1.85 seconds
Started Jul 15 07:24:27 PM PDT 24
Finished Jul 15 07:25:04 PM PDT 24
Peak memory 217564 kb
Host smart-37f32fd3-d09b-44a1-bec0-7882f2ebb221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003090962 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3003090962
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.818271586
Short name T889
Test name
Test status
Simulation time 98061896 ps
CPU time 1.44 seconds
Started Jul 15 07:24:41 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 217592 kb
Host smart-427e0084-6c47-45cc-af56-0dc0006b1a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818271586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.818271586
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.599727049
Short name T985
Test name
Test status
Simulation time 103404573 ps
CPU time 1.72 seconds
Started Jul 15 07:24:41 PM PDT 24
Finished Jul 15 07:25:17 PM PDT 24
Peak memory 217744 kb
Host smart-92fc7a14-a82b-4ab5-9ca0-14a62ae17636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599727049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.599727049
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1903718918
Short name T941
Test name
Test status
Simulation time 84591208 ps
CPU time 1.06 seconds
Started Jul 15 07:24:37 PM PDT 24
Finished Jul 15 07:25:13 PM PDT 24
Peak memory 219740 kb
Host smart-e83b70f2-c6d5-49c4-a648-585e632a4ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903718918 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1903718918
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2972008440
Short name T903
Test name
Test status
Simulation time 17061404 ps
CPU time 0.87 seconds
Started Jul 15 07:24:30 PM PDT 24
Finished Jul 15 07:25:06 PM PDT 24
Peak memory 208920 kb
Host smart-f4c6d94a-f537-47d5-9bee-010d0627da2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972008440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2972008440
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1962613580
Short name T872
Test name
Test status
Simulation time 17755028 ps
CPU time 0.86 seconds
Started Jul 15 07:24:41 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 209132 kb
Host smart-499990f8-f90b-48e4-9faa-a784bbc42b05
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962613580 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1962613580
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.747969345
Short name T164
Test name
Test status
Simulation time 1610287318 ps
CPU time 5.54 seconds
Started Jul 15 07:24:29 PM PDT 24
Finished Jul 15 07:25:10 PM PDT 24
Peak memory 209268 kb
Host smart-b13818b2-108e-4136-a835-10db93d7e325
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747969345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.747969345
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.422788618
Short name T939
Test name
Test status
Simulation time 2032285733 ps
CPU time 10.31 seconds
Started Jul 15 07:24:29 PM PDT 24
Finished Jul 15 07:25:15 PM PDT 24
Peak memory 217128 kb
Host smart-06810f4b-467f-4d00-9494-a63af825be8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422788618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.422788618
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3446212965
Short name T955
Test name
Test status
Simulation time 74249256 ps
CPU time 2.52 seconds
Started Jul 15 07:24:32 PM PDT 24
Finished Jul 15 07:25:10 PM PDT 24
Peak memory 210816 kb
Host smart-1ceb9ee5-37df-47b5-9a26-136d40cc455c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446212965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3446212965
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1504007170
Short name T984
Test name
Test status
Simulation time 81327170 ps
CPU time 1.64 seconds
Started Jul 15 07:24:31 PM PDT 24
Finished Jul 15 07:25:06 PM PDT 24
Peak memory 217600 kb
Host smart-6665c36b-05f7-46ab-846b-b9fea9cf87c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150400
7170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1504007170
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2139345364
Short name T166
Test name
Test status
Simulation time 443099225 ps
CPU time 1.26 seconds
Started Jul 15 07:24:32 PM PDT 24
Finished Jul 15 07:25:08 PM PDT 24
Peak memory 209276 kb
Host smart-33c5c733-22d1-4ec6-b48d-4e1857734acb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139345364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2139345364
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3709119939
Short name T921
Test name
Test status
Simulation time 33697717 ps
CPU time 1.11 seconds
Started Jul 15 07:24:41 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 209216 kb
Host smart-2c2adf89-85ee-4e0c-8bcb-3cc7c4660d57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709119939 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3709119939
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2579033232
Short name T240
Test name
Test status
Simulation time 95979125 ps
CPU time 1.03 seconds
Started Jul 15 07:24:40 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 209440 kb
Host smart-9c3710d5-1d8e-499d-94b5-5923487dcfa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579033232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2579033232
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1066156396
Short name T976
Test name
Test status
Simulation time 333629984 ps
CPU time 5.63 seconds
Started Jul 15 07:24:32 PM PDT 24
Finished Jul 15 07:25:13 PM PDT 24
Peak memory 217452 kb
Host smart-67eca862-e9ce-4e5a-accf-037b354d1b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066156396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1066156396
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.580173638
Short name T155
Test name
Test status
Simulation time 179032751 ps
CPU time 3.15 seconds
Started Jul 15 07:24:31 PM PDT 24
Finished Jul 15 07:25:10 PM PDT 24
Peak memory 217528 kb
Host smart-2f2834dd-b6fb-4a18-a829-cd02d49bd660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580173638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.580173638
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1735780195
Short name T923
Test name
Test status
Simulation time 59049248 ps
CPU time 1.21 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:14 PM PDT 24
Peak memory 217576 kb
Host smart-e1a6ce34-65cd-4bd6-95ed-520172dcdb36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735780195 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1735780195
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1907725569
Short name T870
Test name
Test status
Simulation time 30134055 ps
CPU time 0.86 seconds
Started Jul 15 07:24:42 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 208972 kb
Host smart-ed4d8f24-6451-4c95-b800-ac99c800ae25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907725569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1907725569
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.330913777
Short name T940
Test name
Test status
Simulation time 28727077 ps
CPU time 1.33 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:14 PM PDT 24
Peak memory 209188 kb
Host smart-fa32c5e0-841e-496d-a69d-043e3c00b855
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330913777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.330913777
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3392630669
Short name T925
Test name
Test status
Simulation time 2101301544 ps
CPU time 5.34 seconds
Started Jul 15 07:24:39 PM PDT 24
Finished Jul 15 07:25:18 PM PDT 24
Peak memory 208984 kb
Host smart-c034d8ba-25e9-4654-9a28-53ea3c75a49c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392630669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3392630669
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.194275654
Short name T963
Test name
Test status
Simulation time 977675029 ps
CPU time 8.51 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:21 PM PDT 24
Peak memory 209268 kb
Host smart-c8571889-db71-4fe6-a23d-fa9ff6b1299b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194275654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.194275654
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1649781570
Short name T979
Test name
Test status
Simulation time 390276129 ps
CPU time 2.9 seconds
Started Jul 15 07:24:36 PM PDT 24
Finished Jul 15 07:25:13 PM PDT 24
Peak memory 217500 kb
Host smart-0680b627-d97d-452b-a2d9-dbc86a4d238d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649781570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1649781570
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3976584123
Short name T986
Test name
Test status
Simulation time 957490653 ps
CPU time 5.96 seconds
Started Jul 15 07:24:39 PM PDT 24
Finished Jul 15 07:25:19 PM PDT 24
Peak memory 217748 kb
Host smart-f0f2d3f1-ce8a-41a1-9a7d-7dc1be8b6002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397658
4123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3976584123
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.780637571
Short name T165
Test name
Test status
Simulation time 359134488 ps
CPU time 1.73 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:15 PM PDT 24
Peak memory 217412 kb
Host smart-4b03f0eb-d33a-487f-b5d2-1a67ce44b440
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780637571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.780637571
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.948809559
Short name T242
Test name
Test status
Simulation time 127996430 ps
CPU time 1.31 seconds
Started Jul 15 07:24:40 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 217612 kb
Host smart-02e10f52-5a86-4b42-b4fd-df6b6dc077c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948809559 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.948809559
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.362737898
Short name T947
Test name
Test status
Simulation time 32022927 ps
CPU time 1.13 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:14 PM PDT 24
Peak memory 209328 kb
Host smart-dcaacac4-151c-4438-8d6d-9847990ce1b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362737898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.362737898
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1863884476
Short name T137
Test name
Test status
Simulation time 114940124 ps
CPU time 2.16 seconds
Started Jul 15 07:24:37 PM PDT 24
Finished Jul 15 07:25:15 PM PDT 24
Peak memory 217504 kb
Host smart-cd01fd23-6bc0-4be3-8f91-da0c98516ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863884476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1863884476
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.508512332
Short name T135
Test name
Test status
Simulation time 27808353 ps
CPU time 1.31 seconds
Started Jul 15 07:24:41 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 217684 kb
Host smart-e0b8a157-1f0b-4ba0-9d13-95cfd7cd77dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508512332 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.508512332
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.859143548
Short name T937
Test name
Test status
Simulation time 50463063 ps
CPU time 0.98 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:14 PM PDT 24
Peak memory 209392 kb
Host smart-25339c3a-a853-427b-8e9c-1b3fa457d493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859143548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.859143548
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.95518308
Short name T167
Test name
Test status
Simulation time 78843473 ps
CPU time 1.44 seconds
Started Jul 15 07:24:37 PM PDT 24
Finished Jul 15 07:25:14 PM PDT 24
Peak memory 209192 kb
Host smart-c2165cf4-3291-4607-9527-cb04384eda3c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95518308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_alert_test.95518308
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3291313472
Short name T978
Test name
Test status
Simulation time 868299441 ps
CPU time 19.77 seconds
Started Jul 15 07:24:39 PM PDT 24
Finished Jul 15 07:25:33 PM PDT 24
Peak memory 217136 kb
Host smart-a1b3a57e-ce41-44a7-a780-f8223af45c45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291313472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3291313472
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2004193756
Short name T169
Test name
Test status
Simulation time 3668425962 ps
CPU time 17.64 seconds
Started Jul 15 07:24:42 PM PDT 24
Finished Jul 15 07:25:33 PM PDT 24
Peak memory 209356 kb
Host smart-b57ad2e6-c72a-4cc7-890b-e3d442a2278d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004193756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2004193756
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3278177706
Short name T907
Test name
Test status
Simulation time 90881404 ps
CPU time 1.54 seconds
Started Jul 15 07:24:40 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 217520 kb
Host smart-7770000a-cb4c-4f12-80dc-a7fb9bf46a93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278177706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3278177706
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.694433376
Short name T988
Test name
Test status
Simulation time 703233187 ps
CPU time 2.62 seconds
Started Jul 15 07:24:39 PM PDT 24
Finished Jul 15 07:25:16 PM PDT 24
Peak memory 218852 kb
Host smart-d096b782-27b1-42dc-b364-f1a2ce179bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694433
376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.694433376
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.56577561
Short name T904
Test name
Test status
Simulation time 189412141 ps
CPU time 1.91 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:15 PM PDT 24
Peak memory 209304 kb
Host smart-1b86cd1f-0500-46f9-bb4d-0cf837cf4aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56577561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 9.lc_ctrl_jtag_csr_rw.56577561
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2414202667
Short name T237
Test name
Test status
Simulation time 37597473 ps
CPU time 1.32 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:14 PM PDT 24
Peak memory 209316 kb
Host smart-ac7de25e-7926-4cc9-b470-16c8fbec1d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414202667 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2414202667
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1721372767
Short name T932
Test name
Test status
Simulation time 19892535 ps
CPU time 1.18 seconds
Started Jul 15 07:24:36 PM PDT 24
Finished Jul 15 07:25:11 PM PDT 24
Peak memory 209332 kb
Host smart-c12b915b-b35f-4637-98c4-294e7564d700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721372767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1721372767
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3898262587
Short name T885
Test name
Test status
Simulation time 79735730 ps
CPU time 1.7 seconds
Started Jul 15 07:24:38 PM PDT 24
Finished Jul 15 07:25:15 PM PDT 24
Peak memory 217580 kb
Host smart-b13f9907-4c64-4a77-8907-c0f9c5cd57db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898262587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3898262587
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2448781646
Short name T386
Test name
Test status
Simulation time 252422107 ps
CPU time 2.1 seconds
Started Jul 15 06:29:26 PM PDT 24
Finished Jul 15 06:29:29 PM PDT 24
Peak memory 208960 kb
Host smart-c2fe568b-9c22-4ebc-9232-ef33bddef2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448781646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2448781646
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2239599328
Short name T196
Test name
Test status
Simulation time 146118971 ps
CPU time 0.77 seconds
Started Jul 15 06:29:20 PM PDT 24
Finished Jul 15 06:29:22 PM PDT 24
Peak memory 208844 kb
Host smart-f7c12227-3482-484c-9954-bc4a61cf9f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239599328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2239599328
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.811750039
Short name T402
Test name
Test status
Simulation time 280541704 ps
CPU time 12.68 seconds
Started Jul 15 06:29:23 PM PDT 24
Finished Jul 15 06:29:36 PM PDT 24
Peak memory 225952 kb
Host smart-53ad7e92-15d5-41dc-a16d-0574ec13f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811750039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.811750039
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.816271686
Short name T101
Test name
Test status
Simulation time 1746970246 ps
CPU time 17.94 seconds
Started Jul 15 06:29:21 PM PDT 24
Finished Jul 15 06:29:39 PM PDT 24
Peak memory 218136 kb
Host smart-9ec50a58-2b56-4bc8-8776-e83104b1f024
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816271686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.816271686
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.619975373
Short name T786
Test name
Test status
Simulation time 203724060 ps
CPU time 5.42 seconds
Started Jul 15 06:29:20 PM PDT 24
Finished Jul 15 06:29:26 PM PDT 24
Peak memory 217576 kb
Host smart-ede15c83-9984-4335-8d8f-76a72d78710c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619975373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.619975373
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1902047538
Short name T47
Test name
Test status
Simulation time 516394417 ps
CPU time 6.52 seconds
Started Jul 15 06:29:23 PM PDT 24
Finished Jul 15 06:29:30 PM PDT 24
Peak memory 218116 kb
Host smart-ddd00953-26de-439c-b88f-d75641a5f679
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902047538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1902047538
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.761257777
Short name T844
Test name
Test status
Simulation time 1309211069 ps
CPU time 34.67 seconds
Started Jul 15 06:29:21 PM PDT 24
Finished Jul 15 06:29:56 PM PDT 24
Peak memory 217608 kb
Host smart-effbf2bd-2cfa-4288-9d35-2e30f073c7a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761257777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.761257777
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3821835339
Short name T611
Test name
Test status
Simulation time 1690675489 ps
CPU time 9.66 seconds
Started Jul 15 06:29:19 PM PDT 24
Finished Jul 15 06:29:30 PM PDT 24
Peak memory 217668 kb
Host smart-4c54d99c-7e57-420d-8915-d7e26b3a11c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821835339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3821835339
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2177396760
Short name T757
Test name
Test status
Simulation time 1230019662 ps
CPU time 50.05 seconds
Started Jul 15 06:29:20 PM PDT 24
Finished Jul 15 06:30:10 PM PDT 24
Peak memory 267416 kb
Host smart-66d7f817-5532-4b5f-9ff1-6135622f4ae6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177396760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2177396760
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1505405007
Short name T416
Test name
Test status
Simulation time 768968026 ps
CPU time 12.8 seconds
Started Jul 15 06:29:19 PM PDT 24
Finished Jul 15 06:29:32 PM PDT 24
Peak memory 250928 kb
Host smart-eb602007-39a9-4ee9-ab06-d67061593d57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505405007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1505405007
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3237950567
Short name T303
Test name
Test status
Simulation time 74175355 ps
CPU time 3.73 seconds
Started Jul 15 06:29:20 PM PDT 24
Finished Jul 15 06:29:24 PM PDT 24
Peak memory 222356 kb
Host smart-d58df7eb-aca4-4198-94ab-8700e8c9e092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237950567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3237950567
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2985365025
Short name T84
Test name
Test status
Simulation time 182809152 ps
CPU time 5.28 seconds
Started Jul 15 06:29:19 PM PDT 24
Finished Jul 15 06:29:25 PM PDT 24
Peak memory 217596 kb
Host smart-189d88ad-9374-498f-9ccf-431d1d4c6cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985365025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2985365025
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.201117772
Short name T409
Test name
Test status
Simulation time 778157943 ps
CPU time 9.18 seconds
Started Jul 15 06:29:20 PM PDT 24
Finished Jul 15 06:29:30 PM PDT 24
Peak memory 218760 kb
Host smart-e9632590-4889-4392-b0b1-53025221b840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201117772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.201117772
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3825840225
Short name T259
Test name
Test status
Simulation time 680111532 ps
CPU time 11.66 seconds
Started Jul 15 06:29:24 PM PDT 24
Finished Jul 15 06:29:37 PM PDT 24
Peak memory 225932 kb
Host smart-6a7fbcec-9888-48e3-a309-fde3f720fa70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825840225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3825840225
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1574714283
Short name T213
Test name
Test status
Simulation time 644128941 ps
CPU time 13.05 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:39 PM PDT 24
Peak memory 225412 kb
Host smart-747592d9-fa1d-47cc-a1e8-3117bba5fadf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574714283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
574714283
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.557662817
Short name T286
Test name
Test status
Simulation time 520803115 ps
CPU time 11.77 seconds
Started Jul 15 06:29:21 PM PDT 24
Finished Jul 15 06:29:33 PM PDT 24
Peak memory 225936 kb
Host smart-3099ab1b-f116-4929-ad3a-7b9db5272adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557662817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.557662817
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1563439704
Short name T536
Test name
Test status
Simulation time 38988864 ps
CPU time 3.06 seconds
Started Jul 15 06:29:19 PM PDT 24
Finished Jul 15 06:29:23 PM PDT 24
Peak memory 214388 kb
Host smart-a1d545d9-99ea-4bdd-823f-15cb39141889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563439704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1563439704
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.4091592234
Short name T190
Test name
Test status
Simulation time 424376082 ps
CPU time 27.65 seconds
Started Jul 15 06:29:21 PM PDT 24
Finished Jul 15 06:29:49 PM PDT 24
Peak memory 246008 kb
Host smart-77ed4d10-1211-4cd2-b279-299a5daf6b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091592234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.4091592234
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.82437416
Short name T490
Test name
Test status
Simulation time 138751676 ps
CPU time 7.26 seconds
Started Jul 15 06:29:22 PM PDT 24
Finished Jul 15 06:29:30 PM PDT 24
Peak memory 250308 kb
Host smart-902116a5-47bc-435f-9e70-abdb2fbce729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82437416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.82437416
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2239406570
Short name T88
Test name
Test status
Simulation time 27271080587 ps
CPU time 88.61 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:30:55 PM PDT 24
Peak memory 272064 kb
Host smart-bba1b6cc-6dfd-4872-be09-9cbf558368b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239406570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2239406570
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2798156280
Short name T391
Test name
Test status
Simulation time 73051698 ps
CPU time 1.12 seconds
Started Jul 15 06:29:34 PM PDT 24
Finished Jul 15 06:29:36 PM PDT 24
Peak memory 208872 kb
Host smart-a31346ae-f5bf-41f3-8f2e-d8d42bdf574f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798156280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2798156280
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1752568129
Short name T13
Test name
Test status
Simulation time 41720996 ps
CPU time 0.77 seconds
Started Jul 15 06:29:24 PM PDT 24
Finished Jul 15 06:29:26 PM PDT 24
Peak memory 208876 kb
Host smart-d9422a93-0520-406a-8675-f317dde74333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752568129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1752568129
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3205255501
Short name T589
Test name
Test status
Simulation time 224388872 ps
CPU time 10 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:36 PM PDT 24
Peak memory 225944 kb
Host smart-0b8808cd-9719-4dc2-93f0-0fa54b90cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205255501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3205255501
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3833940899
Short name T10
Test name
Test status
Simulation time 252129367 ps
CPU time 4 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:30 PM PDT 24
Peak memory 217000 kb
Host smart-a8a945ca-982d-44de-9ba8-d70ba08a7c06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833940899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3833940899
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2067700626
Short name T828
Test name
Test status
Simulation time 5474179431 ps
CPU time 41.26 seconds
Started Jul 15 06:29:26 PM PDT 24
Finished Jul 15 06:30:08 PM PDT 24
Peak memory 218920 kb
Host smart-0a30b743-76ab-4f05-aa05-09de5cb75693
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067700626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2067700626
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.976446448
Short name T312
Test name
Test status
Simulation time 285367027 ps
CPU time 4.17 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:30 PM PDT 24
Peak memory 217504 kb
Host smart-8fad6bb6-0e9c-430b-ac22-eab4f550c98c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976446448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.976446448
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3435286535
Short name T748
Test name
Test status
Simulation time 330067571 ps
CPU time 11.22 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:37 PM PDT 24
Peak memory 218152 kb
Host smart-12b6913f-7e2f-4411-a4c4-7e83358e3c0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435286535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3435286535
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3424505312
Short name T90
Test name
Test status
Simulation time 1112706234 ps
CPU time 17.96 seconds
Started Jul 15 06:29:26 PM PDT 24
Finished Jul 15 06:29:45 PM PDT 24
Peak memory 217620 kb
Host smart-2cad38bf-efa0-4960-bf4e-13cb47fc6726
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424505312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3424505312
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3406030258
Short name T28
Test name
Test status
Simulation time 324280684 ps
CPU time 4.88 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:31 PM PDT 24
Peak memory 217672 kb
Host smart-6bd646b0-8f0a-4239-baaa-5d3d3c9c3e09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406030258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3406030258
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1901108371
Short name T647
Test name
Test status
Simulation time 5168742871 ps
CPU time 79.08 seconds
Started Jul 15 06:29:23 PM PDT 24
Finished Jul 15 06:30:43 PM PDT 24
Peak memory 283732 kb
Host smart-6ef7972b-a6fb-4acb-8384-77bd27befd07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901108371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1901108371
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.993324555
Short name T833
Test name
Test status
Simulation time 1913454893 ps
CPU time 22.41 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:48 PM PDT 24
Peak memory 250916 kb
Host smart-5bf7c659-e680-4028-bbc5-30cfbb5f1b97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993324555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.993324555
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1455815299
Short name T48
Test name
Test status
Simulation time 112319138 ps
CPU time 2.02 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:27 PM PDT 24
Peak memory 222000 kb
Host smart-5b2a2890-ea0b-4e70-83de-1324c061a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455815299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1455815299
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.814858441
Short name T75
Test name
Test status
Simulation time 196338959 ps
CPU time 8.19 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:33 PM PDT 24
Peak memory 222924 kb
Host smart-7ebf37c8-4c74-48a8-98a5-71d255b71c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814858441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.814858441
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2965309155
Short name T61
Test name
Test status
Simulation time 116243867 ps
CPU time 23.22 seconds
Started Jul 15 06:29:38 PM PDT 24
Finished Jul 15 06:30:01 PM PDT 24
Peak memory 281416 kb
Host smart-550beb2f-edc9-44c3-bbc7-ea88188f1a9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965309155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2965309155
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2213114424
Short name T741
Test name
Test status
Simulation time 1413781121 ps
CPU time 16.47 seconds
Started Jul 15 06:29:31 PM PDT 24
Finished Jul 15 06:29:47 PM PDT 24
Peak memory 225964 kb
Host smart-ee9a3044-3bbb-49cb-b794-49558ed7cfba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213114424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2213114424
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3468449341
Short name T849
Test name
Test status
Simulation time 6965932751 ps
CPU time 13.74 seconds
Started Jul 15 06:29:31 PM PDT 24
Finished Jul 15 06:29:45 PM PDT 24
Peak memory 226036 kb
Host smart-9061498c-5b2a-4a51-851e-c4c02e3ad9c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468449341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3468449341
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2777152044
Short name T72
Test name
Test status
Simulation time 470533344 ps
CPU time 11.75 seconds
Started Jul 15 06:29:30 PM PDT 24
Finished Jul 15 06:29:42 PM PDT 24
Peak memory 218160 kb
Host smart-cd0c21cb-aff2-489a-aef6-753977a8cb10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777152044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
777152044
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4143067748
Short name T848
Test name
Test status
Simulation time 624968936 ps
CPU time 10.51 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:36 PM PDT 24
Peak memory 218184 kb
Host smart-968784d8-9df6-469f-9adf-ba83eb27775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143067748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4143067748
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.747371709
Short name T769
Test name
Test status
Simulation time 53854811 ps
CPU time 2.28 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:28 PM PDT 24
Peak memory 214392 kb
Host smart-dbea3a6e-95f6-43d6-a6df-75a6ece0612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747371709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.747371709
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2413295535
Short name T713
Test name
Test status
Simulation time 1304668769 ps
CPU time 31.38 seconds
Started Jul 15 06:29:27 PM PDT 24
Finished Jul 15 06:29:58 PM PDT 24
Peak memory 250812 kb
Host smart-3956e7ca-c532-4a5f-863d-c5f21b9fe5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413295535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2413295535
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1932033718
Short name T429
Test name
Test status
Simulation time 227878359 ps
CPU time 3.4 seconds
Started Jul 15 06:29:25 PM PDT 24
Finished Jul 15 06:29:29 PM PDT 24
Peak memory 218084 kb
Host smart-9b051a82-614d-453c-b9fb-4f6d2388f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932033718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1932033718
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3963058225
Short name T191
Test name
Test status
Simulation time 13457588 ps
CPU time 0.91 seconds
Started Jul 15 06:29:27 PM PDT 24
Finished Jul 15 06:29:28 PM PDT 24
Peak memory 211912 kb
Host smart-d29dcf98-0e2a-46f5-89d5-732da1bcff51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963058225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3963058225
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.4124548371
Short name T192
Test name
Test status
Simulation time 24670109 ps
CPU time 0.99 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:29 PM PDT 24
Peak memory 208944 kb
Host smart-1ea1ade6-78ba-4c03-97a8-3f0cde59b667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124548371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4124548371
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1740255652
Short name T125
Test name
Test status
Simulation time 238833715 ps
CPU time 10.42 seconds
Started Jul 15 06:30:25 PM PDT 24
Finished Jul 15 06:30:36 PM PDT 24
Peak memory 218120 kb
Host smart-139cbc2a-7ff5-403d-adf4-60f0394435fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740255652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1740255652
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2775384858
Short name T473
Test name
Test status
Simulation time 526914471 ps
CPU time 2.25 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 217032 kb
Host smart-7d8c4567-ac81-4e86-a050-0574738cf640
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775384858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2775384858
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1317798873
Short name T662
Test name
Test status
Simulation time 8780396908 ps
CPU time 32.15 seconds
Started Jul 15 06:30:23 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 226032 kb
Host smart-c45f5373-62dc-4ad4-8b2c-35bcf01e2172
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317798873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1317798873
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2091449930
Short name T578
Test name
Test status
Simulation time 298185776 ps
CPU time 3.08 seconds
Started Jul 15 06:30:24 PM PDT 24
Finished Jul 15 06:30:28 PM PDT 24
Peak memory 218164 kb
Host smart-2276ba5b-1950-42a2-876d-8519cdeb9ddf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091449930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2091449930
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3887807760
Short name T637
Test name
Test status
Simulation time 283298152 ps
CPU time 4.06 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 217640 kb
Host smart-ce1f17f0-e5c0-42b4-bba7-69a8d1992ee9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887807760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3887807760
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2551305571
Short name T122
Test name
Test status
Simulation time 2431904328 ps
CPU time 75.92 seconds
Started Jul 15 06:30:25 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 250996 kb
Host smart-2f2a70e2-b1bd-40ce-a68b-ba75ada4728b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551305571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2551305571
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2129965848
Short name T573
Test name
Test status
Simulation time 481587381 ps
CPU time 21.5 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:30:45 PM PDT 24
Peak memory 250900 kb
Host smart-0614b0ad-7df7-4966-9715-28e163dc00e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129965848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2129965848
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.559889665
Short name T375
Test name
Test status
Simulation time 67918376 ps
CPU time 2.71 seconds
Started Jul 15 06:30:23 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 222484 kb
Host smart-120fa754-c804-43b8-92dc-331f31802d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559889665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.559889665
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3349396378
Short name T545
Test name
Test status
Simulation time 200108728 ps
CPU time 10.45 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 225904 kb
Host smart-2bc3f3c7-62f1-4bb3-a493-5c2e1e900df3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349396378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3349396378
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1441367266
Short name T299
Test name
Test status
Simulation time 4561469665 ps
CPU time 28.23 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:57 PM PDT 24
Peak memory 226056 kb
Host smart-4fec58b2-be31-4d3c-86e2-b19a0be7c177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441367266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1441367266
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1346064373
Short name T796
Test name
Test status
Simulation time 714800306 ps
CPU time 7.96 seconds
Started Jul 15 06:30:28 PM PDT 24
Finished Jul 15 06:30:37 PM PDT 24
Peak memory 218160 kb
Host smart-fa40da65-acbc-4069-97dd-418922bd894b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346064373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1346064373
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.291238350
Short name T1
Test name
Test status
Simulation time 35849711 ps
CPU time 1.01 seconds
Started Jul 15 06:30:25 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 212076 kb
Host smart-be8048b0-578d-4df5-824a-aa1d18ef3efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291238350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.291238350
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3757104285
Short name T561
Test name
Test status
Simulation time 176860196 ps
CPU time 7.36 seconds
Started Jul 15 06:30:24 PM PDT 24
Finished Jul 15 06:30:32 PM PDT 24
Peak memory 250908 kb
Host smart-fd90dcf5-ff9a-41f8-bd13-3cb5e428abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757104285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3757104285
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2320225398
Short name T648
Test name
Test status
Simulation time 26923095704 ps
CPU time 118.18 seconds
Started Jul 15 06:30:28 PM PDT 24
Finished Jul 15 06:32:27 PM PDT 24
Peak memory 291308 kb
Host smart-0d7e9091-5b92-4baa-ae40-08e91d403737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320225398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2320225398
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2917168216
Short name T455
Test name
Test status
Simulation time 61909695 ps
CPU time 0.93 seconds
Started Jul 15 06:30:24 PM PDT 24
Finished Jul 15 06:30:26 PM PDT 24
Peak memory 212900 kb
Host smart-0d7cd868-66e0-4452-9011-08b546de7465
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917168216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2917168216
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2808811136
Short name T179
Test name
Test status
Simulation time 18061295 ps
CPU time 0.94 seconds
Started Jul 15 06:30:32 PM PDT 24
Finished Jul 15 06:30:33 PM PDT 24
Peak memory 208880 kb
Host smart-aef8073e-0d75-4e3a-8c97-c44b8b82db84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808811136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2808811136
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3246651613
Short name T329
Test name
Test status
Simulation time 521106556 ps
CPU time 10.16 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 218164 kb
Host smart-c347f414-3940-4da1-91ca-604024157fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246651613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3246651613
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2690282058
Short name T803
Test name
Test status
Simulation time 292324812 ps
CPU time 7.38 seconds
Started Jul 15 06:30:26 PM PDT 24
Finished Jul 15 06:30:35 PM PDT 24
Peak memory 217628 kb
Host smart-302d6306-c1f8-45f4-b11a-3feaa611a26d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690282058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2690282058
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1223169395
Short name T765
Test name
Test status
Simulation time 2953648178 ps
CPU time 34.59 seconds
Started Jul 15 06:30:34 PM PDT 24
Finished Jul 15 06:31:09 PM PDT 24
Peak memory 218876 kb
Host smart-b133badc-0a13-4f3d-8fb5-5eab46f5589d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223169395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1223169395
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1528277618
Short name T574
Test name
Test status
Simulation time 1482096086 ps
CPU time 7.36 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:35 PM PDT 24
Peak memory 218280 kb
Host smart-1d077303-1ba0-4c74-a2fb-ad9851b7b1ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528277618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1528277618
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2401433613
Short name T85
Test name
Test status
Simulation time 829280335 ps
CPU time 3.43 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:31 PM PDT 24
Peak memory 217804 kb
Host smart-008a5aec-bc86-4835-b2f1-ec80564d3d04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401433613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2401433613
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.913919402
Short name T733
Test name
Test status
Simulation time 3295764940 ps
CPU time 56.1 seconds
Started Jul 15 06:30:31 PM PDT 24
Finished Jul 15 06:31:28 PM PDT 24
Peak memory 252284 kb
Host smart-155c1cfc-8d78-4833-b938-7073bcb43d40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913919402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.913919402
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3449945106
Short name T295
Test name
Test status
Simulation time 4640804914 ps
CPU time 34.41 seconds
Started Jul 15 06:30:28 PM PDT 24
Finished Jul 15 06:31:03 PM PDT 24
Peak memory 250964 kb
Host smart-c9121f44-4ce7-495b-bd72-c6c1a2539ce7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449945106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3449945106
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2874536991
Short name T543
Test name
Test status
Simulation time 81517018 ps
CPU time 2 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 218076 kb
Host smart-ea5cf642-b800-42ed-af8b-af1ed737478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874536991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2874536991
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2637960478
Short name T676
Test name
Test status
Simulation time 913481635 ps
CPU time 12.9 seconds
Started Jul 15 06:30:29 PM PDT 24
Finished Jul 15 06:30:43 PM PDT 24
Peak memory 225956 kb
Host smart-67fc4163-1fa4-4592-a05d-559bddd98bf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637960478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2637960478
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1992005328
Short name T19
Test name
Test status
Simulation time 596525712 ps
CPU time 12.25 seconds
Started Jul 15 06:30:32 PM PDT 24
Finished Jul 15 06:30:45 PM PDT 24
Peak memory 225916 kb
Host smart-985d559e-67c9-4f85-9e84-cc742cbc0002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992005328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1992005328
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3092377624
Short name T795
Test name
Test status
Simulation time 2225522352 ps
CPU time 8.31 seconds
Started Jul 15 06:30:28 PM PDT 24
Finished Jul 15 06:30:37 PM PDT 24
Peak memory 218140 kb
Host smart-fcb2d236-5e84-47d0-8f09-492997dd72e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092377624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3092377624
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2308625456
Short name T343
Test name
Test status
Simulation time 1093672150 ps
CPU time 12.31 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:40 PM PDT 24
Peak memory 225976 kb
Host smart-fd6ad4bc-4574-4ab1-8166-dffedcab87bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308625456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2308625456
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2906099789
Short name T93
Test name
Test status
Simulation time 1324474657 ps
CPU time 3.39 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:32 PM PDT 24
Peak memory 217736 kb
Host smart-d6fe5966-b58b-4736-97d8-3abc396d5535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906099789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2906099789
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3447002744
Short name T65
Test name
Test status
Simulation time 1058385554 ps
CPU time 26.24 seconds
Started Jul 15 06:30:26 PM PDT 24
Finished Jul 15 06:30:52 PM PDT 24
Peak memory 250896 kb
Host smart-e4fc2d0c-55b6-4a66-91c9-a76f180dba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447002744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3447002744
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2716090805
Short name T197
Test name
Test status
Simulation time 430992073 ps
CPU time 3.31 seconds
Started Jul 15 06:30:28 PM PDT 24
Finished Jul 15 06:30:33 PM PDT 24
Peak memory 222460 kb
Host smart-1c81737c-0ef1-49b8-b426-dcc05f60976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716090805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2716090805
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2690849161
Short name T745
Test name
Test status
Simulation time 1502703993 ps
CPU time 66.41 seconds
Started Jul 15 06:30:31 PM PDT 24
Finished Jul 15 06:31:38 PM PDT 24
Peak memory 250956 kb
Host smart-6ee21586-3174-4940-a2a2-2e71cd7c33e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690849161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2690849161
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2310061112
Short name T170
Test name
Test status
Simulation time 139068061595 ps
CPU time 1118.45 seconds
Started Jul 15 06:30:36 PM PDT 24
Finished Jul 15 06:49:15 PM PDT 24
Peak memory 283848 kb
Host smart-a12fc301-87d2-43d5-83fa-ad5e9f12aefb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2310061112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2310061112
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1994388448
Short name T283
Test name
Test status
Simulation time 37097464 ps
CPU time 0.97 seconds
Started Jul 15 06:30:25 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 211876 kb
Host smart-634cb12a-e288-40f4-a048-9a262c9bd635
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994388448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1994388448
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2334218936
Short name T288
Test name
Test status
Simulation time 30222256 ps
CPU time 1.03 seconds
Started Jul 15 06:30:42 PM PDT 24
Finished Jul 15 06:30:44 PM PDT 24
Peak memory 208868 kb
Host smart-b8cd6a1a-8a54-4a6d-a610-d38a79671d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334218936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2334218936
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1016201335
Short name T44
Test name
Test status
Simulation time 1378065858 ps
CPU time 9.85 seconds
Started Jul 15 06:30:31 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 218060 kb
Host smart-429808bb-d169-460e-9c3c-4bc8ec244015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016201335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1016201335
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2603628244
Short name T34
Test name
Test status
Simulation time 1151302501 ps
CPU time 6.63 seconds
Started Jul 15 06:30:33 PM PDT 24
Finished Jul 15 06:30:40 PM PDT 24
Peak memory 217252 kb
Host smart-d8005dc8-4c6a-4641-a1f6-d6ab0cb4107d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603628244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2603628244
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1777412199
Short name T834
Test name
Test status
Simulation time 9636938883 ps
CPU time 24.22 seconds
Started Jul 15 06:30:31 PM PDT 24
Finished Jul 15 06:30:55 PM PDT 24
Peak memory 225988 kb
Host smart-214b514c-a219-4ba3-a222-d7c9e8f57a5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777412199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1777412199
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3123848452
Short name T395
Test name
Test status
Simulation time 208470568 ps
CPU time 4.85 seconds
Started Jul 15 06:30:34 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 218112 kb
Host smart-d826e869-2c41-4abe-8352-dc8cad5f4f13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123848452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3123848452
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3506617957
Short name T355
Test name
Test status
Simulation time 96530299 ps
CPU time 3.64 seconds
Started Jul 15 06:30:37 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 217796 kb
Host smart-06ea8df5-4d64-4b9d-9598-f44ff7625e8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506617957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3506617957
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2867424138
Short name T778
Test name
Test status
Simulation time 1895428614 ps
CPU time 40.15 seconds
Started Jul 15 06:30:32 PM PDT 24
Finished Jul 15 06:31:13 PM PDT 24
Peak memory 250916 kb
Host smart-f788b5bd-07e5-4c40-ac62-022ae9cd731c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867424138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2867424138
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.336402144
Short name T703
Test name
Test status
Simulation time 336055856 ps
CPU time 12.11 seconds
Started Jul 15 06:30:35 PM PDT 24
Finished Jul 15 06:30:47 PM PDT 24
Peak memory 250924 kb
Host smart-9f1421a8-d2b9-4137-8321-d3202ebe16aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336402144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.336402144
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2384433311
Short name T804
Test name
Test status
Simulation time 362310350 ps
CPU time 4.26 seconds
Started Jul 15 06:30:42 PM PDT 24
Finished Jul 15 06:30:47 PM PDT 24
Peak memory 218080 kb
Host smart-7f165a76-344c-4192-8cb3-a973df40580e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384433311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2384433311
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3612408522
Short name T181
Test name
Test status
Simulation time 1155422198 ps
CPU time 12.78 seconds
Started Jul 15 06:30:42 PM PDT 24
Finished Jul 15 06:30:55 PM PDT 24
Peak memory 225832 kb
Host smart-80a3dfc0-e078-46e2-bcac-df961ad95fff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612408522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3612408522
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.383281779
Short name T707
Test name
Test status
Simulation time 201839320 ps
CPU time 9.05 seconds
Started Jul 15 06:30:36 PM PDT 24
Finished Jul 15 06:30:45 PM PDT 24
Peak memory 225864 kb
Host smart-2e0f8662-ed98-4e00-8245-0c723cc1f39f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383281779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.383281779
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3462148971
Short name T284
Test name
Test status
Simulation time 203713712 ps
CPU time 6.66 seconds
Started Jul 15 06:30:34 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 225908 kb
Host smart-e603d85e-ddc8-4251-aa2e-20ba2550eb14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462148971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3462148971
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2797939454
Short name T249
Test name
Test status
Simulation time 234731964 ps
CPU time 9.27 seconds
Started Jul 15 06:30:31 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 224532 kb
Host smart-674f85ca-acba-41f1-9c91-632de808e1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797939454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2797939454
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1500542586
Short name T362
Test name
Test status
Simulation time 350369927 ps
CPU time 1.74 seconds
Started Jul 15 06:30:32 PM PDT 24
Finished Jul 15 06:30:35 PM PDT 24
Peak memory 213908 kb
Host smart-49b5c175-c863-4997-bbcf-dab619b712df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500542586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1500542586
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1356854951
Short name T628
Test name
Test status
Simulation time 635522897 ps
CPU time 28.27 seconds
Started Jul 15 06:30:33 PM PDT 24
Finished Jul 15 06:31:02 PM PDT 24
Peak memory 250924 kb
Host smart-ad53788f-87d6-4234-a2ae-2a98dec9e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356854951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1356854951
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.4047143166
Short name T633
Test name
Test status
Simulation time 180517899 ps
CPU time 3.27 seconds
Started Jul 15 06:30:33 PM PDT 24
Finished Jul 15 06:30:37 PM PDT 24
Peak memory 226356 kb
Host smart-32b6d04e-f371-4f76-bd18-e211b6af2e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047143166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.4047143166
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3808123239
Short name T505
Test name
Test status
Simulation time 31134559178 ps
CPU time 289.23 seconds
Started Jul 15 06:30:36 PM PDT 24
Finished Jul 15 06:35:26 PM PDT 24
Peak memory 316380 kb
Host smart-45b4f555-e6be-434e-9393-85b1a0a9a155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808123239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3808123239
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2304969213
Short name T127
Test name
Test status
Simulation time 11594068944 ps
CPU time 105.71 seconds
Started Jul 15 06:30:36 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 227852 kb
Host smart-7d8e685a-ca49-4981-9311-95212d89070b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2304969213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2304969213
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4088847135
Short name T555
Test name
Test status
Simulation time 22610699 ps
CPU time 0.92 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 208424 kb
Host smart-cc2edb42-7931-40ff-b2a2-6c7c03328e2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088847135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4088847135
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1650388057
Short name T498
Test name
Test status
Simulation time 1584602593 ps
CPU time 11.87 seconds
Started Jul 15 06:30:37 PM PDT 24
Finished Jul 15 06:30:49 PM PDT 24
Peak memory 218108 kb
Host smart-d4d58399-6194-433f-a492-58ef4ecaea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650388057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1650388057
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.348005175
Short name T596
Test name
Test status
Simulation time 467956542 ps
CPU time 5.97 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:30:45 PM PDT 24
Peak memory 216984 kb
Host smart-ddf0d7b0-cbc7-467d-aad4-d2c99d6a4408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348005175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.348005175
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.646134314
Short name T749
Test name
Test status
Simulation time 2278103801 ps
CPU time 36.81 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:31:15 PM PDT 24
Peak memory 226024 kb
Host smart-f31ed3db-56f9-4a99-9d57-30852092e19d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646134314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.646134314
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.4139985009
Short name T46
Test name
Test status
Simulation time 1499940467 ps
CPU time 6.63 seconds
Started Jul 15 06:30:39 PM PDT 24
Finished Jul 15 06:30:46 PM PDT 24
Peak memory 222804 kb
Host smart-7c3ab932-a682-4e23-91ab-fcb2f41fe2aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139985009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.4139985009
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3667134126
Short name T475
Test name
Test status
Simulation time 1073729491 ps
CPU time 16.02 seconds
Started Jul 15 06:30:42 PM PDT 24
Finished Jul 15 06:30:59 PM PDT 24
Peak memory 217636 kb
Host smart-bf7454ba-35fc-49af-867f-5c8509c8131b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667134126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3667134126
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.954971543
Short name T394
Test name
Test status
Simulation time 5071576137 ps
CPU time 34.25 seconds
Started Jul 15 06:30:35 PM PDT 24
Finished Jul 15 06:31:10 PM PDT 24
Peak memory 283672 kb
Host smart-bc955841-1353-4e6f-b9d3-2c0d204c3692
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954971543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.954971543
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2728784167
Short name T641
Test name
Test status
Simulation time 338645416 ps
CPU time 11.47 seconds
Started Jul 15 06:30:42 PM PDT 24
Finished Jul 15 06:30:54 PM PDT 24
Peak memory 250916 kb
Host smart-dc36927e-a0a7-4bdb-9627-6383674ab3d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728784167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2728784167
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.126188283
Short name T376
Test name
Test status
Simulation time 70149602 ps
CPU time 2.93 seconds
Started Jul 15 06:30:36 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 218056 kb
Host smart-a48c7231-72ca-48fb-9507-cdfe529b2256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126188283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.126188283
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2946979139
Short name T800
Test name
Test status
Simulation time 287151327 ps
CPU time 10.55 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:30:49 PM PDT 24
Peak memory 225976 kb
Host smart-cd8e4496-9c75-40fc-8f0f-b46783a4a547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946979139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2946979139
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1356405288
Short name T353
Test name
Test status
Simulation time 1532101270 ps
CPU time 10.16 seconds
Started Jul 15 06:30:40 PM PDT 24
Finished Jul 15 06:30:51 PM PDT 24
Peak memory 225856 kb
Host smart-f46a9183-8f9a-401c-ba93-af9de926de60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356405288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1356405288
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1035900399
Short name T511
Test name
Test status
Simulation time 1421579273 ps
CPU time 10.35 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:30:49 PM PDT 24
Peak memory 218172 kb
Host smart-436b0835-7c80-4f1e-a4fb-52eb87f8b817
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035900399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1035900399
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3765096881
Short name T863
Test name
Test status
Simulation time 588845233 ps
CPU time 7.79 seconds
Started Jul 15 06:30:42 PM PDT 24
Finished Jul 15 06:30:50 PM PDT 24
Peak memory 224640 kb
Host smart-b7a20184-0b08-40ee-a11f-a9f8365ef61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765096881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3765096881
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.4175763495
Short name T629
Test name
Test status
Simulation time 108296878 ps
CPU time 3.01 seconds
Started Jul 15 06:30:34 PM PDT 24
Finished Jul 15 06:30:37 PM PDT 24
Peak memory 214520 kb
Host smart-10a863b3-b5ff-4d91-bb87-40cce9dcb8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175763495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.4175763495
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.295135507
Short name T605
Test name
Test status
Simulation time 833969327 ps
CPU time 18.15 seconds
Started Jul 15 06:30:33 PM PDT 24
Finished Jul 15 06:30:52 PM PDT 24
Peak memory 250884 kb
Host smart-a7afa15d-5cc0-455a-a4b5-a60a1a9d1917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295135507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.295135507
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.265811111
Short name T658
Test name
Test status
Simulation time 135990210 ps
CPU time 7.67 seconds
Started Jul 15 06:30:35 PM PDT 24
Finished Jul 15 06:30:43 PM PDT 24
Peak memory 250940 kb
Host smart-9cc97687-8f9f-40f1-b869-8a3e1e9ba11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265811111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.265811111
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3812543440
Short name T219
Test name
Test status
Simulation time 5926277393 ps
CPU time 111.44 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:32:31 PM PDT 24
Peak memory 249972 kb
Host smart-13474c25-ba69-4e76-a8c8-45c6df682b39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812543440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3812543440
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2024896669
Short name T575
Test name
Test status
Simulation time 15635489 ps
CPU time 1.12 seconds
Started Jul 15 06:30:35 PM PDT 24
Finished Jul 15 06:30:36 PM PDT 24
Peak memory 211620 kb
Host smart-14554970-6eae-40fa-964e-51ccdaecb778
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024896669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2024896669
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2061356650
Short name T373
Test name
Test status
Simulation time 16641347 ps
CPU time 0.92 seconds
Started Jul 15 06:30:43 PM PDT 24
Finished Jul 15 06:30:45 PM PDT 24
Peak memory 208896 kb
Host smart-7c9dea5a-2d7f-44b8-aa34-59f913abbc1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061356650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2061356650
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1299216049
Short name T207
Test name
Test status
Simulation time 358637581 ps
CPU time 14.58 seconds
Started Jul 15 06:30:46 PM PDT 24
Finished Jul 15 06:31:01 PM PDT 24
Peak memory 225976 kb
Host smart-f92b71b0-d1e7-49f5-b07c-283779000319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299216049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1299216049
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2542733779
Short name T820
Test name
Test status
Simulation time 22161300203 ps
CPU time 31.17 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:31:15 PM PDT 24
Peak memory 218876 kb
Host smart-4ff28f8b-620c-4f0b-82c7-71676e2d76e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542733779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2542733779
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3646017620
Short name T32
Test name
Test status
Simulation time 335981495 ps
CPU time 3.31 seconds
Started Jul 15 06:30:43 PM PDT 24
Finished Jul 15 06:30:46 PM PDT 24
Peak memory 218128 kb
Host smart-f107db7c-ef8d-488a-83d7-222d49629254
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646017620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3646017620
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2716989398
Short name T87
Test name
Test status
Simulation time 233970767 ps
CPU time 1.51 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:30:47 PM PDT 24
Peak memory 217644 kb
Host smart-e4b172ec-1019-46b8-96b4-51054de21c04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716989398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2716989398
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3214881188
Short name T326
Test name
Test status
Simulation time 1692133989 ps
CPU time 51.55 seconds
Started Jul 15 06:30:45 PM PDT 24
Finished Jul 15 06:31:37 PM PDT 24
Peak memory 250884 kb
Host smart-f58f8b6b-81a0-41f3-9900-10742ab79e4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214881188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3214881188
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4178553559
Short name T29
Test name
Test status
Simulation time 1402771717 ps
CPU time 21.72 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:31:07 PM PDT 24
Peak memory 224228 kb
Host smart-d1d4b68e-54f9-4a77-bab2-20ac8bc6014e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178553559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4178553559
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4034988778
Short name T266
Test name
Test status
Simulation time 103612541 ps
CPU time 4.32 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:30:49 PM PDT 24
Peak memory 218144 kb
Host smart-1bd56fe6-8ece-44dc-9c18-ef0e87262e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034988778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4034988778
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2721321629
Short name T425
Test name
Test status
Simulation time 1819849261 ps
CPU time 17.89 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:31:03 PM PDT 24
Peak memory 225984 kb
Host smart-66ea4c32-9f31-4e28-bf65-c397bae38654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721321629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2721321629
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.694012763
Short name T572
Test name
Test status
Simulation time 245713234 ps
CPU time 9.07 seconds
Started Jul 15 06:30:47 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 225964 kb
Host smart-1380a3d7-183a-4d38-9090-e27befa87df8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694012763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.694012763
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.137928415
Short name T298
Test name
Test status
Simulation time 432514601 ps
CPU time 11.04 seconds
Started Jul 15 06:30:43 PM PDT 24
Finished Jul 15 06:30:54 PM PDT 24
Peak memory 218176 kb
Host smart-668e6457-c6e5-4cea-ad9d-6355438e35d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137928415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.137928415
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3754462500
Short name T379
Test name
Test status
Simulation time 944523615 ps
CPU time 12.7 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:30:57 PM PDT 24
Peak memory 225308 kb
Host smart-161a9d4c-809b-468a-9d11-f6b7aad64f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754462500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3754462500
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1212218485
Short name T83
Test name
Test status
Simulation time 173246128 ps
CPU time 3.02 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 217648 kb
Host smart-6973613d-a4fd-4911-a4cd-61f5c1f69c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212218485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1212218485
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3831882923
Short name T858
Test name
Test status
Simulation time 901258217 ps
CPU time 31.45 seconds
Started Jul 15 06:30:45 PM PDT 24
Finished Jul 15 06:31:17 PM PDT 24
Peak memory 250800 kb
Host smart-e73037e3-3bac-4eb9-95ba-56777f525fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831882923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3831882923
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2891403904
Short name T789
Test name
Test status
Simulation time 173845223 ps
CPU time 7.36 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:30:52 PM PDT 24
Peak memory 250900 kb
Host smart-9666dc79-8c38-477a-a836-7af4ffea4567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891403904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2891403904
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.78382830
Short name T359
Test name
Test status
Simulation time 273246796485 ps
CPU time 417.74 seconds
Started Jul 15 06:30:44 PM PDT 24
Finished Jul 15 06:37:42 PM PDT 24
Peak memory 250892 kb
Host smart-074009fb-d9e8-4b7f-80f8-4c7702242cb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78382830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.lc_ctrl_stress_all.78382830
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.281039044
Short name T679
Test name
Test status
Simulation time 89575127 ps
CPU time 0.81 seconds
Started Jul 15 06:30:38 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 211848 kb
Host smart-feacc1e2-d9a4-47b9-b6e2-a22e2507da2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281039044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.281039044
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2765735263
Short name T640
Test name
Test status
Simulation time 102642360 ps
CPU time 1.04 seconds
Started Jul 15 06:30:51 PM PDT 24
Finished Jul 15 06:30:52 PM PDT 24
Peak memory 208892 kb
Host smart-8fa6a3a5-814e-4597-94b5-bea03dad0a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765735263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2765735263
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3722210371
Short name T562
Test name
Test status
Simulation time 583026210 ps
CPU time 3.79 seconds
Started Jul 15 06:30:50 PM PDT 24
Finished Jul 15 06:30:54 PM PDT 24
Peak memory 217060 kb
Host smart-acb0a7f5-391a-4cd2-9257-75b619ec6453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722210371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3722210371
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1049731583
Short name T790
Test name
Test status
Simulation time 7138460734 ps
CPU time 53.58 seconds
Started Jul 15 06:30:51 PM PDT 24
Finished Jul 15 06:31:45 PM PDT 24
Peak memory 226000 kb
Host smart-5be2cac2-028c-4098-9004-cdbf8077ad86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049731583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1049731583
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2020120178
Short name T200
Test name
Test status
Simulation time 2229330942 ps
CPU time 8.39 seconds
Started Jul 15 06:30:52 PM PDT 24
Finished Jul 15 06:31:01 PM PDT 24
Peak memory 218236 kb
Host smart-7fafd8f6-42fa-4650-8518-7dd6705c9a45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020120178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2020120178
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.251179308
Short name T6
Test name
Test status
Simulation time 473763259 ps
CPU time 3.18 seconds
Started Jul 15 06:30:50 PM PDT 24
Finished Jul 15 06:30:54 PM PDT 24
Peak memory 217652 kb
Host smart-385d5579-4c5c-46a9-acbb-40a64d91f981
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251179308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
251179308
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3777548493
Short name T447
Test name
Test status
Simulation time 7388653038 ps
CPU time 76.44 seconds
Started Jul 15 06:30:49 PM PDT 24
Finished Jul 15 06:32:06 PM PDT 24
Peak memory 283676 kb
Host smart-96ad4c61-67e9-4daa-ad9a-6b17efeab526
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777548493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3777548493
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2586470268
Short name T866
Test name
Test status
Simulation time 2541021059 ps
CPU time 11.73 seconds
Started Jul 15 06:30:51 PM PDT 24
Finished Jul 15 06:31:03 PM PDT 24
Peak memory 224108 kb
Host smart-a3de3140-dc06-40c7-a95e-d1238619f8c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586470268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2586470268
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.676569428
Short name T380
Test name
Test status
Simulation time 89344185 ps
CPU time 2.81 seconds
Started Jul 15 06:30:50 PM PDT 24
Finished Jul 15 06:30:53 PM PDT 24
Peak memory 222440 kb
Host smart-1b8da9d7-b261-4d2d-a84b-ad0a7775c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676569428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.676569428
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3608238351
Short name T304
Test name
Test status
Simulation time 768558381 ps
CPU time 8.85 seconds
Started Jul 15 06:30:51 PM PDT 24
Finished Jul 15 06:31:00 PM PDT 24
Peak memory 225948 kb
Host smart-8edb4f43-15fa-47d3-9766-f53a8f7d2831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608238351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3608238351
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3410182870
Short name T701
Test name
Test status
Simulation time 311955623 ps
CPU time 10.18 seconds
Started Jul 15 06:30:52 PM PDT 24
Finished Jul 15 06:31:02 PM PDT 24
Peak memory 225964 kb
Host smart-f3f3137e-b7f5-49d9-a16a-30acc21e3a7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410182870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3410182870
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3250838255
Short name T538
Test name
Test status
Simulation time 344854541 ps
CPU time 9.82 seconds
Started Jul 15 06:30:49 PM PDT 24
Finished Jul 15 06:31:00 PM PDT 24
Peak memory 218152 kb
Host smart-34bd0b50-7e94-4928-8e23-0c5598763326
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250838255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3250838255
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1925637283
Short name T838
Test name
Test status
Simulation time 194921370 ps
CPU time 9.15 seconds
Started Jul 15 06:30:51 PM PDT 24
Finished Jul 15 06:31:00 PM PDT 24
Peak memory 218336 kb
Host smart-1ae79782-b429-4b44-a6e4-1db1ab17d0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925637283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1925637283
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1433309305
Short name T81
Test name
Test status
Simulation time 56149682 ps
CPU time 2.35 seconds
Started Jul 15 06:30:43 PM PDT 24
Finished Jul 15 06:30:46 PM PDT 24
Peak memory 214564 kb
Host smart-c4fb9eb4-2012-4847-b63e-cc491041dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433309305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1433309305
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.700190699
Short name T371
Test name
Test status
Simulation time 211486916 ps
CPU time 18.02 seconds
Started Jul 15 06:30:52 PM PDT 24
Finished Jul 15 06:31:11 PM PDT 24
Peak memory 250900 kb
Host smart-e7f04ebe-1808-4968-91f4-936844e4f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700190699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.700190699
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1272495036
Short name T435
Test name
Test status
Simulation time 66135342 ps
CPU time 6.91 seconds
Started Jul 15 06:30:52 PM PDT 24
Finished Jul 15 06:30:59 PM PDT 24
Peak memory 250412 kb
Host smart-5888dbf0-7950-41bc-a35c-4dbb4b52033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272495036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1272495036
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2524163913
Short name T396
Test name
Test status
Simulation time 43873623700 ps
CPU time 193.6 seconds
Started Jul 15 06:30:53 PM PDT 24
Finished Jul 15 06:34:07 PM PDT 24
Peak memory 272972 kb
Host smart-a330d818-ff5e-4ed1-bdd4-7d3d91847d78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524163913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2524163913
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1113258160
Short name T717
Test name
Test status
Simulation time 21375045482 ps
CPU time 300.69 seconds
Started Jul 15 06:30:49 PM PDT 24
Finished Jul 15 06:35:51 PM PDT 24
Peak memory 272000 kb
Host smart-277ef35b-b82b-4896-bb3b-662198ac170a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1113258160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1113258160
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4133850698
Short name T684
Test name
Test status
Simulation time 13960603 ps
CPU time 1.09 seconds
Started Jul 15 06:30:43 PM PDT 24
Finished Jul 15 06:30:45 PM PDT 24
Peak memory 211796 kb
Host smart-031139cb-91c5-4915-84c9-78246316434d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133850698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4133850698
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.271385901
Short name T323
Test name
Test status
Simulation time 23550552 ps
CPU time 0.98 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:30:57 PM PDT 24
Peak memory 208952 kb
Host smart-bc3e6eb1-d5e0-495d-9008-cc07c22d40ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271385901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.271385901
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2652240460
Short name T846
Test name
Test status
Simulation time 478419768 ps
CPU time 16.77 seconds
Started Jul 15 06:30:53 PM PDT 24
Finished Jul 15 06:31:11 PM PDT 24
Peak memory 225944 kb
Host smart-97c9df9b-982a-44a4-943f-6ff1c5eaaac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652240460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2652240460
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1802027851
Short name T35
Test name
Test status
Simulation time 2161541985 ps
CPU time 6.39 seconds
Started Jul 15 06:30:53 PM PDT 24
Finished Jul 15 06:31:00 PM PDT 24
Peak memory 217412 kb
Host smart-8065a52d-c32a-40f5-83c0-583c9f3068e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802027851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1802027851
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3210890215
Short name T117
Test name
Test status
Simulation time 1363363232 ps
CPU time 26.71 seconds
Started Jul 15 06:30:49 PM PDT 24
Finished Jul 15 06:31:16 PM PDT 24
Peak memory 218256 kb
Host smart-cb077088-a4a3-477e-82f6-99e2a712cf0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210890215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3210890215
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3088511425
Short name T585
Test name
Test status
Simulation time 304918446 ps
CPU time 5.76 seconds
Started Jul 15 06:30:52 PM PDT 24
Finished Jul 15 06:30:58 PM PDT 24
Peak memory 218124 kb
Host smart-e2163cfc-6f41-4e12-a4e1-606e2f248e21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088511425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3088511425
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.114850115
Short name T766
Test name
Test status
Simulation time 121065985 ps
CPU time 2.83 seconds
Started Jul 15 06:30:48 PM PDT 24
Finished Jul 15 06:30:52 PM PDT 24
Peak memory 217548 kb
Host smart-1cebe8f8-34c5-4c10-b82f-948288702bf1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114850115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
114850115
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1394541317
Short name T860
Test name
Test status
Simulation time 2025141303 ps
CPU time 73.43 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:32:09 PM PDT 24
Peak memory 274452 kb
Host smart-719ea6ec-8795-46d4-84a5-a7380307a603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394541317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1394541317
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3662883624
Short name T399
Test name
Test status
Simulation time 590581289 ps
CPU time 9.07 seconds
Started Jul 15 06:30:52 PM PDT 24
Finished Jul 15 06:31:02 PM PDT 24
Peak memory 226300 kb
Host smart-bd4a1b7b-da07-4277-a1b8-589e78708958
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662883624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3662883624
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.390712529
Short name T330
Test name
Test status
Simulation time 46801262 ps
CPU time 1.4 seconds
Started Jul 15 06:30:54 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 221720 kb
Host smart-adc03134-819f-4e23-8a89-7df4c23dd26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390712529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.390712529
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.4064084468
Short name T604
Test name
Test status
Simulation time 211202985 ps
CPU time 11.65 seconds
Started Jul 15 06:30:51 PM PDT 24
Finished Jul 15 06:31:03 PM PDT 24
Peak memory 218192 kb
Host smart-9622f9c9-c35d-481e-8cc4-b7f90931f207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064084468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.4064084468
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3433372994
Short name T322
Test name
Test status
Simulation time 3710762773 ps
CPU time 11.51 seconds
Started Jul 15 06:30:51 PM PDT 24
Finished Jul 15 06:31:03 PM PDT 24
Peak memory 225996 kb
Host smart-8013935d-f787-455f-a0fe-7406d0fbd65e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433372994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3433372994
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4143596768
Short name T443
Test name
Test status
Simulation time 642411831 ps
CPU time 8.39 seconds
Started Jul 15 06:30:50 PM PDT 24
Finished Jul 15 06:30:59 PM PDT 24
Peak memory 226016 kb
Host smart-b844f14c-188a-42fb-86a7-c0d1a0b9ed6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143596768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4143596768
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.517077332
Short name T485
Test name
Test status
Simulation time 329209431 ps
CPU time 12.4 seconds
Started Jul 15 06:30:50 PM PDT 24
Finished Jul 15 06:31:03 PM PDT 24
Peak memory 225964 kb
Host smart-68847d35-5a1e-437c-a5bd-b556073307d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517077332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.517077332
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1316098575
Short name T842
Test name
Test status
Simulation time 39203265 ps
CPU time 2.2 seconds
Started Jul 15 06:30:50 PM PDT 24
Finished Jul 15 06:30:53 PM PDT 24
Peak memory 222468 kb
Host smart-f8071a38-39cc-40f2-bad9-70ffb5ce8d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316098575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1316098575
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.566531657
Short name T106
Test name
Test status
Simulation time 482996997 ps
CPU time 23.59 seconds
Started Jul 15 06:30:53 PM PDT 24
Finished Jul 15 06:31:17 PM PDT 24
Peak memory 250908 kb
Host smart-5ea12612-5992-4d8f-940d-6a04bde5da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566531657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.566531657
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3663570238
Short name T506
Test name
Test status
Simulation time 116162246 ps
CPU time 9.19 seconds
Started Jul 15 06:30:52 PM PDT 24
Finished Jul 15 06:31:01 PM PDT 24
Peak memory 243888 kb
Host smart-148bf857-34d7-4a49-9d7e-c74b4528bc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663570238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3663570238
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3141071887
Short name T794
Test name
Test status
Simulation time 10239906853 ps
CPU time 205.1 seconds
Started Jul 15 06:30:54 PM PDT 24
Finished Jul 15 06:34:19 PM PDT 24
Peak memory 283724 kb
Host smart-7574e699-43b2-4f8b-a1e4-aec93fb98cea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141071887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3141071887
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3712090587
Short name T824
Test name
Test status
Simulation time 42241434 ps
CPU time 0.85 seconds
Started Jul 15 06:30:50 PM PDT 24
Finished Jul 15 06:30:51 PM PDT 24
Peak memory 211828 kb
Host smart-5ed54f3a-3e9d-4027-97a2-4fc2e27da3de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712090587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3712090587
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4215799667
Short name T697
Test name
Test status
Simulation time 49395606 ps
CPU time 0.82 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 208716 kb
Host smart-4767e7b7-d6e1-4ed4-878c-07c8857ff6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215799667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4215799667
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3193952122
Short name T418
Test name
Test status
Simulation time 241664348 ps
CPU time 9.69 seconds
Started Jul 15 06:30:56 PM PDT 24
Finished Jul 15 06:31:07 PM PDT 24
Peak memory 218152 kb
Host smart-98692dee-c1c2-42dc-bfd2-bdd7ed5346a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193952122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3193952122
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.564746098
Short name T626
Test name
Test status
Simulation time 1569367880 ps
CPU time 11.41 seconds
Started Jul 15 06:30:56 PM PDT 24
Finished Jul 15 06:31:08 PM PDT 24
Peak memory 217580 kb
Host smart-2e8516b5-8351-45fb-92e7-064ec1293a2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564746098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.564746098
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3333308153
Short name T31
Test name
Test status
Simulation time 16716947121 ps
CPU time 42.36 seconds
Started Jul 15 06:30:57 PM PDT 24
Finished Jul 15 06:31:40 PM PDT 24
Peak memory 218816 kb
Host smart-191a9b8c-c226-4bad-a1b1-2df8c356538d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333308153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3333308153
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.547237352
Short name T579
Test name
Test status
Simulation time 228232524 ps
CPU time 7.48 seconds
Started Jul 15 06:30:58 PM PDT 24
Finished Jul 15 06:31:05 PM PDT 24
Peak memory 218152 kb
Host smart-70af5d2a-08e6-4d15-8cac-5da489a4ada6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547237352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.547237352
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.468239107
Short name T810
Test name
Test status
Simulation time 276781203 ps
CPU time 8.81 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:31:05 PM PDT 24
Peak memory 217692 kb
Host smart-d00d5e1a-fd11-48a5-a407-fe2fe39965bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468239107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
468239107
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3894375518
Short name T27
Test name
Test status
Simulation time 3484289558 ps
CPU time 112.65 seconds
Started Jul 15 06:30:58 PM PDT 24
Finished Jul 15 06:32:51 PM PDT 24
Peak memory 283660 kb
Host smart-5ac879df-0050-4180-ade5-6dbb55ba1d08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894375518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3894375518
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2093661496
Short name T252
Test name
Test status
Simulation time 1576939291 ps
CPU time 18.33 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:31:14 PM PDT 24
Peak memory 247724 kb
Host smart-df0548c6-aa0b-4368-99b4-725cc6251f85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093661496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2093661496
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3537657096
Short name T428
Test name
Test status
Simulation time 243170891 ps
CPU time 2.92 seconds
Started Jul 15 06:30:53 PM PDT 24
Finished Jul 15 06:30:57 PM PDT 24
Peak memory 218156 kb
Host smart-b699adf8-2848-4a79-84fe-af2c8cdb446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537657096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3537657096
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3797490233
Short name T53
Test name
Test status
Simulation time 1029429895 ps
CPU time 11.77 seconds
Started Jul 15 06:30:54 PM PDT 24
Finished Jul 15 06:31:07 PM PDT 24
Peak memory 225980 kb
Host smart-749f3de3-675b-445b-ba12-42de28998f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797490233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3797490233
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3453666189
Short name T642
Test name
Test status
Simulation time 702796240 ps
CPU time 15.12 seconds
Started Jul 15 06:30:54 PM PDT 24
Finished Jul 15 06:31:09 PM PDT 24
Peak memory 225944 kb
Host smart-b540922c-9bff-4b57-adbe-46efc7b473f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453666189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3453666189
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3870705509
Short name T113
Test name
Test status
Simulation time 325619836 ps
CPU time 8.98 seconds
Started Jul 15 06:30:56 PM PDT 24
Finished Jul 15 06:31:06 PM PDT 24
Peak memory 218100 kb
Host smart-5a3e55dc-9eb1-495c-856b-08488ec406a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870705509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3870705509
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2187494120
Short name T686
Test name
Test status
Simulation time 931677303 ps
CPU time 11.82 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:31:08 PM PDT 24
Peak memory 225972 kb
Host smart-9e9cfbf9-7922-4689-8d93-c3ecd93cc1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187494120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2187494120
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2935020196
Short name T282
Test name
Test status
Simulation time 35332279 ps
CPU time 1.95 seconds
Started Jul 15 06:30:57 PM PDT 24
Finished Jul 15 06:30:59 PM PDT 24
Peak memory 217708 kb
Host smart-faed8753-973b-49e4-8b42-0eccc0f5d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935020196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2935020196
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1104323579
Short name T855
Test name
Test status
Simulation time 2554142153 ps
CPU time 27.41 seconds
Started Jul 15 06:30:57 PM PDT 24
Finished Jul 15 06:31:25 PM PDT 24
Peak memory 250908 kb
Host smart-0a3279af-ace5-4488-9d19-c239ca6f98f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104323579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1104323579
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2180449747
Short name T851
Test name
Test status
Simulation time 42261626 ps
CPU time 3.22 seconds
Started Jul 15 06:30:56 PM PDT 24
Finished Jul 15 06:31:00 PM PDT 24
Peak memory 222264 kb
Host smart-78c30684-6030-47e8-b3c2-d5e1b24a2a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180449747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2180449747
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3399128605
Short name T339
Test name
Test status
Simulation time 9652280280 ps
CPU time 124.12 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:33:00 PM PDT 24
Peak memory 283736 kb
Host smart-60bcf679-cc88-45c0-9d11-618eebaa61dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399128605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3399128605
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1347877647
Short name T256
Test name
Test status
Simulation time 12410116 ps
CPU time 0.8 seconds
Started Jul 15 06:30:55 PM PDT 24
Finished Jul 15 06:30:57 PM PDT 24
Peak memory 208384 kb
Host smart-967bbbdb-6a46-4251-9443-8f55f17bd6f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347877647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1347877647
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1245432413
Short name T360
Test name
Test status
Simulation time 77133341 ps
CPU time 0.87 seconds
Started Jul 15 06:31:02 PM PDT 24
Finished Jul 15 06:31:03 PM PDT 24
Peak memory 208944 kb
Host smart-64bee78e-d587-4793-a938-6235de9537cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245432413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1245432413
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2976565971
Short name T704
Test name
Test status
Simulation time 604461513 ps
CPU time 17.79 seconds
Started Jul 15 06:31:04 PM PDT 24
Finished Jul 15 06:31:22 PM PDT 24
Peak memory 218188 kb
Host smart-ed10d221-031b-45fe-92b2-e9d2f2165458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976565971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2976565971
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3149654068
Short name T327
Test name
Test status
Simulation time 32103616 ps
CPU time 1.22 seconds
Started Jul 15 06:31:02 PM PDT 24
Finished Jul 15 06:31:04 PM PDT 24
Peak memory 217072 kb
Host smart-ccb15e6c-090d-4bcb-a955-e92573b500a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149654068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3149654068
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.268140708
Short name T667
Test name
Test status
Simulation time 4823375783 ps
CPU time 66.02 seconds
Started Jul 15 06:31:03 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 218932 kb
Host smart-bf820be5-1f65-4099-aec4-159cee2a95ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268140708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.268140708
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2466656915
Short name T550
Test name
Test status
Simulation time 2694001709 ps
CPU time 9.17 seconds
Started Jul 15 06:30:59 PM PDT 24
Finished Jul 15 06:31:09 PM PDT 24
Peak memory 224344 kb
Host smart-347e7dcb-5403-4551-a20c-4a032cd125cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466656915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2466656915
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.859499312
Short name T212
Test name
Test status
Simulation time 189766675 ps
CPU time 3.72 seconds
Started Jul 15 06:31:03 PM PDT 24
Finished Jul 15 06:31:07 PM PDT 24
Peak memory 217636 kb
Host smart-bd7e28da-7ed0-4a47-97a4-87b32e4d6752
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859499312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
859499312
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3464623275
Short name T457
Test name
Test status
Simulation time 1463696485 ps
CPU time 60.4 seconds
Started Jul 15 06:31:01 PM PDT 24
Finished Jul 15 06:32:02 PM PDT 24
Peak memory 250972 kb
Host smart-3f607d2e-9e80-498f-8571-60cb6b3625b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464623275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3464623275
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3119330203
Short name T716
Test name
Test status
Simulation time 1493486938 ps
CPU time 20.08 seconds
Started Jul 15 06:31:03 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 250944 kb
Host smart-b73c9126-30cf-485f-990b-9b82fdb432e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119330203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3119330203
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.268565303
Short name T499
Test name
Test status
Simulation time 77942256 ps
CPU time 3.9 seconds
Started Jul 15 06:31:00 PM PDT 24
Finished Jul 15 06:31:05 PM PDT 24
Peak memory 222528 kb
Host smart-ad128eb5-c8b7-4b38-bd26-181c2886d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268565303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.268565303
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1186717611
Short name T570
Test name
Test status
Simulation time 560803805 ps
CPU time 24.02 seconds
Started Jul 15 06:31:01 PM PDT 24
Finished Jul 15 06:31:25 PM PDT 24
Peak memory 218816 kb
Host smart-b73117fe-194c-4b01-955b-be6fc4105550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186717611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1186717611
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.160804205
Short name T387
Test name
Test status
Simulation time 945876684 ps
CPU time 8.67 seconds
Started Jul 15 06:31:00 PM PDT 24
Finished Jul 15 06:31:10 PM PDT 24
Peak memory 225920 kb
Host smart-2b1db566-1421-4e95-b1b4-00185eb960dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160804205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.160804205
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2180678701
Short name T466
Test name
Test status
Simulation time 542255068 ps
CPU time 14.2 seconds
Started Jul 15 06:31:02 PM PDT 24
Finished Jul 15 06:31:17 PM PDT 24
Peak memory 225872 kb
Host smart-5474bc16-2cf6-4244-8316-2d32534f0409
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180678701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2180678701
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2699257551
Short name T663
Test name
Test status
Simulation time 53419120 ps
CPU time 2.41 seconds
Started Jul 15 06:30:54 PM PDT 24
Finished Jul 15 06:30:58 PM PDT 24
Peak memory 214348 kb
Host smart-0020d285-3447-49d6-baab-d7c701883638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699257551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2699257551
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.312338939
Short name T100
Test name
Test status
Simulation time 213353382 ps
CPU time 22.33 seconds
Started Jul 15 06:31:00 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 250972 kb
Host smart-e5b71fa3-2ece-4acb-a48e-0ff88b861bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312338939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.312338939
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3634466651
Short name T318
Test name
Test status
Simulation time 96431753 ps
CPU time 7.17 seconds
Started Jul 15 06:31:02 PM PDT 24
Finished Jul 15 06:31:09 PM PDT 24
Peak memory 250904 kb
Host smart-078a2299-1424-4d1f-8433-e9d792321b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634466651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3634466651
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1063932849
Short name T41
Test name
Test status
Simulation time 29708449561 ps
CPU time 168.84 seconds
Started Jul 15 06:31:07 PM PDT 24
Finished Jul 15 06:33:57 PM PDT 24
Peak memory 221148 kb
Host smart-1bd51e37-1a0b-4773-b632-b1aa922136ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063932849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1063932849
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.30297474
Short name T529
Test name
Test status
Simulation time 13075822 ps
CPU time 1.07 seconds
Started Jul 15 06:30:54 PM PDT 24
Finished Jul 15 06:30:56 PM PDT 24
Peak memory 211748 kb
Host smart-208c9bfe-7576-4004-af75-57e592e1a964
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30297474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_volatile_unlock_smoke.30297474
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.35903438
Short name T82
Test name
Test status
Simulation time 17422936 ps
CPU time 1.22 seconds
Started Jul 15 06:31:15 PM PDT 24
Finished Jul 15 06:31:17 PM PDT 24
Peak memory 208844 kb
Host smart-3869e692-c060-44b7-8a43-c19cbe7ed302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35903438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.35903438
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2299486654
Short name T42
Test name
Test status
Simulation time 382552060 ps
CPU time 10.83 seconds
Started Jul 15 06:31:05 PM PDT 24
Finished Jul 15 06:31:16 PM PDT 24
Peak memory 218084 kb
Host smart-c152d42f-307f-4940-948b-3f610f8f4e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299486654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2299486654
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2292772497
Short name T868
Test name
Test status
Simulation time 896868148 ps
CPU time 12.43 seconds
Started Jul 15 06:31:06 PM PDT 24
Finished Jul 15 06:31:20 PM PDT 24
Peak memory 217620 kb
Host smart-463bfc35-6030-4756-919c-9cd40d5bf058
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292772497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2292772497
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.764275332
Short name T606
Test name
Test status
Simulation time 39081959133 ps
CPU time 105.8 seconds
Started Jul 15 06:31:07 PM PDT 24
Finished Jul 15 06:32:54 PM PDT 24
Peak memory 218232 kb
Host smart-6425d587-c76c-4590-8e9a-79101ca5d719
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764275332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.764275332
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4250725122
Short name T262
Test name
Test status
Simulation time 885354668 ps
CPU time 7.35 seconds
Started Jul 15 06:31:06 PM PDT 24
Finished Jul 15 06:31:15 PM PDT 24
Peak memory 218172 kb
Host smart-2c8636ee-b30f-4b5a-b4d0-cfda97beda61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250725122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4250725122
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4002391573
Short name T491
Test name
Test status
Simulation time 215463951 ps
CPU time 4.02 seconds
Started Jul 15 06:31:04 PM PDT 24
Finished Jul 15 06:31:09 PM PDT 24
Peak memory 217560 kb
Host smart-9bb5b7b2-b8d1-4dbc-b6f0-b9991b875b54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002391573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4002391573
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4143798077
Short name T263
Test name
Test status
Simulation time 2089314496 ps
CPU time 35.28 seconds
Started Jul 15 06:31:05 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 251024 kb
Host smart-edb4b066-494c-45a6-8653-7b9699b49451
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143798077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4143798077
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.705465626
Short name T341
Test name
Test status
Simulation time 1365593831 ps
CPU time 14.12 seconds
Started Jul 15 06:31:03 PM PDT 24
Finished Jul 15 06:31:18 PM PDT 24
Peak memory 248540 kb
Host smart-c6310c65-e42b-407b-a744-5af7aa910903
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705465626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.705465626
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1096506672
Short name T598
Test name
Test status
Simulation time 74545659 ps
CPU time 3.79 seconds
Started Jul 15 06:31:07 PM PDT 24
Finished Jul 15 06:31:12 PM PDT 24
Peak memory 222352 kb
Host smart-629938de-30fc-4740-9212-685242f0174f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096506672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1096506672
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3436422557
Short name T852
Test name
Test status
Simulation time 1137847369 ps
CPU time 13.3 seconds
Started Jul 15 06:31:08 PM PDT 24
Finished Jul 15 06:31:22 PM PDT 24
Peak memory 218812 kb
Host smart-2b262bb2-22da-413d-bb92-4d571067afca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436422557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3436422557
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2143352838
Short name T501
Test name
Test status
Simulation time 388073125 ps
CPU time 8.97 seconds
Started Jul 15 06:31:06 PM PDT 24
Finished Jul 15 06:31:15 PM PDT 24
Peak memory 225580 kb
Host smart-d043bc55-58cd-4c70-8ab0-93077295071d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143352838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2143352838
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.4098171973
Short name T489
Test name
Test status
Simulation time 1437016635 ps
CPU time 13.29 seconds
Started Jul 15 06:31:05 PM PDT 24
Finished Jul 15 06:31:19 PM PDT 24
Peak memory 218180 kb
Host smart-95994bf4-8176-49cd-9946-44fc7bbedb16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098171973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
4098171973
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1788661088
Short name T616
Test name
Test status
Simulation time 717864192 ps
CPU time 13.92 seconds
Started Jul 15 06:31:07 PM PDT 24
Finished Jul 15 06:31:22 PM PDT 24
Peak memory 225976 kb
Host smart-07c72246-3860-4ba0-9a2d-3231b2cfa4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788661088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1788661088
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.504181362
Short name T864
Test name
Test status
Simulation time 213283903 ps
CPU time 2.64 seconds
Started Jul 15 06:31:07 PM PDT 24
Finished Jul 15 06:31:11 PM PDT 24
Peak memory 214372 kb
Host smart-82707055-21e3-4945-879b-6b0844bbf831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504181362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.504181362
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2568529050
Short name T277
Test name
Test status
Simulation time 920939403 ps
CPU time 23.02 seconds
Started Jul 15 06:31:01 PM PDT 24
Finished Jul 15 06:31:25 PM PDT 24
Peak memory 250924 kb
Host smart-10944d97-00f2-4ad4-a76d-7d57c34109c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568529050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2568529050
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2546205132
Short name T381
Test name
Test status
Simulation time 163792929 ps
CPU time 8.36 seconds
Started Jul 15 06:31:04 PM PDT 24
Finished Jul 15 06:31:13 PM PDT 24
Peak memory 250940 kb
Host smart-084ad905-bebb-4d5d-834c-1120329faac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546205132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2546205132
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4066278088
Short name T218
Test name
Test status
Simulation time 2399203225 ps
CPU time 93.43 seconds
Started Jul 15 06:31:08 PM PDT 24
Finished Jul 15 06:32:42 PM PDT 24
Peak memory 250828 kb
Host smart-5c8d3be7-d43e-4f2e-b416-707666ab4aac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066278088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4066278088
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.609889708
Short name T760
Test name
Test status
Simulation time 20602343 ps
CPU time 0.83 seconds
Started Jul 15 06:31:05 PM PDT 24
Finished Jul 15 06:31:06 PM PDT 24
Peak memory 211728 kb
Host smart-2d177ad6-cd45-40c2-9ac7-0ad6bfa53613
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609889708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.609889708
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.371861557
Short name T274
Test name
Test status
Simulation time 63554465 ps
CPU time 0.92 seconds
Started Jul 15 06:29:36 PM PDT 24
Finished Jul 15 06:29:37 PM PDT 24
Peak memory 208904 kb
Host smart-8f66aacc-fb01-47fe-a0ba-17f0293b6f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371861557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.371861557
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.480516499
Short name T815
Test name
Test status
Simulation time 94261752 ps
CPU time 0.83 seconds
Started Jul 15 06:29:37 PM PDT 24
Finished Jul 15 06:29:38 PM PDT 24
Peak memory 208908 kb
Host smart-b2cd83a5-2c4d-4a44-a433-6b53da7108ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480516499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.480516499
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.35268151
Short name T630
Test name
Test status
Simulation time 464124952 ps
CPU time 13.49 seconds
Started Jul 15 06:29:39 PM PDT 24
Finished Jul 15 06:29:53 PM PDT 24
Peak memory 218120 kb
Host smart-6a1836d8-e031-477b-8f6b-861c24d733fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35268151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.35268151
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3828274983
Short name T808
Test name
Test status
Simulation time 2176730714 ps
CPU time 6.04 seconds
Started Jul 15 06:29:35 PM PDT 24
Finished Jul 15 06:29:42 PM PDT 24
Peak memory 217320 kb
Host smart-acfb7510-a6c3-4a8a-a7e4-080c108202b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828274983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3828274983
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3113476106
Short name T423
Test name
Test status
Simulation time 1504697018 ps
CPU time 6.52 seconds
Started Jul 15 06:29:37 PM PDT 24
Finished Jul 15 06:29:44 PM PDT 24
Peak memory 217712 kb
Host smart-b5af8589-240c-4fdb-b91c-bb9159955cb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113476106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
113476106
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.922702697
Short name T732
Test name
Test status
Simulation time 75712748 ps
CPU time 2.1 seconds
Started Jul 15 06:29:41 PM PDT 24
Finished Jul 15 06:29:43 PM PDT 24
Peak memory 218168 kb
Host smart-c73398e0-3a32-4a5e-980c-5af7dce707de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922702697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.922702697
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2917086740
Short name T111
Test name
Test status
Simulation time 5615812555 ps
CPU time 16.8 seconds
Started Jul 15 06:29:38 PM PDT 24
Finished Jul 15 06:29:56 PM PDT 24
Peak memory 217700 kb
Host smart-22150f7c-2f16-4ac3-9804-f3ad4cfc29cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917086740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2917086740
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3773401631
Short name T783
Test name
Test status
Simulation time 6401983366 ps
CPU time 6.55 seconds
Started Jul 15 06:29:38 PM PDT 24
Finished Jul 15 06:29:45 PM PDT 24
Peak memory 217668 kb
Host smart-ea949a9b-89d6-4590-a5a3-47519de243ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773401631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3773401631
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1587813765
Short name T692
Test name
Test status
Simulation time 3634440912 ps
CPU time 44.03 seconds
Started Jul 15 06:29:36 PM PDT 24
Finished Jul 15 06:30:21 PM PDT 24
Peak memory 275612 kb
Host smart-e33f2712-4041-4b8b-8178-b58665395a1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587813765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1587813765
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3603285788
Short name T251
Test name
Test status
Simulation time 515157440 ps
CPU time 15.15 seconds
Started Jul 15 06:29:35 PM PDT 24
Finished Jul 15 06:29:51 PM PDT 24
Peak memory 251040 kb
Host smart-254d5293-9967-4bec-aceb-c9919625264b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603285788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3603285788
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.976688573
Short name T695
Test name
Test status
Simulation time 35849528 ps
CPU time 2.12 seconds
Started Jul 15 06:29:37 PM PDT 24
Finished Jul 15 06:29:39 PM PDT 24
Peak memory 218176 kb
Host smart-7a358530-1ae6-420f-a24e-55816c286acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976688573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.976688573
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3842924762
Short name T426
Test name
Test status
Simulation time 1860826001 ps
CPU time 24.18 seconds
Started Jul 15 06:29:32 PM PDT 24
Finished Jul 15 06:29:57 PM PDT 24
Peak memory 217712 kb
Host smart-9bf2097d-03fa-4414-b1a4-88fe6441bd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842924762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3842924762
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.712173654
Short name T96
Test name
Test status
Simulation time 114763444 ps
CPU time 24.97 seconds
Started Jul 15 06:29:36 PM PDT 24
Finished Jul 15 06:30:01 PM PDT 24
Peak memory 268908 kb
Host smart-172b0bcf-0fb4-4660-a14a-44b18c0fdcf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712173654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.712173654
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1063079895
Short name T651
Test name
Test status
Simulation time 496784695 ps
CPU time 12.94 seconds
Started Jul 15 06:29:42 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 218288 kb
Host smart-6689d1b3-c64e-48f7-9a67-996d83fe81b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063079895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1063079895
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1174208524
Short name T273
Test name
Test status
Simulation time 268240731 ps
CPU time 8.53 seconds
Started Jul 15 06:29:37 PM PDT 24
Finished Jul 15 06:29:46 PM PDT 24
Peak memory 225956 kb
Host smart-4dd2a990-9704-4f6f-ad7d-16995376cea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174208524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1174208524
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2576009026
Short name T777
Test name
Test status
Simulation time 321769859 ps
CPU time 8.98 seconds
Started Jul 15 06:29:36 PM PDT 24
Finished Jul 15 06:29:45 PM PDT 24
Peak memory 225968 kb
Host smart-02f3c1e8-a0fa-467a-92fa-2644c344b107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576009026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
576009026
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2806673650
Short name T514
Test name
Test status
Simulation time 346380705 ps
CPU time 7.76 seconds
Started Jul 15 06:29:31 PM PDT 24
Finished Jul 15 06:29:39 PM PDT 24
Peak memory 225304 kb
Host smart-61e3bf21-25d0-452e-87f6-76f40c2d362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806673650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2806673650
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.742822783
Short name T693
Test name
Test status
Simulation time 60899515 ps
CPU time 3.11 seconds
Started Jul 15 06:29:32 PM PDT 24
Finished Jul 15 06:29:35 PM PDT 24
Peak memory 215092 kb
Host smart-f69914cd-715c-435a-9f0a-5c2de1239947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742822783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.742822783
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.466167693
Short name T787
Test name
Test status
Simulation time 226439379 ps
CPU time 23.8 seconds
Started Jul 15 06:29:31 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 250924 kb
Host smart-fd6d2233-b49e-4b5b-b6fc-36697e21e4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466167693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.466167693
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1968681848
Short name T334
Test name
Test status
Simulation time 85708869 ps
CPU time 3.55 seconds
Started Jul 15 06:29:34 PM PDT 24
Finished Jul 15 06:29:38 PM PDT 24
Peak memory 222772 kb
Host smart-c266557f-bc66-448a-9535-baeda55c1d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968681848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1968681848
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.439620346
Short name T552
Test name
Test status
Simulation time 19389864192 ps
CPU time 168.95 seconds
Started Jul 15 06:29:39 PM PDT 24
Finished Jul 15 06:32:29 PM PDT 24
Peak memory 283656 kb
Host smart-091b51c6-21a3-4c9d-8e57-3760f1dc23ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439620346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.439620346
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4230278456
Short name T646
Test name
Test status
Simulation time 21699843 ps
CPU time 0.9 seconds
Started Jul 15 06:29:32 PM PDT 24
Finished Jul 15 06:29:33 PM PDT 24
Peak memory 211900 kb
Host smart-54aac41a-1577-4010-b7f2-94ccac020ad7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230278456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4230278456
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2350751056
Short name T103
Test name
Test status
Simulation time 13863987 ps
CPU time 1.03 seconds
Started Jul 15 06:31:17 PM PDT 24
Finished Jul 15 06:31:18 PM PDT 24
Peak memory 208876 kb
Host smart-27730478-647c-4725-958e-d149e0814078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350751056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2350751056
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1825388768
Short name T553
Test name
Test status
Simulation time 6918969222 ps
CPU time 16.42 seconds
Started Jul 15 06:31:08 PM PDT 24
Finished Jul 15 06:31:25 PM PDT 24
Peak memory 218580 kb
Host smart-663301d6-1856-4169-b72c-490205143980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825388768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1825388768
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2980150161
Short name T222
Test name
Test status
Simulation time 2121246127 ps
CPU time 11.77 seconds
Started Jul 15 06:31:17 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 217144 kb
Host smart-32b1cd84-81c8-47a7-a897-2de345443efa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980150161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2980150161
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2559710995
Short name T689
Test name
Test status
Simulation time 142926208 ps
CPU time 2.12 seconds
Started Jul 15 06:31:07 PM PDT 24
Finished Jul 15 06:31:10 PM PDT 24
Peak memory 218176 kb
Host smart-7bb19963-51c9-4654-a178-bd8a21d959bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559710995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2559710995
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1402300023
Short name T73
Test name
Test status
Simulation time 1048699778 ps
CPU time 14.67 seconds
Started Jul 15 06:31:17 PM PDT 24
Finished Jul 15 06:31:32 PM PDT 24
Peak memory 225928 kb
Host smart-214566fb-a63f-4f2b-8b0e-95e20bc329cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402300023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1402300023
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2581897263
Short name T862
Test name
Test status
Simulation time 1809176168 ps
CPU time 13.57 seconds
Started Jul 15 06:31:05 PM PDT 24
Finished Jul 15 06:31:19 PM PDT 24
Peak memory 225992 kb
Host smart-78bde54b-d634-4d75-9406-577fabff8179
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581897263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2581897263
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3742654607
Short name T300
Test name
Test status
Simulation time 977469330 ps
CPU time 5.83 seconds
Started Jul 15 06:31:15 PM PDT 24
Finished Jul 15 06:31:22 PM PDT 24
Peak memory 218120 kb
Host smart-0e82009d-6800-43ba-8ea7-d988324bb762
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742654607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3742654607
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3323650805
Short name T210
Test name
Test status
Simulation time 300126417 ps
CPU time 7.51 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:20 PM PDT 24
Peak memory 218444 kb
Host smart-a9b43cb2-a6b2-4cb5-b3d4-728a89c5edb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323650805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3323650805
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2542283615
Short name T74
Test name
Test status
Simulation time 186030373 ps
CPU time 2.43 seconds
Started Jul 15 06:31:16 PM PDT 24
Finished Jul 15 06:31:19 PM PDT 24
Peak memory 214508 kb
Host smart-cf028650-6a4a-40cd-ae98-0805a1b65e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542283615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2542283615
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.491664726
Short name T664
Test name
Test status
Simulation time 466890331 ps
CPU time 24.63 seconds
Started Jul 15 06:31:07 PM PDT 24
Finished Jul 15 06:31:32 PM PDT 24
Peak memory 250936 kb
Host smart-0004d4f7-a07b-4342-96b5-93c74bbbf004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491664726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.491664726
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1904636345
Short name T480
Test name
Test status
Simulation time 125469586 ps
CPU time 5.84 seconds
Started Jul 15 06:31:17 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 246488 kb
Host smart-52ad16e3-e118-4050-a03b-5cb80a7dabc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904636345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1904636345
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2655094992
Short name T71
Test name
Test status
Simulation time 10155725002 ps
CPU time 51.02 seconds
Started Jul 15 06:31:06 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 217784 kb
Host smart-7a163ba6-ca1b-40a5-b257-aa5b2ce1e92e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655094992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2655094992
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1610808459
Short name T669
Test name
Test status
Simulation time 16361558 ps
CPU time 1.11 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:12 PM PDT 24
Peak memory 211964 kb
Host smart-4473468d-f8f8-4b5f-bc6e-e4152f5c7d31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610808459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1610808459
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1419512623
Short name T782
Test name
Test status
Simulation time 23563219 ps
CPU time 1.34 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:14 PM PDT 24
Peak memory 208948 kb
Host smart-0d89b091-61d4-4434-95d6-7a37db9f6d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419512623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1419512623
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2221065789
Short name T458
Test name
Test status
Simulation time 716774619 ps
CPU time 17.31 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 218096 kb
Host smart-68c9c8da-6ee7-4780-8df7-e18de6651e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221065789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2221065789
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3716911032
Short name T722
Test name
Test status
Simulation time 290686524 ps
CPU time 7.34 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:21 PM PDT 24
Peak memory 217100 kb
Host smart-a06dc981-e521-4e77-8c89-306d9c04554a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716911032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3716911032
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3667041785
Short name T522
Test name
Test status
Simulation time 211317576 ps
CPU time 2.51 seconds
Started Jul 15 06:31:06 PM PDT 24
Finished Jul 15 06:31:10 PM PDT 24
Peak memory 218128 kb
Host smart-73c651d9-d880-4c4e-b5a2-8f69d1a17d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667041785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3667041785
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1604082797
Short name T344
Test name
Test status
Simulation time 1225318167 ps
CPU time 9.01 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 218068 kb
Host smart-ab8f54e4-ee1a-40c3-8d5e-338a495769b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604082797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1604082797
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2593189008
Short name T24
Test name
Test status
Simulation time 330929381 ps
CPU time 8.84 seconds
Started Jul 15 06:31:13 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 225964 kb
Host smart-b24d210a-d264-4849-962d-c9017d81b774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593189008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2593189008
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2978838657
Short name T269
Test name
Test status
Simulation time 2015064903 ps
CPU time 11.44 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:25 PM PDT 24
Peak memory 225968 kb
Host smart-b89b7ab2-7b0a-4172-8139-5daa421b9fa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978838657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2978838657
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2935909476
Short name T366
Test name
Test status
Simulation time 377412445 ps
CPU time 11.8 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 226008 kb
Host smart-7e0a3245-6706-49e9-b34d-e68d7ee2e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935909476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2935909476
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3479861122
Short name T524
Test name
Test status
Simulation time 30028765 ps
CPU time 1.72 seconds
Started Jul 15 06:31:09 PM PDT 24
Finished Jul 15 06:31:11 PM PDT 24
Peak memory 213820 kb
Host smart-aa553d14-bc56-4b00-bb0a-b82dab542b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479861122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3479861122
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.227728410
Short name T26
Test name
Test status
Simulation time 598735851 ps
CPU time 28.15 seconds
Started Jul 15 06:31:09 PM PDT 24
Finished Jul 15 06:31:38 PM PDT 24
Peak memory 250936 kb
Host smart-4b8801f9-0c0b-4038-84d0-1eb1a3e77d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227728410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.227728410
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3070634790
Short name T313
Test name
Test status
Simulation time 330802231 ps
CPU time 6.95 seconds
Started Jul 15 06:31:06 PM PDT 24
Finished Jul 15 06:31:14 PM PDT 24
Peak memory 250916 kb
Host smart-33b9c01c-5d62-48cd-b590-0bfbc254c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070634790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3070634790
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2539686003
Short name T253
Test name
Test status
Simulation time 9476277703 ps
CPU time 192.66 seconds
Started Jul 15 06:31:13 PM PDT 24
Finished Jul 15 06:34:27 PM PDT 24
Peak memory 259180 kb
Host smart-d8c52892-e92e-4550-a40a-97c991f57b87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539686003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2539686003
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3218585681
Short name T172
Test name
Test status
Simulation time 9918288973 ps
CPU time 155.34 seconds
Started Jul 15 06:31:15 PM PDT 24
Finished Jul 15 06:33:50 PM PDT 24
Peak memory 270788 kb
Host smart-28a69c84-db75-41f9-9841-c05fb3638159
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3218585681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3218585681
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2783547745
Short name T677
Test name
Test status
Simulation time 34228044 ps
CPU time 0.92 seconds
Started Jul 15 06:31:05 PM PDT 24
Finished Jul 15 06:31:07 PM PDT 24
Peak memory 211816 kb
Host smart-1d9cd214-0016-4037-8ee9-a76c58eca814
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783547745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2783547745
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2550979202
Short name T413
Test name
Test status
Simulation time 47443661 ps
CPU time 1.04 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:13 PM PDT 24
Peak memory 208968 kb
Host smart-633430d3-0400-48f9-8ad7-4b5376a82a27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550979202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2550979202
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2033589434
Short name T54
Test name
Test status
Simulation time 664120242 ps
CPU time 17.44 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:31 PM PDT 24
Peak memory 218164 kb
Host smart-98c2c190-b0f0-4cd7-90ee-8b6720da38a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033589434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2033589434
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2294372075
Short name T389
Test name
Test status
Simulation time 5264711990 ps
CPU time 13.19 seconds
Started Jul 15 06:31:13 PM PDT 24
Finished Jul 15 06:31:27 PM PDT 24
Peak memory 217708 kb
Host smart-b7f81c42-6ea6-45a8-9747-ce0109b46639
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294372075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2294372075
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1422467766
Short name T470
Test name
Test status
Simulation time 131174936 ps
CPU time 2.59 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:16 PM PDT 24
Peak memory 218112 kb
Host smart-c14d8c1e-fda3-4455-9ab5-4dd9677c7838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422467766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1422467766
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.293338969
Short name T599
Test name
Test status
Simulation time 743427123 ps
CPU time 12.77 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:26 PM PDT 24
Peak memory 225988 kb
Host smart-2d759c6b-aa73-4251-9582-00d749363195
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293338969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.293338969
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1779142323
Short name T750
Test name
Test status
Simulation time 727060159 ps
CPU time 8.54 seconds
Started Jul 15 06:31:13 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 225944 kb
Host smart-66bd45e2-d785-4bc1-bef9-4d9f6e65d830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779142323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1779142323
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3072948627
Short name T666
Test name
Test status
Simulation time 626334617 ps
CPU time 12.44 seconds
Started Jul 15 06:31:14 PM PDT 24
Finished Jul 15 06:31:27 PM PDT 24
Peak memory 218128 kb
Host smart-c1cbff3c-c5db-48c8-b2e0-d658407353c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072948627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3072948627
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2225320538
Short name T546
Test name
Test status
Simulation time 1449899037 ps
CPU time 8.89 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:22 PM PDT 24
Peak memory 218224 kb
Host smart-4d939f93-409d-4310-8b36-616ba6ab748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225320538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2225320538
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3930004191
Short name T483
Test name
Test status
Simulation time 15604293 ps
CPU time 1.01 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:13 PM PDT 24
Peak memory 212140 kb
Host smart-d6e1fccb-f346-4c59-ba78-41b080c99288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930004191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3930004191
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3803673096
Short name T690
Test name
Test status
Simulation time 837657598 ps
CPU time 26.87 seconds
Started Jul 15 06:31:14 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 250908 kb
Host smart-524b430e-b63e-424b-87e4-f203c33b5822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803673096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3803673096
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.435376499
Short name T208
Test name
Test status
Simulation time 353471232 ps
CPU time 3.28 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:17 PM PDT 24
Peak memory 222180 kb
Host smart-6e325e60-3145-435d-a79d-3501c8994892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435376499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.435376499
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2715593508
Short name T107
Test name
Test status
Simulation time 366882523 ps
CPU time 14.05 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:26 PM PDT 24
Peak memory 250620 kb
Host smart-2c69d3c1-f259-48b6-bc21-84cf5a9a48a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715593508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2715593508
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.663814514
Short name T728
Test name
Test status
Simulation time 221901941986 ps
CPU time 1077.79 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:49:11 PM PDT 24
Peak memory 316660 kb
Host smart-bf56116d-e47d-4638-bd02-b1af26c3600c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=663814514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.663814514
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2545364637
Short name T406
Test name
Test status
Simulation time 15811413 ps
CPU time 1.02 seconds
Started Jul 15 06:31:10 PM PDT 24
Finished Jul 15 06:31:12 PM PDT 24
Peak memory 211840 kb
Host smart-8cc2e713-7504-40e1-a369-9e4ce9753e10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545364637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2545364637
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2699746452
Short name T476
Test name
Test status
Simulation time 91576723 ps
CPU time 1.29 seconds
Started Jul 15 06:31:18 PM PDT 24
Finished Jul 15 06:31:19 PM PDT 24
Peak memory 208924 kb
Host smart-f42e535e-2ef6-4cfd-b24b-2b503686e19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699746452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2699746452
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.4156267109
Short name T474
Test name
Test status
Simulation time 1763654086 ps
CPU time 14.34 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:28 PM PDT 24
Peak memory 218156 kb
Host smart-5dc7cc6a-be00-4c32-a545-cf3c836f67fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156267109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4156267109
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1006348318
Short name T644
Test name
Test status
Simulation time 2077466164 ps
CPU time 9.13 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 217208 kb
Host smart-87ca9619-21ca-4223-8be0-3937567ae2bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006348318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1006348318
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.199243704
Short name T441
Test name
Test status
Simulation time 166030822 ps
CPU time 2.83 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:16 PM PDT 24
Peak memory 222000 kb
Host smart-25a0aa39-0ee7-4630-91eb-98a83e174e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199243704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.199243704
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3251470029
Short name T446
Test name
Test status
Simulation time 730974822 ps
CPU time 11.49 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 226036 kb
Host smart-31beee6c-c89d-4cf5-9b6a-13017dfee257
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251470029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3251470029
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2397780467
Short name T368
Test name
Test status
Simulation time 683481914 ps
CPU time 12.43 seconds
Started Jul 15 06:31:19 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 225980 kb
Host smart-88bf7c46-7535-49f0-b701-03f01c1ff4ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397780467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2397780467
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1935156220
Short name T316
Test name
Test status
Simulation time 928648223 ps
CPU time 7.02 seconds
Started Jul 15 06:31:20 PM PDT 24
Finished Jul 15 06:31:28 PM PDT 24
Peak memory 225908 kb
Host smart-d9e28ec5-37a3-4267-8574-0b7f96dcab82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935156220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1935156220
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2093232740
Short name T314
Test name
Test status
Simulation time 1706921009 ps
CPU time 16.54 seconds
Started Jul 15 06:31:13 PM PDT 24
Finished Jul 15 06:31:31 PM PDT 24
Peak memory 225956 kb
Host smart-d74be6b4-9ba3-4125-b03b-9c10ab9be99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093232740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2093232740
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.125653452
Short name T321
Test name
Test status
Simulation time 12283718 ps
CPU time 1.14 seconds
Started Jul 15 06:31:13 PM PDT 24
Finished Jul 15 06:31:15 PM PDT 24
Peak memory 211912 kb
Host smart-80d90a02-5f05-4719-bf5c-b997f96dea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125653452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.125653452
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1621361028
Short name T477
Test name
Test status
Simulation time 254084198 ps
CPU time 8.21 seconds
Started Jul 15 06:31:12 PM PDT 24
Finished Jul 15 06:31:22 PM PDT 24
Peak memory 250800 kb
Host smart-636672c0-4850-40cf-9c98-86e27c8565a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621361028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1621361028
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.663926645
Short name T825
Test name
Test status
Simulation time 5531453789 ps
CPU time 80.2 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:32:45 PM PDT 24
Peak memory 243224 kb
Host smart-4e785e74-fdb8-4f3a-a51b-c186ee798fb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663926645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.663926645
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.322478184
Short name T507
Test name
Test status
Simulation time 15397527 ps
CPU time 0.88 seconds
Started Jul 15 06:31:11 PM PDT 24
Finished Jul 15 06:31:13 PM PDT 24
Peak memory 211804 kb
Host smart-254a9fdf-42db-40c5-948c-7481dc89ac54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322478184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.322478184
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3904686961
Short name T337
Test name
Test status
Simulation time 19549388 ps
CPU time 0.93 seconds
Started Jul 15 06:31:19 PM PDT 24
Finished Jul 15 06:31:21 PM PDT 24
Peak memory 208868 kb
Host smart-ccf7ed56-5e4f-41c8-b8cc-e9a48f1fc13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904686961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3904686961
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1290207119
Short name T440
Test name
Test status
Simulation time 2206990243 ps
CPU time 15.82 seconds
Started Jul 15 06:31:19 PM PDT 24
Finished Jul 15 06:31:35 PM PDT 24
Peak memory 218184 kb
Host smart-d98c7b8b-9f27-4dd6-9568-93db3637892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290207119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1290207119
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2647041603
Short name T731
Test name
Test status
Simulation time 1588769227 ps
CPU time 10.58 seconds
Started Jul 15 06:31:19 PM PDT 24
Finished Jul 15 06:31:30 PM PDT 24
Peak memory 217064 kb
Host smart-3b5af3bc-862a-4629-827b-34c13c6dca8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647041603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2647041603
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.260716132
Short name T634
Test name
Test status
Simulation time 76464792 ps
CPU time 3.82 seconds
Started Jul 15 06:31:19 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 218152 kb
Host smart-0bbb175d-05c7-47f4-b150-ca67466ec30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260716132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.260716132
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.460100464
Short name T776
Test name
Test status
Simulation time 459703029 ps
CPU time 18.12 seconds
Started Jul 15 06:31:18 PM PDT 24
Finished Jul 15 06:31:36 PM PDT 24
Peak memory 225976 kb
Host smart-dd282a62-2843-46e0-bd68-4b323e0b7467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460100464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.460100464
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.789371005
Short name T258
Test name
Test status
Simulation time 2497291687 ps
CPU time 15.15 seconds
Started Jul 15 06:31:20 PM PDT 24
Finished Jul 15 06:31:36 PM PDT 24
Peak memory 226004 kb
Host smart-593dd03c-9201-4ae6-9f97-59cbb4211eea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789371005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.789371005
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1652297531
Short name T559
Test name
Test status
Simulation time 2028526070 ps
CPU time 7.99 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:31:30 PM PDT 24
Peak memory 218120 kb
Host smart-20a53b0c-5edc-4e76-88d1-e2a286a2221b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652297531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1652297531
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1908144302
Short name T114
Test name
Test status
Simulation time 1471147161 ps
CPU time 10.2 seconds
Started Jul 15 06:31:18 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 225184 kb
Host smart-49193e3e-fdf2-449c-87d6-09ca483a4ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908144302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1908144302
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.233352454
Short name T211
Test name
Test status
Simulation time 352297647 ps
CPU time 2.76 seconds
Started Jul 15 06:31:17 PM PDT 24
Finished Jul 15 06:31:20 PM PDT 24
Peak memory 217748 kb
Host smart-dc135b62-29cd-4711-9279-30f2fc96e3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233352454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.233352454
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1294694494
Short name T417
Test name
Test status
Simulation time 504053392 ps
CPU time 24.89 seconds
Started Jul 15 06:31:20 PM PDT 24
Finished Jul 15 06:31:45 PM PDT 24
Peak memory 250900 kb
Host smart-5be10b6f-9439-4c2e-8f17-e4e10aa9f955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294694494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1294694494
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1791431843
Short name T347
Test name
Test status
Simulation time 73554061 ps
CPU time 7.45 seconds
Started Jul 15 06:31:16 PM PDT 24
Finished Jul 15 06:31:24 PM PDT 24
Peak memory 250872 kb
Host smart-83592746-45a3-4134-9358-630b0fbb7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791431843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1791431843
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.383909472
Short name T537
Test name
Test status
Simulation time 11843684515 ps
CPU time 43.35 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 267340 kb
Host smart-6d804cbe-83be-442a-9716-45492b5fe2fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383909472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.383909472
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.376090417
Short name T174
Test name
Test status
Simulation time 31120096570 ps
CPU time 304.35 seconds
Started Jul 15 06:31:24 PM PDT 24
Finished Jul 15 06:36:30 PM PDT 24
Peak memory 316772 kb
Host smart-f04537de-0fbe-4a01-9280-a43b3c737486
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=376090417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.376090417
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.379157244
Short name T291
Test name
Test status
Simulation time 43712640 ps
CPU time 0.97 seconds
Started Jul 15 06:31:18 PM PDT 24
Finished Jul 15 06:31:20 PM PDT 24
Peak memory 211844 kb
Host smart-ca50445a-c57c-4b22-8a26-548ef482c627
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379157244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.379157244
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.497467004
Short name T468
Test name
Test status
Simulation time 33332318 ps
CPU time 1.18 seconds
Started Jul 15 06:31:23 PM PDT 24
Finished Jul 15 06:31:26 PM PDT 24
Peak memory 208964 kb
Host smart-b47bc5cf-f530-4491-a190-ca35003b7467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497467004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.497467004
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3448845759
Short name T744
Test name
Test status
Simulation time 2025342986 ps
CPU time 16.62 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 225976 kb
Host smart-2b5f87b2-975f-44d0-aae8-6910f8eba713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448845759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3448845759
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3406850538
Short name T847
Test name
Test status
Simulation time 4496749881 ps
CPU time 8.3 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 217704 kb
Host smart-a533c34e-9504-4071-9dc6-16fa13ec71af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406850538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3406850538
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4033563586
Short name T254
Test name
Test status
Simulation time 79426574 ps
CPU time 2.94 seconds
Started Jul 15 06:31:19 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 222460 kb
Host smart-9ecd3d32-7117-4258-9de4-4e95aabd87c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033563586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4033563586
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.4113498371
Short name T456
Test name
Test status
Simulation time 751737070 ps
CPU time 15.22 seconds
Started Jul 15 06:31:17 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 225972 kb
Host smart-adae96e2-6cd2-4303-9fd5-86c8d07a3df0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113498371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.4113498371
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2940442184
Short name T839
Test name
Test status
Simulation time 324926432 ps
CPU time 13.02 seconds
Started Jul 15 06:31:19 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 225948 kb
Host smart-05bc4c5a-05e3-47a6-bb31-a47efa3e1011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940442184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2940442184
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3941943436
Short name T621
Test name
Test status
Simulation time 1309073143 ps
CPU time 12.67 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:31:34 PM PDT 24
Peak memory 218084 kb
Host smart-a126de32-5301-4129-861f-937426c17acf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941943436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3941943436
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.739087333
Short name T721
Test name
Test status
Simulation time 950274959 ps
CPU time 10.48 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 225908 kb
Host smart-34e96396-b389-4bd2-9a38-a4e2f665e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739087333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.739087333
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2560044963
Short name T515
Test name
Test status
Simulation time 79033148 ps
CPU time 1.35 seconds
Started Jul 15 06:31:18 PM PDT 24
Finished Jul 15 06:31:20 PM PDT 24
Peak memory 213748 kb
Host smart-ef68f998-2df6-4650-9cde-442d7083bed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560044963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2560044963
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.922706730
Short name T773
Test name
Test status
Simulation time 918260402 ps
CPU time 28.31 seconds
Started Jul 15 06:31:18 PM PDT 24
Finished Jul 15 06:31:47 PM PDT 24
Peak memory 250848 kb
Host smart-f98a1936-13c6-4512-89c1-a248cf90c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922706730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.922706730
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1025625277
Short name T533
Test name
Test status
Simulation time 40063458 ps
CPU time 5.8 seconds
Started Jul 15 06:31:20 PM PDT 24
Finished Jul 15 06:31:27 PM PDT 24
Peak memory 246560 kb
Host smart-82d1d920-df58-4790-a17f-5eb2a7c5aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025625277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1025625277
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2935563069
Short name T720
Test name
Test status
Simulation time 16787742619 ps
CPU time 62.47 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:32:26 PM PDT 24
Peak memory 251456 kb
Host smart-858762a7-9ab7-4f57-8dee-5c912248ab75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935563069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2935563069
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.678593387
Short name T292
Test name
Test status
Simulation time 14073343 ps
CPU time 0.88 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:31:23 PM PDT 24
Peak memory 211780 kb
Host smart-01856980-c305-46a3-857a-56e918408616
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678593387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.678593387
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1102612255
Short name T673
Test name
Test status
Simulation time 195966337 ps
CPU time 1.31 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:26 PM PDT 24
Peak memory 208972 kb
Host smart-ed11d315-03ae-4942-adb5-d067ebd96aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102612255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1102612255
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4268589086
Short name T64
Test name
Test status
Simulation time 397649997 ps
CPU time 8.09 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 218152 kb
Host smart-7d888e92-e322-4e84-bc2d-f47e8a8c10b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268589086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4268589086
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1571056053
Short name T829
Test name
Test status
Simulation time 742824827 ps
CPU time 8.34 seconds
Started Jul 15 06:31:23 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 217116 kb
Host smart-0606951a-9878-4008-bfc0-c66c3eb6b543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571056053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1571056053
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2552619103
Short name T481
Test name
Test status
Simulation time 43696818 ps
CPU time 2.76 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:26 PM PDT 24
Peak memory 222268 kb
Host smart-393e992b-5287-49fe-87a0-9cf2cd47a7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552619103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2552619103
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2717826352
Short name T841
Test name
Test status
Simulation time 378861795 ps
CPU time 14.48 seconds
Started Jul 15 06:31:21 PM PDT 24
Finished Jul 15 06:31:36 PM PDT 24
Peak memory 225964 kb
Host smart-38929c38-20e3-4321-a4eb-17ed6763ce8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717826352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2717826352
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3052608421
Short name T270
Test name
Test status
Simulation time 354397009 ps
CPU time 7.65 seconds
Started Jul 15 06:31:23 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 218236 kb
Host smart-cdab5ab1-119f-4234-8f2d-02c88f256ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052608421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3052608421
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2446071364
Short name T730
Test name
Test status
Simulation time 232740563 ps
CPU time 10.38 seconds
Started Jul 15 06:31:23 PM PDT 24
Finished Jul 15 06:31:36 PM PDT 24
Peak memory 225888 kb
Host smart-c460c6d2-2b3a-4abb-a3c7-9f7caaa07a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446071364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2446071364
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3306163724
Short name T734
Test name
Test status
Simulation time 425898258 ps
CPU time 5.5 seconds
Started Jul 15 06:31:26 PM PDT 24
Finished Jul 15 06:31:33 PM PDT 24
Peak memory 222756 kb
Host smart-4c3d9c09-17bf-4aa2-b0df-9fa836d1e1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306163724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3306163724
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.785700775
Short name T718
Test name
Test status
Simulation time 310447899 ps
CPU time 34.11 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:59 PM PDT 24
Peak memory 250888 kb
Host smart-ce05b199-cca6-4c62-a7ba-75f5f7308f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785700775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.785700775
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2322324029
Short name T635
Test name
Test status
Simulation time 110112383 ps
CPU time 7.11 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:31 PM PDT 24
Peak memory 250436 kb
Host smart-f737a02d-c6f7-48ae-81d5-142c47389b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322324029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2322324029
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.649825695
Short name T843
Test name
Test status
Simulation time 17894377346 ps
CPU time 292.08 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:36:16 PM PDT 24
Peak memory 312476 kb
Host smart-fbfeeab2-e394-4c63-93e1-b329e209169d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649825695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.649825695
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4152965750
Short name T698
Test name
Test status
Simulation time 22887633 ps
CPU time 1.13 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:25 PM PDT 24
Peak memory 212840 kb
Host smart-eeeedd5f-c7d3-4b99-ad99-0a1bab6a11fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152965750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4152965750
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2372598422
Short name T835
Test name
Test status
Simulation time 22843492 ps
CPU time 0.98 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:31:39 PM PDT 24
Peak memory 208900 kb
Host smart-b508543c-f49c-4ece-ba37-1951e33f100f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372598422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2372598422
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3537973834
Short name T705
Test name
Test status
Simulation time 1236465825 ps
CPU time 12.62 seconds
Started Jul 15 06:31:23 PM PDT 24
Finished Jul 15 06:31:38 PM PDT 24
Peak memory 218060 kb
Host smart-a0de396f-4ab7-48c4-acc9-d331239c2de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537973834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3537973834
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1940880979
Short name T388
Test name
Test status
Simulation time 1933127694 ps
CPU time 3.07 seconds
Started Jul 15 06:31:27 PM PDT 24
Finished Jul 15 06:31:31 PM PDT 24
Peak memory 217180 kb
Host smart-1a017c88-0429-468e-a370-deabefd3b402
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940880979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1940880979
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.856107517
Short name T564
Test name
Test status
Simulation time 474988631 ps
CPU time 3.67 seconds
Started Jul 15 06:31:23 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 218048 kb
Host smart-b79d9cf3-0b35-4a39-bb8c-ea5fc4df9e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856107517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.856107517
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.414997525
Short name T566
Test name
Test status
Simulation time 309526756 ps
CPU time 10.13 seconds
Started Jul 15 06:31:27 PM PDT 24
Finished Jul 15 06:31:38 PM PDT 24
Peak memory 218828 kb
Host smart-38b020a2-14e3-4591-9669-a7bf3a2b1fee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414997525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.414997525
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3634427238
Short name T23
Test name
Test status
Simulation time 1990347236 ps
CPU time 10.86 seconds
Started Jul 15 06:31:32 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 226028 kb
Host smart-0606ee79-24c7-4edf-b949-488c405b1147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634427238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3634427238
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.992311670
Short name T608
Test name
Test status
Simulation time 209666234 ps
CPU time 7.4 seconds
Started Jul 15 06:31:26 PM PDT 24
Finished Jul 15 06:31:35 PM PDT 24
Peak memory 225928 kb
Host smart-2657bf07-5f2e-416e-9379-b10403276b43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992311670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.992311670
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4020345473
Short name T319
Test name
Test status
Simulation time 921917612 ps
CPU time 9.59 seconds
Started Jul 15 06:31:31 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 225048 kb
Host smart-df6dc443-b8df-4a58-bda6-6c22583db42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020345473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4020345473
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1764632810
Short name T92
Test name
Test status
Simulation time 18432668 ps
CPU time 1.48 seconds
Started Jul 15 06:31:26 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 214048 kb
Host smart-3c7d4869-3c70-4c9e-80f1-983e3803b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764632810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1764632810
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.417670701
Short name T772
Test name
Test status
Simulation time 411061087 ps
CPU time 30.96 seconds
Started Jul 15 06:31:29 PM PDT 24
Finished Jul 15 06:32:01 PM PDT 24
Peak memory 250904 kb
Host smart-b2cb00b4-829e-48c3-9441-faac96145148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417670701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.417670701
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3272830618
Short name T509
Test name
Test status
Simulation time 236876572 ps
CPU time 3.67 seconds
Started Jul 15 06:31:22 PM PDT 24
Finished Jul 15 06:31:28 PM PDT 24
Peak memory 222388 kb
Host smart-99b164fb-7f34-47c9-98c8-1864070ec9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272830618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3272830618
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2522447711
Short name T519
Test name
Test status
Simulation time 20566438136 ps
CPU time 193.33 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:34:50 PM PDT 24
Peak memory 268956 kb
Host smart-0e3e81a2-fa26-47e7-8885-f7fecfdce79a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522447711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2522447711
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2434491268
Short name T583
Test name
Test status
Simulation time 16717170 ps
CPU time 0.89 seconds
Started Jul 15 06:31:26 PM PDT 24
Finished Jul 15 06:31:28 PM PDT 24
Peak memory 211824 kb
Host smart-fec43abc-53c3-49c2-b0bf-1c0911476b18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434491268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2434491268
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.187192129
Short name T86
Test name
Test status
Simulation time 15913306 ps
CPU time 1.12 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:31:39 PM PDT 24
Peak memory 208852 kb
Host smart-26c33e64-75ce-463f-b6cb-fc8542126daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187192129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.187192129
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.650925691
Short name T398
Test name
Test status
Simulation time 370674766 ps
CPU time 8.96 seconds
Started Jul 15 06:31:29 PM PDT 24
Finished Jul 15 06:31:39 PM PDT 24
Peak memory 225972 kb
Host smart-790e7206-54f0-49eb-9bb8-bed87306cf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650925691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.650925691
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.517318588
Short name T617
Test name
Test status
Simulation time 327064086 ps
CPU time 4.84 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 217280 kb
Host smart-016dbc3a-84e6-4e08-90b2-ccaff975f12c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517318588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.517318588
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1862037041
Short name T202
Test name
Test status
Simulation time 223166202 ps
CPU time 2.75 seconds
Started Jul 15 06:31:28 PM PDT 24
Finished Jul 15 06:31:31 PM PDT 24
Peak memory 218028 kb
Host smart-b631a2e0-799f-405a-a327-29361c3e534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862037041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1862037041
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1856490649
Short name T584
Test name
Test status
Simulation time 1003353451 ps
CPU time 11.85 seconds
Started Jul 15 06:31:31 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 225500 kb
Host smart-a82c40eb-b0b7-4ce4-b8da-722c834fb274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856490649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1856490649
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.543409898
Short name T569
Test name
Test status
Simulation time 1479046530 ps
CPU time 9.61 seconds
Started Jul 15 06:31:28 PM PDT 24
Finished Jul 15 06:31:39 PM PDT 24
Peak memory 218224 kb
Host smart-a9394271-0949-4dd3-a26f-c53ba3370fba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543409898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.543409898
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2264259978
Short name T683
Test name
Test status
Simulation time 1528664669 ps
CPU time 7.04 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:44 PM PDT 24
Peak memory 225964 kb
Host smart-38c7f0b9-470d-409a-b7a5-d899b6913eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264259978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2264259978
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1525341496
Short name T459
Test name
Test status
Simulation time 183578532 ps
CPU time 1.94 seconds
Started Jul 15 06:31:35 PM PDT 24
Finished Jul 15 06:31:38 PM PDT 24
Peak memory 214260 kb
Host smart-91ab438e-d9f5-4f01-b655-2aae6b9ef340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525341496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1525341496
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1254192098
Short name T784
Test name
Test status
Simulation time 192457603 ps
CPU time 19.87 seconds
Started Jul 15 06:31:27 PM PDT 24
Finished Jul 15 06:31:48 PM PDT 24
Peak memory 250912 kb
Host smart-79965de3-4b08-4713-9009-c17bafe6f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254192098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1254192098
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1375463579
Short name T700
Test name
Test status
Simulation time 105054837 ps
CPU time 7.61 seconds
Started Jul 15 06:31:31 PM PDT 24
Finished Jul 15 06:31:39 PM PDT 24
Peak memory 250916 kb
Host smart-b5fc018e-9995-465f-bdbd-1549f17f7feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375463579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1375463579
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.4165077850
Short name T307
Test name
Test status
Simulation time 10457712787 ps
CPU time 98.81 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:33:17 PM PDT 24
Peak memory 250980 kb
Host smart-518003ee-0545-4ac2-9b00-03799a0a1b93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165077850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.4165077850
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1972033182
Short name T183
Test name
Test status
Simulation time 36983242 ps
CPU time 0.93 seconds
Started Jul 15 06:31:28 PM PDT 24
Finished Jul 15 06:31:30 PM PDT 24
Peak memory 211756 kb
Host smart-1f872a07-8242-468d-9f78-93f44aa25acd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972033182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1972033182
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1762144919
Short name T655
Test name
Test status
Simulation time 27419033 ps
CPU time 0.97 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 208868 kb
Host smart-847d8318-a0b7-4bae-b650-4b70341bde37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762144919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1762144919
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4130208362
Short name T660
Test name
Test status
Simulation time 3148613558 ps
CPU time 12.58 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:50 PM PDT 24
Peak memory 218888 kb
Host smart-199b9bd2-aad1-4f74-9b12-c18ce5324e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130208362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4130208362
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3707810240
Short name T445
Test name
Test status
Simulation time 1006178424 ps
CPU time 7.08 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 217328 kb
Host smart-df0f4bcc-aa66-4ce9-a500-0d462d335e37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707810240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3707810240
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.876385486
Short name T535
Test name
Test status
Simulation time 62459266 ps
CPU time 2.5 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 218048 kb
Host smart-42e78abc-5a56-4814-bce0-ab528ade305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876385486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.876385486
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1930232152
Short name T602
Test name
Test status
Simulation time 2247562819 ps
CPU time 16.54 seconds
Started Jul 15 06:31:38 PM PDT 24
Finished Jul 15 06:31:55 PM PDT 24
Peak memory 226040 kb
Host smart-99203767-929a-4cf0-92af-a069c6001da5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930232152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1930232152
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.298406354
Short name T320
Test name
Test status
Simulation time 309807488 ps
CPU time 12.39 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:53 PM PDT 24
Peak memory 225916 kb
Host smart-d440d02c-e380-4724-8a43-5da0bf30f601
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298406354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.298406354
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.706749032
Short name T333
Test name
Test status
Simulation time 365748895 ps
CPU time 9.25 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:46 PM PDT 24
Peak memory 225944 kb
Host smart-00ff050b-b612-45a4-a60f-be251184ae5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706749032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.706749032
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1463127843
Short name T325
Test name
Test status
Simulation time 459796345 ps
CPU time 8.34 seconds
Started Jul 15 06:31:38 PM PDT 24
Finished Jul 15 06:31:48 PM PDT 24
Peak memory 225412 kb
Host smart-95bfaf46-ce1d-4b1a-b47c-9fd358c6c41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463127843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1463127843
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1700070779
Short name T436
Test name
Test status
Simulation time 84869754 ps
CPU time 1.97 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 214204 kb
Host smart-2b8acf89-3d1f-4e8f-a558-53240e7f29ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700070779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1700070779
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.505058083
Short name T345
Test name
Test status
Simulation time 192067145 ps
CPU time 18.3 seconds
Started Jul 15 06:31:38 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 250896 kb
Host smart-e2b95db6-674d-4c30-bab6-24d59ea9b4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505058083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.505058083
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1953067351
Short name T643
Test name
Test status
Simulation time 145958132 ps
CPU time 9.47 seconds
Started Jul 15 06:31:38 PM PDT 24
Finished Jul 15 06:31:49 PM PDT 24
Peak memory 250760 kb
Host smart-4467b6b2-637d-417f-9668-81248fd0f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953067351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1953067351
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4001875152
Short name T194
Test name
Test status
Simulation time 23328831542 ps
CPU time 113.05 seconds
Started Jul 15 06:31:40 PM PDT 24
Finished Jul 15 06:33:34 PM PDT 24
Peak memory 269088 kb
Host smart-f68bbe18-3070-4f0d-83a9-042cb56099ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001875152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4001875152
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1880722634
Short name T173
Test name
Test status
Simulation time 253731547940 ps
CPU time 701.69 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:43:19 PM PDT 24
Peak memory 420964 kb
Host smart-e23c2334-79e0-4704-90ca-22dbad19e1af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1880722634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1880722634
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3424081888
Short name T753
Test name
Test status
Simulation time 35004116 ps
CPU time 0.86 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:37 PM PDT 24
Peak memory 211896 kb
Host smart-d25682f3-bc48-4087-99be-856d52d78140
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424081888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3424081888
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3765663452
Short name T110
Test name
Test status
Simulation time 22420747 ps
CPU time 0.98 seconds
Started Jul 15 06:29:43 PM PDT 24
Finished Jul 15 06:29:44 PM PDT 24
Peak memory 208956 kb
Host smart-f4ce7b20-a231-43a3-99a0-5fa4def72dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765663452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3765663452
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1389721902
Short name T567
Test name
Test status
Simulation time 1474670147 ps
CPU time 9.25 seconds
Started Jul 15 06:29:42 PM PDT 24
Finished Jul 15 06:29:52 PM PDT 24
Peak memory 218124 kb
Host smart-2ddbeab7-11ac-418e-a1eb-c1460297b5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389721902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1389721902
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1767452466
Short name T421
Test name
Test status
Simulation time 453770556 ps
CPU time 5.87 seconds
Started Jul 15 06:29:44 PM PDT 24
Finished Jul 15 06:29:50 PM PDT 24
Peak memory 217344 kb
Host smart-9e7d8820-1c0e-41e4-a46b-458b981d5429
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767452466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1767452466
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3553887217
Short name T180
Test name
Test status
Simulation time 2372002291 ps
CPU time 22.4 seconds
Started Jul 15 06:29:42 PM PDT 24
Finished Jul 15 06:30:05 PM PDT 24
Peak memory 219004 kb
Host smart-fdb11eb6-44e4-44c1-862e-b753216a9394
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553887217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3553887217
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3712116816
Short name T819
Test name
Test status
Simulation time 85157457 ps
CPU time 2.95 seconds
Started Jul 15 06:29:42 PM PDT 24
Finished Jul 15 06:29:45 PM PDT 24
Peak memory 217696 kb
Host smart-478be731-2571-4a3e-8697-dd34f2fd5a66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712116816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
712116816
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1666376881
Short name T438
Test name
Test status
Simulation time 239719846 ps
CPU time 8.18 seconds
Started Jul 15 06:29:41 PM PDT 24
Finished Jul 15 06:29:50 PM PDT 24
Peak memory 218156 kb
Host smart-fcf1f603-e171-4926-8c43-f79357e6195d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666376881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1666376881
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3209135578
Short name T30
Test name
Test status
Simulation time 909221683 ps
CPU time 28.92 seconds
Started Jul 15 06:29:42 PM PDT 24
Finished Jul 15 06:30:11 PM PDT 24
Peak memory 217656 kb
Host smart-b251a9c9-feda-4ae0-9878-162a837ef37f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209135578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3209135578
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4057563912
Short name T77
Test name
Test status
Simulation time 372575529 ps
CPU time 9.69 seconds
Started Jul 15 06:29:43 PM PDT 24
Finished Jul 15 06:29:53 PM PDT 24
Peak memory 217592 kb
Host smart-851f59ab-7c2b-4bb2-be9f-db22c8bc0a19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057563912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4057563912
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3967531690
Short name T531
Test name
Test status
Simulation time 4481777233 ps
CPU time 86.18 seconds
Started Jul 15 06:29:44 PM PDT 24
Finished Jul 15 06:31:10 PM PDT 24
Peak memory 280764 kb
Host smart-053bdce9-e537-4a96-8b84-d936212fbcc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967531690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3967531690
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4038084140
Short name T401
Test name
Test status
Simulation time 1462499712 ps
CPU time 11.68 seconds
Started Jul 15 06:29:44 PM PDT 24
Finished Jul 15 06:29:56 PM PDT 24
Peak memory 250692 kb
Host smart-a09e4e57-e967-4e39-acad-e1cff0bfa292
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038084140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4038084140
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3515765158
Short name T393
Test name
Test status
Simulation time 41621584 ps
CPU time 2.2 seconds
Started Jul 15 06:29:38 PM PDT 24
Finished Jul 15 06:29:41 PM PDT 24
Peak memory 222320 kb
Host smart-1d7c9c07-eb48-4397-872e-7cca6beefbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515765158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3515765158
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1783360647
Short name T612
Test name
Test status
Simulation time 1151422324 ps
CPU time 24.97 seconds
Started Jul 15 06:29:41 PM PDT 24
Finished Jul 15 06:30:06 PM PDT 24
Peak memory 214716 kb
Host smart-40a890c5-27cf-4fa3-8e29-fbf4191e4c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783360647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1783360647
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1284586133
Short name T414
Test name
Test status
Simulation time 1200545254 ps
CPU time 12.46 seconds
Started Jul 15 06:29:42 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 218844 kb
Host smart-4257e519-2dd6-4db3-88c7-ad896d799f5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284586133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1284586133
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1029977824
Short name T797
Test name
Test status
Simulation time 5467170614 ps
CPU time 15.31 seconds
Started Jul 15 06:29:43 PM PDT 24
Finished Jul 15 06:29:59 PM PDT 24
Peak memory 226020 kb
Host smart-4eed91de-d1e0-42ec-a34b-1dccab9736d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029977824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1029977824
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3206137927
Short name T670
Test name
Test status
Simulation time 437725686 ps
CPU time 14.9 seconds
Started Jul 15 06:29:44 PM PDT 24
Finished Jul 15 06:29:59 PM PDT 24
Peak memory 218160 kb
Host smart-eca1b6b6-ee9f-4bc3-8f70-45d306d070fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206137927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
206137927
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1341839681
Short name T638
Test name
Test status
Simulation time 5151668664 ps
CPU time 15.07 seconds
Started Jul 15 06:29:39 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 225972 kb
Host smart-5ea03f1c-77fa-45ed-8b25-839ea4efc6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341839681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1341839681
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3440820076
Short name T706
Test name
Test status
Simulation time 269142274 ps
CPU time 5.01 seconds
Started Jul 15 06:29:37 PM PDT 24
Finished Jul 15 06:29:43 PM PDT 24
Peak memory 217652 kb
Host smart-1afe1852-8a77-4ab1-bce7-c22210a23805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440820076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3440820076
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3782801520
Short name T293
Test name
Test status
Simulation time 419224100 ps
CPU time 24.22 seconds
Started Jul 15 06:29:39 PM PDT 24
Finished Jul 15 06:30:03 PM PDT 24
Peak memory 250944 kb
Host smart-f2602995-77b7-46fb-84ed-90cded308b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782801520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3782801520
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.4277980154
Short name T702
Test name
Test status
Simulation time 160469447 ps
CPU time 7.85 seconds
Started Jul 15 06:29:39 PM PDT 24
Finished Jul 15 06:29:47 PM PDT 24
Peak memory 250920 kb
Host smart-da2886ea-5fac-4517-a8e3-38afa6370778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277980154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4277980154
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1492302197
Short name T582
Test name
Test status
Simulation time 15837094835 ps
CPU time 146.37 seconds
Started Jul 15 06:29:44 PM PDT 24
Finished Jul 15 06:32:11 PM PDT 24
Peak memory 282236 kb
Host smart-01878ec6-95c3-46bf-95df-0d3c787fe9e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492302197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1492302197
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.895065883
Short name T338
Test name
Test status
Simulation time 15285652 ps
CPU time 1.07 seconds
Started Jul 15 06:29:37 PM PDT 24
Finished Jul 15 06:29:38 PM PDT 24
Peak memory 211744 kb
Host smart-fa13dbdf-91be-4d7c-b21f-3e914d4eee68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895065883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.895065883
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1508555836
Short name T408
Test name
Test status
Simulation time 21797443 ps
CPU time 0.94 seconds
Started Jul 15 06:31:41 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 208908 kb
Host smart-0ba2a1c8-c3b8-49d8-bd11-9e25ed50f140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508555836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1508555836
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.41521049
Short name T367
Test name
Test status
Simulation time 233621463 ps
CPU time 11.6 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:49 PM PDT 24
Peak memory 218172 kb
Host smart-f1aa9c04-0bc6-490c-93d9-0892cd9a94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41521049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.41521049
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.56597838
Short name T493
Test name
Test status
Simulation time 369470112 ps
CPU time 4.03 seconds
Started Jul 15 06:31:38 PM PDT 24
Finished Jul 15 06:31:44 PM PDT 24
Peak memory 217064 kb
Host smart-6269b68c-1323-4372-9c0e-c0050f762125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56597838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.56597838
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1387196495
Short name T761
Test name
Test status
Simulation time 200636580 ps
CPU time 3.89 seconds
Started Jul 15 06:31:38 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 218172 kb
Host smart-c730e43a-8022-4cb8-afa8-5d9d97d52ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387196495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1387196495
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.505484949
Short name T565
Test name
Test status
Simulation time 272211673 ps
CPU time 10.03 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:47 PM PDT 24
Peak memory 225852 kb
Host smart-bd71464c-60a1-40b6-b0a8-edd362912133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505484949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.505484949
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3578236722
Short name T665
Test name
Test status
Simulation time 1237143956 ps
CPU time 22.85 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:32:03 PM PDT 24
Peak memory 225960 kb
Host smart-fb9877f1-c9c7-4c7b-ba0f-a7be4404a192
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578236722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3578236722
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.482334985
Short name T354
Test name
Test status
Simulation time 1084128266 ps
CPU time 7.15 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:47 PM PDT 24
Peak memory 218184 kb
Host smart-ac0db779-4663-4404-b572-d61318054c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482334985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.482334985
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4257724456
Short name T560
Test name
Test status
Simulation time 259575010 ps
CPU time 10.1 seconds
Started Jul 15 06:31:36 PM PDT 24
Finished Jul 15 06:31:47 PM PDT 24
Peak memory 225332 kb
Host smart-f14d63ff-97e2-49cc-a6b5-e454ed879021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257724456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4257724456
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2449802073
Short name T624
Test name
Test status
Simulation time 99251762 ps
CPU time 1.96 seconds
Started Jul 15 06:31:35 PM PDT 24
Finished Jul 15 06:31:37 PM PDT 24
Peak memory 217652 kb
Host smart-37c1f407-bf4c-4188-a12c-57f95eb4bc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449802073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2449802073
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.204897526
Short name T357
Test name
Test status
Simulation time 677645473 ps
CPU time 17.6 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 250868 kb
Host smart-4edd7881-0b5d-4f66-b2f6-6507359d360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204897526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.204897526
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3843020894
Short name T407
Test name
Test status
Simulation time 73739132 ps
CPU time 3.84 seconds
Started Jul 15 06:31:35 PM PDT 24
Finished Jul 15 06:31:39 PM PDT 24
Peak memory 222352 kb
Host smart-35ed36ec-c2c4-4ef9-b25d-07127ebfa4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843020894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3843020894
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3510248168
Short name T817
Test name
Test status
Simulation time 7093490107 ps
CPU time 220.33 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:35:18 PM PDT 24
Peak memory 267356 kb
Host smart-8b5ca596-8c92-4e3f-afc7-c3bd97644fc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510248168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3510248168
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.944364028
Short name T442
Test name
Test status
Simulation time 13601044 ps
CPU time 1.04 seconds
Started Jul 15 06:31:35 PM PDT 24
Finished Jul 15 06:31:37 PM PDT 24
Peak memory 211884 kb
Host smart-6d8ac132-635c-4fc5-8a75-cef4a7bc43c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944364028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.944364028
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3592491386
Short name T351
Test name
Test status
Simulation time 64087806 ps
CPU time 1.08 seconds
Started Jul 15 06:31:47 PM PDT 24
Finished Jul 15 06:31:49 PM PDT 24
Peak memory 208936 kb
Host smart-594dc4a9-37c5-4261-92c1-8d4942d2adaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592491386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3592491386
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.343385161
Short name T439
Test name
Test status
Simulation time 253750033 ps
CPU time 11.48 seconds
Started Jul 15 06:31:41 PM PDT 24
Finished Jul 15 06:31:53 PM PDT 24
Peak memory 225968 kb
Host smart-22d7bd26-0d3a-4391-98e1-42f058c55571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343385161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.343385161
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2565840290
Short name T444
Test name
Test status
Simulation time 3004678717 ps
CPU time 9.59 seconds
Started Jul 15 06:31:41 PM PDT 24
Finished Jul 15 06:31:51 PM PDT 24
Peak memory 217712 kb
Host smart-b74f5520-d7bb-4160-acd2-08f3d70d645e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565840290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2565840290
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.664098663
Short name T595
Test name
Test status
Simulation time 43822355 ps
CPU time 2.13 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 218132 kb
Host smart-3f923147-d803-48e9-af87-c8c4e504ba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664098663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.664098663
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2095549243
Short name T52
Test name
Test status
Simulation time 412148785 ps
CPU time 14.39 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:54 PM PDT 24
Peak memory 219416 kb
Host smart-5d899ba5-0f08-47f5-b186-6047ee305493
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095549243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2095549243
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2767305593
Short name T431
Test name
Test status
Simulation time 612667088 ps
CPU time 10.7 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:51 PM PDT 24
Peak memory 225924 kb
Host smart-2187053d-770b-4cb7-b678-e50b78f6ca5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767305593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2767305593
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1982427669
Short name T654
Test name
Test status
Simulation time 1008957633 ps
CPU time 10.81 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 225956 kb
Host smart-68620040-0a71-4197-adcc-e9c8f7dde133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982427669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1982427669
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3665195821
Short name T547
Test name
Test status
Simulation time 1639960239 ps
CPU time 15.17 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:32:02 PM PDT 24
Peak memory 225960 kb
Host smart-4e92a6a0-8e57-4614-81de-87917b5f5bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665195821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3665195821
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2910176926
Short name T779
Test name
Test status
Simulation time 515404296 ps
CPU time 7.15 seconds
Started Jul 15 06:31:34 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 217664 kb
Host smart-6cca5c89-2172-496b-b45e-7c67f78406a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910176926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2910176926
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4199567222
Short name T332
Test name
Test status
Simulation time 1174793915 ps
CPU time 20.52 seconds
Started Jul 15 06:31:37 PM PDT 24
Finished Jul 15 06:31:59 PM PDT 24
Peak memory 250820 kb
Host smart-544ef51a-0f28-49b5-a6ea-8cd1383cc3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199567222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4199567222
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1263642754
Short name T255
Test name
Test status
Simulation time 242653021 ps
CPU time 3.79 seconds
Started Jul 15 06:31:38 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 226272 kb
Host smart-b4af9020-359e-497d-9a2d-11ae1f880d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263642754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1263642754
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2386839346
Short name T397
Test name
Test status
Simulation time 4438331456 ps
CPU time 27.13 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 226012 kb
Host smart-bcc2e5e2-edcf-4615-9815-f9f550d74503
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386839346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2386839346
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1917539647
Short name T725
Test name
Test status
Simulation time 26842548 ps
CPU time 1.07 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:41 PM PDT 24
Peak memory 212888 kb
Host smart-355e2590-e8bc-4a0f-b043-a53ee1de2a97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917539647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1917539647
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4275057469
Short name T763
Test name
Test status
Simulation time 49635729 ps
CPU time 0.88 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:31:48 PM PDT 24
Peak memory 208744 kb
Host smart-3d009b2a-b810-4b8d-a2d1-cceb26c69fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275057469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4275057469
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2193600390
Short name T296
Test name
Test status
Simulation time 314598678 ps
CPU time 11.11 seconds
Started Jul 15 06:31:42 PM PDT 24
Finished Jul 15 06:31:53 PM PDT 24
Peak memory 218212 kb
Host smart-f196f024-7fe2-4cd9-a44f-7c68fb3aee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193600390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2193600390
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3855504753
Short name T755
Test name
Test status
Simulation time 7255543691 ps
CPU time 7.41 seconds
Started Jul 15 06:31:44 PM PDT 24
Finished Jul 15 06:31:52 PM PDT 24
Peak memory 217876 kb
Host smart-fd596462-21f2-4cd8-a7d1-efcdc16f3e50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855504753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3855504753
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.713435504
Short name T785
Test name
Test status
Simulation time 22104478 ps
CPU time 1.41 seconds
Started Jul 15 06:31:40 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 218164 kb
Host smart-5cfa586d-e4e3-4302-a5cc-110aa4730f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713435504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.713435504
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.166458047
Short name T528
Test name
Test status
Simulation time 4427418226 ps
CPU time 17.01 seconds
Started Jul 15 06:31:43 PM PDT 24
Finished Jul 15 06:32:01 PM PDT 24
Peak memory 219472 kb
Host smart-98652f60-95ea-4de5-8f11-3350529fd4e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166458047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.166458047
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3748637544
Short name T603
Test name
Test status
Simulation time 228463521 ps
CPU time 7.47 seconds
Started Jul 15 06:31:40 PM PDT 24
Finished Jul 15 06:31:49 PM PDT 24
Peak memory 225916 kb
Host smart-3546ad31-7780-425e-9616-8a973346c957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748637544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3748637544
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1984457045
Short name T335
Test name
Test status
Simulation time 391574222 ps
CPU time 11.29 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 225960 kb
Host smart-daa6eaf7-bcbc-444a-a11b-1ce027c65e89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984457045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1984457045
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.791086423
Short name T59
Test name
Test status
Simulation time 311765500 ps
CPU time 11.83 seconds
Started Jul 15 06:31:43 PM PDT 24
Finished Jul 15 06:31:56 PM PDT 24
Peak memory 225944 kb
Host smart-f8f23328-4151-4351-a973-c2f3bf960289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791086423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.791086423
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4060241602
Short name T215
Test name
Test status
Simulation time 42675083 ps
CPU time 2.53 seconds
Started Jul 15 06:31:40 PM PDT 24
Finished Jul 15 06:31:43 PM PDT 24
Peak memory 217648 kb
Host smart-bdec2d3b-2b54-4cd2-9d57-944d08ed5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060241602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4060241602
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1041435909
Short name T723
Test name
Test status
Simulation time 257438662 ps
CPU time 26.53 seconds
Started Jul 15 06:31:40 PM PDT 24
Finished Jul 15 06:32:07 PM PDT 24
Peak memory 250912 kb
Host smart-ee4dbe26-f024-4af2-8172-88fb616ab30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041435909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1041435909
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3784754401
Short name T287
Test name
Test status
Simulation time 356318987 ps
CPU time 6.92 seconds
Started Jul 15 06:31:40 PM PDT 24
Finished Jul 15 06:31:48 PM PDT 24
Peak memory 246756 kb
Host smart-13c89595-2144-4cab-abaa-0d23cc5d6dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784754401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3784754401
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2292806186
Short name T264
Test name
Test status
Simulation time 14174009400 ps
CPU time 89.92 seconds
Started Jul 15 06:31:47 PM PDT 24
Finished Jul 15 06:33:18 PM PDT 24
Peak memory 279768 kb
Host smart-dad57983-e1ce-4106-9ff7-672f919f0a27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292806186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2292806186
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.852445601
Short name T571
Test name
Test status
Simulation time 48020581 ps
CPU time 0.87 seconds
Started Jul 15 06:31:41 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 211776 kb
Host smart-e892cbbd-0ff7-46c0-87f4-e123cf9a1855
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852445601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.852445601
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3594009823
Short name T503
Test name
Test status
Simulation time 17624933 ps
CPU time 1.19 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:31:48 PM PDT 24
Peak memory 208992 kb
Host smart-77dd1c90-63b9-492d-96ef-e34c47470353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594009823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3594009823
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3470188029
Short name T527
Test name
Test status
Simulation time 938072641 ps
CPU time 10.76 seconds
Started Jul 15 06:31:53 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 218148 kb
Host smart-2cbf0690-e022-4168-85fd-06c5196b64c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470188029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3470188029
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1743922734
Short name T432
Test name
Test status
Simulation time 805840755 ps
CPU time 19.45 seconds
Started Jul 15 06:31:45 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 217324 kb
Host smart-4f270fd2-56ce-420c-b969-014038ebcbe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743922734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1743922734
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2855412434
Short name T645
Test name
Test status
Simulation time 78280837 ps
CPU time 1.57 seconds
Started Jul 15 06:31:49 PM PDT 24
Finished Jul 15 06:31:51 PM PDT 24
Peak memory 218148 kb
Host smart-a2e7004f-b5b4-415a-91d8-a23e35ec5dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855412434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2855412434
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3805291560
Short name T558
Test name
Test status
Simulation time 1771828461 ps
CPU time 14.01 seconds
Started Jul 15 06:31:44 PM PDT 24
Finished Jul 15 06:31:59 PM PDT 24
Peak memory 218772 kb
Host smart-81f60b14-2683-4ce4-ae9b-cd97bf76708b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805291560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3805291560
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1434427381
Short name T390
Test name
Test status
Simulation time 214826059 ps
CPU time 7.09 seconds
Started Jul 15 06:31:53 PM PDT 24
Finished Jul 15 06:32:01 PM PDT 24
Peak memory 225412 kb
Host smart-a7d93f73-a9b5-4fe7-b358-de6e5a69255d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434427381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1434427381
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3974898883
Short name T57
Test name
Test status
Simulation time 563065718 ps
CPU time 20.07 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:32:07 PM PDT 24
Peak memory 218180 kb
Host smart-c463fc98-1d77-4ea7-93e3-c0b7e81368e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974898883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3974898883
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1447237689
Short name T530
Test name
Test status
Simulation time 309928745 ps
CPU time 7.92 seconds
Started Jul 15 06:31:47 PM PDT 24
Finished Jul 15 06:31:56 PM PDT 24
Peak memory 225868 kb
Host smart-74e315ee-c9b4-415d-b12d-65ca329eec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447237689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1447237689
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.733516249
Short name T80
Test name
Test status
Simulation time 27720872 ps
CPU time 1.9 seconds
Started Jul 15 06:31:39 PM PDT 24
Finished Jul 15 06:31:42 PM PDT 24
Peak memory 213952 kb
Host smart-f272474c-fcfb-415d-a4c3-bf860ea26db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733516249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.733516249
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2134031323
Short name T99
Test name
Test status
Simulation time 262015593 ps
CPU time 26.51 seconds
Started Jul 15 06:31:41 PM PDT 24
Finished Jul 15 06:32:08 PM PDT 24
Peak memory 250868 kb
Host smart-7948d593-1180-4917-b4f0-b41153070545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134031323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2134031323
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2644133245
Short name T859
Test name
Test status
Simulation time 74425742 ps
CPU time 7.58 seconds
Started Jul 15 06:31:45 PM PDT 24
Finished Jul 15 06:31:53 PM PDT 24
Peak memory 242784 kb
Host smart-ff473fc7-6cbd-469e-b3ec-e418ed2c3bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644133245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2644133245
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1316017548
Short name T356
Test name
Test status
Simulation time 6109311906 ps
CPU time 121.71 seconds
Started Jul 15 06:31:43 PM PDT 24
Finished Jul 15 06:33:45 PM PDT 24
Peak memory 279772 kb
Host smart-1d97c949-5527-42c8-ac62-1893e9c24149
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316017548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1316017548
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3064287029
Short name T631
Test name
Test status
Simulation time 32629233 ps
CPU time 0.96 seconds
Started Jul 15 06:31:44 PM PDT 24
Finished Jul 15 06:31:46 PM PDT 24
Peak memory 211824 kb
Host smart-02f47f7b-d46c-4063-b1ce-d5e77111b0ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064287029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3064287029
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2203888030
Short name T422
Test name
Test status
Simulation time 59798110 ps
CPU time 0.9 seconds
Started Jul 15 06:31:53 PM PDT 24
Finished Jul 15 06:31:55 PM PDT 24
Peak memory 208876 kb
Host smart-4de5bcaf-2fbc-42c2-844a-2f8dbf6a4e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203888030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2203888030
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1491896858
Short name T452
Test name
Test status
Simulation time 1642983613 ps
CPU time 18.44 seconds
Started Jul 15 06:31:45 PM PDT 24
Finished Jul 15 06:32:04 PM PDT 24
Peak memory 218152 kb
Host smart-3339853f-cfb0-4916-a9de-cf594137cea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491896858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1491896858
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3514937160
Short name T33
Test name
Test status
Simulation time 1219805580 ps
CPU time 8.75 seconds
Started Jul 15 06:31:47 PM PDT 24
Finished Jul 15 06:31:56 PM PDT 24
Peak memory 217248 kb
Host smart-eef9415a-b992-4384-858e-c3733bebcb30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514937160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3514937160
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3148245496
Short name T597
Test name
Test status
Simulation time 40355997 ps
CPU time 2.31 seconds
Started Jul 15 06:31:53 PM PDT 24
Finished Jul 15 06:31:56 PM PDT 24
Peak memory 222208 kb
Host smart-f95e591e-4e01-467f-90e9-c26a455c92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148245496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3148245496
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2754854896
Short name T746
Test name
Test status
Simulation time 1370428004 ps
CPU time 10.95 seconds
Started Jul 15 06:31:53 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 225944 kb
Host smart-12e23ed8-96d1-441e-ba90-448bccac3df5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754854896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2754854896
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2214787886
Short name T563
Test name
Test status
Simulation time 1896170372 ps
CPU time 19.41 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:32:06 PM PDT 24
Peak memory 218164 kb
Host smart-b841110e-253c-4bb2-a2a4-3fa25b1a6ed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214787886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2214787886
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.972071798
Short name T324
Test name
Test status
Simulation time 3514762277 ps
CPU time 8.63 seconds
Started Jul 15 06:31:44 PM PDT 24
Finished Jul 15 06:31:53 PM PDT 24
Peak memory 218328 kb
Host smart-b2c1dc4a-4bba-4d6a-a924-e8ceb0f782bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972071798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.972071798
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4237781433
Short name T867
Test name
Test status
Simulation time 173240948 ps
CPU time 2.34 seconds
Started Jul 15 06:31:45 PM PDT 24
Finished Jul 15 06:31:48 PM PDT 24
Peak memory 214432 kb
Host smart-8ac1dccd-d03f-47bc-ac2b-bf077041ecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237781433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4237781433
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1410510124
Short name T622
Test name
Test status
Simulation time 262221460 ps
CPU time 25.84 seconds
Started Jul 15 06:31:45 PM PDT 24
Finished Jul 15 06:32:11 PM PDT 24
Peak memory 251000 kb
Host smart-cb390809-4cb4-4bec-8761-8128ddde29f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410510124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1410510124
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1510860934
Short name T688
Test name
Test status
Simulation time 495863920 ps
CPU time 8.01 seconds
Started Jul 15 06:31:46 PM PDT 24
Finished Jul 15 06:31:55 PM PDT 24
Peak memory 250280 kb
Host smart-3e34bc84-bf30-4d17-930b-b640b5a61778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510860934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1510860934
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.391159819
Short name T308
Test name
Test status
Simulation time 13261187 ps
CPU time 1.01 seconds
Started Jul 15 06:31:47 PM PDT 24
Finished Jul 15 06:31:49 PM PDT 24
Peak memory 211752 kb
Host smart-b4cc1bf7-1267-4cc5-9b01-360debc2bc40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391159819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.391159819
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2923898333
Short name T568
Test name
Test status
Simulation time 17099854 ps
CPU time 0.9 seconds
Started Jul 15 06:31:52 PM PDT 24
Finished Jul 15 06:31:53 PM PDT 24
Peak memory 208816 kb
Host smart-09f5facc-5f2e-4a9c-b7f0-98255a289559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923898333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2923898333
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3038745092
Short name T516
Test name
Test status
Simulation time 482729123 ps
CPU time 14.33 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:32:06 PM PDT 24
Peak memory 225984 kb
Host smart-3e5befd2-966c-49e1-b3dd-44264d788b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038745092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3038745092
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4070793073
Short name T9
Test name
Test status
Simulation time 1555087063 ps
CPU time 5.47 seconds
Started Jul 15 06:31:52 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 217280 kb
Host smart-85384d75-b232-4c4d-ae8a-caa09198356f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070793073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4070793073
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2909517232
Short name T781
Test name
Test status
Simulation time 68367085 ps
CPU time 3.54 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:31:54 PM PDT 24
Peak memory 218076 kb
Host smart-d3f76229-7f69-4b29-a466-c3187fb021bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909517232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2909517232
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4006578116
Short name T840
Test name
Test status
Simulation time 1602475179 ps
CPU time 17.66 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 225964 kb
Host smart-dbec54a8-ae11-49f4-b4c8-5e9c4368923d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006578116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4006578116
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1761942276
Short name T482
Test name
Test status
Simulation time 300727687 ps
CPU time 12.67 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 225984 kb
Host smart-8909844a-086a-4026-ac3d-477b708ab33d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761942276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1761942276
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4199748212
Short name T609
Test name
Test status
Simulation time 1207069388 ps
CPU time 12.92 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 218176 kb
Host smart-67bcfcff-1e4f-42bb-8adb-6611dcb0fb33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199748212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4199748212
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3145353552
Short name T76
Test name
Test status
Simulation time 58713785 ps
CPU time 1.7 seconds
Started Jul 15 06:31:47 PM PDT 24
Finished Jul 15 06:31:49 PM PDT 24
Peak memory 213928 kb
Host smart-d77674f6-e36e-4be8-9777-2bd0921f921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145353552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3145353552
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.395783412
Short name T830
Test name
Test status
Simulation time 5023595111 ps
CPU time 32.26 seconds
Started Jul 15 06:31:43 PM PDT 24
Finished Jul 15 06:32:17 PM PDT 24
Peak memory 250996 kb
Host smart-1cd4a9fb-6ccf-4028-abb9-24d6130f9b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395783412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.395783412
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1026819959
Short name T554
Test name
Test status
Simulation time 59347454 ps
CPU time 6.39 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 246908 kb
Host smart-3c893c81-4409-400b-99ea-3da7851af930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026819959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1026819959
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1450881468
Short name T791
Test name
Test status
Simulation time 1757233486 ps
CPU time 78.04 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:33:10 PM PDT 24
Peak memory 250900 kb
Host smart-e798a069-8c43-43a8-bc0c-5753a659d48e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450881468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1450881468
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3405426408
Short name T675
Test name
Test status
Simulation time 12717716 ps
CPU time 0.9 seconds
Started Jul 15 06:31:44 PM PDT 24
Finished Jul 15 06:31:46 PM PDT 24
Peak memory 211908 kb
Host smart-aad2e754-5998-4a08-b9ec-1a1fee99aacf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405426408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3405426408
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1587364372
Short name T285
Test name
Test status
Simulation time 16171403 ps
CPU time 1.12 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:31:53 PM PDT 24
Peak memory 208964 kb
Host smart-592c5caa-2b13-434f-857c-7c7f75422666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587364372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1587364372
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.747484480
Short name T576
Test name
Test status
Simulation time 753567802 ps
CPU time 12.65 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:32:04 PM PDT 24
Peak memory 218104 kb
Host smart-577272c7-daea-48c9-b2c5-f63650fe5655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747484480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.747484480
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3986464257
Short name T415
Test name
Test status
Simulation time 973223057 ps
CPU time 6.62 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:31:57 PM PDT 24
Peak memory 217160 kb
Host smart-077bf89f-97c6-460b-9168-b64e9bc5de53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986464257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3986464257
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.255832297
Short name T342
Test name
Test status
Simulation time 41254000 ps
CPU time 2.17 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:31:54 PM PDT 24
Peak memory 218144 kb
Host smart-de281b8a-57b3-441d-a049-ced4aa0276f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255832297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.255832297
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3844458741
Short name T814
Test name
Test status
Simulation time 385792843 ps
CPU time 16.42 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:32:09 PM PDT 24
Peak memory 218816 kb
Host smart-563d012c-cf0e-438f-85c0-357e77dcc954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844458741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3844458741
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.300679575
Short name T737
Test name
Test status
Simulation time 452053520 ps
CPU time 13.09 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:32:04 PM PDT 24
Peak memory 225924 kb
Host smart-2a676053-39a1-42a4-91df-06ff8b76e8af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300679575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.300679575
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2479569476
Short name T309
Test name
Test status
Simulation time 171014450 ps
CPU time 7.38 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:31:59 PM PDT 24
Peak memory 218164 kb
Host smart-eb639489-5372-4908-a76c-a278e9fe2bb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479569476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2479569476
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1306467207
Short name T623
Test name
Test status
Simulation time 959133739 ps
CPU time 16.16 seconds
Started Jul 15 06:31:51 PM PDT 24
Finished Jul 15 06:32:08 PM PDT 24
Peak memory 225976 kb
Host smart-a2850651-3fb4-4be2-939f-0aa25987f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306467207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1306467207
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3861514459
Short name T214
Test name
Test status
Simulation time 398893345 ps
CPU time 6.14 seconds
Started Jul 15 06:31:53 PM PDT 24
Finished Jul 15 06:32:00 PM PDT 24
Peak memory 217800 kb
Host smart-5bec3965-6574-4dff-a268-c112330cf06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861514459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3861514459
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.269796536
Short name T513
Test name
Test status
Simulation time 3068298671 ps
CPU time 23.74 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 250928 kb
Host smart-f25079f5-72c0-485d-b7f2-85092b39d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269796536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.269796536
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.416483546
Short name T740
Test name
Test status
Simulation time 81822344 ps
CPU time 7.83 seconds
Started Jul 15 06:31:49 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 250516 kb
Host smart-ca94d6ee-6f4c-44dd-8e16-604369aab564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416483546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.416483546
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1065613696
Short name T130
Test name
Test status
Simulation time 23834626790 ps
CPU time 376.15 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:38:08 PM PDT 24
Peak memory 283744 kb
Host smart-eb29117d-5dcd-4945-9726-31c8528775b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065613696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1065613696
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.684866462
Short name T297
Test name
Test status
Simulation time 13703457 ps
CPU time 1.01 seconds
Started Jul 15 06:31:50 PM PDT 24
Finished Jul 15 06:31:51 PM PDT 24
Peak memory 211740 kb
Host smart-ec92cc37-24bd-4f8d-b51b-f4f1e506d584
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684866462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.684866462
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.4013751844
Short name T754
Test name
Test status
Simulation time 14898622 ps
CPU time 1.03 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:31:59 PM PDT 24
Peak memory 208852 kb
Host smart-e298e002-2940-4aaf-891f-069449d950ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013751844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4013751844
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.574576623
Short name T267
Test name
Test status
Simulation time 1738085367 ps
CPU time 15.42 seconds
Started Jul 15 06:31:59 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 218052 kb
Host smart-3242c65f-dcf3-45e9-9f84-dcad853e5240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574576623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.574576623
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1559570137
Short name T38
Test name
Test status
Simulation time 603814900 ps
CPU time 6.98 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 217260 kb
Host smart-88603b60-6124-44ba-91c4-7ce4b8a70fc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559570137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1559570137
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.57562419
Short name T120
Test name
Test status
Simulation time 636171864 ps
CPU time 2.74 seconds
Started Jul 15 06:31:55 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 218196 kb
Host smart-5ea3c10c-f032-4763-b9c3-f4edf5bb1686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57562419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.57562419
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.128952535
Short name T462
Test name
Test status
Simulation time 1334314532 ps
CPU time 15.36 seconds
Started Jul 15 06:32:04 PM PDT 24
Finished Jul 15 06:32:21 PM PDT 24
Peak memory 225860 kb
Host smart-1034e456-6fb9-4689-9096-295f244d1e15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128952535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.128952535
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4041158602
Short name T392
Test name
Test status
Simulation time 384706879 ps
CPU time 8.71 seconds
Started Jul 15 06:31:56 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 225992 kb
Host smart-9dbee8f9-c807-4135-b02a-2b99c6fb9d7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041158602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
4041158602
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3285400530
Short name T593
Test name
Test status
Simulation time 1178586290 ps
CPU time 12.92 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:16 PM PDT 24
Peak memory 225228 kb
Host smart-47a3ae06-9e43-40ed-80a9-591133e507b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285400530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3285400530
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2372424544
Short name T271
Test name
Test status
Simulation time 65972322 ps
CPU time 2.11 seconds
Started Jul 15 06:31:48 PM PDT 24
Finished Jul 15 06:31:51 PM PDT 24
Peak memory 217632 kb
Host smart-b163df22-9286-40cd-a5a6-c25fed6da07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372424544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2372424544
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1751912066
Short name T594
Test name
Test status
Simulation time 212377770 ps
CPU time 20.29 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:26 PM PDT 24
Peak memory 250816 kb
Host smart-a89bd454-0d15-4a89-993d-0cd93109af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751912066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1751912066
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3837126595
Short name T12
Test name
Test status
Simulation time 96835529 ps
CPU time 2.81 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:32:01 PM PDT 24
Peak memory 222400 kb
Host smart-ceb4d726-9239-4249-a3c6-0d161ec0c200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837126595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3837126595
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2594780358
Short name T221
Test name
Test status
Simulation time 9227051761 ps
CPU time 186.8 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:35:04 PM PDT 24
Peak memory 251672 kb
Host smart-6c1e96b7-f288-42fd-b8df-e7d229c78c44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594780358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2594780358
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3907376932
Short name T186
Test name
Test status
Simulation time 97825951402 ps
CPU time 472.78 seconds
Started Jul 15 06:31:58 PM PDT 24
Finished Jul 15 06:39:52 PM PDT 24
Peak memory 290484 kb
Host smart-fe91f990-e417-4c49-a1d1-b9b1bccaf551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3907376932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3907376932
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1758849506
Short name T22
Test name
Test status
Simulation time 19329555 ps
CPU time 0.94 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:31:59 PM PDT 24
Peak memory 212932 kb
Host smart-c3c03fec-20c2-499a-b582-0b48052320c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758849506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1758849506
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1142450297
Short name T539
Test name
Test status
Simulation time 441312553 ps
CPU time 1.31 seconds
Started Jul 15 06:31:56 PM PDT 24
Finished Jul 15 06:31:58 PM PDT 24
Peak memory 208952 kb
Host smart-4490c77e-9262-4dae-87e8-9b00b98c7af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142450297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1142450297
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.261222465
Short name T209
Test name
Test status
Simulation time 310577622 ps
CPU time 9.52 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:13 PM PDT 24
Peak memory 225992 kb
Host smart-266152d8-6af1-4980-a086-530f7eb38500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261222465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.261222465
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3651523907
Short name T540
Test name
Test status
Simulation time 288667940 ps
CPU time 4 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:08 PM PDT 24
Peak memory 217032 kb
Host smart-b044f8dc-77d6-4884-9e84-64290932f947
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651523907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3651523907
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1465724264
Short name T619
Test name
Test status
Simulation time 298370956 ps
CPU time 3.96 seconds
Started Jul 15 06:31:56 PM PDT 24
Finished Jul 15 06:32:00 PM PDT 24
Peak memory 218156 kb
Host smart-399212dd-71d1-4029-80e0-17ba065e7df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465724264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1465724264
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1319894840
Short name T743
Test name
Test status
Simulation time 1287778266 ps
CPU time 17.8 seconds
Started Jul 15 06:31:55 PM PDT 24
Finished Jul 15 06:32:14 PM PDT 24
Peak memory 219428 kb
Host smart-bb0d9c9d-1f49-4f59-8307-aa450c993769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319894840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1319894840
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.76530601
Short name T818
Test name
Test status
Simulation time 328973414 ps
CPU time 9.53 seconds
Started Jul 15 06:31:56 PM PDT 24
Finished Jul 15 06:32:07 PM PDT 24
Peak memory 225936 kb
Host smart-14610017-3a11-4bfd-a7df-1e3b0ea80f64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76530601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_dig
est.76530601
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3075399119
Short name T340
Test name
Test status
Simulation time 309543883 ps
CPU time 11.73 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 218140 kb
Host smart-78e32ef4-595b-4237-8686-b246cf684aa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075399119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3075399119
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3004065476
Short name T346
Test name
Test status
Simulation time 969000074 ps
CPU time 8.75 seconds
Started Jul 15 06:32:04 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 224948 kb
Host smart-7305a806-4e36-4a59-9304-1c6163f08d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004065476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3004065476
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2460911823
Short name T95
Test name
Test status
Simulation time 951414808 ps
CPU time 3.21 seconds
Started Jul 15 06:31:56 PM PDT 24
Finished Jul 15 06:32:00 PM PDT 24
Peak memory 214728 kb
Host smart-2887b97f-cab4-4794-be9c-75e35dfb7993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460911823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2460911823
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1434664895
Short name T586
Test name
Test status
Simulation time 566943848 ps
CPU time 20.88 seconds
Started Jul 15 06:31:57 PM PDT 24
Finished Jul 15 06:32:19 PM PDT 24
Peak memory 250820 kb
Host smart-cc09b489-0c74-4499-889c-d65adbd3cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434664895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1434664895
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1914353685
Short name T370
Test name
Test status
Simulation time 3338016284 ps
CPU time 115.99 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:33:59 PM PDT 24
Peak memory 250884 kb
Host smart-8d35e2d8-b797-4e53-a135-82cf9703bd01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914353685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1914353685
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.385584004
Short name T590
Test name
Test status
Simulation time 86720316 ps
CPU time 0.94 seconds
Started Jul 15 06:32:04 PM PDT 24
Finished Jul 15 06:32:07 PM PDT 24
Peak memory 211840 kb
Host smart-c2b8567e-ab01-41bc-8671-3a883243c1a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385584004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.385584004
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2330122878
Short name T301
Test name
Test status
Simulation time 40152365 ps
CPU time 0.97 seconds
Started Jul 15 06:32:04 PM PDT 24
Finished Jul 15 06:32:07 PM PDT 24
Peak memory 208924 kb
Host smart-505842d3-fa8b-457d-b812-c59c8f167560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330122878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2330122878
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1705804240
Short name T216
Test name
Test status
Simulation time 3802916696 ps
CPU time 21.08 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:24 PM PDT 24
Peak memory 218888 kb
Host smart-8a0fe538-e3ed-465f-a31f-d5fe913140b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705804240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1705804240
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.728830663
Short name T11
Test name
Test status
Simulation time 177293578 ps
CPU time 5.02 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 217128 kb
Host smart-15debe9e-f2f3-4897-b788-fc855617938c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728830663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.728830663
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3440881957
Short name T710
Test name
Test status
Simulation time 18284868 ps
CPU time 1.84 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:06 PM PDT 24
Peak memory 221836 kb
Host smart-b7b02c72-97ee-4c12-8d03-a4648434abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440881957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3440881957
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3103754259
Short name T178
Test name
Test status
Simulation time 833195365 ps
CPU time 13.49 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:18 PM PDT 24
Peak memory 225864 kb
Host smart-3548ed15-39a6-45b2-9d46-8911d605b78e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103754259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3103754259
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.957912993
Short name T461
Test name
Test status
Simulation time 606083770 ps
CPU time 11.95 seconds
Started Jul 15 06:32:00 PM PDT 24
Finished Jul 15 06:32:13 PM PDT 24
Peak memory 225928 kb
Host smart-c44e810e-5ac5-47cd-affc-190a53e60e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957912993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.957912993
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2643516248
Short name T736
Test name
Test status
Simulation time 357525371 ps
CPU time 14.08 seconds
Started Jul 15 06:32:00 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 218152 kb
Host smart-8fdee599-d74d-4b28-9433-8270b35cbe43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643516248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2643516248
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.674008571
Short name T463
Test name
Test status
Simulation time 743038897 ps
CPU time 17.11 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:20 PM PDT 24
Peak memory 225964 kb
Host smart-ab30bf07-156f-49b5-904a-fd398d479db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674008571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.674008571
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.628092091
Short name T69
Test name
Test status
Simulation time 117681642 ps
CPU time 3.92 seconds
Started Jul 15 06:32:09 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 217644 kb
Host smart-7d5b0b3c-43e7-49b5-8276-cbc468200507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628092091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.628092091
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3019911907
Short name T358
Test name
Test status
Simulation time 778714988 ps
CPU time 26.75 seconds
Started Jul 15 06:32:01 PM PDT 24
Finished Jul 15 06:32:29 PM PDT 24
Peak memory 250908 kb
Host smart-1bba4024-1f86-46b2-ae44-091163e94e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019911907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3019911907
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3900979361
Short name T685
Test name
Test status
Simulation time 385897306 ps
CPU time 4.21 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:09 PM PDT 24
Peak memory 218148 kb
Host smart-67fd6f22-54bf-4088-b61c-ef0c089ae46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900979361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3900979361
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1376682789
Short name T832
Test name
Test status
Simulation time 15285689288 ps
CPU time 94.88 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:33:37 PM PDT 24
Peak memory 268104 kb
Host smart-d3329593-6e99-4955-8087-7ae443d852df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376682789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1376682789
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2041712009
Short name T51
Test name
Test status
Simulation time 296476532151 ps
CPU time 317.87 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:37:21 PM PDT 24
Peak memory 267488 kb
Host smart-2d85b680-3d54-4159-8b02-28e0b764ab16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2041712009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2041712009
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4073083067
Short name T246
Test name
Test status
Simulation time 15852126 ps
CPU time 1.09 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:04 PM PDT 24
Peak memory 212960 kb
Host smart-163d14b5-8afb-4e6c-b32f-9ceb195690a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073083067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4073083067
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3776021491
Short name T827
Test name
Test status
Simulation time 17913741 ps
CPU time 0.96 seconds
Started Jul 15 06:29:57 PM PDT 24
Finished Jul 15 06:29:59 PM PDT 24
Peak memory 208900 kb
Host smart-7f591654-895b-4b63-afe0-781ff63bddff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776021491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3776021491
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2710709076
Short name T193
Test name
Test status
Simulation time 1402798522 ps
CPU time 16.02 seconds
Started Jul 15 06:29:48 PM PDT 24
Finished Jul 15 06:30:05 PM PDT 24
Peak memory 218132 kb
Host smart-21fbbe7b-ec53-4ec7-87fe-eb93612798e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710709076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2710709076
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.473136350
Short name T8
Test name
Test status
Simulation time 94457416 ps
CPU time 3.05 seconds
Started Jul 15 06:29:50 PM PDT 24
Finished Jul 15 06:29:54 PM PDT 24
Peak memory 217172 kb
Host smart-0ae8cbd8-93de-403f-9f4c-b3803840a79b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473136350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.473136350
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1196044111
Short name T272
Test name
Test status
Simulation time 6478971348 ps
CPU time 41.38 seconds
Started Jul 15 06:29:47 PM PDT 24
Finished Jul 15 06:30:28 PM PDT 24
Peak memory 218324 kb
Host smart-5aa718a1-72cb-4fe6-9827-91c22d3c5c51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196044111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1196044111
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2953804924
Short name T636
Test name
Test status
Simulation time 1091579268 ps
CPU time 5.25 seconds
Started Jul 15 06:29:49 PM PDT 24
Finished Jul 15 06:29:54 PM PDT 24
Peak memory 217684 kb
Host smart-f34a275f-02f3-44c7-869c-b257778b4e28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953804924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
953804924
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2839908121
Short name T715
Test name
Test status
Simulation time 295534461 ps
CPU time 5.74 seconds
Started Jul 15 06:29:49 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 218160 kb
Host smart-54056a5e-808a-4863-93b7-2d8b08b0f085
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839908121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2839908121
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3022301894
Short name T813
Test name
Test status
Simulation time 1829290571 ps
CPU time 26.34 seconds
Started Jul 15 06:29:48 PM PDT 24
Finished Jul 15 06:30:15 PM PDT 24
Peak memory 217652 kb
Host smart-5896c99f-018f-4c90-9278-b61c449a3e64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022301894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3022301894
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1308883125
Short name T182
Test name
Test status
Simulation time 401101883 ps
CPU time 6.42 seconds
Started Jul 15 06:29:48 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 217660 kb
Host smart-75ae0a13-cc01-4c9c-a6c1-6c501c218508
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308883125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1308883125
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2231399761
Short name T672
Test name
Test status
Simulation time 4065803925 ps
CPU time 68.96 seconds
Started Jul 15 06:29:49 PM PDT 24
Finished Jul 15 06:30:58 PM PDT 24
Peak memory 279764 kb
Host smart-148f3f64-92dc-4205-9ec5-c726dab6c9f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231399761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2231399761
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2420068478
Short name T770
Test name
Test status
Simulation time 4354527204 ps
CPU time 20.72 seconds
Started Jul 15 06:29:54 PM PDT 24
Finished Jul 15 06:30:15 PM PDT 24
Peak memory 247496 kb
Host smart-ebf6d16f-b327-49f6-a437-5e1ad0df512a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420068478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2420068478
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1359402756
Short name T257
Test name
Test status
Simulation time 397568608 ps
CPU time 3.16 seconds
Started Jul 15 06:29:53 PM PDT 24
Finished Jul 15 06:29:57 PM PDT 24
Peak memory 218172 kb
Host smart-7f395f24-5662-4b8e-8d14-c0235663b792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359402756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1359402756
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1159431821
Short name T831
Test name
Test status
Simulation time 1250731468 ps
CPU time 7.63 seconds
Started Jul 15 06:29:53 PM PDT 24
Finished Jul 15 06:30:01 PM PDT 24
Peak memory 214112 kb
Host smart-903aefe5-e527-4978-8df1-4f5763cb12a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159431821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1159431821
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.68197918
Short name T118
Test name
Test status
Simulation time 724638215 ps
CPU time 37.61 seconds
Started Jul 15 06:29:58 PM PDT 24
Finished Jul 15 06:30:37 PM PDT 24
Peak memory 270104 kb
Host smart-e7fb9ba1-4888-4536-8dbb-749fdfe4192a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68197918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.68197918
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1087762102
Short name T551
Test name
Test status
Simulation time 2058311036 ps
CPU time 21.23 seconds
Started Jul 15 06:29:49 PM PDT 24
Finished Jul 15 06:30:11 PM PDT 24
Peak memory 225844 kb
Host smart-1580a9cb-9e3a-4c50-808f-b613bfd8746e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087762102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1087762102
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1351196572
Short name T109
Test name
Test status
Simulation time 1121257645 ps
CPU time 14.61 seconds
Started Jul 15 06:29:49 PM PDT 24
Finished Jul 15 06:30:04 PM PDT 24
Peak memory 225956 kb
Host smart-2feb6036-8d98-4959-b0fe-f3bff4943814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351196572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1351196572
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.570671997
Short name T812
Test name
Test status
Simulation time 239880380 ps
CPU time 7.56 seconds
Started Jul 15 06:29:48 PM PDT 24
Finished Jul 15 06:29:56 PM PDT 24
Peak memory 218172 kb
Host smart-f9146b01-d7af-40de-9592-cef8a2cc9783
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570671997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.570671997
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1378879708
Short name T756
Test name
Test status
Simulation time 5053800153 ps
CPU time 6.24 seconds
Started Jul 15 06:29:49 PM PDT 24
Finished Jul 15 06:29:56 PM PDT 24
Peak memory 224948 kb
Host smart-9865044a-4daa-44f0-a1b8-ad8d20ddcb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378879708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1378879708
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.424173486
Short name T94
Test name
Test status
Simulation time 110812457 ps
CPU time 3.26 seconds
Started Jul 15 06:29:44 PM PDT 24
Finished Jul 15 06:29:48 PM PDT 24
Peak memory 217664 kb
Host smart-3e86c689-83dc-44c2-a48d-1114bdea5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424173486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.424173486
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4066630434
Short name T98
Test name
Test status
Simulation time 597012485 ps
CPU time 20.16 seconds
Started Jul 15 06:29:52 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 250928 kb
Host smart-24a65e38-c006-4b31-a211-f0e6f1aea7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066630434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4066630434
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1452509126
Short name T385
Test name
Test status
Simulation time 917970485 ps
CPU time 3.05 seconds
Started Jul 15 06:29:53 PM PDT 24
Finished Jul 15 06:29:57 PM PDT 24
Peak memory 222524 kb
Host smart-215f432b-c2e4-4b99-93e5-21d6f4f30384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452509126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1452509126
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2187168915
Short name T625
Test name
Test status
Simulation time 1829257741 ps
CPU time 93.68 seconds
Started Jul 15 06:29:55 PM PDT 24
Finished Jul 15 06:31:29 PM PDT 24
Peak memory 274352 kb
Host smart-d11c17e9-117f-4f39-aa9f-11bb29ae1bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187168915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2187168915
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1142858275
Short name T289
Test name
Test status
Simulation time 74680405 ps
CPU time 0.99 seconds
Started Jul 15 06:29:47 PM PDT 24
Finished Jul 15 06:29:49 PM PDT 24
Peak memory 211848 kb
Host smart-f2663def-376c-405b-b504-70f2fbcabcc2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142858275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1142858275
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3601059559
Short name T104
Test name
Test status
Simulation time 19881865 ps
CPU time 1.27 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:11 PM PDT 24
Peak memory 208972 kb
Host smart-a5bce249-0751-491d-8012-48fa7156ae94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601059559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3601059559
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2275219774
Short name T121
Test name
Test status
Simulation time 1328892028 ps
CPU time 15.7 seconds
Started Jul 15 06:32:04 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 225972 kb
Host smart-d545cedd-aa69-4de0-bc50-f4e558679004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275219774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2275219774
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3793633427
Short name T494
Test name
Test status
Simulation time 1301155453 ps
CPU time 3.63 seconds
Started Jul 15 06:32:01 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 217156 kb
Host smart-5d8744a5-f201-45a3-8890-0d6ed112aa5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793633427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3793633427
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.632303440
Short name T276
Test name
Test status
Simulation time 71950771 ps
CPU time 2.47 seconds
Started Jul 15 06:32:04 PM PDT 24
Finished Jul 15 06:32:08 PM PDT 24
Peak memory 222120 kb
Host smart-ff7d9a00-64d9-469a-9c44-67d30e0c75a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632303440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.632303440
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1708810887
Short name T668
Test name
Test status
Simulation time 844781823 ps
CPU time 22.05 seconds
Started Jul 15 06:32:10 PM PDT 24
Finished Jul 15 06:32:33 PM PDT 24
Peak memory 225968 kb
Host smart-a9eca5b2-ff2e-4a0c-9c47-1c678dc49fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708810887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1708810887
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2006493945
Short name T260
Test name
Test status
Simulation time 1200540119 ps
CPU time 12 seconds
Started Jul 15 06:32:00 PM PDT 24
Finished Jul 15 06:32:12 PM PDT 24
Peak memory 225960 kb
Host smart-127c0027-1f6c-4cf5-a7b0-8d237c82644b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006493945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2006493945
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3643284088
Short name T405
Test name
Test status
Simulation time 419150332 ps
CPU time 8.64 seconds
Started Jul 15 06:32:01 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 225960 kb
Host smart-14e93302-e012-44ae-9763-47ff19dba000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643284088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3643284088
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.108424364
Short name T434
Test name
Test status
Simulation time 396121020 ps
CPU time 11.9 seconds
Started Jul 15 06:32:09 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 218376 kb
Host smart-9699098f-093f-45f8-9d03-90345ea72125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108424364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.108424364
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.856174123
Short name T742
Test name
Test status
Simulation time 40966045 ps
CPU time 2.37 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:06 PM PDT 24
Peak memory 214452 kb
Host smart-70b11cd5-4235-4fba-9bec-0beda5e6e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856174123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.856174123
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3531814956
Short name T724
Test name
Test status
Simulation time 718869133 ps
CPU time 17.26 seconds
Started Jul 15 06:32:01 PM PDT 24
Finished Jul 15 06:32:19 PM PDT 24
Peak memory 250928 kb
Host smart-cd4f188e-1b5e-4a90-999b-b4a172d38417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531814956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3531814956
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1764253057
Short name T206
Test name
Test status
Simulation time 114814377 ps
CPU time 7.79 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:12 PM PDT 24
Peak memory 250924 kb
Host smart-2f299178-baf2-49d3-9c89-19e790022f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764253057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1764253057
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2878364975
Short name T614
Test name
Test status
Simulation time 25322926025 ps
CPU time 420.68 seconds
Started Jul 15 06:32:00 PM PDT 24
Finished Jul 15 06:39:02 PM PDT 24
Peak memory 250932 kb
Host smart-5cf2a2f5-d9aa-4311-8638-c8650351d67b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878364975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2878364975
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.877375244
Short name T275
Test name
Test status
Simulation time 25325887 ps
CPU time 1.03 seconds
Started Jul 15 06:32:00 PM PDT 24
Finished Jul 15 06:32:02 PM PDT 24
Peak memory 211816 kb
Host smart-4a23b5ae-5deb-4371-bfb7-42c6ef50f0dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877375244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.877375244
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3294672178
Short name T856
Test name
Test status
Simulation time 48202475 ps
CPU time 0.97 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 208936 kb
Host smart-cf67dee4-3370-45be-9386-59f6a97afec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294672178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3294672178
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3154763706
Short name T657
Test name
Test status
Simulation time 721302524 ps
CPU time 13.12 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:18 PM PDT 24
Peak memory 218168 kb
Host smart-e0cd882b-d50d-4c12-9dc8-4f576cf8cfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154763706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3154763706
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.940263880
Short name T471
Test name
Test status
Simulation time 333200732 ps
CPU time 9.39 seconds
Started Jul 15 06:32:06 PM PDT 24
Finished Jul 15 06:32:17 PM PDT 24
Peak memory 217424 kb
Host smart-1b074a74-00ed-4fd7-8eb8-e99d7693e02e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940263880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.940263880
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2387994792
Short name T678
Test name
Test status
Simulation time 243358833 ps
CPU time 4.23 seconds
Started Jul 15 06:32:10 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 222632 kb
Host smart-f7bbedfb-d22c-4355-a1e2-4305930000df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387994792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2387994792
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1698155086
Short name T659
Test name
Test status
Simulation time 412603214 ps
CPU time 14.35 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:24 PM PDT 24
Peak memory 218920 kb
Host smart-65fb5256-021c-46c2-830f-f5a6ebc209de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698155086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1698155086
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1855060650
Short name T577
Test name
Test status
Simulation time 412225093 ps
CPU time 10.49 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:19 PM PDT 24
Peak memory 225924 kb
Host smart-6f16f6d5-f178-4b56-a217-00026381f39d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855060650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1855060650
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4081300983
Short name T771
Test name
Test status
Simulation time 433257792 ps
CPU time 14.42 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:24 PM PDT 24
Peak memory 218132 kb
Host smart-7404e606-25aa-48c6-8e27-27b373547c38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081300983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4081300983
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.110169520
Short name T823
Test name
Test status
Simulation time 1047023173 ps
CPU time 13.86 seconds
Started Jul 15 06:32:11 PM PDT 24
Finished Jul 15 06:32:25 PM PDT 24
Peak memory 218216 kb
Host smart-2a1f2c7f-9d1d-4d57-96f3-550288ab9cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110169520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.110169520
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2868609662
Short name T587
Test name
Test status
Simulation time 37703464 ps
CPU time 1.42 seconds
Started Jul 15 06:32:02 PM PDT 24
Finished Jul 15 06:32:05 PM PDT 24
Peak memory 217756 kb
Host smart-72448c27-e57d-4a4d-b0cc-2b8982688600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868609662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2868609662
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3306165645
Short name T290
Test name
Test status
Simulation time 1146157275 ps
CPU time 18.66 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:23 PM PDT 24
Peak memory 250912 kb
Host smart-b2405640-9964-4e33-8470-621886d3cda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306165645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3306165645
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.179933932
Short name T556
Test name
Test status
Simulation time 133265144 ps
CPU time 8.16 seconds
Started Jul 15 06:32:03 PM PDT 24
Finished Jul 15 06:32:12 PM PDT 24
Peak memory 251012 kb
Host smart-263c8114-7bfb-4b38-8ecf-fb9e2fe172b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179933932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.179933932
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1429781058
Short name T809
Test name
Test status
Simulation time 9039352516 ps
CPU time 69.48 seconds
Started Jul 15 06:32:10 PM PDT 24
Finished Jul 15 06:33:21 PM PDT 24
Peak memory 225988 kb
Host smart-ec74cd52-e7a2-42fd-a376-77bacae211a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429781058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1429781058
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1701901532
Short name T134
Test name
Test status
Simulation time 62500898526 ps
CPU time 547.38 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:41:18 PM PDT 24
Peak memory 296248 kb
Host smart-d731e381-2b41-4439-9f52-780013630e7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1701901532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1701901532
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4168834459
Short name T201
Test name
Test status
Simulation time 25639525 ps
CPU time 1.09 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:11 PM PDT 24
Peak memory 212004 kb
Host smart-5ff97474-673b-481c-ac57-04adee9adf37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168834459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4168834459
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3126091095
Short name T204
Test name
Test status
Simulation time 51151472 ps
CPU time 0.9 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:11 PM PDT 24
Peak memory 208712 kb
Host smart-69f0510e-3d76-45e2-859b-9d842a87d1e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126091095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3126091095
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.831946944
Short name T63
Test name
Test status
Simulation time 527897507 ps
CPU time 8.52 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:17 PM PDT 24
Peak memory 218188 kb
Host smart-5b07103f-0234-426f-8523-de16e9ffc1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831946944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.831946944
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1390080087
Short name T412
Test name
Test status
Simulation time 799610721 ps
CPU time 4.18 seconds
Started Jul 15 06:32:09 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 216968 kb
Host smart-2a0b5b3c-033f-45c1-a489-2a7c433f2d82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390080087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1390080087
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.4142224931
Short name T350
Test name
Test status
Simulation time 65430849 ps
CPU time 3.36 seconds
Started Jul 15 06:32:07 PM PDT 24
Finished Jul 15 06:32:12 PM PDT 24
Peak memory 218200 kb
Host smart-4d7342e7-cc6d-4f36-9c5f-c782094b49f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142224931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.4142224931
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4238001381
Short name T549
Test name
Test status
Simulation time 4254443002 ps
CPU time 18.15 seconds
Started Jul 15 06:32:12 PM PDT 24
Finished Jul 15 06:32:30 PM PDT 24
Peak memory 220052 kb
Host smart-e8f3b276-ed39-4a77-8123-aa402806ca5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238001381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4238001381
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.328827681
Short name T510
Test name
Test status
Simulation time 17548654306 ps
CPU time 19.79 seconds
Started Jul 15 06:32:07 PM PDT 24
Finished Jul 15 06:32:28 PM PDT 24
Peak memory 226072 kb
Host smart-9ca72c4e-825b-4d77-a0ad-78e74ea42a18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328827681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.328827681
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1054988158
Short name T747
Test name
Test status
Simulation time 542843849 ps
CPU time 11.73 seconds
Started Jul 15 06:32:07 PM PDT 24
Finished Jul 15 06:32:20 PM PDT 24
Peak memory 218156 kb
Host smart-5cb5eb04-0b94-429f-9d35-235099a535a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054988158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1054988158
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3938288248
Short name T807
Test name
Test status
Simulation time 2897394878 ps
CPU time 11.41 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:21 PM PDT 24
Peak memory 225976 kb
Host smart-afe84fa9-1fb1-4fcb-85a5-a76f12a5fc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938288248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3938288248
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.290637591
Short name T738
Test name
Test status
Simulation time 59854655 ps
CPU time 2.43 seconds
Started Jul 15 06:32:07 PM PDT 24
Finished Jul 15 06:32:11 PM PDT 24
Peak memory 214308 kb
Host smart-ffc8f8cb-b6cb-4448-9665-c0a3954ba56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290637591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.290637591
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.339176953
Short name T348
Test name
Test status
Simulation time 652949420 ps
CPU time 26.21 seconds
Started Jul 15 06:32:09 PM PDT 24
Finished Jul 15 06:32:37 PM PDT 24
Peak memory 251068 kb
Host smart-f164472b-aef9-4c71-9953-1592bbd60149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339176953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.339176953
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1711656650
Short name T317
Test name
Test status
Simulation time 370590979 ps
CPU time 6.29 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:16 PM PDT 24
Peak memory 245972 kb
Host smart-41c7f6ab-add7-4af4-a314-2fc01ff41362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711656650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1711656650
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.38995045
Short name T43
Test name
Test status
Simulation time 14317551762 ps
CPU time 106.11 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:33:56 PM PDT 24
Peak memory 259008 kb
Host smart-6d4bdadb-ecb9-4c8a-86dd-1b0dff55aae8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.lc_ctrl_stress_all.38995045
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1702571554
Short name T798
Test name
Test status
Simulation time 28682268 ps
CPU time 1 seconds
Started Jul 15 06:32:07 PM PDT 24
Finished Jul 15 06:32:09 PM PDT 24
Peak memory 212960 kb
Host smart-6a2de152-4957-42a7-8c04-a7719504c8c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702571554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1702571554
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.757029627
Short name T464
Test name
Test status
Simulation time 74417922 ps
CPU time 1 seconds
Started Jul 15 06:32:13 PM PDT 24
Finished Jul 15 06:32:15 PM PDT 24
Peak memory 208976 kb
Host smart-9e2ddf6d-409b-46f1-96e1-d0c4d206cc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757029627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.757029627
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3346171856
Short name T18
Test name
Test status
Simulation time 461866390 ps
CPU time 14.31 seconds
Started Jul 15 06:32:07 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 218136 kb
Host smart-6b4e2cd7-f347-4782-af54-861a7339eb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346171856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3346171856
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3180537438
Short name T653
Test name
Test status
Simulation time 630268888 ps
CPU time 2.48 seconds
Started Jul 15 06:32:06 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 217076 kb
Host smart-97226083-4d0e-4b3d-807c-55cecb7d7da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180537438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3180537438
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.4150244886
Short name T472
Test name
Test status
Simulation time 520758966 ps
CPU time 4.26 seconds
Started Jul 15 06:32:07 PM PDT 24
Finished Jul 15 06:32:13 PM PDT 24
Peak memory 218148 kb
Host smart-280a3e52-e2f8-45b5-9542-53b8378e9c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150244886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4150244886
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2396416979
Short name T853
Test name
Test status
Simulation time 1100947744 ps
CPU time 14.7 seconds
Started Jul 15 06:32:06 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 225960 kb
Host smart-04f20285-5ad4-4dde-b69b-5ecb998b6dfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396416979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2396416979
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3817728137
Short name T592
Test name
Test status
Simulation time 1861828045 ps
CPU time 9.75 seconds
Started Jul 15 06:32:08 PM PDT 24
Finished Jul 15 06:32:20 PM PDT 24
Peak memory 218120 kb
Host smart-9982653b-eb2e-4d9e-8075-1d6d09f3de9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817728137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3817728137
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2392748974
Short name T792
Test name
Test status
Simulation time 542028025 ps
CPU time 17.12 seconds
Started Jul 15 06:32:09 PM PDT 24
Finished Jul 15 06:32:28 PM PDT 24
Peak memory 218116 kb
Host smart-faeff307-9807-4870-9625-092e96c82433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392748974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2392748974
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1803911505
Short name T58
Test name
Test status
Simulation time 291225109 ps
CPU time 9.92 seconds
Started Jul 15 06:32:06 PM PDT 24
Finished Jul 15 06:32:17 PM PDT 24
Peak memory 224672 kb
Host smart-60d98d07-75b3-42a7-b104-786411447430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803911505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1803911505
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3334799923
Short name T205
Test name
Test status
Simulation time 84730379 ps
CPU time 6.38 seconds
Started Jul 15 06:32:11 PM PDT 24
Finished Jul 15 06:32:18 PM PDT 24
Peak memory 217676 kb
Host smart-5c6fc2ef-41a9-4757-b70c-93fa5c2ba3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334799923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3334799923
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3139307799
Short name T580
Test name
Test status
Simulation time 276636273 ps
CPU time 32.08 seconds
Started Jul 15 06:32:09 PM PDT 24
Finished Jul 15 06:32:43 PM PDT 24
Peak memory 250852 kb
Host smart-485fd516-0072-4e3d-a42b-2518224cefa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139307799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3139307799
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1215252399
Short name T383
Test name
Test status
Simulation time 205970861 ps
CPU time 2.46 seconds
Started Jul 15 06:32:06 PM PDT 24
Finished Jul 15 06:32:10 PM PDT 24
Peak memory 222200 kb
Host smart-4f4fd8c8-e955-493a-8db9-e5d15fba577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215252399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1215252399
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3132105891
Short name T427
Test name
Test status
Simulation time 4806380992 ps
CPU time 164.59 seconds
Started Jul 15 06:32:11 PM PDT 24
Finished Jul 15 06:34:56 PM PDT 24
Peak memory 275688 kb
Host smart-9b53a465-f34e-494b-bd58-e951a378c5a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132105891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3132105891
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1300455316
Short name T126
Test name
Test status
Simulation time 13946313572 ps
CPU time 504.89 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:40:40 PM PDT 24
Peak memory 405736 kb
Host smart-3e540d89-0c81-414a-9f89-185c35c49308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1300455316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1300455316
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1416318645
Short name T661
Test name
Test status
Simulation time 18347379 ps
CPU time 1 seconds
Started Jul 15 06:32:09 PM PDT 24
Finished Jul 15 06:32:12 PM PDT 24
Peak memory 211760 kb
Host smart-aa6de98b-6de8-47d8-b13e-d7a87ee90909
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416318645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1416318645
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1640778316
Short name T656
Test name
Test status
Simulation time 16371117 ps
CPU time 0.93 seconds
Started Jul 15 06:32:16 PM PDT 24
Finished Jul 15 06:32:17 PM PDT 24
Peak memory 208808 kb
Host smart-7d9f9ac7-bf94-4db0-9906-6cc74d33c98a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640778316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1640778316
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.884405251
Short name T775
Test name
Test status
Simulation time 1526962194 ps
CPU time 12.32 seconds
Started Jul 15 06:32:15 PM PDT 24
Finished Jul 15 06:32:28 PM PDT 24
Peak memory 218176 kb
Host smart-e51ae03c-31da-4ef8-9114-69829528fac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884405251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.884405251
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.395569368
Short name T37
Test name
Test status
Simulation time 904231487 ps
CPU time 11.84 seconds
Started Jul 15 06:32:15 PM PDT 24
Finished Jul 15 06:32:28 PM PDT 24
Peak memory 217352 kb
Host smart-83126e18-0cba-4f70-b9d5-841936589213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395569368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.395569368
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3190174668
Short name T365
Test name
Test status
Simulation time 1028110892 ps
CPU time 8.79 seconds
Started Jul 15 06:32:19 PM PDT 24
Finished Jul 15 06:32:28 PM PDT 24
Peak memory 225872 kb
Host smart-5fd3efd8-26ad-4eb7-8884-e9a5c3bda191
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190174668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3190174668
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2092987924
Short name T788
Test name
Test status
Simulation time 341682440 ps
CPU time 12.83 seconds
Started Jul 15 06:32:15 PM PDT 24
Finished Jul 15 06:32:29 PM PDT 24
Peak memory 225940 kb
Host smart-9f8c873a-098d-4c2f-883d-2a702fb89876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092987924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2092987924
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1759898538
Short name T363
Test name
Test status
Simulation time 2089102975 ps
CPU time 8.71 seconds
Started Jul 15 06:32:19 PM PDT 24
Finished Jul 15 06:32:28 PM PDT 24
Peak memory 218228 kb
Host smart-9b8ec8a0-cae5-4ded-b36b-eb5e718e6519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759898538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1759898538
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1633983432
Short name T115
Test name
Test status
Simulation time 46767341 ps
CPU time 1.87 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:32:16 PM PDT 24
Peak memory 214304 kb
Host smart-cd4d02f6-acd9-4350-b94b-0eaaf3188d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633983432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1633983432
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1751244538
Short name T548
Test name
Test status
Simulation time 1115383293 ps
CPU time 22.74 seconds
Started Jul 15 06:32:18 PM PDT 24
Finished Jul 15 06:32:41 PM PDT 24
Peak memory 250900 kb
Host smart-e7727985-1204-4674-945b-17e1e1bfa0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751244538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1751244538
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2619115054
Short name T712
Test name
Test status
Simulation time 105431986 ps
CPU time 2.67 seconds
Started Jul 15 06:32:17 PM PDT 24
Finished Jul 15 06:32:20 PM PDT 24
Peak memory 222096 kb
Host smart-e01809ea-3720-4c30-bf20-2853c6b40f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619115054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2619115054
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1066241345
Short name T861
Test name
Test status
Simulation time 1910595791 ps
CPU time 29.76 seconds
Started Jul 15 06:32:16 PM PDT 24
Finished Jul 15 06:32:46 PM PDT 24
Peak memory 225984 kb
Host smart-350b63ec-4529-46d2-ac92-e4b7eba4d0cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066241345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1066241345
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.82888345
Short name T248
Test name
Test status
Simulation time 27842100075 ps
CPU time 422.64 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:39:18 PM PDT 24
Peak memory 300372 kb
Host smart-4774d7e5-8868-4715-8aed-e3979e7a5267
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=82888345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.82888345
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1515753549
Short name T382
Test name
Test status
Simulation time 12719488 ps
CPU time 0.95 seconds
Started Jul 15 06:32:18 PM PDT 24
Finished Jul 15 06:32:19 PM PDT 24
Peak memory 211792 kb
Host smart-cb59dc01-8d07-468c-a59b-8bb56b7d661d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515753549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1515753549
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.164306565
Short name T607
Test name
Test status
Simulation time 17955705 ps
CPU time 0.97 seconds
Started Jul 15 06:32:19 PM PDT 24
Finished Jul 15 06:32:21 PM PDT 24
Peak memory 208876 kb
Host smart-96cf85f7-49fb-4bed-9f6b-0f4d6e24ae7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164306565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.164306565
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1280896793
Short name T450
Test name
Test status
Simulation time 1058631048 ps
CPU time 10.47 seconds
Started Jul 15 06:32:17 PM PDT 24
Finished Jul 15 06:32:28 PM PDT 24
Peak memory 218112 kb
Host smart-166b7abe-c476-4947-a35f-f860c85be4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280896793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1280896793
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2228326920
Short name T699
Test name
Test status
Simulation time 304688692 ps
CPU time 4.32 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:32:19 PM PDT 24
Peak memory 217000 kb
Host smart-43cf337d-1b6d-49de-bb60-69a924ea76a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228326920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2228326920
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2852363043
Short name T821
Test name
Test status
Simulation time 140382949 ps
CPU time 1.93 seconds
Started Jul 15 06:32:13 PM PDT 24
Finished Jul 15 06:32:16 PM PDT 24
Peak memory 218184 kb
Host smart-48942a6c-b10e-4ec4-be7a-5d1d7935ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852363043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2852363043
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2650930832
Short name T305
Test name
Test status
Simulation time 2820327106 ps
CPU time 15.2 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:32:30 PM PDT 24
Peak memory 226024 kb
Host smart-e4f3e814-1f9a-4407-9cbf-c00f94fded96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650930832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2650930832
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.97572016
Short name T726
Test name
Test status
Simulation time 441099112 ps
CPU time 10.22 seconds
Started Jul 15 06:32:15 PM PDT 24
Finished Jul 15 06:32:26 PM PDT 24
Peak memory 225968 kb
Host smart-0e465b3e-83a1-4d06-8952-e31a914830bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97572016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_dig
est.97572016
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.194834400
Short name T400
Test name
Test status
Simulation time 890208198 ps
CPU time 7.74 seconds
Started Jul 15 06:32:15 PM PDT 24
Finished Jul 15 06:32:24 PM PDT 24
Peak memory 218128 kb
Host smart-e836b992-5d32-4114-ad3e-9fe494710321
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194834400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.194834400
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1812082082
Short name T581
Test name
Test status
Simulation time 774233496 ps
CPU time 10.51 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:32:26 PM PDT 24
Peak memory 225936 kb
Host smart-fd93eac3-b405-4343-a6e1-61aa7d01f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812082082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1812082082
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1973310437
Short name T495
Test name
Test status
Simulation time 42283995 ps
CPU time 2.88 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:32:23 PM PDT 24
Peak memory 217640 kb
Host smart-32cc7ba4-61c1-489f-aa09-aa062bf1eb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973310437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1973310437
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3522821886
Short name T709
Test name
Test status
Simulation time 833734692 ps
CPU time 28.16 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:32:42 PM PDT 24
Peak memory 251000 kb
Host smart-472e2e68-2e7f-444f-99d1-79b8f2e6d8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522821886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3522821886
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2816312364
Short name T591
Test name
Test status
Simulation time 61865569 ps
CPU time 8.14 seconds
Started Jul 15 06:32:15 PM PDT 24
Finished Jul 15 06:32:24 PM PDT 24
Peak memory 250916 kb
Host smart-9dc49359-07f7-4529-870b-14d826e46fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816312364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2816312364
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.780653482
Short name T68
Test name
Test status
Simulation time 6628768327 ps
CPU time 155.63 seconds
Started Jul 15 06:32:17 PM PDT 24
Finished Jul 15 06:34:53 PM PDT 24
Peak memory 277000 kb
Host smart-385357b5-d7cc-4f89-89a3-aa2db1d14032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780653482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.780653482
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1445543156
Short name T247
Test name
Test status
Simulation time 93057884 ps
CPU time 0.88 seconds
Started Jul 15 06:32:14 PM PDT 24
Finished Jul 15 06:32:16 PM PDT 24
Peak memory 211812 kb
Host smart-7b19a2a7-bd41-4381-a5aa-b03d27217403
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445543156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1445543156
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2800687371
Short name T484
Test name
Test status
Simulation time 39003755 ps
CPU time 1 seconds
Started Jul 15 06:32:18 PM PDT 24
Finished Jul 15 06:32:20 PM PDT 24
Peak memory 208944 kb
Host smart-72d1d5ee-b9e6-4638-adc4-d6234beeb7e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800687371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2800687371
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1658238204
Short name T311
Test name
Test status
Simulation time 1094558156 ps
CPU time 15.47 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:37 PM PDT 24
Peak memory 218164 kb
Host smart-1108ce00-1396-4199-bd3f-714e5f529fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658238204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1658238204
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3165964697
Short name T517
Test name
Test status
Simulation time 1141871473 ps
CPU time 14.16 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:36 PM PDT 24
Peak memory 217408 kb
Host smart-85659cf3-47e2-4089-a233-30f7f95ef02f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165964697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3165964697
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3284485478
Short name T632
Test name
Test status
Simulation time 36975632 ps
CPU time 1.75 seconds
Started Jul 15 06:32:23 PM PDT 24
Finished Jul 15 06:32:25 PM PDT 24
Peak memory 218064 kb
Host smart-eb545915-7a00-4db6-807c-f715a8db83f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284485478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3284485478
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2341836497
Short name T542
Test name
Test status
Simulation time 296445586 ps
CPU time 10.19 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:32:31 PM PDT 24
Peak memory 218828 kb
Host smart-e813f68c-dd87-4fcd-a34b-7255cd52a8d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341836497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2341836497
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3759984330
Short name T176
Test name
Test status
Simulation time 445330980 ps
CPU time 9.62 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:31 PM PDT 24
Peak memory 225872 kb
Host smart-a00eeb0b-efc7-45a3-8792-5845e7d6e132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759984330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3759984330
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3762347861
Short name T557
Test name
Test status
Simulation time 955992093 ps
CPU time 13.9 seconds
Started Jul 15 06:32:19 PM PDT 24
Finished Jul 15 06:32:33 PM PDT 24
Peak memory 218168 kb
Host smart-85d433bd-e07e-4264-b1d1-02d9c068ea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762347861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3762347861
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1511677007
Short name T105
Test name
Test status
Simulation time 25461445 ps
CPU time 1.87 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:32:23 PM PDT 24
Peak memory 217660 kb
Host smart-9fd3c659-099e-45fa-b130-eb98c8a4100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511677007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1511677007
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.138735330
Short name T302
Test name
Test status
Simulation time 370349043 ps
CPU time 34.32 seconds
Started Jul 15 06:32:18 PM PDT 24
Finished Jul 15 06:32:52 PM PDT 24
Peak memory 246880 kb
Host smart-3b85f1d6-108e-4c60-9bce-77a279a312b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138735330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.138735330
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.507718147
Short name T195
Test name
Test status
Simulation time 240398981 ps
CPU time 6.82 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:29 PM PDT 24
Peak memory 250476 kb
Host smart-e4c39213-7437-4b78-97e6-5ba100b3fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507718147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.507718147
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.180872571
Short name T708
Test name
Test status
Simulation time 135902118388 ps
CPU time 803.32 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:45:44 PM PDT 24
Peak memory 277504 kb
Host smart-fa735e1f-f382-43d3-bbce-d60d5c5f2f9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180872571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.180872571
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.20308778
Short name T465
Test name
Test status
Simulation time 15830465 ps
CPU time 1.05 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:23 PM PDT 24
Peak memory 217732 kb
Host smart-72667d37-e4ff-4eca-b710-122b738aa514
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20308778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctr
l_volatile_unlock_smoke.20308778
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.505426305
Short name T331
Test name
Test status
Simulation time 66357094 ps
CPU time 0.95 seconds
Started Jul 15 06:32:19 PM PDT 24
Finished Jul 15 06:32:21 PM PDT 24
Peak memory 208872 kb
Host smart-7f1d7632-f9dc-4740-84d4-a916618acc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505426305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.505426305
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.367469064
Short name T508
Test name
Test status
Simulation time 771935590 ps
CPU time 16.97 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:39 PM PDT 24
Peak memory 218160 kb
Host smart-d74f8f3a-4ab3-40c1-830e-b78f44f5389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367469064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.367469064
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3642035982
Short name T523
Test name
Test status
Simulation time 129106742 ps
CPU time 3.81 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:32:24 PM PDT 24
Peak memory 217100 kb
Host smart-1aa1b86a-507f-4890-a7f3-17673051d17e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642035982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3642035982
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.239462592
Short name T729
Test name
Test status
Simulation time 353213950 ps
CPU time 3.33 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:25 PM PDT 24
Peak memory 222212 kb
Host smart-42d9fa68-b984-487e-a3a7-b29643a6e585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239462592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.239462592
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1573462976
Short name T336
Test name
Test status
Simulation time 1345669047 ps
CPU time 9.13 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:32:30 PM PDT 24
Peak memory 225872 kb
Host smart-155e4ca7-8ebe-4863-bedd-8f1018a0379d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573462976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1573462976
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.507454833
Short name T762
Test name
Test status
Simulation time 1969521447 ps
CPU time 12.58 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:35 PM PDT 24
Peak memory 218208 kb
Host smart-784a27f2-a7c4-4637-8d00-c9dc57642241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507454833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.507454833
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.244425621
Short name T250
Test name
Test status
Simulation time 365739284 ps
CPU time 8.73 seconds
Started Jul 15 06:32:23 PM PDT 24
Finished Jul 15 06:32:32 PM PDT 24
Peak memory 218192 kb
Host smart-9657a8d3-4433-48be-914a-91d30192f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244425621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.244425621
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.116103032
Short name T261
Test name
Test status
Simulation time 48766919 ps
CPU time 1.85 seconds
Started Jul 15 06:32:22 PM PDT 24
Finished Jul 15 06:32:25 PM PDT 24
Peak memory 217640 kb
Host smart-f081143c-6ac0-4ded-93eb-a7928819d195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116103032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.116103032
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2629844222
Short name T711
Test name
Test status
Simulation time 1103997903 ps
CPU time 23.19 seconds
Started Jul 15 06:32:22 PM PDT 24
Finished Jul 15 06:32:46 PM PDT 24
Peak memory 250896 kb
Host smart-f8490e16-a8e8-4386-81ef-2da032acbc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629844222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2629844222
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1957437958
Short name T601
Test name
Test status
Simulation time 55679375 ps
CPU time 7.98 seconds
Started Jul 15 06:32:22 PM PDT 24
Finished Jul 15 06:32:31 PM PDT 24
Peak memory 250892 kb
Host smart-0e069b86-1997-411c-ae32-529820c900a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957437958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1957437958
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3340873791
Short name T198
Test name
Test status
Simulation time 144107206037 ps
CPU time 531.73 seconds
Started Jul 15 06:32:23 PM PDT 24
Finished Jul 15 06:41:15 PM PDT 24
Peak memory 316600 kb
Host smart-9a0d2908-4a34-4396-9c37-4fe2c95c3557
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3340873791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3340873791
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.4111308968
Short name T767
Test name
Test status
Simulation time 11497877 ps
CPU time 0.88 seconds
Started Jul 15 06:32:25 PM PDT 24
Finished Jul 15 06:32:27 PM PDT 24
Peak memory 208612 kb
Host smart-ad3723b7-d20b-4b55-b81c-62cb72be2343
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111308968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.4111308968
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3679073542
Short name T520
Test name
Test status
Simulation time 21273665 ps
CPU time 1.17 seconds
Started Jul 15 06:32:28 PM PDT 24
Finished Jul 15 06:32:30 PM PDT 24
Peak memory 208932 kb
Host smart-65753673-302d-44c0-ab4c-3384bd7f55ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679073542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3679073542
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2342342959
Short name T17
Test name
Test status
Simulation time 508322949 ps
CPU time 16.87 seconds
Started Jul 15 06:32:28 PM PDT 24
Finished Jul 15 06:32:46 PM PDT 24
Peak memory 218076 kb
Host smart-a6bb26f0-77be-4672-8598-240f23ffb975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342342959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2342342959
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2037542231
Short name T836
Test name
Test status
Simulation time 648079064 ps
CPU time 16.15 seconds
Started Jul 15 06:32:25 PM PDT 24
Finished Jul 15 06:32:42 PM PDT 24
Peak memory 217436 kb
Host smart-58c262ae-5991-4f6b-b4e5-57a4e05a5972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037542231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2037542231
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2713653144
Short name T40
Test name
Test status
Simulation time 75007013 ps
CPU time 2.48 seconds
Started Jul 15 06:32:26 PM PDT 24
Finished Jul 15 06:32:29 PM PDT 24
Peak memory 218144 kb
Host smart-afa3f99f-eca4-43c7-9106-fb9fd7b37b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713653144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2713653144
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3008677933
Short name T826
Test name
Test status
Simulation time 469085442 ps
CPU time 8.23 seconds
Started Jul 15 06:32:27 PM PDT 24
Finished Jul 15 06:32:35 PM PDT 24
Peak memory 218404 kb
Host smart-0e2a34b1-b109-4418-b7ef-fea144bfc635
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008677933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3008677933
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4152858962
Short name T805
Test name
Test status
Simulation time 413063489 ps
CPU time 12.24 seconds
Started Jul 15 06:32:28 PM PDT 24
Finished Jul 15 06:32:40 PM PDT 24
Peak memory 225956 kb
Host smart-da3958a7-61c1-4a88-bf2f-0a6d9700d062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152858962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4152858962
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2830810474
Short name T378
Test name
Test status
Simulation time 278756571 ps
CPU time 9.35 seconds
Started Jul 15 06:32:28 PM PDT 24
Finished Jul 15 06:32:38 PM PDT 24
Peak memory 225964 kb
Host smart-eae336b6-a18d-4bf6-8679-91d97b682e91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830810474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2830810474
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3389588752
Short name T518
Test name
Test status
Simulation time 412003035 ps
CPU time 6.43 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:32:36 PM PDT 24
Peak memory 218296 kb
Host smart-5dbb2c93-9fd3-4c9f-84eb-0bc8c44e4e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389588752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3389588752
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1386727742
Short name T217
Test name
Test status
Simulation time 283721373 ps
CPU time 4.76 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:26 PM PDT 24
Peak memory 217636 kb
Host smart-5bc38fd8-774b-479e-932c-0272ada82d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386727742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1386727742
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.880282930
Short name T649
Test name
Test status
Simulation time 260823969 ps
CPU time 26.58 seconds
Started Jul 15 06:32:20 PM PDT 24
Finished Jul 15 06:32:48 PM PDT 24
Peak memory 250904 kb
Host smart-b09dc484-8881-4184-99ba-ee680c67b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880282930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.880282930
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.394316792
Short name T467
Test name
Test status
Simulation time 55660337 ps
CPU time 6.83 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:32:36 PM PDT 24
Peak memory 246816 kb
Host smart-d1389273-5747-4a18-a02b-df73b341be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394316792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.394316792
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.880876426
Short name T751
Test name
Test status
Simulation time 5117281021 ps
CPU time 76.05 seconds
Started Jul 15 06:32:27 PM PDT 24
Finished Jul 15 06:33:44 PM PDT 24
Peak memory 218888 kb
Host smart-c76679e2-0690-4955-90cd-3c1c0582f07b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880876426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.880876426
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4293823220
Short name T268
Test name
Test status
Simulation time 11465578 ps
CPU time 0.91 seconds
Started Jul 15 06:32:21 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 211824 kb
Host smart-5cf5a46a-e2c9-4b6b-a5c8-9dca775136fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293823220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.4293823220
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.833257956
Short name T424
Test name
Test status
Simulation time 23114633 ps
CPU time 1.01 seconds
Started Jul 15 06:32:27 PM PDT 24
Finished Jul 15 06:32:29 PM PDT 24
Peak memory 208908 kb
Host smart-3d4d59b8-b6e2-4604-952b-80e16d5263ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833257956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.833257956
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3488028073
Short name T419
Test name
Test status
Simulation time 5742812349 ps
CPU time 15.06 seconds
Started Jul 15 06:32:25 PM PDT 24
Finished Jul 15 06:32:41 PM PDT 24
Peak memory 225972 kb
Host smart-45df81ac-9b3d-4024-a131-9155ec25632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488028073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3488028073
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3079370890
Short name T36
Test name
Test status
Simulation time 241658844 ps
CPU time 4.05 seconds
Started Jul 15 06:32:25 PM PDT 24
Finished Jul 15 06:32:29 PM PDT 24
Peak memory 217268 kb
Host smart-abad2449-a33d-4c60-abe8-e729dd7162ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079370890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3079370890
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3634716227
Short name T184
Test name
Test status
Simulation time 71165339 ps
CPU time 2.65 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:32:32 PM PDT 24
Peak memory 222304 kb
Host smart-229ee7a1-41fb-4a6c-a28c-050b6cd0d5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634716227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3634716227
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3353522889
Short name T802
Test name
Test status
Simulation time 338225975 ps
CPU time 16.45 seconds
Started Jul 15 06:32:28 PM PDT 24
Finished Jul 15 06:32:46 PM PDT 24
Peak memory 218888 kb
Host smart-0410c60f-4831-4e55-918e-e0b3b5a96e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353522889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3353522889
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3515153147
Short name T764
Test name
Test status
Simulation time 3240961754 ps
CPU time 19.72 seconds
Started Jul 15 06:32:26 PM PDT 24
Finished Jul 15 06:32:46 PM PDT 24
Peak memory 226024 kb
Host smart-ed045404-6f89-4b2f-aac8-08574269d960
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515153147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3515153147
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.717535237
Short name T758
Test name
Test status
Simulation time 210455133 ps
CPU time 6.34 seconds
Started Jul 15 06:32:29 PM PDT 24
Finished Jul 15 06:32:36 PM PDT 24
Peak memory 225988 kb
Host smart-463273b2-329f-4870-8ad5-e78ed211da5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717535237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.717535237
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.957211260
Short name T479
Test name
Test status
Simulation time 412701273 ps
CPU time 14.94 seconds
Started Jul 15 06:32:27 PM PDT 24
Finished Jul 15 06:32:42 PM PDT 24
Peak memory 225144 kb
Host smart-026b24b0-140e-456f-9369-cbbfb77b717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957211260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.957211260
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.908281610
Short name T14
Test name
Test status
Simulation time 125509316 ps
CPU time 2.75 seconds
Started Jul 15 06:32:27 PM PDT 24
Finished Jul 15 06:32:30 PM PDT 24
Peak memory 217612 kb
Host smart-226504b8-46ec-428b-abf2-87a97201e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908281610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.908281610
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.18798305
Short name T532
Test name
Test status
Simulation time 180735046 ps
CPU time 25.25 seconds
Started Jul 15 06:32:30 PM PDT 24
Finished Jul 15 06:32:56 PM PDT 24
Peak memory 250976 kb
Host smart-fe724a7e-8a34-4be1-a31f-303ee54cefb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18798305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.18798305
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3397172726
Short name T674
Test name
Test status
Simulation time 1345752194 ps
CPU time 3.09 seconds
Started Jul 15 06:32:28 PM PDT 24
Finished Jul 15 06:32:31 PM PDT 24
Peak memory 224092 kb
Host smart-a4c8cdd0-e2a8-4a0c-9454-251399b08a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397172726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3397172726
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2949516461
Short name T691
Test name
Test status
Simulation time 57667624286 ps
CPU time 201.32 seconds
Started Jul 15 06:32:30 PM PDT 24
Finished Jul 15 06:35:52 PM PDT 24
Peak memory 283720 kb
Host smart-62d4b42e-5b82-47ac-bb96-743578892e5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949516461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2949516461
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1896854537
Short name T768
Test name
Test status
Simulation time 50618860 ps
CPU time 0.97 seconds
Started Jul 15 06:32:26 PM PDT 24
Finished Jul 15 06:32:27 PM PDT 24
Peak memory 211732 kb
Host smart-d73c1fcf-25dd-4f82-a465-0cd74ecc91b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896854537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1896854537
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.692904851
Short name T696
Test name
Test status
Simulation time 37384501 ps
CPU time 1.22 seconds
Started Jul 15 06:30:05 PM PDT 24
Finished Jul 15 06:30:07 PM PDT 24
Peak memory 208772 kb
Host smart-f57d291e-80d8-4aea-bab7-223097c2e6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692904851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.692904851
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2244863916
Short name T627
Test name
Test status
Simulation time 30736378 ps
CPU time 0.93 seconds
Started Jul 15 06:29:54 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 209080 kb
Host smart-b0eca96b-32d7-4e10-9145-42a6c615b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244863916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2244863916
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4216189391
Short name T50
Test name
Test status
Simulation time 1910020234 ps
CPU time 10.44 seconds
Started Jul 15 06:29:57 PM PDT 24
Finished Jul 15 06:30:09 PM PDT 24
Peak memory 225976 kb
Host smart-7849561d-6df3-41e2-9921-5c5b433d71bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216189391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4216189391
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3389228592
Short name T865
Test name
Test status
Simulation time 3626351890 ps
CPU time 18.61 seconds
Started Jul 15 06:30:05 PM PDT 24
Finished Jul 15 06:30:24 PM PDT 24
Peak memory 217564 kb
Host smart-cfa98838-a591-4900-adef-081b00d85897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389228592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3389228592
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1801418227
Short name T588
Test name
Test status
Simulation time 11044302858 ps
CPU time 70.48 seconds
Started Jul 15 06:30:00 PM PDT 24
Finished Jul 15 06:31:11 PM PDT 24
Peak memory 226020 kb
Host smart-a525f3df-3cfd-44c1-b630-318daf2a8e4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801418227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1801418227
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3244799468
Short name T618
Test name
Test status
Simulation time 554364147 ps
CPU time 3.4 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:06 PM PDT 24
Peak memory 217728 kb
Host smart-ed235ace-8cef-4b45-ad30-2244da437f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244799468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
244799468
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2832121276
Short name T454
Test name
Test status
Simulation time 215096892 ps
CPU time 2.63 seconds
Started Jul 15 06:29:54 PM PDT 24
Finished Jul 15 06:29:57 PM PDT 24
Peak memory 218176 kb
Host smart-170af871-6450-4469-90ce-326946c0d72c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832121276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2832121276
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1714598595
Short name T411
Test name
Test status
Simulation time 1370919160 ps
CPU time 10.99 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 217696 kb
Host smart-4c612fbb-04bc-4772-98d9-beee1ceb4b05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714598595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1714598595
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3837716357
Short name T487
Test name
Test status
Simulation time 1011306350 ps
CPU time 15.4 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:17 PM PDT 24
Peak memory 217628 kb
Host smart-be48da0e-2874-43ff-b693-812a2c3ca5b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837716357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3837716357
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.651576203
Short name T280
Test name
Test status
Simulation time 789117601 ps
CPU time 27.83 seconds
Started Jul 15 06:29:55 PM PDT 24
Finished Jul 15 06:30:24 PM PDT 24
Peak memory 250956 kb
Host smart-d5f8fb6d-1bea-41ee-82e3-5340cfd0c42d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651576203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.651576203
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2502523706
Short name T854
Test name
Test status
Simulation time 8459055818 ps
CPU time 24.59 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 250920 kb
Host smart-b8ab1fa2-0315-47ab-94d5-aaa99d9a6df6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502523706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2502523706
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.954922234
Short name T310
Test name
Test status
Simulation time 37041582 ps
CPU time 1.97 seconds
Started Jul 15 06:29:58 PM PDT 24
Finished Jul 15 06:30:01 PM PDT 24
Peak memory 218116 kb
Host smart-bcb0b13b-5a02-4b7e-a3e7-5ca040f4238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954922234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.954922234
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3724764615
Short name T497
Test name
Test status
Simulation time 292993439 ps
CPU time 7.07 seconds
Started Jul 15 06:29:55 PM PDT 24
Finished Jul 15 06:30:03 PM PDT 24
Peak memory 214640 kb
Host smart-cb080dc2-b41e-4ec0-b29b-853a2adb3e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724764615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3724764615
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.94423640
Short name T799
Test name
Test status
Simulation time 552363044 ps
CPU time 10.71 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 225972 kb
Host smart-aabf7955-290a-4d98-83d6-4ad0f59d23d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94423640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dige
st.94423640
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1523052033
Short name T203
Test name
Test status
Simulation time 3221750446 ps
CPU time 12.2 seconds
Started Jul 15 06:30:00 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 218904 kb
Host smart-88ec3340-0392-4a02-a4ab-f3f0473dd2cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523052033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
523052033
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1033757725
Short name T837
Test name
Test status
Simulation time 841791484 ps
CPU time 10.81 seconds
Started Jul 15 06:29:53 PM PDT 24
Finished Jul 15 06:30:05 PM PDT 24
Peak memory 225948 kb
Host smart-3d0fc457-c18d-4a2d-97f3-902919d83baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033757725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1033757725
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3893968880
Short name T525
Test name
Test status
Simulation time 113001572 ps
CPU time 3.08 seconds
Started Jul 15 06:29:55 PM PDT 24
Finished Jul 15 06:29:59 PM PDT 24
Peak memory 217592 kb
Host smart-8029854a-3a11-402c-880d-d08ff266c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893968880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3893968880
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1014184843
Short name T639
Test name
Test status
Simulation time 165605130 ps
CPU time 22.41 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:24 PM PDT 24
Peak memory 250872 kb
Host smart-2f68b330-abf0-4614-be38-aec95438d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014184843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1014184843
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.883979684
Short name T681
Test name
Test status
Simulation time 94631677 ps
CPU time 6.93 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:09 PM PDT 24
Peak memory 250888 kb
Host smart-c438a2d7-efbc-4d45-aaf2-ec0d555566b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883979684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.883979684
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.435539293
Short name T811
Test name
Test status
Simulation time 4469754480 ps
CPU time 142.33 seconds
Started Jul 15 06:29:59 PM PDT 24
Finished Jul 15 06:32:22 PM PDT 24
Peak memory 267400 kb
Host smart-b8cd1151-efd5-4379-a5b2-d13560b01303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435539293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.435539293
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.23713225
Short name T315
Test name
Test status
Simulation time 30250884 ps
CPU time 0.83 seconds
Started Jul 15 06:29:54 PM PDT 24
Finished Jul 15 06:29:55 PM PDT 24
Peak memory 211772 kb
Host smart-92729627-d4f2-4481-8a35-4355181fd52b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23713225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_volatile_unlock_smoke.23713225
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.260684138
Short name T512
Test name
Test status
Simulation time 23642243 ps
CPU time 1.03 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:08 PM PDT 24
Peak memory 209064 kb
Host smart-d8612cd6-b467-4ff4-917f-a0ea40bfa7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260684138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.260684138
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.869201816
Short name T244
Test name
Test status
Simulation time 19746597 ps
CPU time 0.87 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:03 PM PDT 24
Peak memory 208860 kb
Host smart-cf440e4e-309c-45d9-a705-6237415dc7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869201816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.869201816
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1446424746
Short name T433
Test name
Test status
Simulation time 730152447 ps
CPU time 13.83 seconds
Started Jul 15 06:30:00 PM PDT 24
Finished Jul 15 06:30:15 PM PDT 24
Peak memory 218104 kb
Host smart-4f22daf2-54a2-43d4-96b0-86d7c9e56b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446424746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1446424746
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.866224607
Short name T116
Test name
Test status
Simulation time 3252670621 ps
CPU time 8.14 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:16 PM PDT 24
Peak memory 217640 kb
Host smart-4c08fdf5-dc51-4e0e-8731-8eb06a457320
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866224607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.866224607
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.430563408
Short name T478
Test name
Test status
Simulation time 3338610238 ps
CPU time 28.1 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:36 PM PDT 24
Peak memory 218976 kb
Host smart-7887812c-f73e-4f08-977b-157013f28827
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430563408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.430563408
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1672627473
Short name T374
Test name
Test status
Simulation time 3409342589 ps
CPU time 10.22 seconds
Started Jul 15 06:30:06 PM PDT 24
Finished Jul 15 06:30:17 PM PDT 24
Peak memory 217888 kb
Host smart-ab5d9486-4a79-4a27-8eb3-d6542fbbc293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672627473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
672627473
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3810664827
Short name T453
Test name
Test status
Simulation time 459505816 ps
CPU time 7.78 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:17 PM PDT 24
Peak memory 224048 kb
Host smart-bc3780ee-c9ba-45ee-b5f6-2d0b77fbeb8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810664827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3810664827
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3299562671
Short name T620
Test name
Test status
Simulation time 1263712561 ps
CPU time 39.96 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:48 PM PDT 24
Peak memory 217532 kb
Host smart-9c23e97a-b69e-40dd-9ec1-94b89e8da92e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299562671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3299562671
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.915287051
Short name T650
Test name
Test status
Simulation time 276256541 ps
CPU time 2.08 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:11 PM PDT 24
Peak memory 217652 kb
Host smart-55f207de-a3f5-4f15-b39b-a7f59bbf094c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915287051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.915287051
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1286764585
Short name T306
Test name
Test status
Simulation time 1359388071 ps
CPU time 38.35 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:46 PM PDT 24
Peak memory 270112 kb
Host smart-8950ee03-9030-4883-a477-3591ece25d0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286764585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1286764585
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1042825590
Short name T500
Test name
Test status
Simulation time 281092517 ps
CPU time 13.9 seconds
Started Jul 15 06:30:06 PM PDT 24
Finished Jul 15 06:30:20 PM PDT 24
Peak memory 250960 kb
Host smart-834dd341-b30e-42f4-a411-9bb362fa4e93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042825590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1042825590
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1431804245
Short name T16
Test name
Test status
Simulation time 95593527 ps
CPU time 4.72 seconds
Started Jul 15 06:30:00 PM PDT 24
Finished Jul 15 06:30:05 PM PDT 24
Peak memory 222148 kb
Host smart-106fbd88-d6d1-4902-935f-8e1ce03c71c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431804245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1431804245
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2773163963
Short name T364
Test name
Test status
Simulation time 409478269 ps
CPU time 22.26 seconds
Started Jul 15 06:30:00 PM PDT 24
Finished Jul 15 06:30:23 PM PDT 24
Peak memory 217648 kb
Host smart-a22b80cd-f7a8-4758-9360-b96d040c6bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773163963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2773163963
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3569953528
Short name T801
Test name
Test status
Simulation time 407496858 ps
CPU time 11.49 seconds
Started Jul 15 06:30:09 PM PDT 24
Finished Jul 15 06:30:21 PM PDT 24
Peak memory 218400 kb
Host smart-8493436d-3284-4475-8542-1f0e6da9143c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569953528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3569953528
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2816154681
Short name T714
Test name
Test status
Simulation time 489372065 ps
CPU time 13.03 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:21 PM PDT 24
Peak memory 225936 kb
Host smart-cb5eced0-2f42-4595-ab06-239cee8de6db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816154681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2816154681
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.85698343
Short name T752
Test name
Test status
Simulation time 781980645 ps
CPU time 6.3 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:14 PM PDT 24
Peak memory 218164 kb
Host smart-72d25c44-e88b-413b-8eaa-bd2dfda4e5a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85698343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.85698343
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1935958932
Short name T615
Test name
Test status
Simulation time 1128099566 ps
CPU time 7.96 seconds
Started Jul 15 06:30:03 PM PDT 24
Finished Jul 15 06:30:11 PM PDT 24
Peak memory 225976 kb
Host smart-4799423c-ecba-4244-97d0-48d2b0f147ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935958932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1935958932
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.35835116
Short name T79
Test name
Test status
Simulation time 20324823 ps
CPU time 1.48 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:04 PM PDT 24
Peak memory 213692 kb
Host smart-d1893f37-6004-4a4d-a222-0426ee0138dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35835116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.35835116
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4099849144
Short name T469
Test name
Test status
Simulation time 910981614 ps
CPU time 30.67 seconds
Started Jul 15 06:30:01 PM PDT 24
Finished Jul 15 06:30:33 PM PDT 24
Peak memory 250908 kb
Host smart-a489bf37-98bf-48fb-a813-b24b5c626f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099849144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4099849144
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2220868148
Short name T451
Test name
Test status
Simulation time 215837553 ps
CPU time 3.43 seconds
Started Jul 15 06:30:00 PM PDT 24
Finished Jul 15 06:30:04 PM PDT 24
Peak memory 222124 kb
Host smart-b2d04878-08eb-4af6-ae6b-2ae2301f09b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220868148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2220868148
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1571735472
Short name T793
Test name
Test status
Simulation time 31431062207 ps
CPU time 139.83 seconds
Started Jul 15 06:30:06 PM PDT 24
Finished Jul 15 06:32:27 PM PDT 24
Peak memory 267336 kb
Host smart-ba093d59-83c2-46db-b6a7-0294ec53947a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571735472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1571735472
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3261166907
Short name T739
Test name
Test status
Simulation time 35284709 ps
CPU time 0.98 seconds
Started Jul 15 06:30:05 PM PDT 24
Finished Jul 15 06:30:07 PM PDT 24
Peak memory 211684 kb
Host smart-c5667a6d-81b9-4925-8691-a809d2c194a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261166907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3261166907
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1629798437
Short name T822
Test name
Test status
Simulation time 105976985 ps
CPU time 0.99 seconds
Started Jul 15 06:30:14 PM PDT 24
Finished Jul 15 06:30:16 PM PDT 24
Peak memory 208852 kb
Host smart-fa640505-0f97-4030-b72a-af18b45d2d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629798437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1629798437
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2135566390
Short name T78
Test name
Test status
Simulation time 11414942 ps
CPU time 0.87 seconds
Started Jul 15 06:30:09 PM PDT 24
Finished Jul 15 06:30:11 PM PDT 24
Peak memory 208692 kb
Host smart-7baf3147-8eb6-47d9-92f8-acefcbade15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135566390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2135566390
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.441643055
Short name T420
Test name
Test status
Simulation time 175967673 ps
CPU time 9.57 seconds
Started Jul 15 06:30:06 PM PDT 24
Finished Jul 15 06:30:16 PM PDT 24
Peak memory 225968 kb
Host smart-51675c23-30c8-430d-84a5-6f23eb42abbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441643055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.441643055
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2628081454
Short name T449
Test name
Test status
Simulation time 745540742 ps
CPU time 3.04 seconds
Started Jul 15 06:30:15 PM PDT 24
Finished Jul 15 06:30:18 PM PDT 24
Peak memory 217048 kb
Host smart-f649fb29-83e6-4f69-9f6e-35decea7c954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628081454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2628081454
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3425822868
Short name T281
Test name
Test status
Simulation time 3955444006 ps
CPU time 34.14 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 218932 kb
Host smart-7656ddf7-6f3c-4257-8500-1a1d4294b995
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425822868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3425822868
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3233949098
Short name T352
Test name
Test status
Simulation time 672324022 ps
CPU time 4.93 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:21 PM PDT 24
Peak memory 217676 kb
Host smart-6e6ce153-67e9-4014-879f-792bfd155f7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233949098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
233949098
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2123437093
Short name T112
Test name
Test status
Simulation time 1070405104 ps
CPU time 2.44 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:10 PM PDT 24
Peak memory 218240 kb
Host smart-7631ed22-0e68-47b3-8224-71d85e3e8d0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123437093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2123437093
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1039340001
Short name T680
Test name
Test status
Simulation time 1199569414 ps
CPU time 13.98 seconds
Started Jul 15 06:30:17 PM PDT 24
Finished Jul 15 06:30:32 PM PDT 24
Peak memory 217648 kb
Host smart-a08bc6ae-08f9-4688-992c-2d6f88e34148
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039340001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1039340001
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3591186623
Short name T502
Test name
Test status
Simulation time 662932107 ps
CPU time 5.58 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:14 PM PDT 24
Peak memory 217628 kb
Host smart-16f62e6e-9255-4e8b-acce-9a77576b6aee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591186623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3591186623
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2865033054
Short name T460
Test name
Test status
Simulation time 1318115623 ps
CPU time 45.36 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:54 PM PDT 24
Peak memory 275584 kb
Host smart-4e26293d-9971-4efe-b8b5-a26aa1b35314
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865033054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2865033054
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.876769254
Short name T448
Test name
Test status
Simulation time 3364326928 ps
CPU time 28.64 seconds
Started Jul 15 06:30:10 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 250548 kb
Host smart-37490251-fa03-428f-8921-23b1c149e51b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876769254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.876769254
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.628789261
Short name T600
Test name
Test status
Simulation time 93062752 ps
CPU time 4.24 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:13 PM PDT 24
Peak memory 218176 kb
Host smart-8810e170-5b76-4ddf-aaee-1d5364564017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628789261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.628789261
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3730111384
Short name T694
Test name
Test status
Simulation time 1021578069 ps
CPU time 5.52 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:15 PM PDT 24
Peak memory 217640 kb
Host smart-fc992d5d-5790-405a-b1c4-516a7d46ca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730111384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3730111384
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2756157791
Short name T544
Test name
Test status
Simulation time 1272476480 ps
CPU time 9.04 seconds
Started Jul 15 06:30:20 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 218320 kb
Host smart-8ec17cb8-87b1-428a-bb7c-0fa8f298116c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756157791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
756157791
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.971382327
Short name T652
Test name
Test status
Simulation time 353870995 ps
CPU time 8.75 seconds
Started Jul 15 06:30:06 PM PDT 24
Finished Jul 15 06:30:16 PM PDT 24
Peak memory 225952 kb
Host smart-ae72f73f-d3cb-45dc-9e1c-eea4a413ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971382327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.971382327
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.843276791
Short name T437
Test name
Test status
Simulation time 35307890 ps
CPU time 1.62 seconds
Started Jul 15 06:30:09 PM PDT 24
Finished Jul 15 06:30:12 PM PDT 24
Peak memory 217600 kb
Host smart-a62de717-c339-4741-b175-3faf7547a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843276791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.843276791
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.590959325
Short name T372
Test name
Test status
Simulation time 287788647 ps
CPU time 25.5 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:34 PM PDT 24
Peak memory 250992 kb
Host smart-f8655cb9-c797-4770-b4b1-d2be927a474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590959325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.590959325
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3574334242
Short name T504
Test name
Test status
Simulation time 97740344 ps
CPU time 10.12 seconds
Started Jul 15 06:30:07 PM PDT 24
Finished Jul 15 06:30:18 PM PDT 24
Peak memory 250876 kb
Host smart-e1bd5a60-17b5-4fc3-bf0b-1124b519f817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574334242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3574334242
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1530267436
Short name T128
Test name
Test status
Simulation time 4530273715 ps
CPU time 163.56 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:33:00 PM PDT 24
Peak memory 254764 kb
Host smart-b0962640-4a0f-44bc-93b5-47df9467ca67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530267436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1530267436
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3706898440
Short name T534
Test name
Test status
Simulation time 15163313249 ps
CPU time 401.81 seconds
Started Jul 15 06:30:18 PM PDT 24
Finished Jul 15 06:37:01 PM PDT 24
Peak memory 308556 kb
Host smart-e9c53e60-8912-4564-a4d4-401f917dd51b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3706898440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3706898440
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1869498628
Short name T279
Test name
Test status
Simulation time 26826341 ps
CPU time 0.95 seconds
Started Jul 15 06:30:08 PM PDT 24
Finished Jul 15 06:30:10 PM PDT 24
Peak memory 211804 kb
Host smart-a2a41379-41e7-47f1-ac49-a08af22f3cea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869498628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1869498628
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1720580991
Short name T349
Test name
Test status
Simulation time 18827478 ps
CPU time 0.84 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:30:24 PM PDT 24
Peak memory 208744 kb
Host smart-7afc6187-10ca-4ca2-b065-8e93c8dc50f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720580991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1720580991
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.433955221
Short name T610
Test name
Test status
Simulation time 40663267 ps
CPU time 0.92 seconds
Started Jul 15 06:30:17 PM PDT 24
Finished Jul 15 06:30:18 PM PDT 24
Peak memory 209148 kb
Host smart-3a4364a2-0734-4c82-bbba-84a78140a7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433955221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.433955221
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.892370973
Short name T541
Test name
Test status
Simulation time 1043047541 ps
CPU time 13.3 seconds
Started Jul 15 06:30:15 PM PDT 24
Finished Jul 15 06:30:29 PM PDT 24
Peak memory 218144 kb
Host smart-03367cc6-b29e-4d9d-9fb5-57da2e1ea21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892370973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.892370973
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2983917169
Short name T806
Test name
Test status
Simulation time 317483251 ps
CPU time 8.88 seconds
Started Jul 15 06:30:18 PM PDT 24
Finished Jul 15 06:30:28 PM PDT 24
Peak memory 217364 kb
Host smart-7f348f53-819a-43e2-af6f-09c483ca58e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983917169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2983917169
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1364089118
Short name T328
Test name
Test status
Simulation time 1266888111 ps
CPU time 19.85 seconds
Started Jul 15 06:30:18 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 218136 kb
Host smart-34a83b1e-1e2b-4708-91b3-2727df687a3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364089118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1364089118
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4113455932
Short name T488
Test name
Test status
Simulation time 270638176 ps
CPU time 3.15 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:20 PM PDT 24
Peak memory 217192 kb
Host smart-79ddcb16-a7b9-4581-8709-495235b5f6ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113455932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.4
113455932
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3923064484
Short name T521
Test name
Test status
Simulation time 1673263824 ps
CPU time 6.85 seconds
Started Jul 15 06:30:17 PM PDT 24
Finished Jul 15 06:30:25 PM PDT 24
Peak memory 218188 kb
Host smart-abdda8e8-93b3-49c3-8673-4beab09c7fcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923064484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3923064484
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.398438862
Short name T377
Test name
Test status
Simulation time 6774433628 ps
CPU time 14.36 seconds
Started Jul 15 06:30:17 PM PDT 24
Finished Jul 15 06:30:32 PM PDT 24
Peak memory 217680 kb
Host smart-5c1d8f8a-979f-4df7-93fb-e15b0feaf702
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398438862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.398438862
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2543206926
Short name T361
Test name
Test status
Simulation time 171682980 ps
CPU time 3.62 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:26 PM PDT 24
Peak memory 217800 kb
Host smart-60c709aa-1761-4959-b278-07df80a4e746
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543206926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2543206926
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1645689351
Short name T294
Test name
Test status
Simulation time 5131918357 ps
CPU time 55.43 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:31:13 PM PDT 24
Peak memory 267316 kb
Host smart-bbd9c18c-217a-4d7e-ad0f-eb3df97a7653
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645689351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1645689351
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4179318159
Short name T410
Test name
Test status
Simulation time 389715988 ps
CPU time 12.58 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 250728 kb
Host smart-d6cf0aef-2764-4865-81ab-bbf072597597
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179318159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.4179318159
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4018092535
Short name T492
Test name
Test status
Simulation time 80192789 ps
CPU time 2.86 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:20 PM PDT 24
Peak memory 218148 kb
Host smart-2413633c-ec8b-492a-8336-a434e52f9532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018092535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4018092535
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1608793725
Short name T70
Test name
Test status
Simulation time 1759770449 ps
CPU time 30.23 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:47 PM PDT 24
Peak memory 217700 kb
Host smart-c53802c3-2222-4195-bb58-ab351479cf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608793725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1608793725
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4150459217
Short name T671
Test name
Test status
Simulation time 906639773 ps
CPU time 19.53 seconds
Started Jul 15 06:30:15 PM PDT 24
Finished Jul 15 06:30:36 PM PDT 24
Peak memory 219380 kb
Host smart-e1d71ea4-d713-4b66-af16-bd2e26490b66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150459217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4150459217
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2610368089
Short name T66
Test name
Test status
Simulation time 371551130 ps
CPU time 14.79 seconds
Started Jul 15 06:30:18 PM PDT 24
Finished Jul 15 06:30:33 PM PDT 24
Peak memory 225980 kb
Host smart-6bd29bd0-bcd2-48f9-a676-86df3e65a84c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610368089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2610368089
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1253390135
Short name T845
Test name
Test status
Simulation time 581254082 ps
CPU time 8.72 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:26 PM PDT 24
Peak memory 218144 kb
Host smart-1a00dd08-9ace-49a1-8bc2-02a14a4c75b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253390135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
253390135
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1151350917
Short name T62
Test name
Test status
Simulation time 2439049033 ps
CPU time 9.92 seconds
Started Jul 15 06:30:17 PM PDT 24
Finished Jul 15 06:30:28 PM PDT 24
Peak memory 226040 kb
Host smart-a59984a0-4896-465f-85cc-592dd43192b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151350917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1151350917
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1654540638
Short name T89
Test name
Test status
Simulation time 41106054 ps
CPU time 1.8 seconds
Started Jul 15 06:30:16 PM PDT 24
Finished Jul 15 06:30:18 PM PDT 24
Peak memory 222184 kb
Host smart-2ee103fe-66e6-4238-afa1-c4296b5bbf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654540638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1654540638
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.909292750
Short name T774
Test name
Test status
Simulation time 182357088 ps
CPU time 21.57 seconds
Started Jul 15 06:30:17 PM PDT 24
Finished Jul 15 06:30:39 PM PDT 24
Peak memory 250892 kb
Host smart-39e63726-021b-4439-ad20-b09d393b1269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909292750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.909292750
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1300490593
Short name T496
Test name
Test status
Simulation time 174943941 ps
CPU time 4.6 seconds
Started Jul 15 06:30:15 PM PDT 24
Finished Jul 15 06:30:20 PM PDT 24
Peak memory 226368 kb
Host smart-495c3805-cd39-4933-a7ff-6bf300220684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300490593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1300490593
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.70549733
Short name T850
Test name
Test status
Simulation time 26297947945 ps
CPU time 394.23 seconds
Started Jul 15 06:30:23 PM PDT 24
Finished Jul 15 06:36:58 PM PDT 24
Peak memory 285304 kb
Host smart-f14da47c-40e5-4bbc-b572-ccdcc585fd51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70549733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.lc_ctrl_stress_all.70549733
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1808201814
Short name T175
Test name
Test status
Simulation time 189244767630 ps
CPU time 1642.8 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:57:46 PM PDT 24
Peak memory 513268 kb
Host smart-c77f864d-ba27-4e05-ac47-6d93cda7da73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1808201814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1808201814
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2243739508
Short name T45
Test name
Test status
Simulation time 14218440 ps
CPU time 0.97 seconds
Started Jul 15 06:30:18 PM PDT 24
Finished Jul 15 06:30:20 PM PDT 24
Peak memory 212952 kb
Host smart-ff48f5c6-7f19-461e-bc0a-7b5b89f6a9d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243739508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2243739508
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.590430925
Short name T682
Test name
Test status
Simulation time 37665508 ps
CPU time 0.97 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:30:24 PM PDT 24
Peak memory 208896 kb
Host smart-aa5d4bbe-b76f-4472-95e7-dce60f043725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590430925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.590430925
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1539478411
Short name T687
Test name
Test status
Simulation time 13123588 ps
CPU time 1 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:29 PM PDT 24
Peak memory 208920 kb
Host smart-9039b2f7-607a-4da1-9d1b-c4cd4aacf062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539478411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1539478411
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1983085642
Short name T384
Test name
Test status
Simulation time 1371978195 ps
CPU time 12.73 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:34 PM PDT 24
Peak memory 218160 kb
Host smart-fe3cdd6b-52ab-4bfd-81dc-3af4732c4262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983085642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1983085642
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2614633460
Short name T369
Test name
Test status
Simulation time 427796957 ps
CPU time 5.03 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:27 PM PDT 24
Peak memory 216996 kb
Host smart-86bc2462-96eb-46ed-be32-9c7a00828d0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614633460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2614633460
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.542308886
Short name T735
Test name
Test status
Simulation time 7263577018 ps
CPU time 97.66 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:32:00 PM PDT 24
Peak memory 218876 kb
Host smart-a09c89c4-1b14-41ae-a1f4-46ab528e75a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542308886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.542308886
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2505581228
Short name T223
Test name
Test status
Simulation time 683988787 ps
CPU time 7.4 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:28 PM PDT 24
Peak memory 217736 kb
Host smart-68bf8a13-3649-4283-9f1e-d990f5b29c4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505581228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
505581228
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1836773217
Short name T613
Test name
Test status
Simulation time 623414539 ps
CPU time 5.63 seconds
Started Jul 15 06:30:24 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 218172 kb
Host smart-5ec93b78-1843-4316-9516-1981c856ad6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836773217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1836773217
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3223597657
Short name T91
Test name
Test status
Simulation time 3617203753 ps
CPU time 27.72 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:50 PM PDT 24
Peak memory 217724 kb
Host smart-15e60dd6-fa62-4c0b-9269-ad92621d42b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223597657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3223597657
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1243191763
Short name T404
Test name
Test status
Simulation time 297714091 ps
CPU time 5.84 seconds
Started Jul 15 06:30:23 PM PDT 24
Finished Jul 15 06:30:30 PM PDT 24
Peak memory 217624 kb
Host smart-4a9c7081-22e0-46ae-a912-5477638b9d22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243191763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1243191763
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2852575505
Short name T486
Test name
Test status
Simulation time 1635954255 ps
CPU time 45.65 seconds
Started Jul 15 06:30:25 PM PDT 24
Finished Jul 15 06:31:11 PM PDT 24
Peak memory 275500 kb
Host smart-1e6fe420-8b08-464b-ba61-28e746c19d11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852575505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2852575505
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.152759983
Short name T857
Test name
Test status
Simulation time 1622425996 ps
CPU time 24.01 seconds
Started Jul 15 06:30:24 PM PDT 24
Finished Jul 15 06:30:49 PM PDT 24
Peak memory 224236 kb
Host smart-4eeb1695-f4ac-4af6-8c44-e933e01292aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152759983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.152759983
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1660444690
Short name T727
Test name
Test status
Simulation time 41437342 ps
CPU time 1.45 seconds
Started Jul 15 06:30:23 PM PDT 24
Finished Jul 15 06:30:26 PM PDT 24
Peak memory 218140 kb
Host smart-556e4b07-5ac1-4a89-94aa-91eb056e12aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660444690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1660444690
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3154691531
Short name T220
Test name
Test status
Simulation time 1574820870 ps
CPU time 17.6 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:40 PM PDT 24
Peak memory 214748 kb
Host smart-4ab5c595-4cb4-4836-92c2-a1a0ef56e94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154691531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3154691531
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.280760106
Short name T759
Test name
Test status
Simulation time 448198700 ps
CPU time 17.34 seconds
Started Jul 15 06:30:23 PM PDT 24
Finished Jul 15 06:30:41 PM PDT 24
Peak memory 225968 kb
Host smart-9b0975eb-ff9a-4d2c-9e65-3b45374a84e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280760106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.280760106
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2615574131
Short name T816
Test name
Test status
Simulation time 1918920180 ps
CPU time 13.1 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:30:36 PM PDT 24
Peak memory 225960 kb
Host smart-fd579d4b-38f5-4860-83a3-6f221039033e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615574131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2615574131
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2938212706
Short name T403
Test name
Test status
Simulation time 1277270544 ps
CPU time 9.54 seconds
Started Jul 15 06:30:27 PM PDT 24
Finished Jul 15 06:30:38 PM PDT 24
Peak memory 218108 kb
Host smart-9cc32e75-722b-4ea7-982d-a968f868bc77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938212706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
938212706
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2647889775
Short name T526
Test name
Test status
Simulation time 829705932 ps
CPU time 14.32 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:30:37 PM PDT 24
Peak memory 225972 kb
Host smart-3e9956ea-db73-4bab-bade-6c8e30701281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647889775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2647889775
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1245721363
Short name T719
Test name
Test status
Simulation time 783116041 ps
CPU time 10.36 seconds
Started Jul 15 06:30:26 PM PDT 24
Finished Jul 15 06:30:37 PM PDT 24
Peak memory 217612 kb
Host smart-7afdae08-3806-495d-8696-563f9c3fd0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245721363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1245721363
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2980018435
Short name T780
Test name
Test status
Simulation time 692553934 ps
CPU time 20.39 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:42 PM PDT 24
Peak memory 251000 kb
Host smart-44da6f57-4a77-4542-808c-b090f7b0af6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980018435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2980018435
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1950408463
Short name T177
Test name
Test status
Simulation time 134402134 ps
CPU time 8.91 seconds
Started Jul 15 06:30:22 PM PDT 24
Finished Jul 15 06:30:31 PM PDT 24
Peak memory 250908 kb
Host smart-846888fc-d42c-4ea5-b2c6-c409ad9ad294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950408463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1950408463
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4178871369
Short name T129
Test name
Test status
Simulation time 11205733283 ps
CPU time 128.42 seconds
Started Jul 15 06:30:23 PM PDT 24
Finished Jul 15 06:32:33 PM PDT 24
Peak memory 276016 kb
Host smart-d2a6c2b0-cd34-4702-b8e8-4599599cf38c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178871369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4178871369
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1963179971
Short name T430
Test name
Test status
Simulation time 26839513 ps
CPU time 1.05 seconds
Started Jul 15 06:30:21 PM PDT 24
Finished Jul 15 06:30:23 PM PDT 24
Peak memory 217728 kb
Host smart-e307d0c7-3609-4d77-903b-5ce665bdf835
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963179971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1963179971
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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