Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103802710

1

T1

2760

T2

22897

T3

33650

auto[1]

1440036

1

T3

594

T4

9068

T12

1188

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103834371

1

T1

2760

T2

22897

T3

33749

auto[1]

1408375

1

T3

495

T4

9854

T12

1683

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7483725	1			T1	545		T2	5855		T3	6341
auto[IdleSt]	22269647	1			T1	606		T2	2699		T3	7582
auto[ClkMuxSt]	34069	1			T1	6		T2	68		T3	65
auto[CntIncrSt]	33830	1			T1	6		T2	68		T3	65
auto[CntProgSt]	1697881	1			T1	75		T2	3393		T3	576
auto[TransCheckSt]	26295	1			T1	6		T2	68		T3	48
auto[TokenHashSt]	40469772	1			T1	235		T2	406		T3	6545
auto[FlashRmaSt]	32916	1			T1	6		T2	110		T3	17
auto[TokenCheck0St]	12026	1			T1	6		T2	30		T3	17
auto[TokenCheck1St]	9039	1			T1	6		T2	10		T3	8
auto[TransProgSt]	495602	1			T1	111		T3	67		T4	655
auto[PostTransSt]	13379870	1			T1	1152		T2	10190		T3	11410
auto[ScrapSt]	142621	1			T38	3		T24	1481		T39	3
auto[EscalateSt]	7117328	1			T3	1503		T4	54532		T12	3721
auto[InvalidSt]	12036084	1			T4	98566		T12	1454		T13	1291

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2041	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12036084	1			T4	98566		T12	1454		T13	1291
EscalateSt	7117328	1			T3	1503		T4	54532		T12	3721
ScrapSt	142621	1			T38	3		T24	1481		T39	3
PostTransSt	13379870	1			T1	1152		T2	10190		T3	11410
TransProgSt	495602	1			T1	111		T3	67		T4	655
TokenCheck1St	9039	1			T1	6		T2	10		T3	8
TokenCheck0St	12026	1			T1	6		T2	30		T3	17
FlashRmaSt	32916	1			T1	6		T2	110		T3	17
TokenHashSt	40469772	1			T1	235		T2	406		T3	6545
TransCheckSt	26295	1			T1	6		T2	68		T3	48
CntProgSt	1697881	1			T1	75		T2	3393		T3	576
CntIncrSt	33830	1			T1	6		T2	68		T3	65
ClkMuxSt	34069	1			T1	6		T2	68		T3	65
IdleSt	22269647	1			T1	606		T2	2699		T3	7582
ResetSt	7483725	1			T1	545		T2	5855		T3	6341
arcs[ResetSt=>IdleSt]	52902	1			T1	6		T2	69		T3	66
arcs[IdleSt=>ScrapSt]	292	1			T38	1		T24	1		T39	1
arcs[IdleSt=>ClkMuxSt]	33887	1			T1	6		T2	68		T3	65
arcs[ClkMuxSt=>CntIncrSt]	33830	1			T1	6		T2	68		T3	65
arcs[CntIncrSt=>PostTransSt]	1692	1			T3	6		T4	6		T9	12
arcs[CntIncrSt=>CntProgSt]	32071	1			T1	6		T2	68		T3	59
arcs[CntProgSt=>PostTransSt]	4631	1			T3	11		T4	37		T12	10
arcs[CntProgSt=>TransCheckSt]	26295	1			T1	6		T2	68		T3	48
arcs[TransCheckSt=>PostTransSt]	3499	1			T2	31		T3	7		T4	17
arcs[TransCheckSt=>TokenHashSt]	22673	1			T1	6		T2	37		T3	41
arcs[TokenHashSt=>PostTransSt]	9819	1			T2	7		T3	24		T10	98
arcs[TokenHashSt=>FlashRmaSt]	12147	1			T1	6		T2	30		T3	17
arcs[FlashRmaSt=>TokenCheck0St]	12026	1			T1	6		T2	30		T3	17
arcs[TokenCheck0St=>PostTransSt]	2961	1			T2	20		T3	9		T4	9
arcs[TokenCheck0St=>TokenCheck1St]	9039	1			T1	6		T2	10		T3	8
arcs[TokenCheck1St=>PostTransSt]	606	1			T2	10		T3	1		T4	1
arcs[TransProgSt=>PostTransSt]	7487	1			T1	6		T3	7		T4	24
arcs[IdleSt=>EscalateSt]	211	1			T38	4		T50	5		T51	5
arcs[ClkMuxSt=>EscalateSt]	57	1			T38	1		T50	1		T39	1
arcs[CntIncrSt=>EscalateSt]	67	1			T38	2		T50	2		T39	1
arcs[CntProgSt=>EscalateSt]	1145	1			T38	31		T50	4		T39	39
arcs[TransCheckSt=>EscalateSt]	123	1			T50	3		T51	2		T56	3
arcs[TokenHashSt=>EscalateSt]	707	1			T55	2		T38	6		T50	11
arcs[FlashRmaSt=>EscalateSt]	121	1			T38	2		T50	4		T39	3
arcs[TokenCheck0St=>EscalateSt]	26	1			T38	1		T39	1		T54	1
arcs[TokenCheck1St=>EscalateSt]	148	1			T38	2		T50	2		T39	4
arcs[TransProgSt=>EscalateSt]	798	1			T38	20		T50	12		T39	26
arcs[PostTransSt=>EscalateSt]	4861	1			T3	11		T4	37		T12	10
arcs[InvalidSt=>EscalateSt]	14327	1			T4	155		T12	19		T13	8

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7483570	1			T1	545		T2	5855		T3	6341
auto[0]	auto[IdleSt]	22269523	1			T1	606		T2	2699		T3	7582
auto[0]	auto[ClkMuxSt]	34030	1			T1	6		T2	68		T3	65
auto[0]	auto[CntIncrSt]	33780	1			T1	6		T2	68		T3	65
auto[0]	auto[CntProgSt]	1697098	1			T1	75		T2	3393		T3	576
auto[0]	auto[TransCheckSt]	26217	1			T1	6		T2	68		T3	48
auto[0]	auto[TokenHashSt]	40469293	1			T1	235		T2	406		T3	6545
auto[0]	auto[FlashRmaSt]	32829	1			T1	6		T2	110		T3	17
auto[0]	auto[TokenCheck0St]	12007	1			T1	6		T2	30		T3	17
auto[0]	auto[TokenCheck1St]	8937	1			T1	6		T2	10		T3	8
auto[0]	auto[TransProgSt]	495067	1			T1	111		T3	67		T4	655
auto[0]	auto[PostTransSt]	13377390	1			T1	1152		T2	10190		T3	11404
auto[0]	auto[ScrapSt]	142575	1			T38	3		T24	1481		T39	3
auto[0]	auto[EscalateSt]	5689532	1			T3	915		T4	45556		T12	2545
auto[0]	auto[InvalidSt]	12028821	1			T4	98487		T12	1445		T13	1288
auto[1]	auto[ResetSt]	155	1			T38	3		T50	2		T39	2
auto[1]	auto[IdleSt]	124	1			T38	3		T50	2		T51	2
auto[1]	auto[ClkMuxSt]	39	1			T50	1		T39	1		T218	1
auto[1]	auto[CntIncrSt]	50	1			T38	2		T50	1		T219	2
auto[1]	auto[CntProgSt]	783	1			T38	18		T50	3		T39	26
auto[1]	auto[TransCheckSt]	78	1			T51	2		T56	2		T220	2
auto[1]	auto[TokenHashSt]	479	1			T55	1		T38	5		T50	4
auto[1]	auto[FlashRmaSt]	87	1			T38	2		T50	2		T39	3
auto[1]	auto[TokenCheck0St]	19	1			T54	1		T221	3		T222	1
auto[1]	auto[TokenCheck1St]	102	1			T38	2		T50	1		T39	3
auto[1]	auto[TransProgSt]	535	1			T38	14		T50	7		T39	14
auto[1]	auto[PostTransSt]	2480	1			T3	6		T4	13		T12	3
auto[1]	auto[ScrapSt]	46	1			T51	1		T218	1		T219	1
auto[1]	auto[EscalateSt]	1427796	1			T3	588		T4	8976		T12	1176
auto[1]	auto[InvalidSt]	7263	1			T4	79		T12	9		T13	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7483566	1			T1	545		T2	5855		T3	6341
auto[0]	auto[IdleSt]	22269496	1			T1	606		T2	2699		T3	7582
auto[0]	auto[ClkMuxSt]	34030	1			T1	6		T2	68		T3	65
auto[0]	auto[CntIncrSt]	33795	1			T1	6		T2	68		T3	65
auto[0]	auto[CntProgSt]	1697138	1			T1	75		T2	3393		T3	576
auto[0]	auto[TransCheckSt]	26211	1			T1	6		T2	68		T3	48
auto[0]	auto[TokenHashSt]	40469298	1			T1	235		T2	406		T3	6545
auto[0]	auto[FlashRmaSt]	32834	1			T1	6		T2	110		T3	17
auto[0]	auto[TokenCheck0St]	12009	1			T1	6		T2	30		T3	17
auto[0]	auto[TokenCheck1St]	8952	1			T1	6		T2	10		T3	8
auto[0]	auto[TransProgSt]	495079	1			T1	111		T3	67		T4	655
auto[0]	auto[PostTransSt]	13377409	1			T1	1152		T2	10190		T3	11405
auto[0]	auto[ScrapSt]	142566	1			T38	2		T24	1481		T39	2
auto[0]	auto[EscalateSt]	5720927	1			T3	1013		T4	44778		T12	2055
auto[0]	auto[InvalidSt]	12029020	1			T4	98490		T12	1444		T13	1286
auto[1]	auto[ResetSt]	159	1			T38	4		T50	1		T39	4
auto[1]	auto[IdleSt]	151	1			T38	2		T50	5		T51	4
auto[1]	auto[ClkMuxSt]	39	1			T38	1		T50	1		T39	1
auto[1]	auto[CntIncrSt]	35	1			T38	1		T50	1		T39	1
auto[1]	auto[CntProgSt]	743	1			T38	23		T50	4		T39	28
auto[1]	auto[TransCheckSt]	84	1			T50	3		T51	2		T56	2
auto[1]	auto[TokenHashSt]	474	1			T55	1		T38	3		T50	11
auto[1]	auto[FlashRmaSt]	82	1			T38	2		T50	4		T39	2
auto[1]	auto[TokenCheck0St]	17	1			T38	1		T39	1		T221	2
auto[1]	auto[TokenCheck1St]	87	1			T38	1		T50	1		T39	1
auto[1]	auto[TransProgSt]	523	1			T38	13		T50	8		T39	21
auto[1]	auto[PostTransSt]	2461	1			T3	5		T4	24		T12	7
auto[1]	auto[ScrapSt]	55	1			T38	1		T39	1		T51	1
auto[1]	auto[EscalateSt]	1396401	1			T3	490		T4	9754		T12	1666
auto[1]	auto[InvalidSt]	7064	1			T4	76		T12	10		T13	5