---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmCtrlKmacIfFsmCheck_A	0	0	100522477	0	0	0
tb.dut.FpvSecCmCtrlLcCntCheck_A	0	0	94669406	0	0	0
tb.dut.FpvSecCmCtrlLcFsmCheck_A	0	0	100684473	0	0	0
tb.dut.FpvSecCmTapRegWeOnehotCheck_A	0	0	103310143	0	0	0
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A	0	0	103310143	0	0	2152

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertTxKnown_A	0	0	103310143	99230367	0	0
tb.dut.DecLcCountWidthCheck_A	0	0	802	802	0	0
tb.dut.DecLcIdStateWidthCheck_A	0	0	802	802	0	0
tb.dut.DecLcStateWidthCheck_A	0	0	802	802	0	0
tb.dut.FpvSecCmCtrlLcStateCheck_A	0	0	97506002	2	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	103310143	60	0	0
tb.dut.LcCheckBypassEnKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcClkBypReqKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcCpuEnKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcCreatorSwRwEn_A	0	0	103310143	99230367	0	0
tb.dut.LcDftEnKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcEscalateEnKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcFlashRmaReqKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcFlashRmaSeedKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcHwDebugEnKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcIsoSwRwEn_A	0	0	103310143	99230367	0	0
tb.dut.LcIsoSwWrEn_A	0	0	103310143	99230367	0	0
tb.dut.LcKeymgrDiv_A	0	0	103310143	99230367	0	0
tb.dut.LcKeymgrEnKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcNvmDebugEnKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcOtpProgramKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcOtpTokenKnown_A	0	0	103310143	99230367	0	0
tb.dut.LcOwnerSwRwEn_A	0	0	103310143	99230367	0	0
tb.dut.LcSeedHwRdEn_A	0	0	103310143	99230367	0	0
tb.dut.NumTokenWordsCheck_A	0	0	802	802	0	0
tb.dut.OtpTestCtrlWidth_A	0	0	802	802	0	0
tb.dut.PwrLcKnown_A	0	0	103310143	99230367	0	0
tb.dut.TlOKnown	0	0	103310143	99230367	0	0
tb.dut.lc_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	105242467	15253	0	0
tb.dut.lc_ctrl_csr_assert.claim_transition_if_regwen_rd_A	0	0	105242467	921	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	105242467	3654027	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	105242467	101120396	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	105242467	101120396	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	105242467	5186865	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	105242467	101120396	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	105242467	101120396	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	987	987	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	105243079	384254	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	105242467	6755	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	105243079	1347132	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	105243079	1607997	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	105242467	7192	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	105243079	3654073	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	105243079	5186900	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	105243079	3654073	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	105243079	5186900	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	105243079	5186900	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	105243079	5186900	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	105242467	4533	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	105242467	3836	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	987	987	0	0
tb.dut.u_lc_ctrl_fsm.ClkBypStaysOnOnceAsserted_A	0	0	103310143	5021485	0	63
tb.dut.u_lc_ctrl_fsm.EscStaysOnOnceAsserted_A	0	0	103310143	19204343	0	8
tb.dut.u_lc_ctrl_fsm.FlashRmaStaysOnOnceAsserted_A	0	0	103310143	604032	0	6
tb.dut.u_lc_ctrl_fsm.FsmStateKnown_A	0	0	103310143	99230367	0	0
tb.dut.u_lc_ctrl_fsm.LcCntKnown_A	0	0	103310143	99230367	0	0
tb.dut.u_lc_ctrl_fsm.LcStateKnown_A	0	0	103310143	99230367	0	0
tb.dut.u_lc_ctrl_fsm.NoClkBypInProdStates_A	0	0	103310143	13794662	0	0
tb.dut.u_lc_ctrl_fsm.SecCmCFITerminal0_A	0	0	103310143	13353998	0	0
tb.dut.u_lc_ctrl_fsm.SecCmCFITerminal1_A	0	0	103310143	92990	0	0
tb.dut.u_lc_ctrl_fsm.SecCmCFITerminal2_A	0	0	103310143	7094419	0	0
tb.dut.u_lc_ctrl_fsm.SecCmCFITerminal3_A	0	0	103310143	12033869	0	0
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.NumCopiesMustBeGreaterZero_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.OutputsKnown_A	0	0	103063584	99022050	0	0
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A	0	0	103063584	98860161	0	2376
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.NumCopiesMustBeGreaterZero_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.OutputsKnown_A	0	0	103063584	99022050	0	0
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A	0	0	103063584	98860161	0	2376
tb.dut.u_lc_ctrl_fsm.u_cnt_regs.AssertConnected_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_cnt_regs_A	0	0	94669406	91050700	0	0
tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs.AssertConnected_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs_A	0	0	100684473	96771745	0	0
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.FsmInScrap_A	0	0	103310143	19223319	0	0
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.LcKeymgrDivUnique0_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.LcKeymgrDivUnique1_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.LcKeymgrDivUnique2_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.LcKeymgrDivUnique3_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.SignalsAreOffWhenNotEnabled_A	0	0	103310143	2092151	0	0
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.StateInScrap_A	0	0	103310143	6330	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.NumCopiesMustBeGreaterZero_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.OutputsKnown_A	0	0	103122186	99081699	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.OutputDelay_A	0	0	103122186	98919843	0	2394
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.NumCopiesMustBeGreaterZero_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.OutputsKnown_A	0	0	103063584	99022050	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_no_flops.OutputDelay_A	0	0	103063584	99022050	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.NumCopiesMustBeGreaterZero_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.OutputsKnown_A	0	0	103006928	98969287	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_no_flops.OutputDelay_A	0	0	103006928	98969287	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.NumCopiesMustBeGreaterZero_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.OutputsKnown_A	0	0	103041499	99000546	0	0
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_no_flops.OutputDelay_A	0	0	103041499	99000546	0	0
tb.dut.u_lc_ctrl_fsm.u_state_regs.AssertConnected_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_fsm.u_state_regs_A	0	0	97506002	93894883	0	0
tb.dut.u_lc_ctrl_kmac_if.DataStable_A	0	0	103310143	40447806	0	0
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.SyncReqAckAckNeedsReq	0	0	99356593	20641	0	0
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in.u_prim_sync_reqack.SyncReqAckHoldReq	0	0	103310143	21966	0	0
tb.dut.u_lc_ctrl_kmac_if.u_state_regs.AssertConnected_A	0	0	802	802	0	0
tb.dut.u_lc_ctrl_kmac_if.u_state_regs_A	0	0	100522477	96610302	0	0
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic.selKnown0	0	0	80153394	80152592	0	0
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic.selKnown1	0	0	103310143	103309341	0	0
tb.dut.u_prim_lc_sync.NumCopiesMustBeGreaterZero_A	0	0	802	802	0	0
tb.dut.u_prim_lc_sync.OutputsKnown_A	0	0	103310143	99230367	0	0
tb.dut.u_prim_lc_sync.gen_no_flops.OutputDelay_A	0	0	103310143	99230367	0	0
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic.selKnown0	0	0	54471	53669	0	0
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic.selKnown1	0	0	912	110	0	0
tb.dut.u_reg.en2addrHit	0	0	105242467	3561669	0	0
tb.dut.u_reg.reAfterRv	0	0	105242467	3561669	0	0
tb.dut.u_reg.rePulse	0	0	105242467	3240841	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	987	987	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	987	987	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	987	987	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	987	987	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	987	987	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	987	987	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	987	987	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	987	987	0	0
tb.dut.u_reg.wePulse	0	0	105242467	320828	0	0
tb.dut.u_reg_tap.en2addrHit	0	0	105242467	393285	0	0
tb.dut.u_reg_tap.reAfterRv	0	0	105242467	393285	0	0
tb.dut.u_reg_tap.rePulse	0	0	105242467	251392	0	0
tb.dut.u_reg_tap.u_chk.PayLoadWidthCheck	0	0	987	987	0	0
tb.dut.u_reg_tap.u_reg_if.AllowedLatency_A	0	0	987	987	0	0
tb.dut.u_reg_tap.u_reg_if.MatchedWidthAssert	0	0	987	987	0	0
tb.dut.u_reg_tap.u_reg_if.u_err.dataWidthOnly32_A	0	0	987	987	0	0
tb.dut.u_reg_tap.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	987	987	0	0
tb.dut.u_reg_tap.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	987	987	0	0
tb.dut.u_reg_tap.u_rsp_intg_gen.DataWidthCheck_A	0	0	987	987	0	0
tb.dut.u_reg_tap.u_rsp_intg_gen.PayLoadWidthCheck	0	0	987	987	0	0
tb.dut.u_reg_tap.wePulse	0	0	105242467	141893	0	0
tb.dut.u_tap_tlul_host.DontExceeedMaxReqs	0	0	103310143	383906	0	0
tb.dut.u_tap_tlul_host.u_cmd_intg_gen.PayMaxWidthCheck_A	0	0	802	802	0	0
tb.dut.u_tap_tlul_host.u_rsp_chk.PayLoadWidthCheck	0	0	802	802	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_lc_ctrl_fsm.ClkBypStaysOnOnceAsserted_A	0	0	103310143	5021485	0	63
tb.dut.u_lc_ctrl_fsm.EscStaysOnOnceAsserted_A	0	0	103310143	19204343	0	8
tb.dut.u_lc_ctrl_fsm.FlashRmaStaysOnOnceAsserted_A	0	0	103310143	604032	0	6
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A	0	0	103310143	0	0	2152
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A	0	0	103063584	98860161	0	2376
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A	0	0	103063584	98860161	0	2376
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.OutputDelay_A	0	0	103122186	98919843	0	2394

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	105243079	815	815	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	105243079	65	65	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	105243079	68	68	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	105243079	25	25	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	105243079	29	29	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	105243079	23	23	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	105243079	34	34	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	105243079	3242	3242	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	105243079	8795	8795	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	105243079	919807	919807	300

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	105243079	815	815	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	105243079	65	65	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	105243079	68	68	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	105243079	25	25	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	105243079	29	29	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	105243079	23	23	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	105243079	34	34	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	105243079	3242	3242	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	105243079	8795	8795	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	105243079	919807	919807	300