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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.96 97.92 96.21 93.40 97.62 98.52 98.76 96.29


Total test records in report: 987
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T817 /workspace/coverage/default/18.lc_ctrl_alert_test.643036840 Jul 16 06:30:08 PM PDT 24 Jul 16 06:30:09 PM PDT 24 20463979 ps
T818 /workspace/coverage/default/21.lc_ctrl_security_escalation.1525786442 Jul 16 06:30:20 PM PDT 24 Jul 16 06:30:28 PM PDT 24 1382645216 ps
T819 /workspace/coverage/default/27.lc_ctrl_smoke.1217850992 Jul 16 06:30:38 PM PDT 24 Jul 16 06:30:41 PM PDT 24 350258114 ps
T820 /workspace/coverage/default/38.lc_ctrl_alert_test.20515932 Jul 16 06:31:43 PM PDT 24 Jul 16 06:31:45 PM PDT 24 60516445 ps
T821 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1116835005 Jul 16 06:32:18 PM PDT 24 Jul 16 06:32:20 PM PDT 24 15844839 ps
T822 /workspace/coverage/default/26.lc_ctrl_jtag_access.3801705435 Jul 16 06:30:38 PM PDT 24 Jul 16 06:30:45 PM PDT 24 838883135 ps
T823 /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2660486640 Jul 16 06:28:29 PM PDT 24 Jul 16 06:28:35 PM PDT 24 713323599 ps
T824 /workspace/coverage/default/43.lc_ctrl_errors.2348954399 Jul 16 06:32:04 PM PDT 24 Jul 16 06:32:24 PM PDT 24 1190481504 ps
T825 /workspace/coverage/default/11.lc_ctrl_smoke.3017480215 Jul 16 06:29:09 PM PDT 24 Jul 16 06:29:12 PM PDT 24 89897759 ps
T213 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.297365007 Jul 16 06:28:33 PM PDT 24 Jul 16 06:28:35 PM PDT 24 92974186 ps
T826 /workspace/coverage/default/23.lc_ctrl_errors.3671713757 Jul 16 06:30:28 PM PDT 24 Jul 16 06:30:49 PM PDT 24 439973647 ps
T827 /workspace/coverage/default/33.lc_ctrl_alert_test.1445183188 Jul 16 06:31:15 PM PDT 24 Jul 16 06:31:17 PM PDT 24 46081052 ps
T73 /workspace/coverage/default/47.lc_ctrl_alert_test.2273771195 Jul 16 06:32:16 PM PDT 24 Jul 16 06:32:18 PM PDT 24 14772612 ps
T828 /workspace/coverage/default/38.lc_ctrl_stress_all.1823615915 Jul 16 06:31:44 PM PDT 24 Jul 16 06:34:32 PM PDT 24 7951148752 ps
T829 /workspace/coverage/default/34.lc_ctrl_sec_token_mux.4112592844 Jul 16 06:31:20 PM PDT 24 Jul 16 06:31:35 PM PDT 24 2947758413 ps
T830 /workspace/coverage/default/20.lc_ctrl_alert_test.2286135416 Jul 16 06:30:19 PM PDT 24 Jul 16 06:30:21 PM PDT 24 13515869 ps
T831 /workspace/coverage/default/49.lc_ctrl_smoke.1473811306 Jul 16 06:32:16 PM PDT 24 Jul 16 06:32:19 PM PDT 24 14383906 ps
T832 /workspace/coverage/default/0.lc_ctrl_security_escalation.1271184103 Jul 16 06:27:16 PM PDT 24 Jul 16 06:27:28 PM PDT 24 1925027887 ps
T833 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2569450960 Jul 16 06:27:48 PM PDT 24 Jul 16 06:27:52 PM PDT 24 736013853 ps
T834 /workspace/coverage/default/48.lc_ctrl_errors.3408660938 Jul 16 06:32:17 PM PDT 24 Jul 16 06:32:32 PM PDT 24 816334215 ps
T835 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3538645309 Jul 16 06:29:25 PM PDT 24 Jul 16 06:29:27 PM PDT 24 16868174 ps
T836 /workspace/coverage/default/44.lc_ctrl_jtag_access.1550550014 Jul 16 06:32:06 PM PDT 24 Jul 16 06:32:17 PM PDT 24 1697777880 ps
T837 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2151146387 Jul 16 06:27:25 PM PDT 24 Jul 16 06:27:39 PM PDT 24 4109554296 ps
T838 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1674689401 Jul 16 06:28:36 PM PDT 24 Jul 16 06:28:48 PM PDT 24 398220511 ps
T839 /workspace/coverage/default/21.lc_ctrl_stress_all.1033729818 Jul 16 06:30:27 PM PDT 24 Jul 16 06:31:32 PM PDT 24 2706282492 ps
T840 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1282076771 Jul 16 06:30:27 PM PDT 24 Jul 16 06:30:30 PM PDT 24 27520685 ps
T841 /workspace/coverage/default/11.lc_ctrl_jtag_errors.1399706684 Jul 16 06:29:10 PM PDT 24 Jul 16 06:30:08 PM PDT 24 1909008223 ps
T163 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2837565774 Jul 16 06:30:27 PM PDT 24 Jul 16 06:55:53 PM PDT 24 417438317165 ps
T842 /workspace/coverage/default/26.lc_ctrl_state_post_trans.1066989685 Jul 16 06:30:44 PM PDT 24 Jul 16 06:30:52 PM PDT 24 213095901 ps
T843 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3158681621 Jul 16 06:28:07 PM PDT 24 Jul 16 06:28:18 PM PDT 24 1239283074 ps
T844 /workspace/coverage/default/47.lc_ctrl_errors.1599471500 Jul 16 06:32:16 PM PDT 24 Jul 16 06:32:30 PM PDT 24 1074567387 ps
T845 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3381580233 Jul 16 06:29:56 PM PDT 24 Jul 16 06:30:17 PM PDT 24 3094109698 ps
T846 /workspace/coverage/default/0.lc_ctrl_state_failure.3596041619 Jul 16 06:27:16 PM PDT 24 Jul 16 06:27:37 PM PDT 24 847226681 ps
T847 /workspace/coverage/default/49.lc_ctrl_stress_all.2259469632 Jul 16 06:32:31 PM PDT 24 Jul 16 06:33:09 PM PDT 24 1614324096 ps
T848 /workspace/coverage/default/45.lc_ctrl_state_post_trans.1514721274 Jul 16 06:32:08 PM PDT 24 Jul 16 06:32:18 PM PDT 24 129884759 ps
T849 /workspace/coverage/default/45.lc_ctrl_sec_mubi.2766725921 Jul 16 06:32:10 PM PDT 24 Jul 16 06:32:24 PM PDT 24 1453061864 ps
T850 /workspace/coverage/default/36.lc_ctrl_state_post_trans.2069879952 Jul 16 06:31:33 PM PDT 24 Jul 16 06:31:40 PM PDT 24 53257313 ps
T851 /workspace/coverage/default/31.lc_ctrl_prog_failure.2793767121 Jul 16 06:31:05 PM PDT 24 Jul 16 06:31:09 PM PDT 24 259849983 ps
T852 /workspace/coverage/default/31.lc_ctrl_jtag_access.2672837705 Jul 16 06:31:04 PM PDT 24 Jul 16 06:31:11 PM PDT 24 621536780 ps
T853 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1686187212 Jul 16 06:27:56 PM PDT 24 Jul 16 06:27:57 PM PDT 24 21576425 ps
T854 /workspace/coverage/default/17.lc_ctrl_stress_all.3639949735 Jul 16 06:29:56 PM PDT 24 Jul 16 06:33:56 PM PDT 24 27016329460 ps
T855 /workspace/coverage/default/27.lc_ctrl_sec_mubi.1744509710 Jul 16 06:30:51 PM PDT 24 Jul 16 06:31:14 PM PDT 24 540390348 ps
T74 /workspace/coverage/default/32.lc_ctrl_alert_test.2583178641 Jul 16 06:31:16 PM PDT 24 Jul 16 06:31:19 PM PDT 24 13289300 ps
T856 /workspace/coverage/default/6.lc_ctrl_state_post_trans.3022753254 Jul 16 06:28:21 PM PDT 24 Jul 16 06:28:30 PM PDT 24 83232912 ps
T857 /workspace/coverage/default/43.lc_ctrl_state_failure.2201485148 Jul 16 06:31:58 PM PDT 24 Jul 16 06:32:32 PM PDT 24 1212986648 ps
T858 /workspace/coverage/default/12.lc_ctrl_state_post_trans.3254980925 Jul 16 06:29:24 PM PDT 24 Jul 16 06:29:35 PM PDT 24 240818357 ps
T859 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3286314676 Jul 16 06:29:49 PM PDT 24 Jul 16 06:29:59 PM PDT 24 1822639132 ps
T860 /workspace/coverage/default/45.lc_ctrl_security_escalation.1174012564 Jul 16 06:32:07 PM PDT 24 Jul 16 06:32:22 PM PDT 24 269884102 ps
T79 /workspace/coverage/default/2.lc_ctrl_stress_all.191287399 Jul 16 06:27:48 PM PDT 24 Jul 16 06:30:58 PM PDT 24 8159252342 ps
T861 /workspace/coverage/default/30.lc_ctrl_security_escalation.577711211 Jul 16 06:31:03 PM PDT 24 Jul 16 06:31:12 PM PDT 24 202538056 ps
T862 /workspace/coverage/default/9.lc_ctrl_smoke.3006777491 Jul 16 06:28:48 PM PDT 24 Jul 16 06:28:52 PM PDT 24 107797709 ps
T863 /workspace/coverage/default/7.lc_ctrl_security_escalation.2568539255 Jul 16 06:28:29 PM PDT 24 Jul 16 06:28:45 PM PDT 24 1466389160 ps
T113 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1865421399 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:49 PM PDT 24 68987352 ps
T116 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2042363191 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:56 PM PDT 24 86980698 ps
T122 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.687373014 Jul 16 05:21:49 PM PDT 24 Jul 16 05:21:51 PM PDT 24 34422625 ps
T114 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1288320323 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:54 PM PDT 24 398503388 ps
T146 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4100454743 Jul 16 05:21:46 PM PDT 24 Jul 16 05:21:48 PM PDT 24 190895483 ps
T123 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3433145831 Jul 16 05:21:47 PM PDT 24 Jul 16 05:22:05 PM PDT 24 728497519 ps
T864 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3468112543 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:36 PM PDT 24 133616605 ps
T865 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.966143610 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:55 PM PDT 24 101945460 ps
T202 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.401062936 Jul 16 05:21:54 PM PDT 24 Jul 16 05:21:57 PM PDT 24 54645948 ps
T147 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1759562947 Jul 16 05:22:04 PM PDT 24 Jul 16 05:22:06 PM PDT 24 24800279 ps
T164 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3384099843 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:53 PM PDT 24 70147593 ps
T165 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1606034830 Jul 16 05:21:35 PM PDT 24 Jul 16 05:21:38 PM PDT 24 100083055 ps
T121 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3663494421 Jul 16 05:21:46 PM PDT 24 Jul 16 05:21:48 PM PDT 24 85971264 ps
T145 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.479181305 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:36 PM PDT 24 157990276 ps
T115 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3965391321 Jul 16 05:22:11 PM PDT 24 Jul 16 05:22:13 PM PDT 24 20751715 ps
T203 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2604089282 Jul 16 05:24:17 PM PDT 24 Jul 16 05:24:18 PM PDT 24 22808641 ps
T866 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2005001392 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:56 PM PDT 24 45829821 ps
T117 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1663605596 Jul 16 05:21:49 PM PDT 24 Jul 16 05:21:56 PM PDT 24 198275105 ps
T197 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2592203123 Jul 16 05:23:04 PM PDT 24 Jul 16 05:23:06 PM PDT 24 36495517 ps
T204 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1571430304 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:35 PM PDT 24 23578124 ps
T118 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.116016837 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:57 PM PDT 24 234760978 ps
T867 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3974968153 Jul 16 05:21:35 PM PDT 24 Jul 16 05:21:37 PM PDT 24 88458458 ps
T868 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2188768512 Jul 16 05:22:19 PM PDT 24 Jul 16 05:22:21 PM PDT 24 18549518 ps
T869 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3626883104 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:35 PM PDT 24 49156182 ps
T205 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2202816779 Jul 16 05:25:13 PM PDT 24 Jul 16 05:25:16 PM PDT 24 732513399 ps
T870 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1519100049 Jul 16 05:21:48 PM PDT 24 Jul 16 05:22:11 PM PDT 24 1811985218 ps
T871 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3288343553 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:51 PM PDT 24 81654165 ps
T206 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4037844891 Jul 16 05:21:46 PM PDT 24 Jul 16 05:21:48 PM PDT 24 23668169 ps
T872 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3489519934 Jul 16 05:25:52 PM PDT 24 Jul 16 05:25:55 PM PDT 24 98866443 ps
T873 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4139242990 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:37 PM PDT 24 262624682 ps
T874 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1767407326 Jul 16 05:22:01 PM PDT 24 Jul 16 05:22:03 PM PDT 24 29313553 ps
T124 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2916905092 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:57 PM PDT 24 240968106 ps
T158 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2350033140 Jul 16 05:24:17 PM PDT 24 Jul 16 05:24:19 PM PDT 24 148036003 ps
T875 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1328364408 Jul 16 05:22:45 PM PDT 24 Jul 16 05:22:49 PM PDT 24 414719729 ps
T207 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2343174089 Jul 16 05:21:49 PM PDT 24 Jul 16 05:21:52 PM PDT 24 146894498 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1711842725 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:37 PM PDT 24 94142373 ps
T134 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1676218090 Jul 16 05:23:54 PM PDT 24 Jul 16 05:23:57 PM PDT 24 203800770 ps
T119 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1734956479 Jul 16 05:25:43 PM PDT 24 Jul 16 05:25:48 PM PDT 24 613280696 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4125582060 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:54 PM PDT 24 904030857 ps
T120 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3562145173 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:54 PM PDT 24 327409741 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2789489096 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:37 PM PDT 24 184578291 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2736372391 Jul 16 05:21:31 PM PDT 24 Jul 16 05:21:33 PM PDT 24 82700302 ps
T159 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4197821080 Jul 16 05:22:16 PM PDT 24 Jul 16 05:22:18 PM PDT 24 217099031 ps
T133 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1137099224 Jul 16 05:23:48 PM PDT 24 Jul 16 05:23:54 PM PDT 24 509609672 ps
T880 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4009957465 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:53 PM PDT 24 78686873 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3291188176 Jul 16 05:21:36 PM PDT 24 Jul 16 05:21:39 PM PDT 24 46775880 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3644404938 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:56 PM PDT 24 3158693807 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1452266324 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:38 PM PDT 24 542348333 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2649089020 Jul 16 05:21:59 PM PDT 24 Jul 16 05:22:00 PM PDT 24 13959873 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.333789682 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:36 PM PDT 24 77196074 ps
T128 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2828404338 Jul 16 05:25:13 PM PDT 24 Jul 16 05:25:16 PM PDT 24 54712478 ps
T160 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.325250074 Jul 16 05:21:54 PM PDT 24 Jul 16 05:21:57 PM PDT 24 21909444 ps
T885 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2062862628 Jul 16 05:22:44 PM PDT 24 Jul 16 05:22:46 PM PDT 24 50975978 ps
T188 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2443462675 Jul 16 05:22:03 PM PDT 24 Jul 16 05:22:04 PM PDT 24 23108492 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.867597504 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:54 PM PDT 24 42470556 ps
T189 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1636715176 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:56 PM PDT 24 20864437 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.62937544 Jul 16 05:22:17 PM PDT 24 Jul 16 05:22:20 PM PDT 24 331577699 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1404943947 Jul 16 05:22:15 PM PDT 24 Jul 16 05:22:19 PM PDT 24 200496688 ps
T125 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3730824901 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:35 PM PDT 24 51098313 ps
T888 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1185369035 Jul 16 05:21:51 PM PDT 24 Jul 16 05:22:04 PM PDT 24 1751560810 ps
T889 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2863410670 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:57 PM PDT 24 38126944 ps
T161 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2958483995 Jul 16 05:21:52 PM PDT 24 Jul 16 05:21:55 PM PDT 24 19517586 ps
T890 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2143832591 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:54 PM PDT 24 189137120 ps
T891 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.666813152 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:36 PM PDT 24 44791998 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3988853069 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:49 PM PDT 24 116206149 ps
T138 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4158396926 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:50 PM PDT 24 122035023 ps
T893 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1382052002 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:51 PM PDT 24 142720361 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3634074256 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:50 PM PDT 24 251678053 ps
T895 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3604498652 Jul 16 05:23:36 PM PDT 24 Jul 16 05:23:39 PM PDT 24 38124860 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1328920814 Jul 16 05:26:44 PM PDT 24 Jul 16 05:26:46 PM PDT 24 261029819 ps
T897 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1161482435 Jul 16 05:21:54 PM PDT 24 Jul 16 05:21:58 PM PDT 24 50341446 ps
T898 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.671702886 Jul 16 05:22:38 PM PDT 24 Jul 16 05:22:40 PM PDT 24 57867641 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4024840067 Jul 16 05:23:33 PM PDT 24 Jul 16 05:23:35 PM PDT 24 24004929 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1965984239 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:36 PM PDT 24 64912165 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1999151882 Jul 16 05:21:31 PM PDT 24 Jul 16 05:21:33 PM PDT 24 20971124 ps
T902 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1918418898 Jul 16 05:21:35 PM PDT 24 Jul 16 05:21:39 PM PDT 24 100615155 ps
T903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.634612817 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:50 PM PDT 24 182257986 ps
T904 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1118581524 Jul 16 05:21:46 PM PDT 24 Jul 16 05:21:48 PM PDT 24 377605350 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2119320463 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:35 PM PDT 24 132892595 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3378454366 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:36 PM PDT 24 447506462 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2805991720 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:55 PM PDT 24 863195375 ps
T908 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3056106205 Jul 16 05:25:13 PM PDT 24 Jul 16 05:25:16 PM PDT 24 49100401 ps
T132 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2359948964 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:55 PM PDT 24 112461643 ps
T130 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.334725995 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:55 PM PDT 24 734628706 ps
T131 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3664993358 Jul 16 05:22:03 PM PDT 24 Jul 16 05:22:08 PM PDT 24 101522945 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1380935213 Jul 16 05:23:54 PM PDT 24 Jul 16 05:24:20 PM PDT 24 9300690947 ps
T910 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1923079826 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:56 PM PDT 24 202918269 ps
T911 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.126187253 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:51 PM PDT 24 44120916 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4099017896 Jul 16 05:21:32 PM PDT 24 Jul 16 05:21:38 PM PDT 24 1861742248 ps
T139 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1167965575 Jul 16 05:26:01 PM PDT 24 Jul 16 05:26:05 PM PDT 24 153485152 ps
T913 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2371629883 Jul 16 05:28:04 PM PDT 24 Jul 16 05:28:06 PM PDT 24 18989962 ps
T914 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.300991372 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:50 PM PDT 24 52577223 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3892557089 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:36 PM PDT 24 45241477 ps
T916 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.722078187 Jul 16 05:21:57 PM PDT 24 Jul 16 05:21:59 PM PDT 24 61290829 ps
T917 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.737663099 Jul 16 05:22:01 PM PDT 24 Jul 16 05:22:03 PM PDT 24 98942367 ps
T190 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3168641545 Jul 16 05:21:45 PM PDT 24 Jul 16 05:21:46 PM PDT 24 23022621 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3932565713 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:52 PM PDT 24 1553694977 ps
T191 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1942765602 Jul 16 05:22:22 PM PDT 24 Jul 16 05:22:24 PM PDT 24 25358995 ps
T919 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.792178305 Jul 16 05:21:57 PM PDT 24 Jul 16 05:21:59 PM PDT 24 24846298 ps
T920 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2096826468 Jul 16 05:22:03 PM PDT 24 Jul 16 05:22:04 PM PDT 24 26804814 ps
T921 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1261287132 Jul 16 05:24:37 PM PDT 24 Jul 16 05:24:40 PM PDT 24 392757575 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4241146018 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:54 PM PDT 24 193430432 ps
T923 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.233145010 Jul 16 05:28:05 PM PDT 24 Jul 16 05:28:06 PM PDT 24 14430588 ps
T924 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2343661598 Jul 16 05:21:49 PM PDT 24 Jul 16 05:21:52 PM PDT 24 59337122 ps
T137 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3775703471 Jul 16 05:25:52 PM PDT 24 Jul 16 05:25:56 PM PDT 24 117642104 ps
T192 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.578394851 Jul 16 05:21:36 PM PDT 24 Jul 16 05:21:38 PM PDT 24 69183522 ps
T193 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.558900642 Jul 16 05:22:05 PM PDT 24 Jul 16 05:22:07 PM PDT 24 13974317 ps
T140 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3384630721 Jul 16 05:21:45 PM PDT 24 Jul 16 05:21:48 PM PDT 24 74149083 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1364788669 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:37 PM PDT 24 143499644 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4073735838 Jul 16 05:21:42 PM PDT 24 Jul 16 05:21:44 PM PDT 24 54322477 ps
T142 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2326198138 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:58 PM PDT 24 167767319 ps
T195 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.467240310 Jul 16 05:21:52 PM PDT 24 Jul 16 05:21:54 PM PDT 24 16445112 ps
T926 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2290564618 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:54 PM PDT 24 326036494 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3329788740 Jul 16 05:23:52 PM PDT 24 Jul 16 05:23:54 PM PDT 24 23297793 ps
T928 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2901516369 Jul 16 05:21:54 PM PDT 24 Jul 16 05:21:56 PM PDT 24 13664138 ps
T929 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3689608089 Jul 16 05:24:56 PM PDT 24 Jul 16 05:25:02 PM PDT 24 3028224388 ps
T930 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3935080908 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:58 PM PDT 24 42220563 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3771789599 Jul 16 05:26:43 PM PDT 24 Jul 16 05:26:46 PM PDT 24 52855892 ps
T932 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.940399307 Jul 16 05:21:32 PM PDT 24 Jul 16 05:21:36 PM PDT 24 125750260 ps
T933 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3834073622 Jul 16 05:23:04 PM PDT 24 Jul 16 05:23:06 PM PDT 24 46206644 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1054990029 Jul 16 05:21:30 PM PDT 24 Jul 16 05:21:32 PM PDT 24 308282270 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3271251134 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:59 PM PDT 24 422232943 ps
T936 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2992758165 Jul 16 05:21:32 PM PDT 24 Jul 16 05:21:36 PM PDT 24 105310309 ps
T196 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.333180646 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:48 PM PDT 24 43948119 ps
T937 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4181096412 Jul 16 05:21:45 PM PDT 24 Jul 16 05:21:48 PM PDT 24 259977531 ps
T938 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3994564772 Jul 16 05:27:07 PM PDT 24 Jul 16 05:27:09 PM PDT 24 100088713 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2818517414 Jul 16 05:26:44 PM PDT 24 Jul 16 05:26:54 PM PDT 24 365875588 ps
T940 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1396247507 Jul 16 05:25:50 PM PDT 24 Jul 16 05:25:55 PM PDT 24 186048441 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.888812088 Jul 16 05:27:48 PM PDT 24 Jul 16 05:27:53 PM PDT 24 143221583 ps
T942 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.818874154 Jul 16 05:25:15 PM PDT 24 Jul 16 05:25:18 PM PDT 24 72013953 ps
T943 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2834089488 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:54 PM PDT 24 30582686 ps
T944 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4267625628 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:49 PM PDT 24 54136774 ps
T198 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2972536785 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:37 PM PDT 24 66069435 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4172428301 Jul 16 05:21:49 PM PDT 24 Jul 16 05:21:52 PM PDT 24 22616234 ps
T199 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4012443638 Jul 16 05:25:50 PM PDT 24 Jul 16 05:25:51 PM PDT 24 14453991 ps
T126 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3418968257 Jul 16 05:22:45 PM PDT 24 Jul 16 05:22:48 PM PDT 24 406427979 ps
T946 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.665371347 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:50 PM PDT 24 252574917 ps
T947 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.907279998 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:53 PM PDT 24 28503283 ps
T948 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.634260492 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:36 PM PDT 24 74042203 ps
T949 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4024643063 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:43 PM PDT 24 1696237266 ps
T136 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1950854787 Jul 16 05:21:46 PM PDT 24 Jul 16 05:21:49 PM PDT 24 579687263 ps
T200 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2516369175 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:49 PM PDT 24 35315911 ps
T143 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1597716576 Jul 16 05:22:04 PM PDT 24 Jul 16 05:22:07 PM PDT 24 68989939 ps
T950 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1424802757 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:35 PM PDT 24 48782605 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.220879835 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:56 PM PDT 24 55636099 ps
T127 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1795648954 Jul 16 05:21:32 PM PDT 24 Jul 16 05:21:36 PM PDT 24 117612192 ps
T952 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1735523410 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:34 PM PDT 24 20844449 ps
T144 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1378239020 Jul 16 05:21:49 PM PDT 24 Jul 16 05:21:53 PM PDT 24 158451468 ps
T201 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3094877146 Jul 16 05:23:36 PM PDT 24 Jul 16 05:23:38 PM PDT 24 25996316 ps
T953 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1935923648 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:38 PM PDT 24 4351835557 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2392656900 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:56 PM PDT 24 39692522 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3482687789 Jul 16 05:24:57 PM PDT 24 Jul 16 05:24:59 PM PDT 24 32396878 ps
T956 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1253101533 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:54 PM PDT 24 106798509 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1295979488 Jul 16 05:22:21 PM PDT 24 Jul 16 05:22:23 PM PDT 24 24625206 ps
T141 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1044233478 Jul 16 05:22:44 PM PDT 24 Jul 16 05:22:48 PM PDT 24 91514268 ps
T958 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1590419958 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:36 PM PDT 24 42621175 ps
T959 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2939148667 Jul 16 05:22:10 PM PDT 24 Jul 16 05:22:12 PM PDT 24 93283987 ps
T960 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3762857444 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:55 PM PDT 24 126945656 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3492856969 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:49 PM PDT 24 141883144 ps
T962 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2562362466 Jul 16 05:24:54 PM PDT 24 Jul 16 05:24:56 PM PDT 24 22153004 ps
T963 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2087209295 Jul 16 05:23:03 PM PDT 24 Jul 16 05:23:12 PM PDT 24 2475570281 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3716814200 Jul 16 05:21:49 PM PDT 24 Jul 16 05:21:55 PM PDT 24 514678269 ps
T965 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2593716505 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:48 PM PDT 24 2208836741 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1715816975 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:50 PM PDT 24 285017979 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1731655287 Jul 16 05:21:34 PM PDT 24 Jul 16 05:21:48 PM PDT 24 556887631 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1726696480 Jul 16 05:21:36 PM PDT 24 Jul 16 05:21:43 PM PDT 24 229849536 ps
T969 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3001563387 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:37 PM PDT 24 38345955 ps
T970 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.775670933 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:58 PM PDT 24 192106158 ps
T971 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2857975311 Jul 16 05:25:14 PM PDT 24 Jul 16 05:25:18 PM PDT 24 26696946 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.575465082 Jul 16 05:21:53 PM PDT 24 Jul 16 05:21:56 PM PDT 24 203760774 ps
T973 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2019040309 Jul 16 05:21:52 PM PDT 24 Jul 16 05:21:55 PM PDT 24 73739306 ps
T974 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1875429017 Jul 16 05:22:00 PM PDT 24 Jul 16 05:22:05 PM PDT 24 481277770 ps
T975 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3583077906 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:53 PM PDT 24 113717045 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2751399826 Jul 16 05:25:43 PM PDT 24 Jul 16 05:25:49 PM PDT 24 1816463870 ps
T977 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2591529348 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:53 PM PDT 24 26549721 ps
T978 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3440784378 Jul 16 05:21:32 PM PDT 24 Jul 16 05:21:44 PM PDT 24 424944341 ps
T979 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.890697221 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:53 PM PDT 24 105879031 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3797291614 Jul 16 05:21:49 PM PDT 24 Jul 16 05:22:00 PM PDT 24 1459775410 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3370290087 Jul 16 05:24:56 PM PDT 24 Jul 16 05:24:58 PM PDT 24 46832846 ps
T982 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3930410549 Jul 16 05:22:11 PM PDT 24 Jul 16 05:22:12 PM PDT 24 15445578 ps
T983 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.645585588 Jul 16 05:21:48 PM PDT 24 Jul 16 05:21:50 PM PDT 24 340212067 ps
T984 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2411420387 Jul 16 05:21:47 PM PDT 24 Jul 16 05:21:49 PM PDT 24 35439962 ps
T985 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1540071570 Jul 16 05:21:51 PM PDT 24 Jul 16 05:21:53 PM PDT 24 25272526 ps
T986 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.965056118 Jul 16 05:21:33 PM PDT 24 Jul 16 05:21:35 PM PDT 24 24684911 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3937854773 Jul 16 05:21:50 PM PDT 24 Jul 16 05:21:53 PM PDT 24 114176506 ps

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1259032200
Short name T4
Test name
Test status
Simulation time 17350074440 ps
CPU time 111.99 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:33:08 PM PDT 24
Peak memory 277524 kb
Host smart-ab396a7e-98c9-4e14-92be-148cd0b163eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259032200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1259032200
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4011619472
Short name T38
Test name
Test status
Simulation time 1389783744 ps
CPU time 11.97 seconds
Started Jul 16 06:32:19 PM PDT 24
Finished Jul 16 06:32:33 PM PDT 24
Peak memory 225480 kb
Host smart-885550b9-10a0-4fef-a49c-951e5af990cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011619472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4011619472
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.156907420
Short name T64
Test name
Test status
Simulation time 6208449181 ps
CPU time 19.5 seconds
Started Jul 16 06:31:45 PM PDT 24
Finished Jul 16 06:32:06 PM PDT 24
Peak memory 225964 kb
Host smart-14bd6fd3-465d-419b-9b4d-ca181ef9b029
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156907420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.156907420
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.298296168
Short name T80
Test name
Test status
Simulation time 205648865696 ps
CPU time 1087.29 seconds
Started Jul 16 06:27:49 PM PDT 24
Finished Jul 16 06:45:57 PM PDT 24
Peak memory 422016 kb
Host smart-65a01460-7096-42ad-a0d6-f0ea63538145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=298296168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.298296168
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1865421399
Short name T113
Test name
Test status
Simulation time 68987352 ps
CPU time 1.82 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:49 PM PDT 24
Peak memory 222780 kb
Host smart-20787df1-a901-4fb6-b7b6-13f4394a5c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865421399 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1865421399
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3657089495
Short name T2
Test name
Test status
Simulation time 238551128 ps
CPU time 9.86 seconds
Started Jul 16 06:28:50 PM PDT 24
Finished Jul 16 06:29:01 PM PDT 24
Peak memory 225952 kb
Host smart-f7980cd1-52e5-4c76-94b4-7f4b7dbfc357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657089495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
657089495
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1896506867
Short name T53
Test name
Test status
Simulation time 387602650 ps
CPU time 25.7 seconds
Started Jul 16 06:27:36 PM PDT 24
Finished Jul 16 06:28:02 PM PDT 24
Peak memory 282772 kb
Host smart-65060233-79b1-41be-9b44-013af941d655
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896506867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1896506867
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1106233754
Short name T6
Test name
Test status
Simulation time 2126353538 ps
CPU time 10.76 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:29:56 PM PDT 24
Peak memory 217184 kb
Host smart-7b308b68-4b5f-4da6-b31c-fcb59936acfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106233754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1106233754
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2957431783
Short name T97
Test name
Test status
Simulation time 182546942369 ps
CPU time 1732.99 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 07:01:13 PM PDT 24
Peak memory 480520 kb
Host smart-61e03b49-fecc-4fe8-922d-dcebb34b1632
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2957431783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2957431783
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4177674312
Short name T450
Test name
Test status
Simulation time 457539752 ps
CPU time 9.94 seconds
Started Jul 16 06:29:34 PM PDT 24
Finished Jul 16 06:29:45 PM PDT 24
Peak memory 226012 kb
Host smart-67598783-f066-48fe-9f1c-9e3cf98370f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177674312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4177674312
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3265604638
Short name T12
Test name
Test status
Simulation time 2067586475 ps
CPU time 10.13 seconds
Started Jul 16 06:30:53 PM PDT 24
Finished Jul 16 06:31:04 PM PDT 24
Peak memory 226000 kb
Host smart-36693bbf-e065-4b48-97ca-d1b369a92734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265604638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3265604638
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1734956479
Short name T119
Test name
Test status
Simulation time 613280696 ps
CPU time 4.34 seconds
Started Jul 16 05:25:43 PM PDT 24
Finished Jul 16 05:25:48 PM PDT 24
Peak memory 217208 kb
Host smart-b72c3abd-7229-40d6-9f3b-6646311dd6af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734956479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1734956479
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3495284606
Short name T108
Test name
Test status
Simulation time 46303454436 ps
CPU time 67.71 seconds
Started Jul 16 06:27:35 PM PDT 24
Finished Jul 16 06:28:43 PM PDT 24
Peak memory 250988 kb
Host smart-0ceed10c-201d-49f4-8808-34bb18d871e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495284606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3495284606
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3614481178
Short name T93
Test name
Test status
Simulation time 23866137 ps
CPU time 1.33 seconds
Started Jul 16 06:32:03 PM PDT 24
Finished Jul 16 06:32:05 PM PDT 24
Peak memory 209020 kb
Host smart-b2e8be1e-7fba-4a10-82cd-deda52326502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614481178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3614481178
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1663605596
Short name T117
Test name
Test status
Simulation time 198275105 ps
CPU time 6.31 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 217408 kb
Host smart-082af9ad-d9bd-43a5-88a2-6b43f85dd847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166360
5596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1663605596
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.467240310
Short name T195
Test name
Test status
Simulation time 16445112 ps
CPU time 1.03 seconds
Started Jul 16 05:21:52 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 208772 kb
Host smart-270fec1e-5f4a-4905-b0c8-d61f8519da14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467240310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.467240310
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2296996902
Short name T40
Test name
Test status
Simulation time 250770002 ps
CPU time 10.61 seconds
Started Jul 16 06:29:26 PM PDT 24
Finished Jul 16 06:29:37 PM PDT 24
Peak memory 218108 kb
Host smart-003ae3a2-9e96-4938-afe4-f4a912e4ad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296996902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2296996902
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1795648954
Short name T127
Test name
Test status
Simulation time 117612192 ps
CPU time 2.72 seconds
Started Jul 16 05:21:32 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 212952 kb
Host smart-3df5afba-f5ac-47d4-82e3-1fd506a6c07f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795648954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1795648954
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1950854787
Short name T136
Test name
Test status
Simulation time 579687263 ps
CPU time 3.35 seconds
Started Jul 16 05:21:46 PM PDT 24
Finished Jul 16 05:21:49 PM PDT 24
Peak memory 221840 kb
Host smart-812ebd67-1c7f-4e04-94e0-c044fa8bbc42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950854787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1950854787
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2638406965
Short name T62
Test name
Test status
Simulation time 27466490381 ps
CPU time 487.91 seconds
Started Jul 16 06:27:26 PM PDT 24
Finished Jul 16 06:35:34 PM PDT 24
Peak memory 316332 kb
Host smart-3f0c14e9-be6e-4c24-a8dd-aa98e2eba83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2638406965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2638406965
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1435084543
Short name T20
Test name
Test status
Simulation time 3784727943 ps
CPU time 17.1 seconds
Started Jul 16 06:30:18 PM PDT 24
Finished Jul 16 06:30:36 PM PDT 24
Peak memory 225932 kb
Host smart-b99d5cab-1398-4210-a0cd-6fe96530583d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435084543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1435084543
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2828404338
Short name T128
Test name
Test status
Simulation time 54712478 ps
CPU time 1.92 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 217316 kb
Host smart-8c3b99e2-217f-48ba-b2e5-b138a966f170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828404338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2828404338
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2359948964
Short name T132
Test name
Test status
Simulation time 112461643 ps
CPU time 2.91 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 222028 kb
Host smart-c72b7ea7-5df4-4676-801e-e60aab4e0351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359948964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2359948964
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.401062936
Short name T202
Test name
Test status
Simulation time 54645948 ps
CPU time 1.16 seconds
Started Jul 16 05:21:54 PM PDT 24
Finished Jul 16 05:21:57 PM PDT 24
Peak memory 208992 kb
Host smart-4d30fd36-37ed-45c0-a011-14e033e1978d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401062936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.401062936
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3730824901
Short name T125
Test name
Test status
Simulation time 51098313 ps
CPU time 1.9 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:35 PM PDT 24
Peak memory 221712 kb
Host smart-7e920cd7-ef94-460d-ba24-1e52dfce098f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730824901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3730824901
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1044233478
Short name T141
Test name
Test status
Simulation time 91514268 ps
CPU time 4 seconds
Started Jul 16 05:22:44 PM PDT 24
Finished Jul 16 05:22:48 PM PDT 24
Peak memory 222100 kb
Host smart-2756e17e-11bd-49a6-bf83-9c1cf7fb28f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044233478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1044233478
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4158396926
Short name T138
Test name
Test status
Simulation time 122035023 ps
CPU time 2.19 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:50 PM PDT 24
Peak memory 221236 kb
Host smart-d51e5133-3e3c-41dc-b037-f0877b072286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158396926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4158396926
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1597716576
Short name T143
Test name
Test status
Simulation time 68989939 ps
CPU time 2.04 seconds
Started Jul 16 05:22:04 PM PDT 24
Finished Jul 16 05:22:07 PM PDT 24
Peak memory 221184 kb
Host smart-d71c3880-feee-42ed-bb09-cce517e1f839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597716576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1597716576
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.920905048
Short name T212
Test name
Test status
Simulation time 39535759 ps
CPU time 0.82 seconds
Started Jul 16 06:27:27 PM PDT 24
Finished Jul 16 06:27:28 PM PDT 24
Peak memory 208456 kb
Host smart-76a29e53-24f1-43ca-a6df-c4060bc669b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920905048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.920905048
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2374339611
Short name T262
Test name
Test status
Simulation time 12182562 ps
CPU time 1.07 seconds
Started Jul 16 06:29:46 PM PDT 24
Finished Jul 16 06:29:47 PM PDT 24
Peak memory 211868 kb
Host smart-66b7fecc-2f4d-447f-b006-269ae2322831
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374339611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2374339611
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.4285254993
Short name T635
Test name
Test status
Simulation time 314624420 ps
CPU time 10.18 seconds
Started Jul 16 06:29:54 PM PDT 24
Finished Jul 16 06:30:05 PM PDT 24
Peak memory 225988 kb
Host smart-6866b7af-4997-4152-99c5-b8bcbe6aaba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285254993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.4285254993
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2295593392
Short name T215
Test name
Test status
Simulation time 64047243 ps
CPU time 0.8 seconds
Started Jul 16 06:27:56 PM PDT 24
Finished Jul 16 06:27:57 PM PDT 24
Peak memory 208916 kb
Host smart-0ebaf74d-82f7-4f5b-b803-661d79f1749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295593392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2295593392
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2361968939
Short name T217
Test name
Test status
Simulation time 10247136 ps
CPU time 0.81 seconds
Started Jul 16 06:28:08 PM PDT 24
Finished Jul 16 06:28:10 PM PDT 24
Peak memory 208932 kb
Host smart-b9939af3-683f-4978-b475-86ae39cf61ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361968939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2361968939
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3827812965
Short name T216
Test name
Test status
Simulation time 23595708 ps
CPU time 0.84 seconds
Started Jul 16 06:28:49 PM PDT 24
Finished Jul 16 06:28:51 PM PDT 24
Peak memory 208404 kb
Host smart-9472cc6b-9dc9-4665-9c73-120816af4aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827812965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3827812965
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2187062110
Short name T34
Test name
Test status
Simulation time 159730644 ps
CPU time 3.21 seconds
Started Jul 16 06:31:52 PM PDT 24
Finished Jul 16 06:31:56 PM PDT 24
Peak memory 218128 kb
Host smart-e174721b-bae5-42f8-bc5e-677ba1275c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187062110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2187062110
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3418968257
Short name T126
Test name
Test status
Simulation time 406427979 ps
CPU time 3.19 seconds
Started Jul 16 05:22:45 PM PDT 24
Finished Jul 16 05:22:48 PM PDT 24
Peak memory 222148 kb
Host smart-ba655927-f1ae-45ad-83c4-2b31beb6a05c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418968257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3418968257
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3562145173
Short name T120
Test name
Test status
Simulation time 327409741 ps
CPU time 1.99 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 221324 kb
Host smart-3eacc105-a189-475b-b780-0734b58bc557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562145173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3562145173
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2326198138
Short name T142
Test name
Test status
Simulation time 167767319 ps
CPU time 2.98 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:58 PM PDT 24
Peak memory 217204 kb
Host smart-d4873884-e92e-43a8-b2fe-569cbdb42d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326198138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2326198138
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1137099224
Short name T133
Test name
Test status
Simulation time 509609672 ps
CPU time 5.06 seconds
Started Jul 16 05:23:48 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 217144 kb
Host smart-60030a68-5671-4cfc-a52b-35f04dbdb988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137099224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1137099224
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3901275835
Short name T47
Test name
Test status
Simulation time 64411255168 ps
CPU time 445.92 seconds
Started Jul 16 06:29:37 PM PDT 24
Finished Jul 16 06:37:04 PM PDT 24
Peak memory 251044 kb
Host smart-152f2acf-b2ba-4e7e-b9e7-87d0e0de5a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901275835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3901275835
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.728752003
Short name T45
Test name
Test status
Simulation time 26341269225 ps
CPU time 251.78 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:34:41 PM PDT 24
Peak memory 248248 kb
Host smart-b3cc1fd1-5868-41a7-97b0-038f16111140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728752003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.728752003
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2704078092
Short name T9
Test name
Test status
Simulation time 1554963214 ps
CPU time 50.53 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:30:36 PM PDT 24
Peak memory 225536 kb
Host smart-4b619b70-cb65-4b36-b39f-9652cb207ca8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704078092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2704078092
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2808425012
Short name T17
Test name
Test status
Simulation time 1780865472 ps
CPU time 51.96 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:30:17 PM PDT 24
Peak memory 218088 kb
Host smart-3dd8a19d-aded-4ab0-80e4-d9f4fdaf03f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808425012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2808425012
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.333789682
Short name T884
Test name
Test status
Simulation time 77196074 ps
CPU time 1.06 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 208944 kb
Host smart-5f9f1bf0-fcfa-40c7-8a27-bdc7ac533d5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333789682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.333789682
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3468112543
Short name T864
Test name
Test status
Simulation time 133616605 ps
CPU time 2.66 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 208968 kb
Host smart-6d23fc51-5ecb-485c-87a8-9f58937e7bbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468112543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3468112543
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.578394851
Short name T192
Test name
Test status
Simulation time 69183522 ps
CPU time 1.02 seconds
Started Jul 16 05:21:36 PM PDT 24
Finished Jul 16 05:21:38 PM PDT 24
Peak memory 209384 kb
Host smart-e621796a-5f51-420e-8b04-017d8c56a2e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578394851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.578394851
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3482687789
Short name T955
Test name
Test status
Simulation time 32396878 ps
CPU time 1.16 seconds
Started Jul 16 05:24:57 PM PDT 24
Finished Jul 16 05:24:59 PM PDT 24
Peak memory 217268 kb
Host smart-e878cc22-3061-43b8-95ba-5e2867de6e6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482687789 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3482687789
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.965056118
Short name T986
Test name
Test status
Simulation time 24684911 ps
CPU time 1.07 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:35 PM PDT 24
Peak memory 216900 kb
Host smart-6d7b2bf8-cdd1-4564-bd11-ed4aab6cb82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965056118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.965056118
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1965984239
Short name T900
Test name
Test status
Simulation time 64912165 ps
CPU time 1.67 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 207584 kb
Host smart-5a27c139-8738-44f0-842c-2c8f3e2f2ec9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965984239 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1965984239
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2593716505
Short name T965
Test name
Test status
Simulation time 2208836741 ps
CPU time 13.62 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 208748 kb
Host smart-b2383c55-83be-4ff7-ab6f-2c047a246fc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593716505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2593716505
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3271251134
Short name T935
Test name
Test status
Simulation time 422232943 ps
CPU time 11.17 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:59 PM PDT 24
Peak memory 208564 kb
Host smart-e839bb23-54fb-4dfd-a40b-08d5ba9682ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271251134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3271251134
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3291188176
Short name T881
Test name
Test status
Simulation time 46775880 ps
CPU time 1.23 seconds
Started Jul 16 05:21:36 PM PDT 24
Finished Jul 16 05:21:39 PM PDT 24
Peak memory 210252 kb
Host smart-02328aa6-994a-4614-973d-2a6f10312ec2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291188176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3291188176
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2992758165
Short name T936
Test name
Test status
Simulation time 105310309 ps
CPU time 3.98 seconds
Started Jul 16 05:21:32 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 217356 kb
Host smart-ca76bd8d-e436-4c0c-afe1-2352083546dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299275
8165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2992758165
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2789489096
Short name T878
Test name
Test status
Simulation time 184578291 ps
CPU time 1.61 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:37 PM PDT 24
Peak memory 208860 kb
Host smart-df4ed8fd-a6e9-47a5-8415-244ab9670406
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789489096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2789489096
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1054990029
Short name T934
Test name
Test status
Simulation time 308282270 ps
CPU time 1.24 seconds
Started Jul 16 05:21:30 PM PDT 24
Finished Jul 16 05:21:32 PM PDT 24
Peak memory 208896 kb
Host smart-f85a30bd-ca9b-4dd7-909f-27c715f48a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054990029 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1054990029
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2562362466
Short name T962
Test name
Test status
Simulation time 22153004 ps
CPU time 0.97 seconds
Started Jul 16 05:24:54 PM PDT 24
Finished Jul 16 05:24:56 PM PDT 24
Peak memory 209136 kb
Host smart-e20230ba-9c0f-4b6c-a7ee-3d379583bfb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562362466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2562362466
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.888812088
Short name T941
Test name
Test status
Simulation time 143221583 ps
CPU time 4 seconds
Started Jul 16 05:27:48 PM PDT 24
Finished Jul 16 05:27:53 PM PDT 24
Peak memory 217016 kb
Host smart-5338a4fc-0a95-43b5-9256-be1094036370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888812088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.888812088
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1590419958
Short name T958
Test name
Test status
Simulation time 42621175 ps
CPU time 1.1 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 208916 kb
Host smart-05fed5d3-de0e-440d-8eb5-6b1921b15a8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590419958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1590419958
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4139242990
Short name T873
Test name
Test status
Simulation time 262624682 ps
CPU time 2.02 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:37 PM PDT 24
Peak memory 208744 kb
Host smart-c308c124-6f22-4911-be83-43be546eb2b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139242990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.4139242990
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1999151882
Short name T901
Test name
Test status
Simulation time 20971124 ps
CPU time 1.18 seconds
Started Jul 16 05:21:31 PM PDT 24
Finished Jul 16 05:21:33 PM PDT 24
Peak memory 218828 kb
Host smart-90e9e0fe-cf07-43fc-af83-901549f43f6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999151882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1999151882
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.666813152
Short name T891
Test name
Test status
Simulation time 44791998 ps
CPU time 1.18 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 218636 kb
Host smart-befad340-ec67-4ef2-9520-78dce9acec4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666813152 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.666813152
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2972536785
Short name T198
Test name
Test status
Simulation time 66069435 ps
CPU time 1.21 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:37 PM PDT 24
Peak memory 208884 kb
Host smart-d4c267be-a49b-4e79-afb7-f4e6edb29aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972536785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2972536785
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3378454366
Short name T906
Test name
Test status
Simulation time 447506462 ps
CPU time 1.13 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 207508 kb
Host smart-b6901228-3307-4552-8ac5-ec8418871cfa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378454366 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3378454366
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1935923648
Short name T953
Test name
Test status
Simulation time 4351835557 ps
CPU time 4.64 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:38 PM PDT 24
Peak memory 208904 kb
Host smart-458253e5-c733-4f01-8219-71d518e31f5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935923648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1935923648
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3440784378
Short name T978
Test name
Test status
Simulation time 424944341 ps
CPU time 10.91 seconds
Started Jul 16 05:21:32 PM PDT 24
Finished Jul 16 05:21:44 PM PDT 24
Peak memory 208896 kb
Host smart-4ae76ef0-4a9a-42e7-a05b-13815274a285
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440784378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3440784378
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1711842725
Short name T876
Test name
Test status
Simulation time 94142373 ps
CPU time 1.88 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:37 PM PDT 24
Peak memory 210568 kb
Host smart-0a6a2290-f70f-4ab7-a59c-9930926cf613
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711842725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1711842725
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1328364408
Short name T875
Test name
Test status
Simulation time 414719729 ps
CPU time 3.67 seconds
Started Jul 16 05:22:45 PM PDT 24
Finished Jul 16 05:22:49 PM PDT 24
Peak memory 217372 kb
Host smart-b09e2d56-2755-4a1b-9ac5-14c73eae31fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132836
4408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1328364408
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1364788669
Short name T925
Test name
Test status
Simulation time 143499644 ps
CPU time 2.62 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:37 PM PDT 24
Peak memory 208752 kb
Host smart-75c51a68-6c62-4bd0-8ce6-fa54f5e894a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364788669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1364788669
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1424802757
Short name T950
Test name
Test status
Simulation time 48782605 ps
CPU time 1.45 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:35 PM PDT 24
Peak memory 210828 kb
Host smart-58f9e5fa-9881-4d99-ab19-57736f3d306a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424802757 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1424802757
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.634260492
Short name T948
Test name
Test status
Simulation time 74042203 ps
CPU time 1.4 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 211160 kb
Host smart-d3b9fba9-7039-45ab-af84-93de8f46510c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634260492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.634260492
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.940399307
Short name T932
Test name
Test status
Simulation time 125750260 ps
CPU time 3.66 seconds
Started Jul 16 05:21:32 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 217492 kb
Host smart-80fe9a9b-40e6-4b27-bb5f-4c56af92fbc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940399307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.940399307
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2834089488
Short name T943
Test name
Test status
Simulation time 30582686 ps
CPU time 2.05 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 219120 kb
Host smart-f2563670-211e-438b-a7fb-ca67b0954c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834089488 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2834089488
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.907279998
Short name T947
Test name
Test status
Simulation time 28503283 ps
CPU time 1.74 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 217164 kb
Host smart-5546c9f1-a3ba-4629-bc52-65b3db64344f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907279998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.907279998
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.334725995
Short name T130
Test name
Test status
Simulation time 734628706 ps
CPU time 3.37 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 221836 kb
Host smart-680bfc01-bca7-4970-a36f-4766647885f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334725995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.334725995
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1253101533
Short name T956
Test name
Test status
Simulation time 106798509 ps
CPU time 1.36 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 217152 kb
Host smart-999b4e14-2b64-46e0-a728-47aeaac650fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253101533 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1253101533
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1540071570
Short name T985
Test name
Test status
Simulation time 25272526 ps
CPU time 0.9 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 208704 kb
Host smart-3a2e73b4-6107-4665-869d-e8e561fbaa61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540071570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1540071570
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.233145010
Short name T923
Test name
Test status
Simulation time 14430588 ps
CPU time 1.1 seconds
Started Jul 16 05:28:05 PM PDT 24
Finished Jul 16 05:28:06 PM PDT 24
Peak memory 208868 kb
Host smart-8be86d19-7f99-4571-acc8-c72314a0e737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233145010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.233145010
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.116016837
Short name T118
Test name
Test status
Simulation time 234760978 ps
CPU time 3.89 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:57 PM PDT 24
Peak memory 217568 kb
Host smart-3a107fcd-978c-43e0-953f-320fdde352d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116016837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.116016837
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4009957465
Short name T880
Test name
Test status
Simulation time 78686873 ps
CPU time 1.13 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 218436 kb
Host smart-c09b4f46-fcd5-4394-8dfb-f5f75af8e54c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009957465 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4009957465
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2592203123
Short name T197
Test name
Test status
Simulation time 36495517 ps
CPU time 0.91 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:06 PM PDT 24
Peak memory 208520 kb
Host smart-8646451a-dc32-4e0c-af04-d09e19f0bc48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592203123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2592203123
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.818874154
Short name T942
Test name
Test status
Simulation time 72013953 ps
CPU time 1.79 seconds
Started Jul 16 05:25:15 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 217208 kb
Host smart-dd77d22e-8962-4bb3-aea2-011ce7bee1a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818874154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.818874154
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3288343553
Short name T871
Test name
Test status
Simulation time 81654165 ps
CPU time 1.77 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:51 PM PDT 24
Peak memory 218200 kb
Host smart-e6fbd7c2-4e64-48c5-b306-0a76e1d15573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288343553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3288343553
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.325250074
Short name T160
Test name
Test status
Simulation time 21909444 ps
CPU time 1.34 seconds
Started Jul 16 05:21:54 PM PDT 24
Finished Jul 16 05:21:57 PM PDT 24
Peak memory 217708 kb
Host smart-e6ee7284-3c97-44c5-a4bb-64c34a148610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325250074 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.325250074
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1636715176
Short name T189
Test name
Test status
Simulation time 20864437 ps
CPU time 0.87 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 208884 kb
Host smart-4c7210ed-f832-426b-8332-930987ab9d04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636715176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1636715176
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3930410549
Short name T982
Test name
Test status
Simulation time 15445578 ps
CPU time 0.94 seconds
Started Jul 16 05:22:11 PM PDT 24
Finished Jul 16 05:22:12 PM PDT 24
Peak memory 208840 kb
Host smart-83c0f7ab-4772-41c2-ac9b-8c12a930fe42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930410549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3930410549
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2290564618
Short name T926
Test name
Test status
Simulation time 326036494 ps
CPU time 2.03 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 217056 kb
Host smart-86b7e859-5cd4-4f66-aa72-1a6eeddceef3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290564618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2290564618
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.126187253
Short name T911
Test name
Test status
Simulation time 44120916 ps
CPU time 1.94 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:51 PM PDT 24
Peak memory 217384 kb
Host smart-86ee2727-198e-4860-aa82-21f9f5e4e783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126187253 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.126187253
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2958483995
Short name T161
Test name
Test status
Simulation time 19517586 ps
CPU time 1.2 seconds
Started Jul 16 05:21:52 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 208824 kb
Host smart-51b78bad-16f3-492b-9e0e-21bdaa205fc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958483995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2958483995
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1161482435
Short name T897
Test name
Test status
Simulation time 50341446 ps
CPU time 2.04 seconds
Started Jul 16 05:21:54 PM PDT 24
Finished Jul 16 05:21:58 PM PDT 24
Peak memory 209032 kb
Host smart-da544527-ce30-4ffc-9207-d467fad871ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161482435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1161482435
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3935080908
Short name T930
Test name
Test status
Simulation time 42220563 ps
CPU time 2.98 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:58 PM PDT 24
Peak memory 217268 kb
Host smart-992b8364-d975-4cfa-98c2-e14b530815ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935080908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3935080908
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3762857444
Short name T960
Test name
Test status
Simulation time 126945656 ps
CPU time 2.6 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 217344 kb
Host smart-354638d5-fe8a-45ec-bfcf-3943029e7985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762857444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3762857444
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.722078187
Short name T916
Test name
Test status
Simulation time 61290829 ps
CPU time 1.23 seconds
Started Jul 16 05:21:57 PM PDT 24
Finished Jul 16 05:21:59 PM PDT 24
Peak memory 217280 kb
Host smart-1f78f6b0-a2d7-405e-85df-06d0e6a31ee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722078187 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.722078187
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2901516369
Short name T928
Test name
Test status
Simulation time 13664138 ps
CPU time 1.03 seconds
Started Jul 16 05:21:54 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 208676 kb
Host smart-1ae5bae9-75db-4472-921c-db58412e4c11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901516369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2901516369
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2939148667
Short name T959
Test name
Test status
Simulation time 93283987 ps
CPU time 1.26 seconds
Started Jul 16 05:22:10 PM PDT 24
Finished Jul 16 05:22:12 PM PDT 24
Peak memory 208820 kb
Host smart-c2a650ce-bc32-40ed-94cd-12d3769b5ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939148667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2939148667
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.62937544
Short name T887
Test name
Test status
Simulation time 331577699 ps
CPU time 2.92 seconds
Started Jul 16 05:22:17 PM PDT 24
Finished Jul 16 05:22:20 PM PDT 24
Peak memory 218016 kb
Host smart-a82805e0-8ba4-4843-a87f-f4fef2c09274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62937544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.62937544
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1767407326
Short name T874
Test name
Test status
Simulation time 29313553 ps
CPU time 1.43 seconds
Started Jul 16 05:22:01 PM PDT 24
Finished Jul 16 05:22:03 PM PDT 24
Peak memory 221812 kb
Host smart-d891431d-529e-4cc1-8b80-3f06b6bc35e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767407326 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1767407326
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.558900642
Short name T193
Test name
Test status
Simulation time 13974317 ps
CPU time 1.06 seconds
Started Jul 16 05:22:05 PM PDT 24
Finished Jul 16 05:22:07 PM PDT 24
Peak memory 208896 kb
Host smart-5bade05e-83c8-468a-9d6f-83d613e6766c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558900642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.558900642
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2202816779
Short name T205
Test name
Test status
Simulation time 732513399 ps
CPU time 1.42 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 217236 kb
Host smart-444b15ec-0376-4483-a480-a980eaf425bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202816779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2202816779
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1167965575
Short name T139
Test name
Test status
Simulation time 153485152 ps
CPU time 3.45 seconds
Started Jul 16 05:26:01 PM PDT 24
Finished Jul 16 05:26:05 PM PDT 24
Peak memory 217200 kb
Host smart-fd4996e5-fd65-44d5-ac40-fc6cf148f7e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167965575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1167965575
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2062862628
Short name T885
Test name
Test status
Simulation time 50975978 ps
CPU time 1.34 seconds
Started Jul 16 05:22:44 PM PDT 24
Finished Jul 16 05:22:46 PM PDT 24
Peak memory 217416 kb
Host smart-84a32508-b0de-4eb8-a7e2-4b612ef4f794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062862628 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2062862628
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.737663099
Short name T917
Test name
Test status
Simulation time 98942367 ps
CPU time 0.9 seconds
Started Jul 16 05:22:01 PM PDT 24
Finished Jul 16 05:22:03 PM PDT 24
Peak memory 208868 kb
Host smart-8db40f8f-c321-4655-b730-94c792e8b3f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737663099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.737663099
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.792178305
Short name T919
Test name
Test status
Simulation time 24846298 ps
CPU time 1.3 seconds
Started Jul 16 05:21:57 PM PDT 24
Finished Jul 16 05:21:59 PM PDT 24
Peak memory 209000 kb
Host smart-645f9d36-6403-44ef-82f6-4deba5532d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792178305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.792178305
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.671702886
Short name T898
Test name
Test status
Simulation time 57867641 ps
CPU time 1.76 seconds
Started Jul 16 05:22:38 PM PDT 24
Finished Jul 16 05:22:40 PM PDT 24
Peak memory 218124 kb
Host smart-735d3cc7-71dd-4e71-94c3-2756bfaf410d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671702886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.671702886
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3775703471
Short name T137
Test name
Test status
Simulation time 117642104 ps
CPU time 3.4 seconds
Started Jul 16 05:25:52 PM PDT 24
Finished Jul 16 05:25:56 PM PDT 24
Peak memory 221936 kb
Host smart-3b688de5-d675-47cd-92dc-89d09297dea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775703471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3775703471
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3994564772
Short name T938
Test name
Test status
Simulation time 100088713 ps
CPU time 1.48 seconds
Started Jul 16 05:27:07 PM PDT 24
Finished Jul 16 05:27:09 PM PDT 24
Peak memory 218896 kb
Host smart-c79f78c5-f6ef-4923-b267-380bcbe617d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994564772 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3994564772
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2443462675
Short name T188
Test name
Test status
Simulation time 23108492 ps
CPU time 0.81 seconds
Started Jul 16 05:22:03 PM PDT 24
Finished Jul 16 05:22:04 PM PDT 24
Peak memory 208600 kb
Host smart-a9d8bc1d-80e1-495f-abff-096e84589741
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443462675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2443462675
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1759562947
Short name T147
Test name
Test status
Simulation time 24800279 ps
CPU time 1.4 seconds
Started Jul 16 05:22:04 PM PDT 24
Finished Jul 16 05:22:06 PM PDT 24
Peak memory 209008 kb
Host smart-9a8ade5c-ee59-42c2-98a7-181ab22bf10d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759562947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1759562947
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1676218090
Short name T134
Test name
Test status
Simulation time 203800770 ps
CPU time 1.64 seconds
Started Jul 16 05:23:54 PM PDT 24
Finished Jul 16 05:23:57 PM PDT 24
Peak memory 217140 kb
Host smart-70ac4d09-58af-49dc-8412-e67a0cd4a057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676218090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1676218090
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3664993358
Short name T131
Test name
Test status
Simulation time 101522945 ps
CPU time 3.76 seconds
Started Jul 16 05:22:03 PM PDT 24
Finished Jul 16 05:22:08 PM PDT 24
Peak memory 217232 kb
Host smart-8f55223e-7b10-4330-b7b9-9e349ec35be5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664993358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3664993358
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2649089020
Short name T135
Test name
Test status
Simulation time 13959873 ps
CPU time 1.2 seconds
Started Jul 16 05:21:59 PM PDT 24
Finished Jul 16 05:22:00 PM PDT 24
Peak memory 217248 kb
Host smart-75b90507-ce43-4267-b7b3-b8d2384cfd3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649089020 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2649089020
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4012443638
Short name T199
Test name
Test status
Simulation time 14453991 ps
CPU time 0.85 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:25:51 PM PDT 24
Peak memory 208772 kb
Host smart-fedacc5b-e379-4fc3-bfb5-34c1d82d9460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012443638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.4012443638
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2096826468
Short name T920
Test name
Test status
Simulation time 26804814 ps
CPU time 1.08 seconds
Started Jul 16 05:22:03 PM PDT 24
Finished Jul 16 05:22:04 PM PDT 24
Peak memory 208952 kb
Host smart-f5410a62-429c-4182-831c-09877b752c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096826468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2096826468
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1875429017
Short name T974
Test name
Test status
Simulation time 481277770 ps
CPU time 3.56 seconds
Started Jul 16 05:22:00 PM PDT 24
Finished Jul 16 05:22:05 PM PDT 24
Peak memory 218184 kb
Host smart-2c76925e-a1d9-4694-b466-12ed48d1dc8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875429017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1875429017
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4024840067
Short name T899
Test name
Test status
Simulation time 24004929 ps
CPU time 1.36 seconds
Started Jul 16 05:23:33 PM PDT 24
Finished Jul 16 05:23:35 PM PDT 24
Peak memory 208940 kb
Host smart-2e8c546c-0ded-40a1-85f4-d692076568b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024840067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.4024840067
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1918418898
Short name T902
Test name
Test status
Simulation time 100615155 ps
CPU time 2.17 seconds
Started Jul 16 05:21:35 PM PDT 24
Finished Jul 16 05:21:39 PM PDT 24
Peak memory 208800 kb
Host smart-7eb3703d-1c96-44db-bd36-0bc496303b72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918418898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1918418898
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3094877146
Short name T201
Test name
Test status
Simulation time 25996316 ps
CPU time 1.08 seconds
Started Jul 16 05:23:36 PM PDT 24
Finished Jul 16 05:23:38 PM PDT 24
Peak memory 210024 kb
Host smart-217e4d8a-ffd3-4d86-bfc7-05546b221852
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094877146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3094877146
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1606034830
Short name T165
Test name
Test status
Simulation time 100083055 ps
CPU time 1.29 seconds
Started Jul 16 05:21:35 PM PDT 24
Finished Jul 16 05:21:38 PM PDT 24
Peak memory 217288 kb
Host smart-adfe300a-72ea-4162-b40d-8c1d2da61bb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606034830 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1606034830
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1735523410
Short name T952
Test name
Test status
Simulation time 20844449 ps
CPU time 0.99 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:34 PM PDT 24
Peak memory 208892 kb
Host smart-fc5a2afa-af5e-448f-aa22-5e0af5eb7962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735523410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1735523410
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3974968153
Short name T867
Test name
Test status
Simulation time 88458458 ps
CPU time 1.08 seconds
Started Jul 16 05:21:35 PM PDT 24
Finished Jul 16 05:21:37 PM PDT 24
Peak memory 208860 kb
Host smart-539371c6-17c7-4e30-b50a-8b75e43b52ed
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974968153 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3974968153
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1726696480
Short name T968
Test name
Test status
Simulation time 229849536 ps
CPU time 5.43 seconds
Started Jul 16 05:21:36 PM PDT 24
Finished Jul 16 05:21:43 PM PDT 24
Peak memory 208816 kb
Host smart-27f024f1-9c33-4e09-a01f-434dede39765
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726696480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1726696480
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4099017896
Short name T912
Test name
Test status
Simulation time 1861742248 ps
CPU time 5.4 seconds
Started Jul 16 05:21:32 PM PDT 24
Finished Jul 16 05:21:38 PM PDT 24
Peak memory 208868 kb
Host smart-e068a0a2-5db3-4013-a487-28481c970573
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099017896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4099017896
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3626883104
Short name T869
Test name
Test status
Simulation time 49156182 ps
CPU time 1.33 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:35 PM PDT 24
Peak memory 210348 kb
Host smart-bcf58227-7dd9-4b4d-affb-8fe4bf70f417
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626883104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3626883104
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2119320463
Short name T905
Test name
Test status
Simulation time 132892595 ps
CPU time 1.48 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:35 PM PDT 24
Peak memory 218324 kb
Host smart-11a1ed0e-572d-49ee-bd94-bec1f9398881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211932
0463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2119320463
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.479181305
Short name T145
Test name
Test status
Simulation time 157990276 ps
CPU time 1.78 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 208720 kb
Host smart-566e89c8-b712-46f3-8161-fd92b8c59de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479181305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.479181305
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1571430304
Short name T204
Test name
Test status
Simulation time 23578124 ps
CPU time 1.04 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:35 PM PDT 24
Peak memory 209044 kb
Host smart-2c35a998-9a13-439b-8ca1-2fa11bbb7174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571430304 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1571430304
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3604498652
Short name T895
Test name
Test status
Simulation time 38124860 ps
CPU time 2.09 seconds
Started Jul 16 05:23:36 PM PDT 24
Finished Jul 16 05:23:39 PM PDT 24
Peak memory 211176 kb
Host smart-5ffed084-f5c0-4b0d-9a69-e9f9c9f4d261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604498652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3604498652
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3001563387
Short name T969
Test name
Test status
Simulation time 38345955 ps
CPU time 2.89 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:37 PM PDT 24
Peak memory 218240 kb
Host smart-ce2b2bec-9bd8-4a35-ac85-55299aacdfb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001563387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3001563387
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4073735838
Short name T194
Test name
Test status
Simulation time 54322477 ps
CPU time 1.05 seconds
Started Jul 16 05:21:42 PM PDT 24
Finished Jul 16 05:21:44 PM PDT 24
Peak memory 208988 kb
Host smart-c40c071d-8bd2-4ee4-bc96-9bafb8965e1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073735838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4073735838
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2188768512
Short name T868
Test name
Test status
Simulation time 18549518 ps
CPU time 1.18 seconds
Started Jul 16 05:22:19 PM PDT 24
Finished Jul 16 05:22:21 PM PDT 24
Peak memory 208780 kb
Host smart-5f04ac89-d62f-45d7-b864-0398236658cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188768512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2188768512
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3834073622
Short name T933
Test name
Test status
Simulation time 46206644 ps
CPU time 0.88 seconds
Started Jul 16 05:23:04 PM PDT 24
Finished Jul 16 05:23:06 PM PDT 24
Peak memory 209400 kb
Host smart-fc348904-f6ee-4628-be9f-32d0e01c6c9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834073622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3834073622
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3384099843
Short name T164
Test name
Test status
Simulation time 70147593 ps
CPU time 1.29 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 220564 kb
Host smart-a13d6365-9da9-405b-88af-1bd4d855bb7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384099843 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3384099843
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1942765602
Short name T191
Test name
Test status
Simulation time 25358995 ps
CPU time 0.98 seconds
Started Jul 16 05:22:22 PM PDT 24
Finished Jul 16 05:22:24 PM PDT 24
Peak memory 208812 kb
Host smart-e6e708e1-51bf-4508-b12a-bb5afc22c7a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942765602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1942765602
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2736372391
Short name T879
Test name
Test status
Simulation time 82700302 ps
CPU time 1.64 seconds
Started Jul 16 05:21:31 PM PDT 24
Finished Jul 16 05:21:33 PM PDT 24
Peak memory 208652 kb
Host smart-ac87a1ab-685e-4a16-8e04-cf0de1158b4f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736372391 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2736372391
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2818517414
Short name T939
Test name
Test status
Simulation time 365875588 ps
CPU time 9.49 seconds
Started Jul 16 05:26:44 PM PDT 24
Finished Jul 16 05:26:54 PM PDT 24
Peak memory 208764 kb
Host smart-ac0f2eed-7736-4c34-a84b-82b0a38cf9ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818517414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2818517414
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1731655287
Short name T967
Test name
Test status
Simulation time 556887631 ps
CPU time 13.26 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 208144 kb
Host smart-cdeecab1-548b-4bde-996a-de6b913618c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731655287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1731655287
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1452266324
Short name T883
Test name
Test status
Simulation time 542348333 ps
CPU time 3.91 seconds
Started Jul 16 05:21:33 PM PDT 24
Finished Jul 16 05:21:38 PM PDT 24
Peak memory 210488 kb
Host smart-365a954c-3105-4db3-bbfb-f7efe142d356
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452266324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1452266324
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4024643063
Short name T949
Test name
Test status
Simulation time 1696237266 ps
CPU time 7.69 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:43 PM PDT 24
Peak memory 218304 kb
Host smart-e9c2c0c1-ab10-484f-a1a3-5668bde44995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402464
3063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4024643063
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1396247507
Short name T940
Test name
Test status
Simulation time 186048441 ps
CPU time 4.36 seconds
Started Jul 16 05:25:50 PM PDT 24
Finished Jul 16 05:25:55 PM PDT 24
Peak memory 208712 kb
Host smart-a4d66243-9702-4b07-ad0d-8e1dd4cb4aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396247507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1396247507
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3892557089
Short name T915
Test name
Test status
Simulation time 45241477 ps
CPU time 1.37 seconds
Started Jul 16 05:21:34 PM PDT 24
Finished Jul 16 05:21:36 PM PDT 24
Peak memory 208776 kb
Host smart-8ff8a7e3-2e56-49c5-942a-b31800153f29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892557089 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3892557089
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2143832591
Short name T890
Test name
Test status
Simulation time 189137120 ps
CPU time 1.39 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 208928 kb
Host smart-7936efbc-17a3-4f32-b5ee-6eff115d0079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143832591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2143832591
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1404943947
Short name T129
Test name
Test status
Simulation time 200496688 ps
CPU time 3.31 seconds
Started Jul 16 05:22:15 PM PDT 24
Finished Jul 16 05:22:19 PM PDT 24
Peak memory 217132 kb
Host smart-c708d4d5-1a41-4506-8d6d-339dce041dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404943947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1404943947
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1295979488
Short name T957
Test name
Test status
Simulation time 24625206 ps
CPU time 1.39 seconds
Started Jul 16 05:22:21 PM PDT 24
Finished Jul 16 05:22:23 PM PDT 24
Peak memory 208820 kb
Host smart-7c74a174-252f-4ab7-bf8f-84a13900ffe5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295979488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1295979488
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2371629883
Short name T913
Test name
Test status
Simulation time 18989962 ps
CPU time 1.14 seconds
Started Jul 16 05:28:04 PM PDT 24
Finished Jul 16 05:28:06 PM PDT 24
Peak memory 208780 kb
Host smart-226d2912-ddff-4c9c-b0bb-d4aa028a1719
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371629883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2371629883
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.333180646
Short name T196
Test name
Test status
Simulation time 43948119 ps
CPU time 0.91 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 209104 kb
Host smart-fc602013-57e0-4738-a89c-d3a3a7c7fe2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333180646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.333180646
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3329788740
Short name T927
Test name
Test status
Simulation time 23297793 ps
CPU time 1.4 seconds
Started Jul 16 05:23:52 PM PDT 24
Finished Jul 16 05:23:54 PM PDT 24
Peak memory 219000 kb
Host smart-30d06ff8-e0ab-42f5-ba0b-40a546ad7904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329788740 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3329788740
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3370290087
Short name T981
Test name
Test status
Simulation time 46832846 ps
CPU time 1.06 seconds
Started Jul 16 05:24:56 PM PDT 24
Finished Jul 16 05:24:58 PM PDT 24
Peak memory 208908 kb
Host smart-d8995ae7-54f8-4df0-949b-2adb8c57ceff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370290087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3370290087
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2005001392
Short name T866
Test name
Test status
Simulation time 45829821 ps
CPU time 1.17 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 208940 kb
Host smart-eb08a7e4-61e2-42d3-896b-5db405904157
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005001392 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2005001392
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3433145831
Short name T123
Test name
Test status
Simulation time 728497519 ps
CPU time 17.47 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:22:05 PM PDT 24
Peak memory 208636 kb
Host smart-27c77b80-dc47-4985-86a6-ecad68fd817f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433145831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3433145831
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3689608089
Short name T929
Test name
Test status
Simulation time 3028224388 ps
CPU time 5.03 seconds
Started Jul 16 05:24:56 PM PDT 24
Finished Jul 16 05:25:02 PM PDT 24
Peak memory 209096 kb
Host smart-560b9f39-dfce-45ad-9cb6-49ade1218720
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689608089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3689608089
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3932565713
Short name T918
Test name
Test status
Simulation time 1553694977 ps
CPU time 5.24 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:52 PM PDT 24
Peak memory 210704 kb
Host smart-adb15048-293f-4739-87f7-30ead1469645
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932565713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3932565713
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2042363191
Short name T116
Test name
Test status
Simulation time 86980698 ps
CPU time 1.65 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 218384 kb
Host smart-d213769c-1826-49e1-9702-281e27241723
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204236
3191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2042363191
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.665371347
Short name T946
Test name
Test status
Simulation time 252574917 ps
CPU time 1.2 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:50 PM PDT 24
Peak memory 209012 kb
Host smart-5dd7cd46-30bd-40ea-8ce9-928ac5120812
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665371347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.665371347
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4267625628
Short name T944
Test name
Test status
Simulation time 54136774 ps
CPU time 0.97 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:49 PM PDT 24
Peak memory 208436 kb
Host smart-ec9ef273-dc74-42af-a419-335e6343a242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267625628 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4267625628
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1261287132
Short name T921
Test name
Test status
Simulation time 392757575 ps
CPU time 1.87 seconds
Started Jul 16 05:24:37 PM PDT 24
Finished Jul 16 05:24:40 PM PDT 24
Peak memory 208684 kb
Host smart-5e02bfe1-a77b-4814-86b5-253f49ad6597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261287132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1261287132
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2916905092
Short name T124
Test name
Test status
Simulation time 240968106 ps
CPU time 2.07 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:57 PM PDT 24
Peak memory 216464 kb
Host smart-ccbdf2ec-fc80-4849-a5f9-e88a8cf957da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916905092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2916905092
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3384630721
Short name T140
Test name
Test status
Simulation time 74149083 ps
CPU time 2.63 seconds
Started Jul 16 05:21:45 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 221732 kb
Host smart-8925338d-6a9b-445b-813b-78732bed411e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384630721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3384630721
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2857975311
Short name T971
Test name
Test status
Simulation time 26696946 ps
CPU time 1.63 seconds
Started Jul 16 05:25:14 PM PDT 24
Finished Jul 16 05:25:18 PM PDT 24
Peak memory 225472 kb
Host smart-993528b7-b948-4d55-b98d-536faa69b721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857975311 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2857975311
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2516369175
Short name T200
Test name
Test status
Simulation time 35315911 ps
CPU time 0.9 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:49 PM PDT 24
Peak memory 209000 kb
Host smart-265733c2-73d4-4e2a-bd9e-2f10f660eb36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516369175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2516369175
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1715816975
Short name T966
Test name
Test status
Simulation time 285017979 ps
CPU time 1.23 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:50 PM PDT 24
Peak memory 208772 kb
Host smart-e41acd9f-d5fa-4423-b890-8144f88a0e22
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715816975 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1715816975
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3644404938
Short name T882
Test name
Test status
Simulation time 3158693807 ps
CPU time 5.54 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 208240 kb
Host smart-0cf4c554-db1c-4876-bb2d-ed201a6400fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644404938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3644404938
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2751399826
Short name T976
Test name
Test status
Simulation time 1816463870 ps
CPU time 5.31 seconds
Started Jul 16 05:25:43 PM PDT 24
Finished Jul 16 05:25:49 PM PDT 24
Peak memory 207648 kb
Host smart-cf7dc133-5b71-45e1-a8ba-569eb9d8b46e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751399826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2751399826
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.634612817
Short name T903
Test name
Test status
Simulation time 182257986 ps
CPU time 1.91 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:50 PM PDT 24
Peak memory 210788 kb
Host smart-3f79a67f-c701-4f23-8b34-3755d9b8b26c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634612817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.634612817
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.575465082
Short name T972
Test name
Test status
Simulation time 203760774 ps
CPU time 2.26 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 217260 kb
Host smart-f666755d-feaa-4d80-9c3c-fcd9eee381a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575465
082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.575465082
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3492856969
Short name T961
Test name
Test status
Simulation time 141883144 ps
CPU time 1.56 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:49 PM PDT 24
Peak memory 208844 kb
Host smart-06f19b73-e429-4d16-9945-af0b812538f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492856969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3492856969
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4037844891
Short name T206
Test name
Test status
Simulation time 23668169 ps
CPU time 1.48 seconds
Started Jul 16 05:21:46 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 209016 kb
Host smart-a59847b8-6494-4a86-ac99-20b3766768b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037844891 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4037844891
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2350033140
Short name T158
Test name
Test status
Simulation time 148036003 ps
CPU time 1.45 seconds
Started Jul 16 05:24:17 PM PDT 24
Finished Jul 16 05:24:19 PM PDT 24
Peak memory 209124 kb
Host smart-99b74f84-8e47-44bc-90c2-348e2855be86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350033140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2350033140
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4181096412
Short name T937
Test name
Test status
Simulation time 259977531 ps
CPU time 3.3 seconds
Started Jul 16 05:21:45 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 217352 kb
Host smart-15f4d0e2-412b-43b8-b22a-afeda9203619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181096412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.4181096412
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3168641545
Short name T190
Test name
Test status
Simulation time 23022621 ps
CPU time 0.89 seconds
Started Jul 16 05:21:45 PM PDT 24
Finished Jul 16 05:21:46 PM PDT 24
Peak memory 208624 kb
Host smart-bd167572-ac76-4a41-9d7f-39968b32c312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168641545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3168641545
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2591529348
Short name T977
Test name
Test status
Simulation time 26549721 ps
CPU time 1.06 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 208784 kb
Host smart-70573119-1cbb-4878-b49b-10d357241c30
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591529348 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2591529348
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3716814200
Short name T964
Test name
Test status
Simulation time 514678269 ps
CPU time 5.7 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 208068 kb
Host smart-575452b5-5708-43ad-aead-03a494cf701b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716814200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3716814200
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2087209295
Short name T963
Test name
Test status
Simulation time 2475570281 ps
CPU time 7.27 seconds
Started Jul 16 05:23:03 PM PDT 24
Finished Jul 16 05:23:12 PM PDT 24
Peak memory 208940 kb
Host smart-4d4c0f08-6513-44ce-b8f3-eb394708c952
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087209295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2087209295
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4100454743
Short name T146
Test name
Test status
Simulation time 190895483 ps
CPU time 1.52 seconds
Started Jul 16 05:21:46 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 210376 kb
Host smart-ad797083-e492-4ff0-86d0-699e65008b7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100454743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4100454743
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3056106205
Short name T908
Test name
Test status
Simulation time 49100401 ps
CPU time 1.24 seconds
Started Jul 16 05:25:13 PM PDT 24
Finished Jul 16 05:25:16 PM PDT 24
Peak memory 208868 kb
Host smart-3438541f-2207-41a4-b57c-0730490682f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056106205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3056106205
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.867597504
Short name T886
Test name
Test status
Simulation time 42470556 ps
CPU time 1.11 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 208896 kb
Host smart-4335e900-f2a6-459e-94c3-4fb70345da7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867597504 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.867597504
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.645585588
Short name T983
Test name
Test status
Simulation time 340212067 ps
CPU time 1.34 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:50 PM PDT 24
Peak memory 208948 kb
Host smart-33209e48-be61-4a0c-815b-16f34aafb6f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645585588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.645585588
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2411420387
Short name T984
Test name
Test status
Simulation time 35439962 ps
CPU time 2.47 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:49 PM PDT 24
Peak memory 218176 kb
Host smart-4b2035bc-0378-44e1-a297-c8fc67c64ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411420387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2411420387
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1288320323
Short name T114
Test name
Test status
Simulation time 398503388 ps
CPU time 2.82 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 217204 kb
Host smart-8963a654-265d-44f2-b546-e1a1a1f43837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288320323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1288320323
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3965391321
Short name T115
Test name
Test status
Simulation time 20751715 ps
CPU time 1.5 seconds
Started Jul 16 05:22:11 PM PDT 24
Finished Jul 16 05:22:13 PM PDT 24
Peak memory 217100 kb
Host smart-97193fbb-e872-4ebe-9e91-b418fb7a60d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965391321 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3965391321
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1923079826
Short name T910
Test name
Test status
Simulation time 202918269 ps
CPU time 1.05 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 208948 kb
Host smart-bdbc52d5-739b-4d46-90a1-98bc332ace27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923079826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1923079826
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2863410670
Short name T889
Test name
Test status
Simulation time 38126944 ps
CPU time 1.19 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:57 PM PDT 24
Peak memory 208816 kb
Host smart-45490f89-95c1-42f6-bb74-860c8b694b00
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863410670 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2863410670
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2805991720
Short name T907
Test name
Test status
Simulation time 863195375 ps
CPU time 3.16 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 208652 kb
Host smart-6eff1326-b392-47a1-84b8-b0822bdad3d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805991720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2805991720
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4125582060
Short name T877
Test name
Test status
Simulation time 904030857 ps
CPU time 5.21 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 208144 kb
Host smart-8f97adb8-f047-4bda-acd9-115fc263ea16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125582060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.4125582060
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1118581524
Short name T904
Test name
Test status
Simulation time 377605350 ps
CPU time 2 seconds
Started Jul 16 05:21:46 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 210512 kb
Host smart-3253f280-e923-4545-9933-5132049fce61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118581524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1118581524
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3663494421
Short name T121
Test name
Test status
Simulation time 85971264 ps
CPU time 1.96 seconds
Started Jul 16 05:21:46 PM PDT 24
Finished Jul 16 05:21:48 PM PDT 24
Peak memory 218264 kb
Host smart-2ef8ac69-7265-418d-9a3f-803ca270bd04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366349
4421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3663494421
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3583077906
Short name T975
Test name
Test status
Simulation time 113717045 ps
CPU time 1.31 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 208904 kb
Host smart-fc93f4f0-98c8-4f4e-bc77-6eefa8e2d520
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583077906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3583077906
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4172428301
Short name T945
Test name
Test status
Simulation time 22616234 ps
CPU time 1.61 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:21:52 PM PDT 24
Peak memory 217228 kb
Host smart-b0f905b0-7ae0-4ce6-a1bf-b52ab6931a87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172428301 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4172428301
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4197821080
Short name T159
Test name
Test status
Simulation time 217099031 ps
CPU time 1.73 seconds
Started Jul 16 05:22:16 PM PDT 24
Finished Jul 16 05:22:18 PM PDT 24
Peak memory 208988 kb
Host smart-a828137e-4d11-4f6f-a03e-d1edc3cc20db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197821080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4197821080
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4241146018
Short name T922
Test name
Test status
Simulation time 193430432 ps
CPU time 2.23 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:54 PM PDT 24
Peak memory 217276 kb
Host smart-5fdce78e-06e9-4b2d-9ab4-3118b931af16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241146018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4241146018
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2343661598
Short name T924
Test name
Test status
Simulation time 59337122 ps
CPU time 1.38 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:21:52 PM PDT 24
Peak memory 218596 kb
Host smart-1d66ad09-90db-4f39-9411-1c452062b18a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343661598 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2343661598
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2604089282
Short name T203
Test name
Test status
Simulation time 22808641 ps
CPU time 0.9 seconds
Started Jul 16 05:24:17 PM PDT 24
Finished Jul 16 05:24:18 PM PDT 24
Peak memory 208876 kb
Host smart-b4a2f266-4f63-4c65-83d8-ab44b7b4e5e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604089282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2604089282
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3634074256
Short name T894
Test name
Test status
Simulation time 251678053 ps
CPU time 1.16 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:50 PM PDT 24
Peak memory 207476 kb
Host smart-a9672381-5434-476f-93de-dcf9dd8d310d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634074256 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3634074256
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3797291614
Short name T980
Test name
Test status
Simulation time 1459775410 ps
CPU time 9.76 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:22:00 PM PDT 24
Peak memory 208688 kb
Host smart-408b5461-0d13-44f3-9690-62857dee0092
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797291614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3797291614
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1519100049
Short name T870
Test name
Test status
Simulation time 1811985218 ps
CPU time 21.26 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:22:11 PM PDT 24
Peak memory 208604 kb
Host smart-83496a77-8c5b-47c1-99e0-e0b944924041
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519100049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1519100049
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1328920814
Short name T896
Test name
Test status
Simulation time 261029819 ps
CPU time 1.29 seconds
Started Jul 16 05:26:44 PM PDT 24
Finished Jul 16 05:26:46 PM PDT 24
Peak memory 210324 kb
Host smart-dd51f329-8269-4edb-94c8-02570614c629
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328920814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1328920814
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1382052002
Short name T893
Test name
Test status
Simulation time 142720361 ps
CPU time 2.51 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:51 PM PDT 24
Peak memory 218796 kb
Host smart-e48e8f9d-058f-4d72-b7a5-d527269d5695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138205
2002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1382052002
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.966143610
Short name T865
Test name
Test status
Simulation time 101945460 ps
CPU time 3.06 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 208900 kb
Host smart-0fc31367-b2c8-4c0d-96d1-ca5964f1c4bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966143610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.966143610
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.687373014
Short name T122
Test name
Test status
Simulation time 34422625 ps
CPU time 1.28 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:21:51 PM PDT 24
Peak memory 211124 kb
Host smart-ea673af3-dba5-401e-a26f-bbf8f2768a35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687373014 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.687373014
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2343174089
Short name T207
Test name
Test status
Simulation time 146894498 ps
CPU time 1.27 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:21:52 PM PDT 24
Peak memory 209108 kb
Host smart-0f6c4205-faad-4a78-b6d1-0c39c493ec5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343174089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2343174089
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3988853069
Short name T892
Test name
Test status
Simulation time 116206149 ps
CPU time 2.02 seconds
Started Jul 16 05:21:47 PM PDT 24
Finished Jul 16 05:21:49 PM PDT 24
Peak memory 217364 kb
Host smart-1c515863-20c6-4e85-836b-d8cdb15171cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988853069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3988853069
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2019040309
Short name T973
Test name
Test status
Simulation time 73739306 ps
CPU time 1.33 seconds
Started Jul 16 05:21:52 PM PDT 24
Finished Jul 16 05:21:55 PM PDT 24
Peak memory 218108 kb
Host smart-6866f09f-d14c-449a-8c1a-83b3646e5974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019040309 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2019040309
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.220879835
Short name T951
Test name
Test status
Simulation time 55636099 ps
CPU time 0.81 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 208408 kb
Host smart-98d5dbf9-0423-484a-b44d-08491020cdb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220879835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.220879835
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3489519934
Short name T872
Test name
Test status
Simulation time 98866443 ps
CPU time 2.03 seconds
Started Jul 16 05:25:52 PM PDT 24
Finished Jul 16 05:25:55 PM PDT 24
Peak memory 207504 kb
Host smart-0cbcaf4e-e3c9-4387-882a-80b8903b32dc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489519934 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3489519934
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1185369035
Short name T888
Test name
Test status
Simulation time 1751560810 ps
CPU time 11.37 seconds
Started Jul 16 05:21:51 PM PDT 24
Finished Jul 16 05:22:04 PM PDT 24
Peak memory 208020 kb
Host smart-8f3a40a4-d3a2-414e-bbf4-6007a6dd28ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185369035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1185369035
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1380935213
Short name T909
Test name
Test status
Simulation time 9300690947 ps
CPU time 25.12 seconds
Started Jul 16 05:23:54 PM PDT 24
Finished Jul 16 05:24:20 PM PDT 24
Peak memory 208948 kb
Host smart-510474e4-d10c-4f1b-890f-86257277687f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380935213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1380935213
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3937854773
Short name T987
Test name
Test status
Simulation time 114176506 ps
CPU time 1.82 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 210408 kb
Host smart-2e65c0e3-9132-431e-ab71-4a06a7c4d2cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937854773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3937854773
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.775670933
Short name T970
Test name
Test status
Simulation time 192106158 ps
CPU time 3.55 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:58 PM PDT 24
Peak memory 218936 kb
Host smart-190a3de9-6576-4aac-adec-5403a8e31228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775670
933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.775670933
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2392656900
Short name T954
Test name
Test status
Simulation time 39692522 ps
CPU time 1.61 seconds
Started Jul 16 05:21:53 PM PDT 24
Finished Jul 16 05:21:56 PM PDT 24
Peak memory 208880 kb
Host smart-17c10193-360d-488b-baf2-d7fe2d23b865
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392656900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2392656900
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.300991372
Short name T914
Test name
Test status
Simulation time 52577223 ps
CPU time 1.38 seconds
Started Jul 16 05:21:48 PM PDT 24
Finished Jul 16 05:21:50 PM PDT 24
Peak memory 209020 kb
Host smart-4b30e5e4-9179-4853-af92-043588b97ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300991372 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.300991372
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.890697221
Short name T979
Test name
Test status
Simulation time 105879031 ps
CPU time 1 seconds
Started Jul 16 05:21:50 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 208956 kb
Host smart-6319042c-2266-4ac5-b88e-1dee58023ca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890697221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.890697221
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3771789599
Short name T931
Test name
Test status
Simulation time 52855892 ps
CPU time 1.9 seconds
Started Jul 16 05:26:43 PM PDT 24
Finished Jul 16 05:26:46 PM PDT 24
Peak memory 217288 kb
Host smart-a4bb961d-52fa-456d-a3c3-67e828e0a66b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771789599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3771789599
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1378239020
Short name T144
Test name
Test status
Simulation time 158451468 ps
CPU time 2.75 seconds
Started Jul 16 05:21:49 PM PDT 24
Finished Jul 16 05:21:53 PM PDT 24
Peak memory 222116 kb
Host smart-29a326f2-d8dc-4c61-8583-e9967351a756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378239020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1378239020
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1443778556
Short name T756
Test name
Test status
Simulation time 51266267 ps
CPU time 1.03 seconds
Started Jul 16 06:27:30 PM PDT 24
Finished Jul 16 06:27:32 PM PDT 24
Peak memory 208836 kb
Host smart-276877a1-5711-47f9-a243-e00a98995871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443778556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1443778556
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3849910732
Short name T587
Test name
Test status
Simulation time 13893173 ps
CPU time 0.97 seconds
Started Jul 16 06:27:24 PM PDT 24
Finished Jul 16 06:27:26 PM PDT 24
Peak memory 208684 kb
Host smart-7461977e-07e6-4c9b-8b2b-d40508620f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849910732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3849910732
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.332849718
Short name T3
Test name
Test status
Simulation time 3804967527 ps
CPU time 11.03 seconds
Started Jul 16 06:27:17 PM PDT 24
Finished Jul 16 06:27:29 PM PDT 24
Peak memory 219016 kb
Host smart-5c65de2e-33fc-47ab-9863-20bcc9b5505c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332849718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.332849718
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.4184291159
Short name T170
Test name
Test status
Simulation time 912829097 ps
CPU time 4.07 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:30 PM PDT 24
Peak memory 217344 kb
Host smart-5fe78780-e9a5-4e4b-920b-546720c2b914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184291159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.4184291159
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1724049672
Short name T578
Test name
Test status
Simulation time 1203969201 ps
CPU time 24.21 seconds
Started Jul 16 06:27:26 PM PDT 24
Finished Jul 16 06:27:51 PM PDT 24
Peak memory 226028 kb
Host smart-d4b1f21b-7b6a-4ed2-8718-0354d740af7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724049672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1724049672
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.4011146223
Short name T740
Test name
Test status
Simulation time 2288585813 ps
CPU time 16.2 seconds
Started Jul 16 06:27:28 PM PDT 24
Finished Jul 16 06:27:46 PM PDT 24
Peak memory 217728 kb
Host smart-73259903-955b-4367-a4f6-8d3e2bd0b947
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011146223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.4
011146223
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.4265000817
Short name T402
Test name
Test status
Simulation time 2626108589 ps
CPU time 11.22 seconds
Started Jul 16 06:27:30 PM PDT 24
Finished Jul 16 06:27:42 PM PDT 24
Peak memory 218224 kb
Host smart-143c1098-f623-4274-b7a8-dc3dbc05776e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265000817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.4265000817
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1635930886
Short name T683
Test name
Test status
Simulation time 1057710840 ps
CPU time 32.91 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:59 PM PDT 24
Peak memory 217612 kb
Host smart-ea104590-eac6-45d4-b083-be89b21dc354
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635930886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1635930886
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2151146387
Short name T837
Test name
Test status
Simulation time 4109554296 ps
CPU time 13.21 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:39 PM PDT 24
Peak memory 217644 kb
Host smart-1790ee04-7ebe-442c-a55d-d7be46cdcbe3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151146387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2151146387
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.479495340
Short name T446
Test name
Test status
Simulation time 4484008735 ps
CPU time 66.13 seconds
Started Jul 16 06:27:26 PM PDT 24
Finished Jul 16 06:28:33 PM PDT 24
Peak memory 251324 kb
Host smart-44385d69-1f4e-44be-8c11-4293d21eda54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479495340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.479495340
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.152036078
Short name T676
Test name
Test status
Simulation time 1753992496 ps
CPU time 19.25 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:45 PM PDT 24
Peak memory 248252 kb
Host smart-627819bd-6531-4955-9b9b-4442b263131f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152036078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.152036078
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.711370155
Short name T290
Test name
Test status
Simulation time 106028400 ps
CPU time 2.44 seconds
Started Jul 16 06:27:16 PM PDT 24
Finished Jul 16 06:27:19 PM PDT 24
Peak memory 222156 kb
Host smart-223b00e3-d84a-4cc2-9993-1a7867a49d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711370155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.711370155
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1099366731
Short name T315
Test name
Test status
Simulation time 250057115 ps
CPU time 9.07 seconds
Started Jul 16 06:27:16 PM PDT 24
Finished Jul 16 06:27:26 PM PDT 24
Peak memory 217480 kb
Host smart-6be7089e-9ca9-490c-9998-f3a034c5c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099366731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1099366731
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.414556496
Short name T91
Test name
Test status
Simulation time 243446469 ps
CPU time 20.54 seconds
Started Jul 16 06:27:26 PM PDT 24
Finished Jul 16 06:27:47 PM PDT 24
Peak memory 267720 kb
Host smart-7e3c2cb1-ee19-4426-a7c3-31a64aee596a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414556496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.414556496
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1369179514
Short name T796
Test name
Test status
Simulation time 1421808627 ps
CPU time 14 seconds
Started Jul 16 06:27:23 PM PDT 24
Finished Jul 16 06:27:38 PM PDT 24
Peak memory 225968 kb
Host smart-f8d91b3f-8951-4479-9d7a-8297f456a512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369179514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1369179514
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.926008441
Short name T529
Test name
Test status
Simulation time 804353182 ps
CPU time 10.28 seconds
Started Jul 16 06:27:26 PM PDT 24
Finished Jul 16 06:27:37 PM PDT 24
Peak memory 225952 kb
Host smart-0b640713-433c-426d-ba08-01e333650e82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926008441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.926008441
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1271184103
Short name T832
Test name
Test status
Simulation time 1925027887 ps
CPU time 10.52 seconds
Started Jul 16 06:27:16 PM PDT 24
Finished Jul 16 06:27:28 PM PDT 24
Peak memory 218288 kb
Host smart-5e2cecb0-c1f2-4fe2-85f0-83baa79fb3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271184103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1271184103
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3283198615
Short name T308
Test name
Test status
Simulation time 102248660 ps
CPU time 2.3 seconds
Started Jul 16 06:27:16 PM PDT 24
Finished Jul 16 06:27:19 PM PDT 24
Peak memory 214532 kb
Host smart-6bdbbe8f-fedc-4cab-bf6b-61ca874ac0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283198615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3283198615
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3596041619
Short name T846
Test name
Test status
Simulation time 847226681 ps
CPU time 19.33 seconds
Started Jul 16 06:27:16 PM PDT 24
Finished Jul 16 06:27:37 PM PDT 24
Peak memory 246480 kb
Host smart-da5d1ce9-f915-4884-86fc-c5b25657ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596041619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3596041619
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1673334133
Short name T462
Test name
Test status
Simulation time 168607162 ps
CPU time 9.63 seconds
Started Jul 16 06:27:15 PM PDT 24
Finished Jul 16 06:27:25 PM PDT 24
Peak memory 250516 kb
Host smart-e042727f-fec3-4806-8204-fdc3f03efda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673334133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1673334133
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1209184168
Short name T571
Test name
Test status
Simulation time 46403287086 ps
CPU time 95.19 seconds
Started Jul 16 06:27:28 PM PDT 24
Finished Jul 16 06:29:04 PM PDT 24
Peak memory 249792 kb
Host smart-7cea9217-b0c2-46eb-916a-0e730379722d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209184168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1209184168
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1154650749
Short name T403
Test name
Test status
Simulation time 32467547 ps
CPU time 0.84 seconds
Started Jul 16 06:27:17 PM PDT 24
Finished Jul 16 06:27:19 PM PDT 24
Peak memory 211888 kb
Host smart-4c7dbcc8-399d-4939-9aac-c11f48abb12d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154650749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1154650749
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.386456846
Short name T68
Test name
Test status
Simulation time 59099347 ps
CPU time 0.91 seconds
Started Jul 16 06:27:37 PM PDT 24
Finished Jul 16 06:27:39 PM PDT 24
Peak memory 208844 kb
Host smart-61266d36-5460-4db6-baa4-b1c773459add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386456846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.386456846
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2402603432
Short name T509
Test name
Test status
Simulation time 335474090 ps
CPU time 11.81 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:38 PM PDT 24
Peak memory 225920 kb
Host smart-a79c84fd-d764-4c11-b491-6f7e913950e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402603432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2402603432
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.71598409
Short name T33
Test name
Test status
Simulation time 178935185 ps
CPU time 5.21 seconds
Started Jul 16 06:27:35 PM PDT 24
Finished Jul 16 06:27:41 PM PDT 24
Peak memory 217040 kb
Host smart-7d572c68-5d1a-4c09-b44d-d4c04f21afe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71598409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.71598409
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1154118924
Short name T352
Test name
Test status
Simulation time 6818478602 ps
CPU time 37.09 seconds
Started Jul 16 06:27:36 PM PDT 24
Finished Jul 16 06:28:14 PM PDT 24
Peak memory 218612 kb
Host smart-0273f9e6-802a-4297-bbe0-a7c50d6e3a2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154118924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1154118924
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3110575100
Short name T67
Test name
Test status
Simulation time 348335652 ps
CPU time 5.32 seconds
Started Jul 16 06:27:42 PM PDT 24
Finished Jul 16 06:27:48 PM PDT 24
Peak memory 217644 kb
Host smart-12f31ba9-80d8-4658-9352-03c2a0bc255c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110575100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
110575100
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1206612255
Short name T98
Test name
Test status
Simulation time 1775380176 ps
CPU time 13.23 seconds
Started Jul 16 06:27:37 PM PDT 24
Finished Jul 16 06:27:50 PM PDT 24
Peak memory 218116 kb
Host smart-7d9db656-5aa0-48ec-81f0-6505b4e75487
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206612255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1206612255
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2688225254
Short name T776
Test name
Test status
Simulation time 1213661449 ps
CPU time 32.77 seconds
Started Jul 16 06:27:41 PM PDT 24
Finished Jul 16 06:28:15 PM PDT 24
Peak memory 217560 kb
Host smart-bab6b850-ebc2-42ba-b486-7df38b8e23d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688225254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2688225254
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.204912081
Short name T809
Test name
Test status
Simulation time 923427148 ps
CPU time 8.41 seconds
Started Jul 16 06:27:24 PM PDT 24
Finished Jul 16 06:27:33 PM PDT 24
Peak memory 217508 kb
Host smart-d6f443a8-2bb2-4d88-b924-23acfbc29c42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204912081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.204912081
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.52906215
Short name T273
Test name
Test status
Simulation time 1065712418 ps
CPU time 28.26 seconds
Started Jul 16 06:27:38 PM PDT 24
Finished Jul 16 06:28:06 PM PDT 24
Peak memory 249396 kb
Host smart-78784eac-e1ac-4b61-bcd9-bdf5bbc9b1b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52906215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
state_failure.52906215
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3210965251
Short name T362
Test name
Test status
Simulation time 694900779 ps
CPU time 11.44 seconds
Started Jul 16 06:27:36 PM PDT 24
Finished Jul 16 06:27:48 PM PDT 24
Peak memory 224728 kb
Host smart-40e38016-95a3-4446-bc23-ae724a836a87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210965251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3210965251
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2456859587
Short name T537
Test name
Test status
Simulation time 112720413 ps
CPU time 2.11 seconds
Started Jul 16 06:27:28 PM PDT 24
Finished Jul 16 06:27:31 PM PDT 24
Peak memory 218188 kb
Host smart-ae47447c-36a9-46dd-ae8b-eedf4f748381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456859587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2456859587
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2518069043
Short name T182
Test name
Test status
Simulation time 316473939 ps
CPU time 8.45 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:34 PM PDT 24
Peak memory 214588 kb
Host smart-395c1b5d-e083-4930-878e-33a77d7d8013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518069043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2518069043
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2119825975
Short name T490
Test name
Test status
Simulation time 192109961 ps
CPU time 10.12 seconds
Started Jul 16 06:27:41 PM PDT 24
Finished Jul 16 06:27:52 PM PDT 24
Peak memory 226136 kb
Host smart-a3c42e67-42ea-433b-bcd9-c515c014e0c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119825975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2119825975
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1463998705
Short name T414
Test name
Test status
Simulation time 830672715 ps
CPU time 10.26 seconds
Started Jul 16 06:27:35 PM PDT 24
Finished Jul 16 06:27:46 PM PDT 24
Peak memory 225848 kb
Host smart-eb53af3d-bfaa-446e-9651-663233a25ed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463998705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1463998705
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1753278448
Short name T153
Test name
Test status
Simulation time 173897223 ps
CPU time 7.83 seconds
Started Jul 16 06:27:33 PM PDT 24
Finished Jul 16 06:27:41 PM PDT 24
Peak memory 225876 kb
Host smart-9e8228ca-fd48-488d-960f-d5330c45b8e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753278448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
753278448
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1292269074
Short name T722
Test name
Test status
Simulation time 382377019 ps
CPU time 8.82 seconds
Started Jul 16 06:27:28 PM PDT 24
Finished Jul 16 06:27:38 PM PDT 24
Peak memory 218280 kb
Host smart-b15ab351-112a-410e-ba01-bde33e46755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292269074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1292269074
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1209964626
Short name T1
Test name
Test status
Simulation time 29069639 ps
CPU time 1.65 seconds
Started Jul 16 06:27:28 PM PDT 24
Finished Jul 16 06:27:30 PM PDT 24
Peak memory 213736 kb
Host smart-3f4c58b2-a7cf-47ee-8391-00d9b99329c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209964626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1209964626
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3316437147
Short name T176
Test name
Test status
Simulation time 407741064 ps
CPU time 15.74 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:41 PM PDT 24
Peak memory 250956 kb
Host smart-1917775b-7b8c-436d-83d6-506221733778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316437147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3316437147
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1143999439
Short name T629
Test name
Test status
Simulation time 101145313 ps
CPU time 6.77 seconds
Started Jul 16 06:27:26 PM PDT 24
Finished Jul 16 06:27:33 PM PDT 24
Peak memory 250444 kb
Host smart-c809d6e3-2978-4cb5-97aa-f38b374727f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143999439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1143999439
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1371223234
Short name T105
Test name
Test status
Simulation time 11996890 ps
CPU time 0.89 seconds
Started Jul 16 06:27:25 PM PDT 24
Finished Jul 16 06:27:26 PM PDT 24
Peak memory 211732 kb
Host smart-bc9238fe-9c1c-47b7-a109-e33fcf7e7d72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371223234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1371223234
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2369433133
Short name T494
Test name
Test status
Simulation time 22963440 ps
CPU time 1.23 seconds
Started Jul 16 06:29:10 PM PDT 24
Finished Jul 16 06:29:13 PM PDT 24
Peak memory 208892 kb
Host smart-a9a3e5fc-6412-4912-8ce9-ce4c930a4fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369433133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2369433133
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3813983442
Short name T532
Test name
Test status
Simulation time 858807938 ps
CPU time 10.15 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:10 PM PDT 24
Peak memory 218204 kb
Host smart-7fd1c89a-17a4-4f2d-8814-ffb9f19b9b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813983442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3813983442
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3077145360
Short name T350
Test name
Test status
Simulation time 534758401 ps
CPU time 6.43 seconds
Started Jul 16 06:29:12 PM PDT 24
Finished Jul 16 06:29:20 PM PDT 24
Peak memory 217252 kb
Host smart-51a0d445-9e2a-45d7-a942-0f038d32a1c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077145360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3077145360
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1655732780
Short name T324
Test name
Test status
Simulation time 62125814190 ps
CPU time 46.21 seconds
Started Jul 16 06:29:10 PM PDT 24
Finished Jul 16 06:29:58 PM PDT 24
Peak memory 225968 kb
Host smart-71edce99-c496-4544-8fec-4c095aa0327b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655732780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1655732780
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1033667588
Short name T374
Test name
Test status
Simulation time 461349978 ps
CPU time 7.51 seconds
Started Jul 16 06:29:11 PM PDT 24
Finished Jul 16 06:29:20 PM PDT 24
Peak memory 222876 kb
Host smart-630a4005-114f-4866-b2dd-f84a1f3a87f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033667588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1033667588
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2731575314
Short name T517
Test name
Test status
Simulation time 909637229 ps
CPU time 11.77 seconds
Started Jul 16 06:28:59 PM PDT 24
Finished Jul 16 06:29:12 PM PDT 24
Peak memory 217560 kb
Host smart-41ba525b-88fb-4beb-b7a7-edfaf468292b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731575314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2731575314
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1863054973
Short name T732
Test name
Test status
Simulation time 4863664420 ps
CPU time 87.46 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:30:26 PM PDT 24
Peak memory 250876 kb
Host smart-3f67faf9-2a21-470d-8717-b5bf27382309
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863054973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1863054973
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2370826921
Short name T382
Test name
Test status
Simulation time 350244168 ps
CPU time 16.11 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:15 PM PDT 24
Peak memory 250836 kb
Host smart-745042e9-f6e0-490b-af9a-515b194b7f96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370826921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2370826921
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4248072035
Short name T35
Test name
Test status
Simulation time 120303490 ps
CPU time 2.54 seconds
Started Jul 16 06:28:56 PM PDT 24
Finished Jul 16 06:29:00 PM PDT 24
Peak memory 222212 kb
Host smart-ff7c1bbc-5822-4fdd-9f57-8fcdeff9f336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248072035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4248072035
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2299888376
Short name T757
Test name
Test status
Simulation time 533546075 ps
CPU time 13.77 seconds
Started Jul 16 06:29:10 PM PDT 24
Finished Jul 16 06:29:26 PM PDT 24
Peak memory 226040 kb
Host smart-b7fee146-6a09-4523-b99d-899fa08b8410
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299888376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2299888376
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2981155517
Short name T799
Test name
Test status
Simulation time 455793700 ps
CPU time 14.42 seconds
Started Jul 16 06:29:11 PM PDT 24
Finished Jul 16 06:29:28 PM PDT 24
Peak memory 225884 kb
Host smart-c735471d-f043-4290-846e-80c8d253eda3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981155517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2981155517
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1492736351
Short name T245
Test name
Test status
Simulation time 1058107318 ps
CPU time 8.33 seconds
Started Jul 16 06:29:09 PM PDT 24
Finished Jul 16 06:29:18 PM PDT 24
Peak memory 218240 kb
Host smart-da04aaf5-57f7-43dc-bdd1-5458734b22c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492736351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1492736351
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4204034007
Short name T695
Test name
Test status
Simulation time 1399952377 ps
CPU time 8.31 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:07 PM PDT 24
Peak memory 225124 kb
Host smart-ec934702-59a9-4c5b-8289-8870388ef535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204034007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4204034007
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2925066978
Short name T620
Test name
Test status
Simulation time 40417100 ps
CPU time 2.08 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:00 PM PDT 24
Peak memory 217716 kb
Host smart-3d1b5984-707e-4dbb-9d99-22555d971e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925066978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2925066978
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3014966957
Short name T378
Test name
Test status
Simulation time 340674405 ps
CPU time 23.62 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:21 PM PDT 24
Peak memory 250864 kb
Host smart-87192b80-4d04-43bd-9bc2-78bee49c20c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014966957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3014966957
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3042640575
Short name T515
Test name
Test status
Simulation time 333045539 ps
CPU time 8 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:06 PM PDT 24
Peak memory 250924 kb
Host smart-f0c9b813-c985-4ded-9416-8fb10745cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042640575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3042640575
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3693110272
Short name T530
Test name
Test status
Simulation time 15262078304 ps
CPU time 178.33 seconds
Started Jul 16 06:29:11 PM PDT 24
Finished Jul 16 06:32:11 PM PDT 24
Peak memory 283688 kb
Host smart-5cd88c86-7e45-4473-ae21-f462db9998cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693110272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3693110272
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2733327753
Short name T607
Test name
Test status
Simulation time 134696003 ps
CPU time 0.84 seconds
Started Jul 16 06:28:56 PM PDT 24
Finished Jul 16 06:28:57 PM PDT 24
Peak memory 211780 kb
Host smart-3eaabde8-fcaf-4655-8eba-bb42f498fc6d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733327753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2733327753
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1082920828
Short name T381
Test name
Test status
Simulation time 32508965 ps
CPU time 0.94 seconds
Started Jul 16 06:29:29 PM PDT 24
Finished Jul 16 06:29:30 PM PDT 24
Peak memory 208816 kb
Host smart-b2254696-b694-4041-80a2-467633a1045a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082920828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1082920828
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2600340689
Short name T520
Test name
Test status
Simulation time 791592442 ps
CPU time 12.27 seconds
Started Jul 16 06:29:12 PM PDT 24
Finished Jul 16 06:29:26 PM PDT 24
Peak memory 218220 kb
Host smart-1eea41f7-2a9f-49ec-aa44-971506da3842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600340689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2600340689
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.4133696519
Short name T748
Test name
Test status
Simulation time 362400787 ps
CPU time 4.97 seconds
Started Jul 16 06:29:26 PM PDT 24
Finished Jul 16 06:29:32 PM PDT 24
Peak memory 217172 kb
Host smart-7d398362-6e6c-4ff7-add2-7507ebcee666
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133696519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.4133696519
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1399706684
Short name T841
Test name
Test status
Simulation time 1909008223 ps
CPU time 55.56 seconds
Started Jul 16 06:29:10 PM PDT 24
Finished Jul 16 06:30:08 PM PDT 24
Peak memory 225884 kb
Host smart-b1507e25-4d97-4656-b594-2676000e193d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399706684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1399706684
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1908657326
Short name T527
Test name
Test status
Simulation time 1499292499 ps
CPU time 10.07 seconds
Started Jul 16 06:29:12 PM PDT 24
Finished Jul 16 06:29:24 PM PDT 24
Peak memory 218060 kb
Host smart-89416180-ba6a-4425-83d3-a78f88e157c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908657326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1908657326
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.500635282
Short name T443
Test name
Test status
Simulation time 301343069 ps
CPU time 6.14 seconds
Started Jul 16 06:29:11 PM PDT 24
Finished Jul 16 06:29:19 PM PDT 24
Peak memory 217580 kb
Host smart-6dbd9206-a451-4e8f-aa30-66c51279b8ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500635282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
500635282
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.365644636
Short name T25
Test name
Test status
Simulation time 1354290637 ps
CPU time 43.45 seconds
Started Jul 16 06:29:11 PM PDT 24
Finished Jul 16 06:29:56 PM PDT 24
Peak memory 267188 kb
Host smart-4dba62d1-c04c-475a-aee5-6ee4c8993b7b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365644636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.365644636
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4155229830
Short name T473
Test name
Test status
Simulation time 858005553 ps
CPU time 12.97 seconds
Started Jul 16 06:29:09 PM PDT 24
Finished Jul 16 06:29:23 PM PDT 24
Peak memory 248492 kb
Host smart-cc812b85-139d-4c8d-bb8f-c7000e859ac5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155229830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4155229830
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3074654848
Short name T811
Test name
Test status
Simulation time 106218589 ps
CPU time 2.28 seconds
Started Jul 16 06:29:11 PM PDT 24
Finished Jul 16 06:29:15 PM PDT 24
Peak memory 218212 kb
Host smart-3b9d2a75-db40-4073-98e7-983fcdd2c15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074654848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3074654848
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2365238504
Short name T588
Test name
Test status
Simulation time 2047839086 ps
CPU time 11.02 seconds
Started Jul 16 06:29:28 PM PDT 24
Finished Jul 16 06:29:40 PM PDT 24
Peak memory 226000 kb
Host smart-fc5287f7-c908-4d86-b89b-6cd0e5ad2edc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365238504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2365238504
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3140226766
Short name T228
Test name
Test status
Simulation time 619435687 ps
CPU time 12.61 seconds
Started Jul 16 06:29:29 PM PDT 24
Finished Jul 16 06:29:43 PM PDT 24
Peak memory 225956 kb
Host smart-a7b3b312-201f-4fce-8adc-319c0151d8e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140226766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3140226766
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2121570015
Short name T461
Test name
Test status
Simulation time 1922973268 ps
CPU time 10.55 seconds
Started Jul 16 06:29:22 PM PDT 24
Finished Jul 16 06:29:33 PM PDT 24
Peak memory 218184 kb
Host smart-01d1e2ea-a0f0-4a6b-a521-26bb3eefdc8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121570015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2121570015
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3338409626
Short name T220
Test name
Test status
Simulation time 285563190 ps
CPU time 11.19 seconds
Started Jul 16 06:29:11 PM PDT 24
Finished Jul 16 06:29:24 PM PDT 24
Peak memory 225724 kb
Host smart-47b51d55-a2f3-44ee-b9a5-76a38a6907e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338409626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3338409626
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3017480215
Short name T825
Test name
Test status
Simulation time 89897759 ps
CPU time 1.43 seconds
Started Jul 16 06:29:09 PM PDT 24
Finished Jul 16 06:29:12 PM PDT 24
Peak memory 213676 kb
Host smart-484b9e74-667e-4276-89be-7dcc05788f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017480215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3017480215
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1294638751
Short name T469
Test name
Test status
Simulation time 960417566 ps
CPU time 30.22 seconds
Started Jul 16 06:29:10 PM PDT 24
Finished Jul 16 06:29:42 PM PDT 24
Peak memory 250852 kb
Host smart-7104af38-7fb7-4e88-ad69-7dcc385d6de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294638751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1294638751
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3903352167
Short name T103
Test name
Test status
Simulation time 51016494 ps
CPU time 6.88 seconds
Started Jul 16 06:29:09 PM PDT 24
Finished Jul 16 06:29:17 PM PDT 24
Peak memory 250376 kb
Host smart-ebf42e63-764e-407e-b2a5-ac8fc3668972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903352167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3903352167
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.252366111
Short name T805
Test name
Test status
Simulation time 43943517815 ps
CPU time 335.02 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:34:59 PM PDT 24
Peak memory 253480 kb
Host smart-e34c3ef4-32eb-4908-a777-c4b0e4d29d20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252366111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.252366111
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3253075939
Short name T765
Test name
Test status
Simulation time 34113217 ps
CPU time 0.83 seconds
Started Jul 16 06:29:12 PM PDT 24
Finished Jul 16 06:29:15 PM PDT 24
Peak memory 211792 kb
Host smart-c49bd5c3-ba74-4643-b930-24da45975200
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253075939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3253075939
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1505161028
Short name T741
Test name
Test status
Simulation time 14211425 ps
CPU time 1.02 seconds
Started Jul 16 06:29:26 PM PDT 24
Finished Jul 16 06:29:28 PM PDT 24
Peak memory 208720 kb
Host smart-6e4abf17-1420-4d7c-9ce5-3d3936fe2748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505161028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1505161028
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3495734136
Short name T343
Test name
Test status
Simulation time 1866252090 ps
CPU time 3.08 seconds
Started Jul 16 06:29:26 PM PDT 24
Finished Jul 16 06:29:30 PM PDT 24
Peak memory 216992 kb
Host smart-7d3cd8fe-b90a-47bd-9a04-8c0131a792c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495734136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3495734136
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.198512680
Short name T226
Test name
Test status
Simulation time 1887851262 ps
CPU time 8.3 seconds
Started Jul 16 06:29:29 PM PDT 24
Finished Jul 16 06:29:37 PM PDT 24
Peak memory 218152 kb
Host smart-d0e1b53a-6da1-4322-b614-000574e0dab2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198512680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.198512680
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2976132588
Short name T625
Test name
Test status
Simulation time 134482111 ps
CPU time 1.71 seconds
Started Jul 16 06:29:29 PM PDT 24
Finished Jul 16 06:29:31 PM PDT 24
Peak memory 217560 kb
Host smart-38fac844-7f59-41ab-9d65-eed5cde65d85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976132588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2976132588
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3761023215
Short name T239
Test name
Test status
Simulation time 1450169076 ps
CPU time 65.79 seconds
Started Jul 16 06:29:27 PM PDT 24
Finished Jul 16 06:30:34 PM PDT 24
Peak memory 283472 kb
Host smart-5c2c3600-37d1-4ea9-91fe-0fb0b17b4373
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761023215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3761023215
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.871738599
Short name T545
Test name
Test status
Simulation time 373358957 ps
CPU time 12.12 seconds
Started Jul 16 06:29:27 PM PDT 24
Finished Jul 16 06:29:40 PM PDT 24
Peak memory 222800 kb
Host smart-02b426e1-ba54-404e-99b6-0f18ce630f19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871738599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.871738599
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1044748632
Short name T14
Test name
Test status
Simulation time 139759283 ps
CPU time 1.91 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:26 PM PDT 24
Peak memory 218208 kb
Host smart-7fac85a7-feef-4b03-9eae-3686d085c720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044748632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1044748632
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1641137106
Short name T636
Test name
Test status
Simulation time 1606872164 ps
CPU time 16.96 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:41 PM PDT 24
Peak memory 225980 kb
Host smart-187f58a8-7f46-4a1b-bc2b-460346cb9aad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641137106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1641137106
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2516097029
Short name T634
Test name
Test status
Simulation time 833240289 ps
CPU time 12.39 seconds
Started Jul 16 06:29:24 PM PDT 24
Finished Jul 16 06:29:38 PM PDT 24
Peak memory 225952 kb
Host smart-ecc1bb2a-8b57-4da6-ae91-5ea01c4fcdfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516097029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2516097029
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1322131784
Short name T287
Test name
Test status
Simulation time 628053664 ps
CPU time 7.16 seconds
Started Jul 16 06:29:24 PM PDT 24
Finished Jul 16 06:29:32 PM PDT 24
Peak memory 218240 kb
Host smart-184d5368-dc3e-45eb-9109-ff4062fdab64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322131784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1322131784
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3375655886
Short name T301
Test name
Test status
Simulation time 511191363 ps
CPU time 9.33 seconds
Started Jul 16 06:29:29 PM PDT 24
Finished Jul 16 06:29:39 PM PDT 24
Peak memory 225292 kb
Host smart-b7c80d2e-4f36-49e0-aada-926de1fd2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375655886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3375655886
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.50890643
Short name T546
Test name
Test status
Simulation time 171141512 ps
CPU time 2.95 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:28 PM PDT 24
Peak memory 214608 kb
Host smart-767b0590-0a01-4dcc-b923-30bcbfe3946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50890643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.50890643
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.817477059
Short name T624
Test name
Test status
Simulation time 3482048096 ps
CPU time 23.67 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:48 PM PDT 24
Peak memory 250948 kb
Host smart-5f35f09e-2a97-43f4-b7da-275a270c780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817477059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.817477059
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3254980925
Short name T858
Test name
Test status
Simulation time 240818357 ps
CPU time 9.71 seconds
Started Jul 16 06:29:24 PM PDT 24
Finished Jul 16 06:29:35 PM PDT 24
Peak memory 250404 kb
Host smart-adf63d1f-452c-40f3-aeaa-64402ac3dd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254980925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3254980925
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3279567967
Short name T770
Test name
Test status
Simulation time 8784621241 ps
CPU time 84.34 seconds
Started Jul 16 06:29:24 PM PDT 24
Finished Jul 16 06:30:50 PM PDT 24
Peak memory 250956 kb
Host smart-fdec9c52-f188-4a38-8608-e8997b55a504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279567967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3279567967
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3538645309
Short name T835
Test name
Test status
Simulation time 16868174 ps
CPU time 0.87 seconds
Started Jul 16 06:29:25 PM PDT 24
Finished Jul 16 06:29:27 PM PDT 24
Peak memory 211780 kb
Host smart-5a6fc3f1-d382-4bcf-8cbe-b9c16285122e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538645309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3538645309
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1708447829
Short name T627
Test name
Test status
Simulation time 26268394 ps
CPU time 1 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:29:46 PM PDT 24
Peak memory 208720 kb
Host smart-489bf7c3-4252-4ca4-96e8-7adbec173a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708447829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1708447829
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3054668877
Short name T152
Test name
Test status
Simulation time 365893460 ps
CPU time 15.47 seconds
Started Jul 16 06:29:28 PM PDT 24
Finished Jul 16 06:29:44 PM PDT 24
Peak memory 225964 kb
Host smart-87cc9939-4f96-4f5b-84ba-f1fcc5ca30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054668877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3054668877
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2032225180
Short name T511
Test name
Test status
Simulation time 591604828 ps
CPU time 4.21 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:29 PM PDT 24
Peak memory 217084 kb
Host smart-e85b52f5-e8be-4454-91d6-8a0703f7cca8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032225180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2032225180
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.539992581
Short name T761
Test name
Test status
Simulation time 1057171157 ps
CPU time 21.61 seconds
Started Jul 16 06:29:24 PM PDT 24
Finished Jul 16 06:29:47 PM PDT 24
Peak memory 218044 kb
Host smart-fe728c38-b4a4-466e-9ba5-3b19d174df28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539992581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.539992581
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2112125470
Short name T600
Test name
Test status
Simulation time 1515006355 ps
CPU time 6.83 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:31 PM PDT 24
Peak memory 218140 kb
Host smart-4b94f0e9-f9b4-4435-a53f-c4c76293dc9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112125470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2112125470
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2391869656
Short name T753
Test name
Test status
Simulation time 1212136378 ps
CPU time 5.25 seconds
Started Jul 16 06:29:26 PM PDT 24
Finished Jul 16 06:29:32 PM PDT 24
Peak memory 217516 kb
Host smart-1798b1d8-ff75-46d6-b5e8-bf0c83f29424
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391869656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2391869656
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.4010832027
Short name T705
Test name
Test status
Simulation time 12114528316 ps
CPU time 95.7 seconds
Started Jul 16 06:29:29 PM PDT 24
Finished Jul 16 06:31:05 PM PDT 24
Peak memory 283576 kb
Host smart-bf8624ab-002b-4349-b9e6-2158fd44ada8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010832027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.4010832027
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1281876440
Short name T433
Test name
Test status
Simulation time 968823911 ps
CPU time 7.08 seconds
Started Jul 16 06:29:25 PM PDT 24
Finished Jul 16 06:29:33 PM PDT 24
Peak memory 222812 kb
Host smart-fa41acd6-010d-427e-9d59-b441a6e22b59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281876440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1281876440
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4255379281
Short name T459
Test name
Test status
Simulation time 194570923 ps
CPU time 2.13 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:26 PM PDT 24
Peak memory 218160 kb
Host smart-456cb23f-025b-4b6d-bb62-4e2d3629b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255379281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4255379281
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3695776255
Short name T609
Test name
Test status
Simulation time 978247723 ps
CPU time 21.22 seconds
Started Jul 16 06:29:34 PM PDT 24
Finished Jul 16 06:29:56 PM PDT 24
Peak memory 225884 kb
Host smart-06e172c4-c8d8-40b8-9b20-176a73b8fcc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695776255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3695776255
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3094239352
Short name T671
Test name
Test status
Simulation time 429597461 ps
CPU time 14.56 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:52 PM PDT 24
Peak memory 218152 kb
Host smart-ed67b4e4-ad4f-4a80-a5fe-1d5c0568990d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094239352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3094239352
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2953970994
Short name T376
Test name
Test status
Simulation time 2234617254 ps
CPU time 11.51 seconds
Started Jul 16 06:29:25 PM PDT 24
Finished Jul 16 06:29:37 PM PDT 24
Peak memory 226060 kb
Host smart-0f067684-c9ab-446f-a8c3-30d477e9e27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953970994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2953970994
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3449843645
Short name T760
Test name
Test status
Simulation time 40669406 ps
CPU time 1.28 seconds
Started Jul 16 06:29:22 PM PDT 24
Finished Jul 16 06:29:24 PM PDT 24
Peak memory 221932 kb
Host smart-d1d29a4a-8bd1-44f2-9aba-16ac1b630b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449843645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3449843645
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.401889030
Short name T723
Test name
Test status
Simulation time 1098851286 ps
CPU time 35.77 seconds
Started Jul 16 06:29:29 PM PDT 24
Finished Jul 16 06:30:05 PM PDT 24
Peak memory 246416 kb
Host smart-16ff6936-a18f-45ff-95a3-4d0ad3a45bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401889030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.401889030
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1932241692
Short name T456
Test name
Test status
Simulation time 108852505 ps
CPU time 3.23 seconds
Started Jul 16 06:29:22 PM PDT 24
Finished Jul 16 06:29:26 PM PDT 24
Peak memory 226416 kb
Host smart-3d86e8d7-e58d-4b89-af56-27faa1703214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932241692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1932241692
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1120202081
Short name T808
Test name
Test status
Simulation time 27029148538 ps
CPU time 113.7 seconds
Started Jul 16 06:29:35 PM PDT 24
Finished Jul 16 06:31:29 PM PDT 24
Peak memory 280480 kb
Host smart-afe790bb-c483-4777-b3c3-da28fd167b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120202081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1120202081
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3749019161
Short name T751
Test name
Test status
Simulation time 18406799 ps
CPU time 0.91 seconds
Started Jul 16 06:29:23 PM PDT 24
Finished Jul 16 06:29:26 PM PDT 24
Peak memory 211832 kb
Host smart-3c19519d-9b5e-4498-a955-c1bc9ef2358f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749019161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3749019161
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.743667675
Short name T94
Test name
Test status
Simulation time 14231381 ps
CPU time 0.84 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:38 PM PDT 24
Peak memory 208552 kb
Host smart-f7f6b8ac-8237-4850-bfd9-ff7756da7b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743667675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.743667675
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1866837949
Short name T151
Test name
Test status
Simulation time 2311412519 ps
CPU time 13.47 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:50 PM PDT 24
Peak memory 226004 kb
Host smart-a46cce5a-b8d8-4738-84ab-5aa8a65ffaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866837949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1866837949
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3661722232
Short name T807
Test name
Test status
Simulation time 589453391 ps
CPU time 4.52 seconds
Started Jul 16 06:29:37 PM PDT 24
Finished Jul 16 06:29:43 PM PDT 24
Peak memory 217004 kb
Host smart-44c60395-cab2-4e8d-9251-0fcda4eb5373
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661722232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3661722232
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2880426888
Short name T326
Test name
Test status
Simulation time 6724437361 ps
CPU time 60.24 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:30:37 PM PDT 24
Peak memory 226044 kb
Host smart-a41fe01e-da94-460b-9356-f1a1b8dbb9d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880426888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2880426888
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.417764877
Short name T294
Test name
Test status
Simulation time 410163853 ps
CPU time 8.56 seconds
Started Jul 16 06:29:35 PM PDT 24
Finished Jul 16 06:29:44 PM PDT 24
Peak memory 218136 kb
Host smart-ed482768-6bff-4d63-a114-6a044867be35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417764877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.417764877
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2297746594
Short name T641
Test name
Test status
Simulation time 181663359 ps
CPU time 4.02 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:41 PM PDT 24
Peak memory 217564 kb
Host smart-dc695890-fe3d-46dc-8030-dc44db22941b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297746594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2297746594
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1733550795
Short name T512
Test name
Test status
Simulation time 22932932020 ps
CPU time 84.17 seconds
Started Jul 16 06:29:34 PM PDT 24
Finished Jul 16 06:30:59 PM PDT 24
Peak memory 267356 kb
Host smart-06de3f80-0ed7-4291-a1b6-9acbffa5dfa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733550795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1733550795
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.152507727
Short name T803
Test name
Test status
Simulation time 668594901 ps
CPU time 19.43 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:30:04 PM PDT 24
Peak memory 222416 kb
Host smart-80652db5-5bf0-4024-8b0f-961724569d22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152507727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.152507727
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1967791059
Short name T581
Test name
Test status
Simulation time 79750422 ps
CPU time 2.85 seconds
Started Jul 16 06:29:43 PM PDT 24
Finished Jul 16 06:29:46 PM PDT 24
Peak memory 222420 kb
Host smart-4f76cd9c-45f6-426c-9df5-811dbdc6592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967791059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1967791059
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3184169447
Short name T304
Test name
Test status
Simulation time 265134927 ps
CPU time 13.28 seconds
Started Jul 16 06:29:34 PM PDT 24
Finished Jul 16 06:29:48 PM PDT 24
Peak memory 225884 kb
Host smart-d8414d22-63ec-4900-b1b2-165ac629e004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184169447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3184169447
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3089530866
Short name T486
Test name
Test status
Simulation time 381682704 ps
CPU time 10.64 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:48 PM PDT 24
Peak memory 225928 kb
Host smart-e00d960f-d597-43bd-9134-721eec80689d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089530866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3089530866
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1898848637
Short name T533
Test name
Test status
Simulation time 1228484565 ps
CPU time 11.62 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:29:56 PM PDT 24
Peak memory 225728 kb
Host smart-a25fdca1-8d38-416f-ad09-a1383a1dc385
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898848637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1898848637
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3455893540
Short name T60
Test name
Test status
Simulation time 135723487 ps
CPU time 4.29 seconds
Started Jul 16 06:29:35 PM PDT 24
Finished Jul 16 06:29:40 PM PDT 24
Peak memory 217580 kb
Host smart-ca67b572-522e-4223-9a0e-ddea85ac56e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455893540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3455893540
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2560980395
Short name T783
Test name
Test status
Simulation time 1208962710 ps
CPU time 22.74 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:30:00 PM PDT 24
Peak memory 251060 kb
Host smart-7b1e6f51-85d1-41b4-a007-ceb9143dcedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560980395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2560980395
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.450525101
Short name T440
Test name
Test status
Simulation time 60448769 ps
CPU time 2.95 seconds
Started Jul 16 06:29:35 PM PDT 24
Finished Jul 16 06:29:39 PM PDT 24
Peak memory 222464 kb
Host smart-70f7d974-b2d8-4413-9354-b114517c30f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450525101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.450525101
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3116914247
Short name T356
Test name
Test status
Simulation time 3392166545 ps
CPU time 73.17 seconds
Started Jul 16 06:29:34 PM PDT 24
Finished Jul 16 06:30:48 PM PDT 24
Peak memory 272088 kb
Host smart-d43228f7-2504-4482-a088-58d4da165d0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116914247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3116914247
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3042730864
Short name T149
Test name
Test status
Simulation time 23798343861 ps
CPU time 468.63 seconds
Started Jul 16 06:29:37 PM PDT 24
Finished Jul 16 06:37:26 PM PDT 24
Peak memory 333136 kb
Host smart-b1b0ae92-1fd2-48b0-b9c2-c3212f4935f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3042730864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3042730864
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1469769965
Short name T359
Test name
Test status
Simulation time 12576697 ps
CPU time 0.84 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:38 PM PDT 24
Peak memory 211864 kb
Host smart-ba028fd4-17c9-408d-96e5-58e61ceb7ba0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469769965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1469769965
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3853708541
Short name T249
Test name
Test status
Simulation time 67070841 ps
CPU time 1.1 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:30:40 PM PDT 24
Peak memory 208932 kb
Host smart-bdb5d02f-1982-4466-a062-3e88039a06f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853708541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3853708541
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2833370240
Short name T432
Test name
Test status
Simulation time 342094987 ps
CPU time 13.9 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:29:59 PM PDT 24
Peak memory 225796 kb
Host smart-1b56c6be-cd23-429a-b7dd-9dd5c195ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833370240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2833370240
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2450856323
Short name T49
Test name
Test status
Simulation time 793046761 ps
CPU time 3.07 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:40 PM PDT 24
Peak memory 217000 kb
Host smart-8ffcd35c-db17-4a1d-b9e4-9bb64d3cb45e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450856323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2450856323
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1478191250
Short name T550
Test name
Test status
Simulation time 9425205025 ps
CPU time 33.31 seconds
Started Jul 16 06:29:48 PM PDT 24
Finished Jul 16 06:30:22 PM PDT 24
Peak memory 225952 kb
Host smart-36e3cd9b-1eae-4cca-b20b-80eaf939b7bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478191250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1478191250
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3452853619
Short name T475
Test name
Test status
Simulation time 661764526 ps
CPU time 10.14 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:48 PM PDT 24
Peak memory 218140 kb
Host smart-5cd7df53-e2b2-4c2d-be09-027e686f9762
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452853619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3452853619
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.287163259
Short name T615
Test name
Test status
Simulation time 287976441 ps
CPU time 4.74 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:41 PM PDT 24
Peak memory 217524 kb
Host smart-482144b6-79c0-4fdc-aa1c-2d8ca0594af8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287163259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
287163259
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.28626609
Short name T699
Test name
Test status
Simulation time 7092479063 ps
CPU time 111.71 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:31:37 PM PDT 24
Peak memory 282240 kb
Host smart-fe857c17-4d71-480a-af95-47860c2f739a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28626609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_state_failure.28626609
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.133293972
Short name T223
Test name
Test status
Simulation time 554281607 ps
CPU time 20.67 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:30:06 PM PDT 24
Peak memory 241760 kb
Host smart-f5e4c88b-55f6-4d38-ac4a-7c7f2e2c9f6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133293972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.133293972
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.629326427
Short name T471
Test name
Test status
Simulation time 85321055 ps
CPU time 1.94 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:29:47 PM PDT 24
Peak memory 218088 kb
Host smart-94f11c0a-318d-429d-baad-f34766b0fc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629326427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.629326427
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.172669258
Short name T570
Test name
Test status
Simulation time 3194709939 ps
CPU time 8.74 seconds
Started Jul 16 06:29:38 PM PDT 24
Finished Jul 16 06:29:47 PM PDT 24
Peak memory 218512 kb
Host smart-6d070418-1765-4f08-b720-336e43938060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172669258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.172669258
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3614001237
Short name T247
Test name
Test status
Simulation time 265158369 ps
CPU time 9.39 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:46 PM PDT 24
Peak memory 225972 kb
Host smart-2e983e83-bb75-4014-a94f-b7dbdb62f730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614001237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3614001237
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.4052755781
Short name T543
Test name
Test status
Simulation time 360807204 ps
CPU time 10.02 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:48 PM PDT 24
Peak memory 225912 kb
Host smart-225888d7-5cd4-44ec-a565-47d36e26bf44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052755781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
4052755781
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.4025033329
Short name T734
Test name
Test status
Simulation time 1392339198 ps
CPU time 12.6 seconds
Started Jul 16 06:29:36 PM PDT 24
Finished Jul 16 06:29:50 PM PDT 24
Peak memory 225944 kb
Host smart-1db13d38-6bc1-4870-bd75-7303a4e829b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025033329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4025033329
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.262064104
Short name T639
Test name
Test status
Simulation time 88772403 ps
CPU time 2.75 seconds
Started Jul 16 06:29:35 PM PDT 24
Finished Jul 16 06:29:38 PM PDT 24
Peak memory 217628 kb
Host smart-66daf7ff-874b-433e-a6a0-3d2a52b0e3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262064104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.262064104
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1729678256
Short name T271
Test name
Test status
Simulation time 548365486 ps
CPU time 18.12 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:30:03 PM PDT 24
Peak memory 246468 kb
Host smart-f98395de-d1da-467f-8c5c-249c29aaaa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729678256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1729678256
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2485296156
Short name T386
Test name
Test status
Simulation time 153570637 ps
CPU time 7.21 seconds
Started Jul 16 06:29:37 PM PDT 24
Finished Jul 16 06:29:45 PM PDT 24
Peak memory 250940 kb
Host smart-d4a39690-d4bf-4095-b46c-8260e15a2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485296156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2485296156
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2543841822
Short name T660
Test name
Test status
Simulation time 30506288 ps
CPU time 0.88 seconds
Started Jul 16 06:29:34 PM PDT 24
Finished Jul 16 06:29:36 PM PDT 24
Peak memory 211768 kb
Host smart-74d22dd7-fa70-4083-ba56-4fbd4cae0ad2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543841822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2543841822
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1627434031
Short name T339
Test name
Test status
Simulation time 143981125 ps
CPU time 0.98 seconds
Started Jul 16 06:29:46 PM PDT 24
Finished Jul 16 06:29:48 PM PDT 24
Peak memory 208828 kb
Host smart-b55eee6e-4438-44b3-b682-4931b598f116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627434031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1627434031
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1835844460
Short name T552
Test name
Test status
Simulation time 734191473 ps
CPU time 14.98 seconds
Started Jul 16 06:29:45 PM PDT 24
Finished Jul 16 06:30:01 PM PDT 24
Peak memory 218224 kb
Host smart-c368b18d-98fa-4a4b-8092-5390423d7001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835844460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1835844460
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3249066869
Short name T347
Test name
Test status
Simulation time 533431878 ps
CPU time 8.49 seconds
Started Jul 16 06:29:45 PM PDT 24
Finished Jul 16 06:29:54 PM PDT 24
Peak memory 218168 kb
Host smart-0b198fec-cfee-496f-bff4-eccea95053d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249066869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3249066869
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1214298978
Short name T180
Test name
Test status
Simulation time 392441545 ps
CPU time 5.96 seconds
Started Jul 16 06:29:44 PM PDT 24
Finished Jul 16 06:29:50 PM PDT 24
Peak memory 217576 kb
Host smart-28c6b81d-e695-4f58-8e9d-f92a70b7094d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214298978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1214298978
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2904943244
Short name T409
Test name
Test status
Simulation time 5219612407 ps
CPU time 46.29 seconds
Started Jul 16 06:29:45 PM PDT 24
Finished Jul 16 06:30:32 PM PDT 24
Peak memory 252216 kb
Host smart-f56b0993-629d-46c6-8368-2024d1c4d2f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904943244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2904943244
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.500342984
Short name T333
Test name
Test status
Simulation time 3967232369 ps
CPU time 18.55 seconds
Started Jul 16 06:29:45 PM PDT 24
Finished Jul 16 06:30:05 PM PDT 24
Peak memory 247380 kb
Host smart-2efb51b5-24dc-4ef7-b58f-0bbff354bab4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500342984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.500342984
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1447698450
Short name T500
Test name
Test status
Simulation time 558566489 ps
CPU time 3.8 seconds
Started Jul 16 06:29:48 PM PDT 24
Finished Jul 16 06:29:53 PM PDT 24
Peak memory 218128 kb
Host smart-a9dfefb4-31cf-40cd-b48c-c63d70bbb3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447698450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1447698450
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1973852472
Short name T289
Test name
Test status
Simulation time 647421555 ps
CPU time 9.8 seconds
Started Jul 16 06:29:45 PM PDT 24
Finished Jul 16 06:29:56 PM PDT 24
Peak memory 226012 kb
Host smart-220b51c1-7dd4-4218-80b4-fd2b27a61248
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973852472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1973852472
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2124809632
Short name T331
Test name
Test status
Simulation time 880312378 ps
CPU time 10.87 seconds
Started Jul 16 06:29:51 PM PDT 24
Finished Jul 16 06:30:02 PM PDT 24
Peak memory 225616 kb
Host smart-e474ade1-e70b-4780-b722-c0d7f9edb5e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124809632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2124809632
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3286314676
Short name T859
Test name
Test status
Simulation time 1822639132 ps
CPU time 9.25 seconds
Started Jul 16 06:29:49 PM PDT 24
Finished Jul 16 06:29:59 PM PDT 24
Peak memory 217876 kb
Host smart-026fa703-f0d0-400f-bf09-55d4a5eff3ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286314676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3286314676
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1182941168
Short name T522
Test name
Test status
Simulation time 1009402343 ps
CPU time 10.62 seconds
Started Jul 16 06:29:53 PM PDT 24
Finished Jul 16 06:30:04 PM PDT 24
Peak memory 225884 kb
Host smart-096cc3d7-caa7-4f42-81d4-85e189db762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182941168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1182941168
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.79166243
Short name T388
Test name
Test status
Simulation time 173558566 ps
CPU time 3.2 seconds
Started Jul 16 06:29:45 PM PDT 24
Finished Jul 16 06:29:49 PM PDT 24
Peak memory 217608 kb
Host smart-c10bdc61-09eb-4c57-aa34-9e7778fe73e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79166243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.79166243
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3285487434
Short name T257
Test name
Test status
Simulation time 2790825801 ps
CPU time 30.03 seconds
Started Jul 16 06:29:46 PM PDT 24
Finished Jul 16 06:30:17 PM PDT 24
Peak memory 250760 kb
Host smart-af86b7e8-0bad-49b5-be38-53af74187fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285487434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3285487434
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2155743305
Short name T557
Test name
Test status
Simulation time 468301109 ps
CPU time 7.05 seconds
Started Jul 16 06:29:47 PM PDT 24
Finished Jul 16 06:29:55 PM PDT 24
Peak memory 246988 kb
Host smart-9bda0d63-ff41-4dc0-897b-795e58f188aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155743305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2155743305
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3665346138
Short name T187
Test name
Test status
Simulation time 15981294096 ps
CPU time 476.62 seconds
Started Jul 16 06:29:48 PM PDT 24
Finished Jul 16 06:37:45 PM PDT 24
Peak memory 496560 kb
Host smart-26c408a4-22b9-47e1-b956-d8878cb5205e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665346138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3665346138
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1781309983
Short name T654
Test name
Test status
Simulation time 6961987801 ps
CPU time 166.63 seconds
Started Jul 16 06:29:45 PM PDT 24
Finished Jul 16 06:32:33 PM PDT 24
Peak memory 267448 kb
Host smart-4cee07f3-add7-4494-85ab-daac48f05ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1781309983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1781309983
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1493239897
Short name T373
Test name
Test status
Simulation time 33302019 ps
CPU time 0.79 seconds
Started Jul 16 06:29:54 PM PDT 24
Finished Jul 16 06:29:56 PM PDT 24
Peak memory 208920 kb
Host smart-131e7486-f3be-4f05-a140-22bb5a55eb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493239897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1493239897
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1605305747
Short name T442
Test name
Test status
Simulation time 345957713 ps
CPU time 13.79 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:10 PM PDT 24
Peak memory 218224 kb
Host smart-9139d45c-0fc9-450e-806c-d15404967ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605305747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1605305747
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3684996320
Short name T772
Test name
Test status
Simulation time 552107394 ps
CPU time 6.47 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:02 PM PDT 24
Peak memory 216976 kb
Host smart-5ed769dd-df5e-4b95-b6c4-1089efc69ae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684996320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3684996320
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.740509546
Short name T269
Test name
Test status
Simulation time 11355901698 ps
CPU time 36.17 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:32 PM PDT 24
Peak memory 218436 kb
Host smart-300aa31e-2ec7-43d2-83b8-f6f04765ea52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740509546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.740509546
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4221948288
Short name T611
Test name
Test status
Simulation time 707832113 ps
CPU time 20.44 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:17 PM PDT 24
Peak memory 218148 kb
Host smart-2db53468-f9c0-484c-b5e3-c82a4336af2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221948288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4221948288
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1117866352
Short name T787
Test name
Test status
Simulation time 839179998 ps
CPU time 12.13 seconds
Started Jul 16 06:29:57 PM PDT 24
Finished Jul 16 06:30:10 PM PDT 24
Peak memory 217560 kb
Host smart-ce4a3b3b-08ed-4b2d-b48b-677f37b96aa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117866352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1117866352
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3861144970
Short name T795
Test name
Test status
Simulation time 1696819641 ps
CPU time 43.4 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:30:41 PM PDT 24
Peak memory 269188 kb
Host smart-9031d9ce-a2aa-4de7-9da7-56b94fd84c56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861144970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3861144970
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3036654236
Short name T670
Test name
Test status
Simulation time 6959785498 ps
CPU time 29.84 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:30:27 PM PDT 24
Peak memory 250976 kb
Host smart-e7012c46-e7d1-4034-a776-acc8a89336cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036654236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3036654236
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2699743678
Short name T652
Test name
Test status
Simulation time 33647588 ps
CPU time 1.4 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:29:59 PM PDT 24
Peak memory 218192 kb
Host smart-3bd76522-fead-4e8e-a9ad-92970c6817e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699743678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2699743678
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2247715342
Short name T303
Test name
Test status
Simulation time 1396905575 ps
CPU time 9.91 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:17 PM PDT 24
Peak memory 225532 kb
Host smart-c6b413b5-921f-446b-998f-d8349939cd8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247715342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2247715342
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1225937187
Short name T241
Test name
Test status
Simulation time 2132793788 ps
CPU time 6.79 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:03 PM PDT 24
Peak memory 218076 kb
Host smart-c5ac13c5-c0d5-411b-b00a-e062bf3c05cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225937187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1225937187
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2815557092
Short name T801
Test name
Test status
Simulation time 460658126 ps
CPU time 18.1 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:30:15 PM PDT 24
Peak memory 226036 kb
Host smart-873abf5a-1e7b-4180-857e-1eb685bf3701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815557092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2815557092
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.309610811
Short name T694
Test name
Test status
Simulation time 122233276 ps
CPU time 2.73 seconds
Started Jul 16 06:29:47 PM PDT 24
Finished Jul 16 06:29:51 PM PDT 24
Peak memory 214164 kb
Host smart-c432334e-73ce-4deb-973c-84e0f44cf27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309610811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.309610811
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1744409654
Short name T497
Test name
Test status
Simulation time 1244413348 ps
CPU time 22.19 seconds
Started Jul 16 06:29:51 PM PDT 24
Finished Jul 16 06:30:14 PM PDT 24
Peak memory 247428 kb
Host smart-8e95bd97-9b3e-4611-a202-cd424d8686ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744409654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1744409654
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2331071216
Short name T710
Test name
Test status
Simulation time 199085354 ps
CPU time 6.78 seconds
Started Jul 16 06:29:49 PM PDT 24
Finished Jul 16 06:29:56 PM PDT 24
Peak memory 250368 kb
Host smart-966f5b2e-ec2e-4be3-b7bd-50fe64a69401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331071216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2331071216
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3639949735
Short name T854
Test name
Test status
Simulation time 27016329460 ps
CPU time 239.28 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:33:56 PM PDT 24
Peak memory 283736 kb
Host smart-6f8329a6-b454-40c1-8d10-50dbe0f488aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639949735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3639949735
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.4098669614
Short name T649
Test name
Test status
Simulation time 6302701932 ps
CPU time 85.9 seconds
Started Jul 16 06:29:57 PM PDT 24
Finished Jul 16 06:31:23 PM PDT 24
Peak memory 226180 kb
Host smart-fd813c62-4a6f-41d9-a056-c75dec8b6551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4098669614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.4098669614
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1758140159
Short name T154
Test name
Test status
Simulation time 16194352 ps
CPU time 0.9 seconds
Started Jul 16 06:29:49 PM PDT 24
Finished Jul 16 06:29:51 PM PDT 24
Peak memory 211544 kb
Host smart-51fcc579-840b-430c-aad3-5547caf0e75d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758140159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1758140159
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.643036840
Short name T817
Test name
Test status
Simulation time 20463979 ps
CPU time 0.82 seconds
Started Jul 16 06:30:08 PM PDT 24
Finished Jul 16 06:30:09 PM PDT 24
Peak memory 208604 kb
Host smart-6a975327-065c-423e-8138-368d12a58bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643036840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.643036840
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.137803116
Short name T762
Test name
Test status
Simulation time 576810621 ps
CPU time 9.93 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:17 PM PDT 24
Peak memory 225568 kb
Host smart-ed27c4d0-688b-40d0-a881-99102bbc4e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137803116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.137803116
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.64389004
Short name T677
Test name
Test status
Simulation time 1013140864 ps
CPU time 11.91 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:30:09 PM PDT 24
Peak memory 217356 kb
Host smart-7a6391f6-c59c-48fd-83f3-0e9b074c1463
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64389004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.64389004
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1294376845
Short name T42
Test name
Test status
Simulation time 2148198672 ps
CPU time 62.72 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:59 PM PDT 24
Peak memory 226028 kb
Host smart-da2bebc5-5504-41af-8dda-7a16c17b3165
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294376845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1294376845
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3290071317
Short name T554
Test name
Test status
Simulation time 404976396 ps
CPU time 7.64 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:30:05 PM PDT 24
Peak memory 223152 kb
Host smart-3c6fbfc2-e961-412a-841d-7bd083bd6cf5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290071317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3290071317
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1010584579
Short name T76
Test name
Test status
Simulation time 1724705049 ps
CPU time 5.15 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:13 PM PDT 24
Peak memory 217504 kb
Host smart-17013aa2-e4a7-4a0e-b04f-4a1e94a31426
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010584579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1010584579
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1763421542
Short name T531
Test name
Test status
Simulation time 1769965539 ps
CPU time 36.41 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:32 PM PDT 24
Peak memory 251088 kb
Host smart-51715f49-e54a-4458-b997-8eaf45110ef9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763421542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1763421542
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3381580233
Short name T845
Test name
Test status
Simulation time 3094109698 ps
CPU time 19.95 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:30:17 PM PDT 24
Peak memory 247640 kb
Host smart-c4dee63a-fdea-4266-8a83-7133c89657ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381580233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3381580233
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1609806128
Short name T665
Test name
Test status
Simulation time 66655751 ps
CPU time 1.8 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:09 PM PDT 24
Peak memory 222036 kb
Host smart-c7397513-e706-4465-ab61-33707782c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609806128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1609806128
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.922429307
Short name T379
Test name
Test status
Simulation time 517756995 ps
CPU time 10.99 seconds
Started Jul 16 06:30:07 PM PDT 24
Finished Jul 16 06:30:19 PM PDT 24
Peak memory 218848 kb
Host smart-7e70d139-18f1-45dc-8560-fb788f5297a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922429307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.922429307
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3246380335
Short name T681
Test name
Test status
Simulation time 2138947356 ps
CPU time 11.73 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:18 PM PDT 24
Peak memory 225924 kb
Host smart-7704bd67-96a5-4981-9258-47b1d00e7b22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246380335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3246380335
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2764398166
Short name T305
Test name
Test status
Simulation time 322138037 ps
CPU time 12.49 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:19 PM PDT 24
Peak memory 225972 kb
Host smart-ccba8ceb-e040-45f3-aa39-4f89a8549426
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764398166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2764398166
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1217875268
Short name T708
Test name
Test status
Simulation time 29365571 ps
CPU time 1.19 seconds
Started Jul 16 06:29:56 PM PDT 24
Finished Jul 16 06:29:58 PM PDT 24
Peak memory 213588 kb
Host smart-588aa198-f1a5-4bd1-b0b6-1710214fe690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217875268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1217875268
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2010586234
Short name T380
Test name
Test status
Simulation time 447153306 ps
CPU time 23.63 seconds
Started Jul 16 06:29:55 PM PDT 24
Finished Jul 16 06:30:19 PM PDT 24
Peak memory 250972 kb
Host smart-b16e4037-7e1b-44df-85a5-2212f7be3528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010586234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2010586234
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2487245256
Short name T725
Test name
Test status
Simulation time 223384086 ps
CPU time 2.54 seconds
Started Jul 16 06:29:54 PM PDT 24
Finished Jul 16 06:29:57 PM PDT 24
Peak memory 226512 kb
Host smart-d129d863-1c55-41fa-8ee1-d141f95d3b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487245256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2487245256
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2786930829
Short name T185
Test name
Test status
Simulation time 8567880209 ps
CPU time 166.91 seconds
Started Jul 16 06:30:08 PM PDT 24
Finished Jul 16 06:32:56 PM PDT 24
Peak memory 251024 kb
Host smart-908809ec-47b8-4f34-9afb-7769509a623e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786930829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2786930829
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.876058102
Short name T148
Test name
Test status
Simulation time 156219045906 ps
CPU time 789.78 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:43:17 PM PDT 24
Peak memory 333060 kb
Host smart-39a7c2e2-1e5f-4719-8c71-4fe6d73090a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=876058102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.876058102
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2198589204
Short name T690
Test name
Test status
Simulation time 17961395 ps
CPU time 0.73 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:08 PM PDT 24
Peak memory 206868 kb
Host smart-bcedec17-eae8-4a28-b5af-cd0ce44b9177
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198589204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2198589204
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.511485547
Short name T458
Test name
Test status
Simulation time 34526912 ps
CPU time 0.96 seconds
Started Jul 16 06:30:18 PM PDT 24
Finished Jul 16 06:30:20 PM PDT 24
Peak memory 208852 kb
Host smart-117232ad-8910-4bf4-81a6-51350405c13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511485547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.511485547
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3934226464
Short name T240
Test name
Test status
Simulation time 1796057283 ps
CPU time 17.75 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:25 PM PDT 24
Peak memory 218124 kb
Host smart-c396b3f4-03f9-4614-9adb-cf4288827496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934226464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3934226464
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.4239903603
Short name T567
Test name
Test status
Simulation time 710994612 ps
CPU time 7.97 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:16 PM PDT 24
Peak memory 217380 kb
Host smart-1ce852d9-f850-4f87-8ee1-22c120aa508a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239903603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.4239903603
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1468528141
Short name T258
Test name
Test status
Simulation time 6223907925 ps
CPU time 29.4 seconds
Started Jul 16 06:30:07 PM PDT 24
Finished Jul 16 06:30:37 PM PDT 24
Peak memory 219000 kb
Host smart-9505e32b-3178-4aa0-8bab-a3a75e385589
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468528141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1468528141
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2345402450
Short name T564
Test name
Test status
Simulation time 1286111093 ps
CPU time 10.07 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:16 PM PDT 24
Peak memory 222980 kb
Host smart-81009738-8744-457f-ba41-acf8c7eef9c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345402450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2345402450
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1689525779
Short name T768
Test name
Test status
Simulation time 255798125 ps
CPU time 8.21 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:16 PM PDT 24
Peak memory 217448 kb
Host smart-2119f702-81e4-4a47-8443-f71b0384d9ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689525779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1689525779
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3253554966
Short name T495
Test name
Test status
Simulation time 1119125755 ps
CPU time 27.3 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:35 PM PDT 24
Peak memory 250908 kb
Host smart-da7feed5-b47a-498e-8cdd-205f57cb9c67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253554966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3253554966
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1000507333
Short name T411
Test name
Test status
Simulation time 1782910825 ps
CPU time 12.97 seconds
Started Jul 16 06:30:08 PM PDT 24
Finished Jul 16 06:30:22 PM PDT 24
Peak memory 250808 kb
Host smart-51dd40c8-f24a-4d72-aab8-a752450795d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000507333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1000507333
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3825057906
Short name T508
Test name
Test status
Simulation time 85703150 ps
CPU time 3.12 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:11 PM PDT 24
Peak memory 218304 kb
Host smart-f44d7ff6-0b68-4f1b-8241-22da19889098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825057906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3825057906
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.848465623
Short name T360
Test name
Test status
Simulation time 532779668 ps
CPU time 13.64 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:20 PM PDT 24
Peak memory 225932 kb
Host smart-e841cdfd-c713-4b30-ac9c-490ab7d7f7f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848465623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.848465623
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.4152302980
Short name T400
Test name
Test status
Simulation time 264150103 ps
CPU time 10.69 seconds
Started Jul 16 06:30:11 PM PDT 24
Finished Jul 16 06:30:22 PM PDT 24
Peak memory 225896 kb
Host smart-8dcbc713-8019-45e1-856a-9488e1a0c0fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152302980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.4152302980
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1443623143
Short name T669
Test name
Test status
Simulation time 541634884 ps
CPU time 13.17 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:20 PM PDT 24
Peak memory 218124 kb
Host smart-e2400166-27b0-403d-9155-9f0c92c39562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443623143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1443623143
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.284186226
Short name T50
Test name
Test status
Simulation time 229487942 ps
CPU time 6.93 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:13 PM PDT 24
Peak memory 226020 kb
Host smart-a6e42f1c-6b0f-49a1-b14b-c2e31aec5eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284186226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.284186226
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.162197505
Short name T69
Test name
Test status
Simulation time 18894884 ps
CPU time 1.49 seconds
Started Jul 16 06:30:05 PM PDT 24
Finished Jul 16 06:30:08 PM PDT 24
Peak memory 213644 kb
Host smart-e5334312-349a-45cc-97a8-b9a2c75cbb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162197505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.162197505
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2909809156
Short name T37
Test name
Test status
Simulation time 804817763 ps
CPU time 16.69 seconds
Started Jul 16 06:30:08 PM PDT 24
Finished Jul 16 06:30:25 PM PDT 24
Peak memory 250964 kb
Host smart-b829d66a-e13a-45db-b4c8-80918628df46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909809156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2909809156
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.932775900
Short name T389
Test name
Test status
Simulation time 222476711 ps
CPU time 6.85 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:30:14 PM PDT 24
Peak memory 250276 kb
Host smart-d4f4d525-c9ef-404d-b4cd-e3e59e2810cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932775900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.932775900
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.42331716
Short name T253
Test name
Test status
Simulation time 42194053268 ps
CPU time 311.48 seconds
Started Jul 16 06:30:06 PM PDT 24
Finished Jul 16 06:35:19 PM PDT 24
Peak memory 267260 kb
Host smart-c6c181cc-b189-4a34-adfc-badb7eb1d422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42331716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.lc_ctrl_stress_all.42331716
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3125093761
Short name T702
Test name
Test status
Simulation time 40735415 ps
CPU time 0.95 seconds
Started Jul 16 06:30:07 PM PDT 24
Finished Jul 16 06:30:09 PM PDT 24
Peak memory 211828 kb
Host smart-933a1331-dabc-49ac-a6ef-5cab588c1877
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125093761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3125093761
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.620096900
Short name T71
Test name
Test status
Simulation time 187377533 ps
CPU time 1.02 seconds
Started Jul 16 06:27:55 PM PDT 24
Finished Jul 16 06:27:57 PM PDT 24
Peak memory 208756 kb
Host smart-5ec41ab5-7f49-4575-8bbb-fd8fc2dbec07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620096900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.620096900
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3767422269
Short name T804
Test name
Test status
Simulation time 72418759 ps
CPU time 0.78 seconds
Started Jul 16 06:27:42 PM PDT 24
Finished Jul 16 06:27:43 PM PDT 24
Peak memory 208908 kb
Host smart-2d2d4837-bca2-4f34-b3bf-01f13bdeae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767422269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3767422269
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1361728283
Short name T397
Test name
Test status
Simulation time 364498533 ps
CPU time 10.89 seconds
Started Jul 16 06:27:34 PM PDT 24
Finished Jul 16 06:27:46 PM PDT 24
Peak memory 218200 kb
Host smart-80f22d46-9282-4bbd-b372-1eecaa7fb966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361728283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1361728283
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.4003931127
Short name T28
Test name
Test status
Simulation time 303146537 ps
CPU time 4.52 seconds
Started Jul 16 06:27:48 PM PDT 24
Finished Jul 16 06:27:54 PM PDT 24
Peak memory 216904 kb
Host smart-8be0297f-956c-427c-ad04-c28475d93fc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003931127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.4003931127
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.428646767
Short name T18
Test name
Test status
Simulation time 18795170557 ps
CPU time 33.15 seconds
Started Jul 16 06:27:48 PM PDT 24
Finished Jul 16 06:28:22 PM PDT 24
Peak memory 225916 kb
Host smart-1f26629b-ce6f-4f46-8bb7-717ac9f9cad9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428646767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.428646767
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3314193259
Short name T773
Test name
Test status
Simulation time 1943465594 ps
CPU time 6.17 seconds
Started Jul 16 06:27:50 PM PDT 24
Finished Jul 16 06:27:57 PM PDT 24
Peak memory 217232 kb
Host smart-6fb97686-2650-44f1-80b1-24a1927e7dc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314193259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
314193259
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2179380912
Short name T544
Test name
Test status
Simulation time 284859542 ps
CPU time 9.61 seconds
Started Jul 16 06:27:48 PM PDT 24
Finished Jul 16 06:27:59 PM PDT 24
Peak memory 218128 kb
Host smart-5834f2b7-40e0-483f-ad00-299945d64bf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179380912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2179380912
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.872133735
Short name T260
Test name
Test status
Simulation time 3570833725 ps
CPU time 26.37 seconds
Started Jul 16 06:27:46 PM PDT 24
Finished Jul 16 06:28:13 PM PDT 24
Peak memory 217640 kb
Host smart-eea71f87-6b3d-4470-89da-4ed7d5a2adca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872133735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.872133735
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2569450960
Short name T833
Test name
Test status
Simulation time 736013853 ps
CPU time 3 seconds
Started Jul 16 06:27:48 PM PDT 24
Finished Jul 16 06:27:52 PM PDT 24
Peak memory 217544 kb
Host smart-b65bcdd1-a75e-494f-be72-8590b546d450
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569450960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2569450960
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.728000951
Short name T377
Test name
Test status
Simulation time 2383152794 ps
CPU time 66.75 seconds
Started Jul 16 06:27:47 PM PDT 24
Finished Jul 16 06:28:55 PM PDT 24
Peak memory 267396 kb
Host smart-63e4d460-fa70-48c4-bff4-b711563ae10f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728000951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.728000951
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.266903343
Short name T299
Test name
Test status
Simulation time 2024659322 ps
CPU time 12.91 seconds
Started Jul 16 06:27:48 PM PDT 24
Finished Jul 16 06:28:02 PM PDT 24
Peak memory 250572 kb
Host smart-e3c3848b-1ba7-4def-9334-980b45b2649e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266903343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.266903343
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.4269165751
Short name T678
Test name
Test status
Simulation time 863779376 ps
CPU time 3.24 seconds
Started Jul 16 06:27:36 PM PDT 24
Finished Jul 16 06:27:40 PM PDT 24
Peak memory 222272 kb
Host smart-cd0a4045-3137-479f-85a5-d51e179828ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269165751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.4269165751
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1714597859
Short name T323
Test name
Test status
Simulation time 4703125712 ps
CPU time 7.49 seconds
Started Jul 16 06:27:34 PM PDT 24
Finished Jul 16 06:27:42 PM PDT 24
Peak memory 217600 kb
Host smart-dbe5d471-4de9-4e6e-a2fb-977d36d385a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714597859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1714597859
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2403974568
Short name T92
Test name
Test status
Simulation time 114558926 ps
CPU time 22.62 seconds
Started Jul 16 06:27:55 PM PDT 24
Finished Jul 16 06:28:19 PM PDT 24
Peak memory 268828 kb
Host smart-05d3a826-4089-4159-ac88-d426fa65ce9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403974568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2403974568
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.976865528
Short name T355
Test name
Test status
Simulation time 1879374220 ps
CPU time 14.79 seconds
Started Jul 16 06:27:49 PM PDT 24
Finished Jul 16 06:28:05 PM PDT 24
Peak memory 225936 kb
Host smart-2c01bc82-e214-4274-a9e7-dcd19866c78e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976865528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.976865528
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.834814802
Short name T19
Test name
Test status
Simulation time 276803632 ps
CPU time 12.12 seconds
Started Jul 16 06:27:47 PM PDT 24
Finished Jul 16 06:28:00 PM PDT 24
Peak memory 218132 kb
Host smart-72856714-76f1-4db3-a5f4-670ba9452cee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834814802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.834814802
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3936532942
Short name T661
Test name
Test status
Simulation time 275547997 ps
CPU time 7.3 seconds
Started Jul 16 06:27:35 PM PDT 24
Finished Jul 16 06:27:43 PM PDT 24
Peak memory 226036 kb
Host smart-4192fed0-8aae-47f6-8853-32bda831a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936532942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3936532942
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.824907070
Short name T65
Test name
Test status
Simulation time 229054650 ps
CPU time 2.15 seconds
Started Jul 16 06:27:36 PM PDT 24
Finished Jul 16 06:27:39 PM PDT 24
Peak memory 214348 kb
Host smart-deabdbe4-9af2-432a-b62a-55acd4d616d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824907070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.824907070
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.4190587198
Short name T617
Test name
Test status
Simulation time 373165500 ps
CPU time 32.8 seconds
Started Jul 16 06:27:37 PM PDT 24
Finished Jul 16 06:28:10 PM PDT 24
Peak memory 250968 kb
Host smart-8b3e7894-56ad-4e93-b84a-78f96cabf973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190587198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4190587198
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1018749938
Short name T421
Test name
Test status
Simulation time 421288510 ps
CPU time 8.19 seconds
Started Jul 16 06:27:36 PM PDT 24
Finished Jul 16 06:27:45 PM PDT 24
Peak memory 247012 kb
Host smart-1a9a3c75-6eff-4ba6-93ba-95a4b76f0260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018749938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1018749938
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.191287399
Short name T79
Test name
Test status
Simulation time 8159252342 ps
CPU time 189.73 seconds
Started Jul 16 06:27:48 PM PDT 24
Finished Jul 16 06:30:58 PM PDT 24
Peak memory 278928 kb
Host smart-1759b269-429e-4c12-a1de-beec5caac8e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191287399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.191287399
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2454723101
Short name T688
Test name
Test status
Simulation time 39561216 ps
CPU time 0.94 seconds
Started Jul 16 06:27:42 PM PDT 24
Finished Jul 16 06:27:43 PM PDT 24
Peak memory 211784 kb
Host smart-10f24b7f-e637-43f7-8b80-b0fe8d596ec5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454723101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2454723101
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2286135416
Short name T830
Test name
Test status
Simulation time 13515869 ps
CPU time 0.81 seconds
Started Jul 16 06:30:19 PM PDT 24
Finished Jul 16 06:30:21 PM PDT 24
Peak memory 208584 kb
Host smart-7bc493e4-89c7-48df-afcf-3bb6514002b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286135416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2286135416
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2365606269
Short name T48
Test name
Test status
Simulation time 1000771418 ps
CPU time 12.5 seconds
Started Jul 16 06:30:19 PM PDT 24
Finished Jul 16 06:30:33 PM PDT 24
Peak memory 226000 kb
Host smart-1553cf1c-e326-4e26-83a6-84a0b226d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365606269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2365606269
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2132542489
Short name T579
Test name
Test status
Simulation time 275369606 ps
CPU time 7.61 seconds
Started Jul 16 06:30:17 PM PDT 24
Finished Jul 16 06:30:26 PM PDT 24
Peak memory 217184 kb
Host smart-d992b28e-e433-4e46-9910-fad16ed84559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132542489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2132542489
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.513860344
Short name T312
Test name
Test status
Simulation time 197174736 ps
CPU time 2.84 seconds
Started Jul 16 06:30:16 PM PDT 24
Finished Jul 16 06:30:20 PM PDT 24
Peak memory 218164 kb
Host smart-ac850bb9-4d37-4df4-8d2b-4b19cd132dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513860344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.513860344
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.190650252
Short name T246
Test name
Test status
Simulation time 363285464 ps
CPU time 10.79 seconds
Started Jul 16 06:30:17 PM PDT 24
Finished Jul 16 06:30:29 PM PDT 24
Peak memory 226016 kb
Host smart-cda8034f-ced7-49d8-a13c-f6ceb15a08ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190650252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.190650252
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3501190315
Short name T364
Test name
Test status
Simulation time 1074363060 ps
CPU time 7.45 seconds
Started Jul 16 06:30:17 PM PDT 24
Finished Jul 16 06:30:25 PM PDT 24
Peak memory 218072 kb
Host smart-32b03362-d431-420d-95db-1e909ca4ac8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501190315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3501190315
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2183670536
Short name T519
Test name
Test status
Simulation time 3453783263 ps
CPU time 7.5 seconds
Started Jul 16 06:30:21 PM PDT 24
Finished Jul 16 06:30:29 PM PDT 24
Peak memory 225060 kb
Host smart-24dd4f8b-598a-4517-a90e-fe91e9b24436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183670536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2183670536
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.607146130
Short name T72
Test name
Test status
Simulation time 163594306 ps
CPU time 2.77 seconds
Started Jul 16 06:30:19 PM PDT 24
Finished Jul 16 06:30:23 PM PDT 24
Peak memory 223692 kb
Host smart-13ac2242-afdb-4cab-a0c6-43352252c437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607146130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.607146130
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.281113795
Short name T685
Test name
Test status
Simulation time 1456592419 ps
CPU time 26.76 seconds
Started Jul 16 06:30:18 PM PDT 24
Finished Jul 16 06:30:46 PM PDT 24
Peak memory 250908 kb
Host smart-5cd3c91b-3db5-480f-9813-8b0781ad67c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281113795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.281113795
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2457512402
Short name T88
Test name
Test status
Simulation time 72497077 ps
CPU time 7.54 seconds
Started Jul 16 06:30:17 PM PDT 24
Finished Jul 16 06:30:25 PM PDT 24
Peak memory 250952 kb
Host smart-8ae87c3c-5378-41d1-b565-2a28924adde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457512402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2457512402
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1065799105
Short name T523
Test name
Test status
Simulation time 6261118362 ps
CPU time 117.36 seconds
Started Jul 16 06:30:17 PM PDT 24
Finished Jul 16 06:32:15 PM PDT 24
Peak memory 283860 kb
Host smart-5de17a40-da81-4069-a19b-f2c652415d64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065799105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1065799105
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1027322523
Short name T285
Test name
Test status
Simulation time 15189444 ps
CPU time 0.94 seconds
Started Jul 16 06:30:19 PM PDT 24
Finished Jul 16 06:30:21 PM PDT 24
Peak memory 211844 kb
Host smart-0be0180c-15d8-4daa-9bef-d6fb78bd5aa3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027322523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1027322523
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2501269395
Short name T463
Test name
Test status
Simulation time 64724420 ps
CPU time 0.96 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:31 PM PDT 24
Peak memory 208784 kb
Host smart-4953522b-fead-4d03-93f1-c966970088d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501269395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2501269395
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.841042261
Short name T562
Test name
Test status
Simulation time 1354570844 ps
CPU time 9.78 seconds
Started Jul 16 06:30:17 PM PDT 24
Finished Jul 16 06:30:28 PM PDT 24
Peak memory 218192 kb
Host smart-953b9f61-4938-4e59-9342-aec017246aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841042261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.841042261
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.178382577
Short name T784
Test name
Test status
Simulation time 1139858358 ps
CPU time 4.12 seconds
Started Jul 16 06:30:20 PM PDT 24
Finished Jul 16 06:30:25 PM PDT 24
Peak memory 217272 kb
Host smart-911a8853-4354-4256-b7d9-85dff1aad747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178382577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.178382577
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1972461972
Short name T608
Test name
Test status
Simulation time 45348516 ps
CPU time 2.31 seconds
Started Jul 16 06:30:25 PM PDT 24
Finished Jul 16 06:30:28 PM PDT 24
Peak memory 218204 kb
Host smart-89a37e9a-9d7f-4fb3-a9c2-32463634e2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972461972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1972461972
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3684397498
Short name T606
Test name
Test status
Simulation time 1155353723 ps
CPU time 13.77 seconds
Started Jul 16 06:30:16 PM PDT 24
Finished Jul 16 06:30:31 PM PDT 24
Peak memory 225940 kb
Host smart-f62b5837-0605-4860-86b2-ac1171265d53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684397498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3684397498
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2929434554
Short name T648
Test name
Test status
Simulation time 2314037554 ps
CPU time 13.83 seconds
Started Jul 16 06:30:18 PM PDT 24
Finished Jul 16 06:30:32 PM PDT 24
Peak memory 218228 kb
Host smart-9ba9af2c-87d7-4c47-9887-1100c3ba466b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929434554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2929434554
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3750294189
Short name T368
Test name
Test status
Simulation time 509425894 ps
CPU time 7.15 seconds
Started Jul 16 06:30:17 PM PDT 24
Finished Jul 16 06:30:25 PM PDT 24
Peak memory 218028 kb
Host smart-8478fc64-3b95-4b04-9ee1-75f2bafc8912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750294189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3750294189
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1525786442
Short name T818
Test name
Test status
Simulation time 1382645216 ps
CPU time 7.65 seconds
Started Jul 16 06:30:20 PM PDT 24
Finished Jul 16 06:30:28 PM PDT 24
Peak memory 226024 kb
Host smart-43b9ebca-18dc-4ada-a981-46c52ada4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525786442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1525786442
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.39958751
Short name T358
Test name
Test status
Simulation time 513748408 ps
CPU time 2.17 seconds
Started Jul 16 06:30:19 PM PDT 24
Finished Jul 16 06:30:22 PM PDT 24
Peak memory 223356 kb
Host smart-2e8525e0-fe78-4211-8a9d-bf7c2ecc067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39958751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.39958751
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3430647933
Short name T717
Test name
Test status
Simulation time 1780893125 ps
CPU time 32.09 seconds
Started Jul 16 06:30:18 PM PDT 24
Finished Jul 16 06:30:51 PM PDT 24
Peak memory 246432 kb
Host smart-347d6b64-87e0-4607-b564-49a2c9176ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430647933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3430647933
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.801583822
Short name T716
Test name
Test status
Simulation time 244755326 ps
CPU time 6.13 seconds
Started Jul 16 06:30:20 PM PDT 24
Finished Jul 16 06:30:27 PM PDT 24
Peak memory 246664 kb
Host smart-c581bec8-ab45-4f7c-961d-eddb3408dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801583822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.801583822
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1033729818
Short name T839
Test name
Test status
Simulation time 2706282492 ps
CPU time 63.63 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:31:32 PM PDT 24
Peak memory 250980 kb
Host smart-7599886f-8c95-4559-8777-830f54e39830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033729818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1033729818
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4055977851
Short name T349
Test name
Test status
Simulation time 13786446 ps
CPU time 0.88 seconds
Started Jul 16 06:30:19 PM PDT 24
Finished Jul 16 06:30:21 PM PDT 24
Peak memory 211784 kb
Host smart-81241aed-dff5-4835-9462-9d6f9f6a20b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055977851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4055977851
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1939113720
Short name T306
Test name
Test status
Simulation time 32497414 ps
CPU time 0.83 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:31 PM PDT 24
Peak memory 208472 kb
Host smart-f58cf8e3-709a-4e5c-9719-2ecf1b96c064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939113720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1939113720
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1019310969
Short name T441
Test name
Test status
Simulation time 7267008208 ps
CPU time 14.18 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:44 PM PDT 24
Peak memory 218536 kb
Host smart-7d6b8572-33e9-4da6-8778-dcf6d384ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019310969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1019310969
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3622345023
Short name T385
Test name
Test status
Simulation time 60409911 ps
CPU time 2.25 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:30:30 PM PDT 24
Peak memory 216928 kb
Host smart-2d340891-cdb3-424e-9b01-ad986d4c48ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622345023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3622345023
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3645995469
Short name T227
Test name
Test status
Simulation time 193616117 ps
CPU time 3.21 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:33 PM PDT 24
Peak memory 222288 kb
Host smart-cbd8751e-44e9-4425-a78d-2ae21e7638bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645995469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3645995469
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1711730733
Short name T788
Test name
Test status
Simulation time 454891860 ps
CPU time 18.6 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:48 PM PDT 24
Peak memory 219948 kb
Host smart-1f8672e2-5681-45c3-aee3-14f374acf052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711730733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1711730733
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2440471700
Short name T448
Test name
Test status
Simulation time 565910278 ps
CPU time 11.88 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:30:41 PM PDT 24
Peak memory 225996 kb
Host smart-55a196b2-03fc-44b4-8563-c5f01f157325
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440471700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2440471700
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2563631273
Short name T744
Test name
Test status
Simulation time 282306893 ps
CPU time 10.04 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:40 PM PDT 24
Peak memory 218080 kb
Host smart-458111dd-21e6-45c9-a2f4-9480bf89d358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563631273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2563631273
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3843740554
Short name T470
Test name
Test status
Simulation time 333181320 ps
CPU time 11.3 seconds
Started Jul 16 06:30:33 PM PDT 24
Finished Jul 16 06:30:45 PM PDT 24
Peak memory 225920 kb
Host smart-dcce622b-da1f-4504-a3cc-3e7ce7b15c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843740554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3843740554
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.463681120
Short name T755
Test name
Test status
Simulation time 121986795 ps
CPU time 2.94 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:30:31 PM PDT 24
Peak memory 214376 kb
Host smart-296e2310-898b-44cd-9222-5102c2836da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463681120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.463681120
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2568958616
Short name T281
Test name
Test status
Simulation time 353786799 ps
CPU time 18.14 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:48 PM PDT 24
Peak memory 250844 kb
Host smart-33cabfb6-8d8f-451a-893a-53860299d34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568958616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2568958616
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2178801733
Short name T745
Test name
Test status
Simulation time 251931526 ps
CPU time 3.11 seconds
Started Jul 16 06:30:33 PM PDT 24
Finished Jul 16 06:30:36 PM PDT 24
Peak memory 222488 kb
Host smart-d83038bc-a3cd-4d08-84a3-2ad53dd00e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178801733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2178801733
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1202993085
Short name T480
Test name
Test status
Simulation time 30811615344 ps
CPU time 104.4 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:32:12 PM PDT 24
Peak memory 275576 kb
Host smart-bac83456-0b10-402d-9f2b-9a63973356af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202993085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1202993085
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2986981619
Short name T109
Test name
Test status
Simulation time 17213815099 ps
CPU time 406.03 seconds
Started Jul 16 06:30:31 PM PDT 24
Finished Jul 16 06:37:18 PM PDT 24
Peak memory 496808 kb
Host smart-5948a0af-749e-460b-85e0-737332c5c085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2986981619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2986981619
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3010568584
Short name T244
Test name
Test status
Simulation time 13909313 ps
CPU time 1.09 seconds
Started Jul 16 06:30:26 PM PDT 24
Finished Jul 16 06:30:28 PM PDT 24
Peak memory 211676 kb
Host smart-f3286d97-d806-4646-b519-0a881517dfe8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010568584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3010568584
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2371520215
Short name T481
Test name
Test status
Simulation time 27506510 ps
CPU time 0.89 seconds
Started Jul 16 06:30:32 PM PDT 24
Finished Jul 16 06:30:33 PM PDT 24
Peak memory 208656 kb
Host smart-239f61be-7730-49a1-a95c-6131cc8a164b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371520215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2371520215
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3671713757
Short name T826
Test name
Test status
Simulation time 439973647 ps
CPU time 19.66 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:49 PM PDT 24
Peak memory 218216 kb
Host smart-cd28d14e-3a93-495c-ba12-5fca0578cfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671713757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3671713757
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2003457470
Short name T7
Test name
Test status
Simulation time 599882083 ps
CPU time 6.18 seconds
Started Jul 16 06:30:29 PM PDT 24
Finished Jul 16 06:30:37 PM PDT 24
Peak memory 217140 kb
Host smart-0c9ef52e-93e6-442b-ba3b-393959e22454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003457470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2003457470
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1223937348
Short name T675
Test name
Test status
Simulation time 57224120 ps
CPU time 3.24 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:30:31 PM PDT 24
Peak memory 218160 kb
Host smart-b1cf4515-5ad8-4b0a-b093-77e7f434671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223937348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1223937348
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.910099491
Short name T58
Test name
Test status
Simulation time 299619033 ps
CPU time 13.22 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:43 PM PDT 24
Peak memory 225944 kb
Host smart-ef949e17-75c4-4a7e-a140-d8648e2d9a91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910099491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.910099491
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3060585398
Short name T393
Test name
Test status
Simulation time 1197074456 ps
CPU time 9.26 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:39 PM PDT 24
Peak memory 218112 kb
Host smart-dd136abc-2cd4-4285-bab6-e6724db79a6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060585398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3060585398
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1299846566
Short name T56
Test name
Test status
Simulation time 759833381 ps
CPU time 9.71 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:39 PM PDT 24
Peak memory 225976 kb
Host smart-dd25d29d-098b-4f3c-a78f-fb2f35fbe63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299846566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1299846566
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1428591958
Short name T516
Test name
Test status
Simulation time 224937119 ps
CPU time 3.05 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:33 PM PDT 24
Peak memory 217632 kb
Host smart-ad84aa99-9fc5-4dc8-aa1c-10256ace388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428591958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1428591958
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4283198913
Short name T284
Test name
Test status
Simulation time 527600961 ps
CPU time 23.25 seconds
Started Jul 16 06:30:26 PM PDT 24
Finished Jul 16 06:30:51 PM PDT 24
Peak memory 250968 kb
Host smart-2c1fc7ca-78c3-4923-9a4d-0d474154f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283198913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4283198913
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3979206557
Short name T336
Test name
Test status
Simulation time 162879444 ps
CPU time 3.58 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:34 PM PDT 24
Peak memory 222348 kb
Host smart-306f92c7-4648-48b4-a929-cd48b668cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979206557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3979206557
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3653182193
Short name T429
Test name
Test status
Simulation time 8066331017 ps
CPU time 107.02 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:32:16 PM PDT 24
Peak memory 273036 kb
Host smart-d1484259-7caa-4bbf-9e25-9ba44c3b64d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653182193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3653182193
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2837565774
Short name T163
Test name
Test status
Simulation time 417438317165 ps
CPU time 1523.79 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:55:53 PM PDT 24
Peak memory 529836 kb
Host smart-6a480940-c89a-42bc-960a-5819e29d4680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2837565774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2837565774
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1282076771
Short name T840
Test name
Test status
Simulation time 27520685 ps
CPU time 0.76 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:30:30 PM PDT 24
Peak memory 207284 kb
Host smart-94d78e22-a808-4c9c-9b76-1b8ec8ff2e76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282076771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1282076771
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1121541698
Short name T283
Test name
Test status
Simulation time 50235155 ps
CPU time 0.85 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:30:39 PM PDT 24
Peak memory 208576 kb
Host smart-7643975c-3d74-4aba-9d27-040d783493d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121541698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1121541698
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3480456026
Short name T278
Test name
Test status
Simulation time 890662105 ps
CPU time 9.33 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:40 PM PDT 24
Peak memory 226028 kb
Host smart-0099c069-2bcb-4f0b-9b2d-9b6d35806458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480456026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3480456026
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.824083944
Short name T714
Test name
Test status
Simulation time 1435447033 ps
CPU time 5.38 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:30:33 PM PDT 24
Peak memory 217484 kb
Host smart-15d4a520-da29-4042-8a0b-fc32707a6d3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824083944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.824083944
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3315066612
Short name T599
Test name
Test status
Simulation time 88494329 ps
CPU time 2.33 seconds
Started Jul 16 06:30:27 PM PDT 24
Finished Jul 16 06:30:31 PM PDT 24
Peak memory 218212 kb
Host smart-31581135-4c9e-4f79-bc7f-dbec6c08ff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315066612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3315066612
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2326092089
Short name T700
Test name
Test status
Simulation time 4622726961 ps
CPU time 12.58 seconds
Started Jul 16 06:30:26 PM PDT 24
Finished Jul 16 06:30:40 PM PDT 24
Peak memory 226020 kb
Host smart-33016c0f-29ad-4f7f-836d-8f10f5e7f3cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326092089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2326092089
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1497444543
Short name T404
Test name
Test status
Simulation time 1309083649 ps
CPU time 11.31 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:41 PM PDT 24
Peak memory 218172 kb
Host smart-639943ff-96fa-4580-bc57-8182788b4906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497444543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1497444543
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2079726904
Short name T602
Test name
Test status
Simulation time 1568905670 ps
CPU time 15.51 seconds
Started Jul 16 06:30:28 PM PDT 24
Finished Jul 16 06:30:45 PM PDT 24
Peak memory 226000 kb
Host smart-6784dda4-dec4-42d9-8fd0-e7820dbdf753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079726904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2079726904
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.581781386
Short name T792
Test name
Test status
Simulation time 142966766 ps
CPU time 2.46 seconds
Started Jul 16 06:30:31 PM PDT 24
Finished Jul 16 06:30:35 PM PDT 24
Peak memory 217536 kb
Host smart-7881da2f-2a1b-4315-8f6b-666b15994feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581781386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.581781386
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1497904854
Short name T701
Test name
Test status
Simulation time 1471478757 ps
CPU time 26.26 seconds
Started Jul 16 06:30:26 PM PDT 24
Finished Jul 16 06:30:54 PM PDT 24
Peak memory 250932 kb
Host smart-a5df6d0d-10f7-4a83-87c5-4959e7f62b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497904854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1497904854
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2838862030
Short name T478
Test name
Test status
Simulation time 102665265 ps
CPU time 9.1 seconds
Started Jul 16 06:30:30 PM PDT 24
Finished Jul 16 06:30:40 PM PDT 24
Peak memory 250968 kb
Host smart-74f3b236-bd4e-44ed-8af6-e3f1fc0460c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838862030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2838862030
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1686808389
Short name T583
Test name
Test status
Simulation time 44755111 ps
CPU time 0.85 seconds
Started Jul 16 06:30:29 PM PDT 24
Finished Jul 16 06:30:31 PM PDT 24
Peak memory 211840 kb
Host smart-e919fd28-aa17-4d9c-9da6-2b03adb4f026
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686808389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1686808389
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2697531234
Short name T556
Test name
Test status
Simulation time 20545819 ps
CPU time 1.22 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:30:39 PM PDT 24
Peak memory 208904 kb
Host smart-1807aa4f-9b9b-42d3-8211-ec2613214f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697531234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2697531234
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.956852855
Short name T667
Test name
Test status
Simulation time 473047552 ps
CPU time 14.07 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:30:51 PM PDT 24
Peak memory 218140 kb
Host smart-5bb3d6bf-b709-4fd3-9252-ed8977aac301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956852855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.956852855
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3072082746
Short name T591
Test name
Test status
Simulation time 979109177 ps
CPU time 3.76 seconds
Started Jul 16 06:30:40 PM PDT 24
Finished Jul 16 06:30:45 PM PDT 24
Peak memory 217556 kb
Host smart-68e62c83-d00d-4ec9-91cc-7976f8cc8c57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072082746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3072082746
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1082427016
Short name T736
Test name
Test status
Simulation time 155710967 ps
CPU time 2.3 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:30:42 PM PDT 24
Peak memory 222100 kb
Host smart-e394c200-1185-4ac5-a8ef-97444c7a78c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082427016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1082427016
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.151888771
Short name T643
Test name
Test status
Simulation time 332877211 ps
CPU time 16.65 seconds
Started Jul 16 06:30:39 PM PDT 24
Finished Jul 16 06:30:57 PM PDT 24
Peak memory 226016 kb
Host smart-6470c1ee-815a-4d86-a500-e55a51da62e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151888771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.151888771
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1205493286
Short name T673
Test name
Test status
Simulation time 1337763338 ps
CPU time 16.8 seconds
Started Jul 16 06:30:39 PM PDT 24
Finished Jul 16 06:30:57 PM PDT 24
Peak memory 225908 kb
Host smart-db38e8af-3e14-43df-b33d-0ff19d6b00bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205493286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1205493286
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.969358503
Short name T619
Test name
Test status
Simulation time 316680260 ps
CPU time 9.55 seconds
Started Jul 16 06:30:39 PM PDT 24
Finished Jul 16 06:30:50 PM PDT 24
Peak memory 218040 kb
Host smart-69f39072-2728-4b81-a897-793e394fa93b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969358503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.969358503
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1580239889
Short name T738
Test name
Test status
Simulation time 244369024 ps
CPU time 9.04 seconds
Started Jul 16 06:30:45 PM PDT 24
Finished Jul 16 06:30:54 PM PDT 24
Peak memory 218452 kb
Host smart-566501a6-615b-48a6-bbf9-3a6181ec16f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580239889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1580239889
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.563408683
Short name T630
Test name
Test status
Simulation time 87735402 ps
CPU time 2.49 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:30:41 PM PDT 24
Peak memory 217480 kb
Host smart-851a6c2c-82bb-4c44-9485-975595d4ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563408683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.563408683
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.399716015
Short name T793
Test name
Test status
Simulation time 667827179 ps
CPU time 22.87 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:31:02 PM PDT 24
Peak memory 250900 kb
Host smart-085a089e-04e3-499d-85c2-e948585bcec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399716015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.399716015
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1867245292
Short name T771
Test name
Test status
Simulation time 291858160 ps
CPU time 8.34 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:30:47 PM PDT 24
Peak memory 242732 kb
Host smart-2a38e9bf-522c-45ee-bc52-706643c489dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867245292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1867245292
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1602477313
Short name T499
Test name
Test status
Simulation time 87487203934 ps
CPU time 289.64 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:35:28 PM PDT 24
Peak memory 276540 kb
Host smart-de5946c3-4165-4674-a30a-81794c57c92b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602477313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1602477313
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2128377136
Short name T150
Test name
Test status
Simulation time 109235856890 ps
CPU time 426.32 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:37:45 PM PDT 24
Peak memory 422140 kb
Host smart-515a4901-ff29-4e0e-9e4b-63740d09a84a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2128377136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2128377136
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.4285235141
Short name T642
Test name
Test status
Simulation time 68689281 ps
CPU time 1.18 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:30:39 PM PDT 24
Peak memory 212960 kb
Host smart-0e086671-8158-41a2-9dbe-9b720e811807
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285235141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.4285235141
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1675113319
Short name T107
Test name
Test status
Simulation time 167078006 ps
CPU time 0.95 seconds
Started Jul 16 06:30:41 PM PDT 24
Finished Jul 16 06:30:42 PM PDT 24
Peak memory 208812 kb
Host smart-023cd8b4-1749-4e8c-8cbd-a5ce4f003322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675113319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1675113319
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3758999703
Short name T538
Test name
Test status
Simulation time 423129737 ps
CPU time 12.49 seconds
Started Jul 16 06:30:41 PM PDT 24
Finished Jul 16 06:30:54 PM PDT 24
Peak memory 225916 kb
Host smart-effde58b-c27d-4c11-8b5f-e186fc6a958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758999703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3758999703
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3801705435
Short name T822
Test name
Test status
Simulation time 838883135 ps
CPU time 6.23 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:30:45 PM PDT 24
Peak memory 216952 kb
Host smart-2c979ab1-322d-4b5d-97db-6e82f26d6420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801705435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3801705435
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1511620980
Short name T447
Test name
Test status
Simulation time 28797336 ps
CPU time 2.08 seconds
Started Jul 16 06:30:40 PM PDT 24
Finished Jul 16 06:30:43 PM PDT 24
Peak memory 218096 kb
Host smart-a5fca030-20bd-49ff-843d-4c4dc06c341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511620980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1511620980
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3766832569
Short name T10
Test name
Test status
Simulation time 475859659 ps
CPU time 12.84 seconds
Started Jul 16 06:30:41 PM PDT 24
Finished Jul 16 06:30:54 PM PDT 24
Peak memory 225968 kb
Host smart-b708619c-77dc-4d95-a11c-b859c5834a91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766832569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3766832569
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.208448535
Short name T707
Test name
Test status
Simulation time 836612257 ps
CPU time 8.33 seconds
Started Jul 16 06:30:39 PM PDT 24
Finished Jul 16 06:30:49 PM PDT 24
Peak memory 218068 kb
Host smart-3d8a106f-1cff-41fe-9acb-b978339cd1e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208448535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.208448535
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3080609732
Short name T54
Test name
Test status
Simulation time 555110352 ps
CPU time 10.73 seconds
Started Jul 16 06:30:41 PM PDT 24
Finished Jul 16 06:30:53 PM PDT 24
Peak memory 226016 kb
Host smart-829f9c27-980c-47a5-ad08-cf46cf168d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080609732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3080609732
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2101940713
Short name T272
Test name
Test status
Simulation time 599572513 ps
CPU time 10.88 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:30:51 PM PDT 24
Peak memory 217628 kb
Host smart-be370819-dacd-4eca-94bf-8f5b97405288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101940713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2101940713
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2315157622
Short name T302
Test name
Test status
Simulation time 1099135110 ps
CPU time 32.99 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:31:11 PM PDT 24
Peak memory 250928 kb
Host smart-27f981b7-9f69-4a97-99b8-0a5b62bc4cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315157622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2315157622
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1066989685
Short name T842
Test name
Test status
Simulation time 213095901 ps
CPU time 7.42 seconds
Started Jul 16 06:30:44 PM PDT 24
Finished Jul 16 06:30:52 PM PDT 24
Peak memory 243264 kb
Host smart-150bbaaf-5439-4b9c-8596-051904e9eca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066989685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1066989685
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2700132303
Short name T46
Test name
Test status
Simulation time 12618093667 ps
CPU time 170.14 seconds
Started Jul 16 06:30:41 PM PDT 24
Finished Jul 16 06:33:32 PM PDT 24
Peak memory 283720 kb
Host smart-a86eaf20-08e5-4654-9181-b975e0bb768c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700132303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2700132303
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1637642593
Short name T687
Test name
Test status
Simulation time 30883045546 ps
CPU time 316.98 seconds
Started Jul 16 06:30:52 PM PDT 24
Finished Jul 16 06:36:10 PM PDT 24
Peak memory 422244 kb
Host smart-d33b74ce-e398-48fe-b643-ad32daec05d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1637642593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1637642593
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.375433450
Short name T626
Test name
Test status
Simulation time 25765066 ps
CPU time 0.94 seconds
Started Jul 16 06:30:37 PM PDT 24
Finished Jul 16 06:30:39 PM PDT 24
Peak memory 217664 kb
Host smart-b8051448-5143-4483-8d08-f2a768bdcaf6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375433450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.375433450
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.92833813
Short name T455
Test name
Test status
Simulation time 25374909 ps
CPU time 0.88 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:30:54 PM PDT 24
Peak memory 208496 kb
Host smart-d9d7294a-5180-4c04-b73f-c34ee9aad5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92833813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.92833813
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1490961498
Short name T59
Test name
Test status
Simulation time 288122236 ps
CPU time 10.04 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:03 PM PDT 24
Peak memory 218156 kb
Host smart-9b31cf2f-053d-48bc-9b21-3c3c8db9f2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490961498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1490961498
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.4127581151
Short name T806
Test name
Test status
Simulation time 44072534 ps
CPU time 1.85 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:30:54 PM PDT 24
Peak memory 217076 kb
Host smart-6221acd0-d7db-4063-9e18-c802c9e9d8f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127581151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.4127581151
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.874731980
Short name T534
Test name
Test status
Simulation time 102209192 ps
CPU time 4.56 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:30:57 PM PDT 24
Peak memory 218248 kb
Host smart-dcc84157-44c9-41a5-b2fa-da1105297773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874731980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.874731980
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1744509710
Short name T855
Test name
Test status
Simulation time 540390348 ps
CPU time 20.91 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:14 PM PDT 24
Peak memory 219988 kb
Host smart-5546bd56-4c4b-489f-8ca4-361b96625c67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744509710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1744509710
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2845249675
Short name T16
Test name
Test status
Simulation time 5252013263 ps
CPU time 11.99 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:04 PM PDT 24
Peak memory 226012 kb
Host smart-07248bc9-fcc5-426a-bc3c-c46649113a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845249675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2845249675
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2397551100
Short name T662
Test name
Test status
Simulation time 374295489 ps
CPU time 10.4 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:02 PM PDT 24
Peak memory 218172 kb
Host smart-d4000e8e-ce2f-46b3-9e8e-dd4a1f9cad49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397551100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2397551100
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2291451525
Short name T653
Test name
Test status
Simulation time 2244020548 ps
CPU time 17.8 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:10 PM PDT 24
Peak memory 218304 kb
Host smart-b1895722-48b9-41b9-9308-ee7a6d90f490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291451525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2291451525
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1217850992
Short name T819
Test name
Test status
Simulation time 350258114 ps
CPU time 1.52 seconds
Started Jul 16 06:30:38 PM PDT 24
Finished Jul 16 06:30:41 PM PDT 24
Peak memory 222376 kb
Host smart-8244c007-399b-4611-be4f-b82bfcb9cb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217850992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1217850992
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3369778078
Short name T674
Test name
Test status
Simulation time 662158180 ps
CPU time 27.86 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:21 PM PDT 24
Peak memory 250896 kb
Host smart-56ac14b1-0baa-4d46-85e6-027930be1aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369778078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3369778078
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3774385654
Short name T810
Test name
Test status
Simulation time 288684801 ps
CPU time 7.47 seconds
Started Jul 16 06:30:52 PM PDT 24
Finished Jul 16 06:31:01 PM PDT 24
Peak memory 250812 kb
Host smart-83c0b25e-d4f7-4aa6-a1bf-bb1ffbba89eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774385654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3774385654
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2249558052
Short name T410
Test name
Test status
Simulation time 3695374932 ps
CPU time 82.09 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:32:15 PM PDT 24
Peak memory 275600 kb
Host smart-845f606c-6e58-4b80-be4f-cd4ff93aa9e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249558052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2249558052
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2409960489
Short name T82
Test name
Test status
Simulation time 28183418025 ps
CPU time 461.07 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:38:34 PM PDT 24
Peak memory 278628 kb
Host smart-86f4736e-2152-4fcb-bffb-ece6844f5818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2409960489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2409960489
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3857525640
Short name T328
Test name
Test status
Simulation time 24014422 ps
CPU time 0.94 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:30:52 PM PDT 24
Peak memory 217660 kb
Host smart-e8ce55f9-9687-444f-a028-f0b2d100ee08
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857525640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3857525640
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1936211908
Short name T341
Test name
Test status
Simulation time 59737888 ps
CPU time 0.93 seconds
Started Jul 16 06:31:05 PM PDT 24
Finished Jul 16 06:31:07 PM PDT 24
Peak memory 208828 kb
Host smart-4caa67b8-0777-49b8-bc2f-7f958f4fa371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936211908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1936211908
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3252206499
Short name T577
Test name
Test status
Simulation time 519700632 ps
CPU time 15.73 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:09 PM PDT 24
Peak memory 218156 kb
Host smart-b91bff11-ffbe-4d8e-8609-5aa1efb78451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252206499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3252206499
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3728984762
Short name T370
Test name
Test status
Simulation time 1042127859 ps
CPU time 15.2 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:31:07 PM PDT 24
Peak memory 217248 kb
Host smart-d7ddc402-c9b8-4cd2-9ec8-384eb272120d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728984762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3728984762
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1182600790
Short name T83
Test name
Test status
Simulation time 115353195 ps
CPU time 3.22 seconds
Started Jul 16 06:30:51 PM PDT 24
Finished Jul 16 06:30:56 PM PDT 24
Peak memory 218212 kb
Host smart-51dd07cd-8e5a-4d0b-a0b3-2f3b76f2a6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182600790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1182600790
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3172596025
Short name T575
Test name
Test status
Simulation time 1253620485 ps
CPU time 8.65 seconds
Started Jul 16 06:30:52 PM PDT 24
Finished Jul 16 06:31:03 PM PDT 24
Peak memory 225980 kb
Host smart-81879166-c004-45b7-88c2-2e283b73308c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172596025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3172596025
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.713855452
Short name T781
Test name
Test status
Simulation time 780841481 ps
CPU time 13.37 seconds
Started Jul 16 06:30:53 PM PDT 24
Finished Jul 16 06:31:07 PM PDT 24
Peak memory 218164 kb
Host smart-0178128f-06ad-4b79-827f-a541b1861307
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713855452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.713855452
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1904237529
Short name T282
Test name
Test status
Simulation time 1661556716 ps
CPU time 14.7 seconds
Started Jul 16 06:30:50 PM PDT 24
Finished Jul 16 06:31:06 PM PDT 24
Peak memory 218188 kb
Host smart-02124581-2eaa-4713-9795-5a523fbbc000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904237529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1904237529
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4234345077
Short name T584
Test name
Test status
Simulation time 55884044 ps
CPU time 2.02 seconds
Started Jul 16 06:30:52 PM PDT 24
Finished Jul 16 06:30:55 PM PDT 24
Peak memory 217588 kb
Host smart-ec3befc0-e50e-466a-b751-a8ddf9892f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234345077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4234345077
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.470309851
Short name T431
Test name
Test status
Simulation time 917119712 ps
CPU time 24.33 seconds
Started Jul 16 06:30:50 PM PDT 24
Finished Jul 16 06:31:15 PM PDT 24
Peak memory 250980 kb
Host smart-92916d6b-6ad4-44e6-ab83-8100d919fcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470309851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.470309851
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3586330340
Short name T718
Test name
Test status
Simulation time 268641528 ps
CPU time 6.09 seconds
Started Jul 16 06:30:53 PM PDT 24
Finished Jul 16 06:31:01 PM PDT 24
Peak memory 242788 kb
Host smart-02042857-605d-415e-8e2a-006bd1dc18b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586330340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3586330340
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2119331716
Short name T595
Test name
Test status
Simulation time 7003193180 ps
CPU time 140.05 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:33:25 PM PDT 24
Peak memory 251016 kb
Host smart-fb2673c6-724b-4bd2-b9f4-a2a5e10e036d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119331716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2119331716
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1371354975
Short name T157
Test name
Test status
Simulation time 267973392877 ps
CPU time 383.88 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:37:29 PM PDT 24
Peak memory 283864 kb
Host smart-9596b33d-1a85-4079-af29-1b5a818a2293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1371354975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1371354975
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1882834379
Short name T235
Test name
Test status
Simulation time 32541801 ps
CPU time 0.94 seconds
Started Jul 16 06:30:52 PM PDT 24
Finished Jul 16 06:30:55 PM PDT 24
Peak memory 211772 kb
Host smart-3624f516-4619-4cc9-805c-1f31e9c8a3f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882834379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1882834379
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3489087985
Short name T712
Test name
Test status
Simulation time 52699205 ps
CPU time 1.01 seconds
Started Jul 16 06:31:07 PM PDT 24
Finished Jul 16 06:31:09 PM PDT 24
Peak memory 208864 kb
Host smart-c608775a-e21b-40a9-ae71-9c152e151d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489087985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3489087985
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3257769166
Short name T815
Test name
Test status
Simulation time 256194584 ps
CPU time 8.89 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:12 PM PDT 24
Peak memory 225984 kb
Host smart-d9c97d44-d48d-4cdc-9567-2e88f18a10fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257769166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3257769166
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2434894788
Short name T558
Test name
Test status
Simulation time 146733173 ps
CPU time 2.17 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:06 PM PDT 24
Peak memory 217216 kb
Host smart-1f5774f5-1d91-4419-a553-b830891c089c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434894788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2434894788
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3170418844
Short name T168
Test name
Test status
Simulation time 30325421 ps
CPU time 2.07 seconds
Started Jul 16 06:31:07 PM PDT 24
Finished Jul 16 06:31:10 PM PDT 24
Peak memory 218220 kb
Host smart-cee7182f-65a6-467a-a992-5f2e43ea7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170418844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3170418844
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.156720367
Short name T300
Test name
Test status
Simulation time 432996669 ps
CPU time 11.77 seconds
Started Jul 16 06:31:07 PM PDT 24
Finished Jul 16 06:31:20 PM PDT 24
Peak memory 225892 kb
Host smart-e4b238a3-0b29-401e-ac5d-3ba69071e305
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156720367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.156720367
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.619155780
Short name T555
Test name
Test status
Simulation time 835682162 ps
CPU time 9.37 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:31:15 PM PDT 24
Peak memory 218072 kb
Host smart-1b083af1-7b81-415f-bdba-88add65cc39b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619155780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.619155780
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2966735449
Short name T703
Test name
Test status
Simulation time 1062191333 ps
CPU time 10.56 seconds
Started Jul 16 06:31:07 PM PDT 24
Finished Jul 16 06:31:18 PM PDT 24
Peak memory 225744 kb
Host smart-d8e7bca3-9a28-4d39-8200-d9948536872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966735449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2966735449
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4131038873
Short name T267
Test name
Test status
Simulation time 121083369 ps
CPU time 2.8 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:31:08 PM PDT 24
Peak memory 214620 kb
Host smart-15739bfe-4a50-42c2-87ee-8481496b5a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131038873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4131038873
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.4084537528
Short name T110
Test name
Test status
Simulation time 399193013 ps
CPU time 24.07 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:31:31 PM PDT 24
Peak memory 250756 kb
Host smart-63c1aeed-d9f1-454c-97e9-2eb17dbf82e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084537528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.4084537528
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.695633151
Short name T375
Test name
Test status
Simulation time 575923386 ps
CPU time 6.07 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:09 PM PDT 24
Peak memory 246976 kb
Host smart-5f438aae-ecc3-4495-8428-15481eb48a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695633151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.695633151
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2315129012
Short name T427
Test name
Test status
Simulation time 30293703867 ps
CPU time 984.45 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:47:43 PM PDT 24
Peak memory 272484 kb
Host smart-b6b58a31-e86d-44a9-888c-48e672452b19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315129012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2315129012
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.263926497
Short name T491
Test name
Test status
Simulation time 11848220 ps
CPU time 0.84 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:31:08 PM PDT 24
Peak memory 211828 kb
Host smart-aea0d979-80f7-498a-9030-673d8d3d25c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263926497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.263926497
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1904889384
Short name T672
Test name
Test status
Simulation time 12456669 ps
CPU time 0.87 seconds
Started Jul 16 06:28:10 PM PDT 24
Finished Jul 16 06:28:12 PM PDT 24
Peak memory 208488 kb
Host smart-0525ce9d-4fc9-487f-8470-39274d80e564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904889384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1904889384
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.653451789
Short name T693
Test name
Test status
Simulation time 320259615 ps
CPU time 14.65 seconds
Started Jul 16 06:27:54 PM PDT 24
Finished Jul 16 06:28:09 PM PDT 24
Peak memory 225904 kb
Host smart-e22917ad-1a63-4f3b-b0a8-6d3dc71752dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653451789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.653451789
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3734449549
Short name T32
Test name
Test status
Simulation time 1016597438 ps
CPU time 8.33 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:17 PM PDT 24
Peak memory 217316 kb
Host smart-07873d97-9007-4e2c-a1b9-1210eb2bfbda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734449549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3734449549
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1840934656
Short name T482
Test name
Test status
Simulation time 4629690540 ps
CPU time 35.36 seconds
Started Jul 16 06:28:08 PM PDT 24
Finished Jul 16 06:28:45 PM PDT 24
Peak memory 218200 kb
Host smart-086b9d35-3e3e-4c9f-aedc-f9a1f21c4e07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840934656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1840934656
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2154172874
Short name T337
Test name
Test status
Simulation time 3326000785 ps
CPU time 8.44 seconds
Started Jul 16 06:28:10 PM PDT 24
Finished Jul 16 06:28:19 PM PDT 24
Peak memory 217684 kb
Host smart-b064d6a0-f92e-4789-911a-169e1e59f2ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154172874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
154172874
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3158681621
Short name T843
Test name
Test status
Simulation time 1239283074 ps
CPU time 9.18 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:18 PM PDT 24
Peak memory 222832 kb
Host smart-dfc65b59-21de-49f6-8bc6-cc49cb0cae6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158681621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3158681621
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.7338135
Short name T77
Test name
Test status
Simulation time 1200669937 ps
CPU time 19.03 seconds
Started Jul 16 06:28:06 PM PDT 24
Finished Jul 16 06:28:26 PM PDT 24
Peak memory 217572 kb
Host smart-a16f420b-5867-45be-8fc5-5bc221619098
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7338135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_re
gwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_regwen_during_op.7338135
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2372533113
Short name T75
Test name
Test status
Simulation time 178298802 ps
CPU time 6.12 seconds
Started Jul 16 06:28:00 PM PDT 24
Finished Jul 16 06:28:06 PM PDT 24
Peak memory 217548 kb
Host smart-1001e440-2cac-457b-b740-d187168d289c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372533113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2372533113
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.236292698
Short name T417
Test name
Test status
Simulation time 11685837616 ps
CPU time 95.22 seconds
Started Jul 16 06:27:55 PM PDT 24
Finished Jul 16 06:29:31 PM PDT 24
Peak memory 280804 kb
Host smart-1ec73265-f64b-4fd5-82ff-03882fe1b4cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236292698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.236292698
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3646742416
Short name T383
Test name
Test status
Simulation time 4364435685 ps
CPU time 23.14 seconds
Started Jul 16 06:27:55 PM PDT 24
Finished Jul 16 06:28:18 PM PDT 24
Peak memory 250956 kb
Host smart-5244a60a-7040-429f-9105-292ee1b0e955
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646742416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3646742416
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3198942523
Short name T229
Test name
Test status
Simulation time 217110530 ps
CPU time 2.41 seconds
Started Jul 16 06:27:56 PM PDT 24
Finished Jul 16 06:27:59 PM PDT 24
Peak memory 218204 kb
Host smart-4bf02aec-5a93-42d0-8a49-0fb72c90ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198942523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3198942523
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.683497441
Short name T396
Test name
Test status
Simulation time 1865038637 ps
CPU time 6.21 seconds
Started Jul 16 06:27:56 PM PDT 24
Finished Jul 16 06:28:03 PM PDT 24
Peak memory 222152 kb
Host smart-40f90355-fe13-4d82-bca8-90c9cf1bfbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683497441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.683497441
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.38209349
Short name T90
Test name
Test status
Simulation time 1027205485 ps
CPU time 41.2 seconds
Started Jul 16 06:28:09 PM PDT 24
Finished Jul 16 06:28:51 PM PDT 24
Peak memory 269000 kb
Host smart-b7960f46-bc3b-4331-b053-85ff3b04efcb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.38209349
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.256818065
Short name T13
Test name
Test status
Simulation time 265307585 ps
CPU time 9.54 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:18 PM PDT 24
Peak memory 226032 kb
Host smart-89cf516b-9f32-4c9e-aa34-30faa94e156a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256818065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.256818065
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2404007879
Short name T684
Test name
Test status
Simulation time 2788856714 ps
CPU time 10.61 seconds
Started Jul 16 06:28:10 PM PDT 24
Finished Jul 16 06:28:21 PM PDT 24
Peak memory 225908 kb
Host smart-fb89d341-ad63-4085-90c3-3815c5c5fad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404007879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2404007879
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2156203095
Short name T179
Test name
Test status
Simulation time 882706466 ps
CPU time 8.44 seconds
Started Jul 16 06:28:06 PM PDT 24
Finished Jul 16 06:28:16 PM PDT 24
Peak memory 218080 kb
Host smart-ca08fc6e-8631-4012-aa80-2d7c2934697a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156203095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
156203095
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2433785134
Short name T521
Test name
Test status
Simulation time 684913708 ps
CPU time 11.5 seconds
Started Jul 16 06:27:55 PM PDT 24
Finished Jul 16 06:28:07 PM PDT 24
Peak memory 218268 kb
Host smart-52b15f55-14ab-4abb-bbee-9953016d57dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433785134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2433785134
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3031475971
Short name T78
Test name
Test status
Simulation time 61064637 ps
CPU time 1.97 seconds
Started Jul 16 06:27:55 PM PDT 24
Finished Jul 16 06:27:57 PM PDT 24
Peak memory 217572 kb
Host smart-19bc8c19-c2fc-4abd-987f-38c7e918f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031475971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3031475971
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3516042278
Short name T307
Test name
Test status
Simulation time 481835589 ps
CPU time 33.75 seconds
Started Jul 16 06:27:55 PM PDT 24
Finished Jul 16 06:28:29 PM PDT 24
Peak memory 246560 kb
Host smart-f20fec0f-2279-4a38-80fb-10300e9762de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516042278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3516042278
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1985851429
Short name T633
Test name
Test status
Simulation time 107118649 ps
CPU time 3.58 seconds
Started Jul 16 06:27:54 PM PDT 24
Finished Jul 16 06:27:58 PM PDT 24
Peak memory 218256 kb
Host smart-4e4a2752-0fb2-4f6d-be7e-5fad70503cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985851429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1985851429
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2533901934
Short name T330
Test name
Test status
Simulation time 9392235117 ps
CPU time 109.06 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:29:57 PM PDT 24
Peak memory 267356 kb
Host smart-416a29ec-8b6d-4a64-9913-5eadbc7a01f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533901934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2533901934
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1686187212
Short name T853
Test name
Test status
Simulation time 21576425 ps
CPU time 0.93 seconds
Started Jul 16 06:27:56 PM PDT 24
Finished Jul 16 06:27:57 PM PDT 24
Peak memory 211780 kb
Host smart-6df52e46-7cd0-48bf-a962-0a3ee6438915
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686187212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1686187212
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.586681129
Short name T767
Test name
Test status
Simulation time 19434427 ps
CPU time 0.97 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:31:08 PM PDT 24
Peak memory 208700 kb
Host smart-f0cf5696-63ea-468e-aae0-757bcdfcfcf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586681129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.586681129
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2730970544
Short name T696
Test name
Test status
Simulation time 503881603 ps
CPU time 13.05 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:31:18 PM PDT 24
Peak memory 226008 kb
Host smart-56048873-4b0e-4ad2-b9d7-5d53a6331df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730970544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2730970544
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1432047793
Short name T424
Test name
Test status
Simulation time 3874587654 ps
CPU time 22.5 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:27 PM PDT 24
Peak memory 217660 kb
Host smart-ebf1942d-afb6-4a9a-bedd-b231a50188a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432047793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1432047793
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3523482087
Short name T36
Test name
Test status
Simulation time 165106130 ps
CPU time 3.9 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:08 PM PDT 24
Peak memory 218160 kb
Host smart-60a66c01-18fc-4e71-8978-dc57e63e149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523482087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3523482087
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4274927558
Short name T317
Test name
Test status
Simulation time 776540194 ps
CPU time 9.34 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:31:16 PM PDT 24
Peak memory 226024 kb
Host smart-6d6edf0a-47b3-4d5c-be93-71db0aab2441
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274927558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4274927558
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1008473640
Short name T605
Test name
Test status
Simulation time 280932046 ps
CPU time 11.78 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:31:19 PM PDT 24
Peak memory 225944 kb
Host smart-cfc76e30-9096-4004-ab93-59d5b9fee9ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008473640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1008473640
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3029157457
Short name T264
Test name
Test status
Simulation time 1387446388 ps
CPU time 9.04 seconds
Started Jul 16 06:31:07 PM PDT 24
Finished Jul 16 06:31:17 PM PDT 24
Peak memory 225896 kb
Host smart-43801104-5d3b-48a4-b078-4d6c1d2a0f4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029157457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3029157457
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.577711211
Short name T861
Test name
Test status
Simulation time 202538056 ps
CPU time 8.46 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:12 PM PDT 24
Peak memory 224744 kb
Host smart-959da974-0e53-4417-9338-3bdd9680a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577711211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.577711211
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.4122340947
Short name T590
Test name
Test status
Simulation time 16836707 ps
CPU time 1.34 seconds
Started Jul 16 06:31:02 PM PDT 24
Finished Jul 16 06:31:04 PM PDT 24
Peak memory 217628 kb
Host smart-2527acc3-aa8b-40b0-873a-4a50c2eef170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122340947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.4122340947
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1844572606
Short name T111
Test name
Test status
Simulation time 2624496940 ps
CPU time 28.91 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:32 PM PDT 24
Peak memory 250996 kb
Host smart-fbf4bb07-58b4-4cc9-895d-db3c408af8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844572606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1844572606
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.970716669
Short name T327
Test name
Test status
Simulation time 51341446 ps
CPU time 7.37 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:31:12 PM PDT 24
Peak memory 250880 kb
Host smart-5ce0541c-1aeb-4ca7-8e3f-818b38f67eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970716669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.970716669
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.929603690
Short name T322
Test name
Test status
Simulation time 11024380475 ps
CPU time 109.38 seconds
Started Jul 16 06:31:07 PM PDT 24
Finished Jul 16 06:32:57 PM PDT 24
Peak memory 283776 kb
Host smart-0cbe91d2-ea4c-4672-ad03-b8e4950dfb1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929603690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.929603690
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2915139762
Short name T628
Test name
Test status
Simulation time 37001012967 ps
CPU time 739.44 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:43:26 PM PDT 24
Peak memory 332848 kb
Host smart-9957cc52-8c76-41d0-8f5e-ea128bdd2a73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2915139762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2915139762
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1923474143
Short name T412
Test name
Test status
Simulation time 40663051 ps
CPU time 0.85 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:05 PM PDT 24
Peak memory 211724 kb
Host smart-e6a7ac61-0a24-447e-b069-4a2757c79f2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923474143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1923474143
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3735893976
Short name T464
Test name
Test status
Simulation time 65664940 ps
CPU time 1.12 seconds
Started Jul 16 06:31:17 PM PDT 24
Finished Jul 16 06:31:20 PM PDT 24
Peak memory 208884 kb
Host smart-8b5a6158-8281-4d81-890e-2b0a40c5cb3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735893976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3735893976
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.553794360
Short name T259
Test name
Test status
Simulation time 409276785 ps
CPU time 10.3 seconds
Started Jul 16 06:31:05 PM PDT 24
Finished Jul 16 06:31:17 PM PDT 24
Peak memory 218220 kb
Host smart-4467f748-1633-40b5-b283-3afd661d6fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553794360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.553794360
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2672837705
Short name T852
Test name
Test status
Simulation time 621536780 ps
CPU time 5.79 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:31:11 PM PDT 24
Peak memory 217284 kb
Host smart-0fb11998-a67d-42d9-bc10-55822fcdacd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672837705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2672837705
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2793767121
Short name T851
Test name
Test status
Simulation time 259849983 ps
CPU time 3.14 seconds
Started Jul 16 06:31:05 PM PDT 24
Finished Jul 16 06:31:09 PM PDT 24
Peak memory 218188 kb
Host smart-6dae475c-99c9-4935-9f34-ec0f2f861835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793767121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2793767121
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2017379267
Short name T691
Test name
Test status
Simulation time 1162338358 ps
CPU time 11.5 seconds
Started Jul 16 06:31:05 PM PDT 24
Finished Jul 16 06:31:18 PM PDT 24
Peak memory 225992 kb
Host smart-a276d80a-aa30-4901-8e01-f30d0f4a167c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017379267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2017379267
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1294067060
Short name T594
Test name
Test status
Simulation time 1073049342 ps
CPU time 8.6 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:31:16 PM PDT 24
Peak memory 225964 kb
Host smart-bb147fc6-04db-4838-a6e6-0320122f7733
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294067060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1294067060
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1874347415
Short name T730
Test name
Test status
Simulation time 577615223 ps
CPU time 9.55 seconds
Started Jul 16 06:31:03 PM PDT 24
Finished Jul 16 06:31:14 PM PDT 24
Peak memory 226036 kb
Host smart-5e5646b2-02af-4705-8ab3-28f2301600d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874347415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1874347415
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2424949852
Short name T664
Test name
Test status
Simulation time 21724929 ps
CPU time 1.24 seconds
Started Jul 16 06:31:02 PM PDT 24
Finished Jul 16 06:31:04 PM PDT 24
Peak memory 217636 kb
Host smart-a681c0fb-ca8f-4e31-bbe4-e4d9f12e5829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424949852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2424949852
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2273458257
Short name T743
Test name
Test status
Simulation time 1234552526 ps
CPU time 24.3 seconds
Started Jul 16 06:31:05 PM PDT 24
Finished Jul 16 06:31:30 PM PDT 24
Peak memory 250932 kb
Host smart-27e849e6-b50d-4166-b9b2-58431a6c6551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273458257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2273458257
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2006041885
Short name T766
Test name
Test status
Simulation time 248757180 ps
CPU time 6.33 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:31:13 PM PDT 24
Peak memory 250760 kb
Host smart-9a075142-f791-4348-8c4d-2ef87c47590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006041885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2006041885
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1934097422
Short name T61
Test name
Test status
Simulation time 11355813468 ps
CPU time 55.25 seconds
Started Jul 16 06:31:06 PM PDT 24
Finished Jul 16 06:32:02 PM PDT 24
Peak memory 226000 kb
Host smart-d08292d3-9154-4bdc-970e-242941bcd2ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934097422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1934097422
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3807768568
Short name T156
Test name
Test status
Simulation time 180346477913 ps
CPU time 633.03 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:41:52 PM PDT 24
Peak memory 422080 kb
Host smart-0f171e6b-9913-47cb-acc0-ebed6d00589a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3807768568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3807768568
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3374458974
Short name T210
Test name
Test status
Simulation time 155391013 ps
CPU time 0.91 seconds
Started Jul 16 06:31:04 PM PDT 24
Finished Jul 16 06:31:06 PM PDT 24
Peak memory 212896 kb
Host smart-615c5e67-e412-4bc0-a2ec-dedc199cbf6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374458974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3374458974
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2583178641
Short name T74
Test name
Test status
Simulation time 13289300 ps
CPU time 0.88 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:19 PM PDT 24
Peak memory 208764 kb
Host smart-3966dcb6-ff22-4f75-98b0-a842d9463587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583178641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2583178641
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1509021826
Short name T553
Test name
Test status
Simulation time 823055011 ps
CPU time 9.18 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:28 PM PDT 24
Peak memory 225972 kb
Host smart-97522850-75b7-4ccd-95d7-3d5c6faeff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509021826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1509021826
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.397395072
Short name T30
Test name
Test status
Simulation time 418794063 ps
CPU time 11.64 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:29 PM PDT 24
Peak memory 217068 kb
Host smart-635069ed-5144-4d3f-8a74-47c9e2d5e6e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397395072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.397395072
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4277680128
Short name T601
Test name
Test status
Simulation time 93464818 ps
CPU time 4.07 seconds
Started Jul 16 06:31:41 PM PDT 24
Finished Jul 16 06:31:45 PM PDT 24
Peak memory 218148 kb
Host smart-d554b50e-4120-429f-aec8-7e2ab1535c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277680128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4277680128
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1743039308
Short name T657
Test name
Test status
Simulation time 528145641 ps
CPU time 11.74 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:27 PM PDT 24
Peak memory 225968 kb
Host smart-464d386c-5f1f-42b3-8cfe-6a718b110eac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743039308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1743039308
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3546518575
Short name T351
Test name
Test status
Simulation time 1532599507 ps
CPU time 14.92 seconds
Started Jul 16 06:31:20 PM PDT 24
Finished Jul 16 06:31:35 PM PDT 24
Peak memory 225860 kb
Host smart-c825a72f-d8d7-4c67-8f24-8e4bb3dc43bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546518575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3546518575
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3688249401
Short name T102
Test name
Test status
Simulation time 539780279 ps
CPU time 18.26 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:37 PM PDT 24
Peak memory 218128 kb
Host smart-2ac7bb89-3243-4737-b9f9-dc54534b4485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688249401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3688249401
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3695483715
Short name T218
Test name
Test status
Simulation time 1398926710 ps
CPU time 12.93 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:32 PM PDT 24
Peak memory 226028 kb
Host smart-c99b0f10-aee6-4dea-852e-ff78253266b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695483715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3695483715
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3950983945
Short name T280
Test name
Test status
Simulation time 40563612 ps
CPU time 2.56 seconds
Started Jul 16 06:31:14 PM PDT 24
Finished Jul 16 06:31:17 PM PDT 24
Peak memory 214200 kb
Host smart-a7168d08-2204-4a58-96f6-0ba2c4abfe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950983945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3950983945
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3244270566
Short name T485
Test name
Test status
Simulation time 395354450 ps
CPU time 31.28 seconds
Started Jul 16 06:31:17 PM PDT 24
Finished Jul 16 06:31:50 PM PDT 24
Peak memory 250840 kb
Host smart-237c398a-c11d-4a03-a1e3-038e51d09e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244270566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3244270566
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1016734837
Short name T638
Test name
Test status
Simulation time 256581874 ps
CPU time 7.59 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:26 PM PDT 24
Peak memory 250900 kb
Host smart-b1ad4be2-565a-468c-847b-56fd339c7d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016734837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1016734837
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4108131579
Short name T57
Test name
Test status
Simulation time 73822406882 ps
CPU time 732.9 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:43:32 PM PDT 24
Peak memory 529684 kb
Host smart-a88b55d9-5a66-450e-a102-ef42ba8d09aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4108131579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.4108131579
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1564850802
Short name T752
Test name
Test status
Simulation time 12330219 ps
CPU time 0.96 seconds
Started Jul 16 06:31:17 PM PDT 24
Finished Jul 16 06:31:20 PM PDT 24
Peak memory 211788 kb
Host smart-f06e22e2-31f1-491f-9b2e-5f550dd5a3a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564850802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1564850802
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1445183188
Short name T827
Test name
Test status
Simulation time 46081052 ps
CPU time 1.24 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:17 PM PDT 24
Peak memory 209028 kb
Host smart-87dc6c4e-1017-4680-b14f-157c23e29948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445183188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1445183188
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3038919771
Short name T254
Test name
Test status
Simulation time 2198833071 ps
CPU time 17.43 seconds
Started Jul 16 06:31:19 PM PDT 24
Finished Jul 16 06:31:38 PM PDT 24
Peak memory 218168 kb
Host smart-a7a604e7-985c-4a2f-bdde-756aebe70231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038919771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3038919771
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.805038508
Short name T645
Test name
Test status
Simulation time 262609766 ps
CPU time 2.58 seconds
Started Jul 16 06:31:17 PM PDT 24
Finished Jul 16 06:31:22 PM PDT 24
Peak memory 216908 kb
Host smart-7a334042-5e82-4d5e-b4a4-d82cbc2b91cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805038508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.805038508
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1338399721
Short name T528
Test name
Test status
Simulation time 164699769 ps
CPU time 3.97 seconds
Started Jul 16 06:31:18 PM PDT 24
Finished Jul 16 06:31:24 PM PDT 24
Peak memory 218096 kb
Host smart-11942a66-8a8f-41dc-baf0-106deccb3272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338399721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1338399721
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2380356275
Short name T479
Test name
Test status
Simulation time 455564124 ps
CPU time 18.7 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:34 PM PDT 24
Peak memory 226032 kb
Host smart-289a2298-4cb4-493e-9e98-dfb590437d04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380356275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2380356275
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.63822519
Short name T764
Test name
Test status
Simulation time 521645517 ps
CPU time 10.23 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:28 PM PDT 24
Peak memory 225812 kb
Host smart-bc2e4b6c-4733-4cd5-b77b-23fc90380e27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63822519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_dig
est.63822519
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.516713425
Short name T371
Test name
Test status
Simulation time 983092281 ps
CPU time 8.79 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:27 PM PDT 24
Peak memory 218156 kb
Host smart-9e8b06c8-a92f-4910-9d1a-05e6cfad4cdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516713425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.516713425
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.619335691
Short name T780
Test name
Test status
Simulation time 291961264 ps
CPU time 7.8 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:25 PM PDT 24
Peak memory 225976 kb
Host smart-0204c8af-6f0a-444d-919e-08fac77295fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619335691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.619335691
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2565350489
Short name T704
Test name
Test status
Simulation time 162853326 ps
CPU time 1.27 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:19 PM PDT 24
Peak memory 213564 kb
Host smart-fb0da7e0-72ce-4a68-8fa5-6c4b283be9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565350489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2565350489
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2516781724
Short name T261
Test name
Test status
Simulation time 3318318106 ps
CPU time 25.52 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:42 PM PDT 24
Peak memory 250948 kb
Host smart-4fd9a585-eab4-49f9-ba64-df12cf2ca530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516781724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2516781724
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2703518964
Short name T334
Test name
Test status
Simulation time 255159385 ps
CPU time 5.79 seconds
Started Jul 16 06:31:18 PM PDT 24
Finished Jul 16 06:31:25 PM PDT 24
Peak memory 246484 kb
Host smart-410f503b-8fb5-4dff-9a43-a0f19d5d95a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703518964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2703518964
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2718907930
Short name T186
Test name
Test status
Simulation time 20398851297 ps
CPU time 169.92 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:34:09 PM PDT 24
Peak memory 250888 kb
Host smart-566a1f78-7f4d-4094-bc05-ad8273476084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718907930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2718907930
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.275374205
Short name T488
Test name
Test status
Simulation time 31484063 ps
CPU time 0.99 seconds
Started Jul 16 06:31:19 PM PDT 24
Finished Jul 16 06:31:21 PM PDT 24
Peak memory 211912 kb
Host smart-de919118-468d-4f45-8e98-0848ff5d3fb6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275374205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.275374205
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3151755326
Short name T398
Test name
Test status
Simulation time 22601261 ps
CPU time 1.32 seconds
Started Jul 16 06:31:14 PM PDT 24
Finished Jul 16 06:31:16 PM PDT 24
Peak memory 208796 kb
Host smart-f0970005-f348-4c52-acb8-abdd71582ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151755326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3151755326
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1215149821
Short name T55
Test name
Test status
Simulation time 638947129 ps
CPU time 9.62 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:27 PM PDT 24
Peak memory 218276 kb
Host smart-05269a55-cd63-4012-9c37-fc91539b8b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215149821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1215149821
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1158992518
Short name T484
Test name
Test status
Simulation time 156842713 ps
CPU time 4.78 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:21 PM PDT 24
Peak memory 216980 kb
Host smart-204e694d-b49c-4937-996c-32e7d21a92a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158992518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1158992518
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3968507667
Short name T310
Test name
Test status
Simulation time 277831889 ps
CPU time 1.69 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:19 PM PDT 24
Peak memory 218176 kb
Host smart-6b4823b5-5277-4cdd-90c2-d2b120a9abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968507667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3968507667
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3383526888
Short name T230
Test name
Test status
Simulation time 1332028604 ps
CPU time 14.8 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:32 PM PDT 24
Peak memory 226036 kb
Host smart-76524cf1-87a5-452d-9613-6abf41f094fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383526888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3383526888
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3619435386
Short name T614
Test name
Test status
Simulation time 322600494 ps
CPU time 11.41 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:28 PM PDT 24
Peak memory 225868 kb
Host smart-6e3fbe4a-b266-42a6-977c-6c699b27a590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619435386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3619435386
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.4112592844
Short name T829
Test name
Test status
Simulation time 2947758413 ps
CPU time 14.35 seconds
Started Jul 16 06:31:20 PM PDT 24
Finished Jul 16 06:31:35 PM PDT 24
Peak memory 225924 kb
Host smart-afe4fafc-ebc3-47b8-a6ed-33d9fce464c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112592844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
4112592844
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.968409946
Short name T778
Test name
Test status
Simulation time 1001420219 ps
CPU time 8.08 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:26 PM PDT 24
Peak memory 218520 kb
Host smart-b55bb8d0-f6bb-4953-aea4-e4b5efdc17e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968409946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.968409946
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2897717033
Short name T70
Test name
Test status
Simulation time 25027249 ps
CPU time 1 seconds
Started Jul 16 06:31:19 PM PDT 24
Finished Jul 16 06:31:21 PM PDT 24
Peak memory 208876 kb
Host smart-b9ba0ff1-67ae-4d2f-81ab-34a93dd3260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897717033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2897717033
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1510909569
Short name T430
Test name
Test status
Simulation time 574419484 ps
CPU time 22.21 seconds
Started Jul 16 06:31:21 PM PDT 24
Finished Jul 16 06:31:44 PM PDT 24
Peak memory 245524 kb
Host smart-b2b3ee66-9070-46db-a588-97f200c0a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510909569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1510909569
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.234721801
Short name T750
Test name
Test status
Simulation time 426127895 ps
CPU time 8.1 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:27 PM PDT 24
Peak memory 250440 kb
Host smart-43d18331-c468-44ef-99a1-344b41ec42b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234721801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.234721801
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2419461871
Short name T565
Test name
Test status
Simulation time 13260688794 ps
CPU time 104.98 seconds
Started Jul 16 06:31:18 PM PDT 24
Finished Jul 16 06:33:04 PM PDT 24
Peak memory 272880 kb
Host smart-d90e33cc-a655-4e80-a7cc-9b523df0b320
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419461871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2419461871
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3512798554
Short name T539
Test name
Test status
Simulation time 11349279 ps
CPU time 0.87 seconds
Started Jul 16 06:31:15 PM PDT 24
Finished Jul 16 06:31:18 PM PDT 24
Peak memory 211804 kb
Host smart-b265f20e-11c1-4c34-a1cd-e001061a3f92
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512798554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3512798554
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2667035888
Short name T612
Test name
Test status
Simulation time 18963417 ps
CPU time 1.18 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:32 PM PDT 24
Peak memory 209064 kb
Host smart-1e2e97bc-9f9b-43a0-a4bb-003e7b064fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667035888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2667035888
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.4038539123
Short name T41
Test name
Test status
Simulation time 295621430 ps
CPU time 12.29 seconds
Started Jul 16 06:31:32 PM PDT 24
Finished Jul 16 06:31:46 PM PDT 24
Peak memory 218204 kb
Host smart-ffd4fad3-2ebb-4f65-b4ba-873a2169fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038539123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.4038539123
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4195092090
Short name T31
Test name
Test status
Simulation time 949094733 ps
CPU time 12.27 seconds
Started Jul 16 06:31:32 PM PDT 24
Finished Jul 16 06:31:46 PM PDT 24
Peak memory 217072 kb
Host smart-874e5180-1212-4c33-97d4-733203b2922f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195092090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4195092090
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1165393200
Short name T233
Test name
Test status
Simulation time 30092329 ps
CPU time 2.14 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:35 PM PDT 24
Peak memory 221960 kb
Host smart-7dbde825-d1e9-4adf-9afb-b940311c0624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165393200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1165393200
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.688844733
Short name T43
Test name
Test status
Simulation time 571505689 ps
CPU time 14.78 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:47 PM PDT 24
Peak memory 226008 kb
Host smart-0c63d0a6-5ce6-45f0-9785-c87706c67fe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688844733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.688844733
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3798682898
Short name T802
Test name
Test status
Simulation time 328202974 ps
CPU time 9.99 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:31:44 PM PDT 24
Peak memory 218088 kb
Host smart-350d9cb4-6c7c-4286-87d5-e2954f36ecb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798682898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3798682898
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2263439400
Short name T618
Test name
Test status
Simulation time 1065458070 ps
CPU time 10.22 seconds
Started Jul 16 06:31:34 PM PDT 24
Finished Jul 16 06:31:45 PM PDT 24
Peak memory 218160 kb
Host smart-e41b0438-de4a-42b1-954a-1f2173accd84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263439400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2263439400
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.502874789
Short name T222
Test name
Test status
Simulation time 195988838 ps
CPU time 8.18 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:31:43 PM PDT 24
Peak memory 226012 kb
Host smart-f81c2005-16a4-401b-a699-e9ef7e76e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502874789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.502874789
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1872550023
Short name T746
Test name
Test status
Simulation time 826949761 ps
CPU time 5.25 seconds
Started Jul 16 06:31:16 PM PDT 24
Finished Jul 16 06:31:24 PM PDT 24
Peak memory 217652 kb
Host smart-d88f1ef8-f36b-4d21-8114-5658cebefc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872550023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1872550023
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3530870047
Short name T232
Test name
Test status
Simulation time 1260574572 ps
CPU time 21.04 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:54 PM PDT 24
Peak memory 245736 kb
Host smart-30b160b3-fcdb-4c7d-8d95-57dacff503d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530870047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3530870047
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3842668549
Short name T726
Test name
Test status
Simulation time 136543365 ps
CPU time 8.35 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:40 PM PDT 24
Peak memory 250960 kb
Host smart-263f8107-be3c-4d25-add1-3d10b0b9da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842668549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3842668549
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2441832461
Short name T737
Test name
Test status
Simulation time 2713979103 ps
CPU time 66.7 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:32:37 PM PDT 24
Peak memory 250996 kb
Host smart-21b5a95e-36be-434d-8120-2b494a19125a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441832461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2441832461
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.4084509531
Short name T208
Test name
Test status
Simulation time 19619691 ps
CPU time 1.27 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:34 PM PDT 24
Peak memory 217616 kb
Host smart-2e1c27f1-48ea-4322-a8e5-eef91d120f9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084509531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.4084509531
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3732979179
Short name T173
Test name
Test status
Simulation time 42287302 ps
CPU time 0.96 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:31:35 PM PDT 24
Peak memory 208932 kb
Host smart-b980aa73-5e2d-42b3-b7bb-1ab07a62cf76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732979179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3732979179
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.4204840545
Short name T405
Test name
Test status
Simulation time 10008210147 ps
CPU time 17.43 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:49 PM PDT 24
Peak memory 218508 kb
Host smart-16570fa2-a33b-431a-9989-5ed3b87a7326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204840545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.4204840545
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3308741243
Short name T8
Test name
Test status
Simulation time 680210873 ps
CPU time 16.99 seconds
Started Jul 16 06:32:00 PM PDT 24
Finished Jul 16 06:32:17 PM PDT 24
Peak memory 217384 kb
Host smart-a4bb594c-0f89-45ce-8526-e23d247c7ef6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308741243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3308741243
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.226242563
Short name T658
Test name
Test status
Simulation time 29719021 ps
CPU time 1.4 seconds
Started Jul 16 06:31:32 PM PDT 24
Finished Jul 16 06:31:35 PM PDT 24
Peak memory 218192 kb
Host smart-3979f3c5-ace2-4445-af84-03912af50679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226242563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.226242563
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3241506973
Short name T814
Test name
Test status
Simulation time 229330058 ps
CPU time 7.52 seconds
Started Jul 16 06:31:32 PM PDT 24
Finished Jul 16 06:31:41 PM PDT 24
Peak memory 225968 kb
Host smart-3417c534-fa67-45eb-86de-8ca3d3e560cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241506973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3241506973
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3921394093
Short name T256
Test name
Test status
Simulation time 306555038 ps
CPU time 12.18 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:44 PM PDT 24
Peak memory 225972 kb
Host smart-7838e9b7-220d-41f9-9148-372b158f0d60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921394093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3921394093
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3504468371
Short name T621
Test name
Test status
Simulation time 3678314828 ps
CPU time 11.7 seconds
Started Jul 16 06:31:32 PM PDT 24
Finished Jul 16 06:31:45 PM PDT 24
Peak memory 226100 kb
Host smart-9d16098e-4aa2-4fee-ba7e-1538307b68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504468371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3504468371
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1937605527
Short name T395
Test name
Test status
Simulation time 80424524 ps
CPU time 1.97 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:35 PM PDT 24
Peak memory 214084 kb
Host smart-d56e89c6-a171-4ff0-b3e8-c103272c7b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937605527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1937605527
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2106216824
Short name T319
Test name
Test status
Simulation time 268262864 ps
CPU time 28.51 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:32:03 PM PDT 24
Peak memory 250900 kb
Host smart-10f35fdd-3dee-4821-b14c-10b0993bf62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106216824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2106216824
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2069879952
Short name T850
Test name
Test status
Simulation time 53257313 ps
CPU time 5.93 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:31:40 PM PDT 24
Peak memory 246684 kb
Host smart-d35b901b-1891-47dc-a7f1-c6ade7088e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069879952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2069879952
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2677918839
Short name T363
Test name
Test status
Simulation time 28354273520 ps
CPU time 212.65 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:35:07 PM PDT 24
Peak memory 283788 kb
Host smart-671899a3-f5e7-42b1-a681-6f4659861046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677918839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2677918839
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.740507157
Short name T162
Test name
Test status
Simulation time 171403588997 ps
CPU time 835.3 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:45:28 PM PDT 24
Peak memory 447760 kb
Host smart-adf708d1-d60d-48b7-8840-816296d834c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=740507157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.740507157
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1809176183
Short name T644
Test name
Test status
Simulation time 20877306 ps
CPU time 0.88 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:31 PM PDT 24
Peak memory 211876 kb
Host smart-0d00ad20-8383-466b-a24e-09c6be50fe4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809176183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1809176183
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.4207337586
Short name T420
Test name
Test status
Simulation time 27996901 ps
CPU time 1 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:33 PM PDT 24
Peak memory 208804 kb
Host smart-fa3a6db5-391e-49e4-b098-39d81b8ccf26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207337586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4207337586
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.774576243
Short name T348
Test name
Test status
Simulation time 7030891644 ps
CPU time 10.86 seconds
Started Jul 16 06:31:32 PM PDT 24
Finished Jul 16 06:31:44 PM PDT 24
Peak memory 218396 kb
Host smart-b0e2c4e4-4a98-4def-82c5-fb10b418956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774576243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.774576243
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3948800377
Short name T729
Test name
Test status
Simulation time 104529214 ps
CPU time 1.38 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:33 PM PDT 24
Peak memory 216968 kb
Host smart-681db3f5-7bf3-4bc5-97aa-57d66cc6b149
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948800377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3948800377
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3760441357
Short name T298
Test name
Test status
Simulation time 80288398 ps
CPU time 3.79 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:31:38 PM PDT 24
Peak memory 222764 kb
Host smart-23e3c817-87b3-4424-a61d-0fac85fa8bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760441357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3760441357
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.944024389
Short name T551
Test name
Test status
Simulation time 267469621 ps
CPU time 11.98 seconds
Started Jul 16 06:31:33 PM PDT 24
Finished Jul 16 06:31:46 PM PDT 24
Peak memory 218136 kb
Host smart-da2598ec-3346-48c8-b72c-3fca828e693d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944024389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.944024389
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2183123902
Short name T451
Test name
Test status
Simulation time 478902809 ps
CPU time 11.98 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:43 PM PDT 24
Peak memory 218188 kb
Host smart-2d1be7ac-d91b-4422-a3a6-7ca4fe0a3d1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183123902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2183123902
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2404777084
Short name T560
Test name
Test status
Simulation time 519020238 ps
CPU time 8.15 seconds
Started Jul 16 06:31:32 PM PDT 24
Finished Jul 16 06:31:42 PM PDT 24
Peak memory 226032 kb
Host smart-b0d43aae-a172-4489-a6d4-6c025a2de16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404777084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2404777084
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2176626338
Short name T436
Test name
Test status
Simulation time 85118622 ps
CPU time 6.04 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:38 PM PDT 24
Peak memory 217936 kb
Host smart-24c75eca-b252-45d4-9b18-d426857ec775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176626338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2176626338
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.357749701
Short name T622
Test name
Test status
Simulation time 785886357 ps
CPU time 20.36 seconds
Started Jul 16 06:31:31 PM PDT 24
Finished Jul 16 06:31:53 PM PDT 24
Peak memory 246280 kb
Host smart-70e987a4-78f8-496b-86a8-0aeac8dff9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357749701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.357749701
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3210758122
Short name T338
Test name
Test status
Simulation time 5722099448 ps
CPU time 83.57 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:32:55 PM PDT 24
Peak memory 226116 kb
Host smart-4215e3ad-849b-446d-bdca-9c1119306302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210758122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3210758122
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1486836638
Short name T332
Test name
Test status
Simulation time 13798789 ps
CPU time 1.03 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:31 PM PDT 24
Peak memory 211620 kb
Host smart-19e9c9de-c89d-4bc9-803e-d7ebc1c3a71c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486836638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1486836638
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.20515932
Short name T820
Test name
Test status
Simulation time 60516445 ps
CPU time 0.89 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:31:45 PM PDT 24
Peak memory 208796 kb
Host smart-ecbb917c-5e98-4d56-baad-cc8076ee7f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20515932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.20515932
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.950526950
Short name T715
Test name
Test status
Simulation time 391340534 ps
CPU time 12.82 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:31:57 PM PDT 24
Peak memory 218140 kb
Host smart-c7902781-5853-4af7-ab5a-bef11223f7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950526950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.950526950
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3262502999
Short name T5
Test name
Test status
Simulation time 68339144 ps
CPU time 1.55 seconds
Started Jul 16 06:31:47 PM PDT 24
Finished Jul 16 06:31:50 PM PDT 24
Peak memory 216888 kb
Host smart-e460b72a-ee9c-423d-843c-991847d9e745
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262502999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3262502999
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1707111784
Short name T659
Test name
Test status
Simulation time 106682102 ps
CPU time 1.75 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:31:46 PM PDT 24
Peak memory 218184 kb
Host smart-fe8fa761-c82f-4ad5-bd4d-9d612c519b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707111784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1707111784
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2614069790
Short name T311
Test name
Test status
Simulation time 391153208 ps
CPU time 8.48 seconds
Started Jul 16 06:31:48 PM PDT 24
Finished Jul 16 06:31:57 PM PDT 24
Peak memory 225828 kb
Host smart-b2782e95-e932-4737-a458-184e53eb13f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614069790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2614069790
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1452874547
Short name T251
Test name
Test status
Simulation time 692008542 ps
CPU time 14.88 seconds
Started Jul 16 06:31:42 PM PDT 24
Finished Jul 16 06:31:57 PM PDT 24
Peak memory 218148 kb
Host smart-a1d6f9e8-c8bc-4561-afe2-6d27d1f47b77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452874547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1452874547
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.4024014249
Short name T576
Test name
Test status
Simulation time 1309544597 ps
CPU time 10.01 seconds
Started Jul 16 06:31:45 PM PDT 24
Finished Jul 16 06:31:56 PM PDT 24
Peak memory 218340 kb
Host smart-bd1141c5-12ee-4c15-84f1-c6990f8db5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024014249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4024014249
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.935318452
Short name T604
Test name
Test status
Simulation time 44508163 ps
CPU time 1.58 seconds
Started Jul 16 06:31:30 PM PDT 24
Finished Jul 16 06:31:33 PM PDT 24
Peak memory 217652 kb
Host smart-c6286cce-c7fc-4eea-a753-5a1c7f7e2d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935318452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.935318452
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1322565410
Short name T231
Test name
Test status
Simulation time 227930679 ps
CPU time 24.03 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:32:09 PM PDT 24
Peak memory 250892 kb
Host smart-34ddc08b-1f2c-4773-9fb0-8bfb43c731a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322565410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1322565410
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1107497423
Short name T224
Test name
Test status
Simulation time 240977433 ps
CPU time 7.75 seconds
Started Jul 16 06:31:48 PM PDT 24
Finished Jul 16 06:31:56 PM PDT 24
Peak memory 250912 kb
Host smart-b852bce4-6d88-4787-b01f-985cdf40b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107497423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1107497423
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1823615915
Short name T828
Test name
Test status
Simulation time 7951148752 ps
CPU time 166.44 seconds
Started Jul 16 06:31:44 PM PDT 24
Finished Jul 16 06:34:32 PM PDT 24
Peak memory 325396 kb
Host smart-70ca6c8e-47db-4286-bd16-d3f6bfb711d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823615915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1823615915
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.799184161
Short name T406
Test name
Test status
Simulation time 131776327 ps
CPU time 0.86 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:31:46 PM PDT 24
Peak memory 211836 kb
Host smart-1ed5efee-8128-40a5-b05d-7fdd46aba43b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799184161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.799184161
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3272342519
Short name T728
Test name
Test status
Simulation time 26567421 ps
CPU time 1.28 seconds
Started Jul 16 06:31:48 PM PDT 24
Finished Jul 16 06:31:50 PM PDT 24
Peak memory 208872 kb
Host smart-fb7009a7-4601-4b91-8b65-321b7f033858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272342519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3272342519
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1322040758
Short name T713
Test name
Test status
Simulation time 320270259 ps
CPU time 11.64 seconds
Started Jul 16 06:31:45 PM PDT 24
Finished Jul 16 06:31:58 PM PDT 24
Peak memory 218152 kb
Host smart-b27d27a2-465c-49d0-a569-2aa6628a9c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322040758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1322040758
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1248130749
Short name T507
Test name
Test status
Simulation time 5842267405 ps
CPU time 8.32 seconds
Started Jul 16 06:31:41 PM PDT 24
Finished Jul 16 06:31:50 PM PDT 24
Peak memory 217684 kb
Host smart-16ab0a01-9a50-49fa-814e-5a94305316a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248130749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1248130749
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1862651425
Short name T524
Test name
Test status
Simulation time 149846356 ps
CPU time 1.59 seconds
Started Jul 16 06:31:44 PM PDT 24
Finished Jul 16 06:31:47 PM PDT 24
Peak memory 218180 kb
Host smart-8db36bbc-dcf3-4c22-a378-2488fb86c1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862651425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1862651425
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.4047687657
Short name T763
Test name
Test status
Simulation time 1431180271 ps
CPU time 12.68 seconds
Started Jul 16 06:31:44 PM PDT 24
Finished Jul 16 06:31:59 PM PDT 24
Peak memory 218740 kb
Host smart-a4b6c9a9-d2e4-4c21-9b2b-5d91c6196094
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047687657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.4047687657
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3732808852
Short name T449
Test name
Test status
Simulation time 1474224799 ps
CPU time 8.39 seconds
Started Jul 16 06:31:48 PM PDT 24
Finished Jul 16 06:31:57 PM PDT 24
Peak memory 225816 kb
Host smart-e3517a52-c0cc-41ed-9349-5a7679ca3aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732808852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3732808852
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1258942602
Short name T288
Test name
Test status
Simulation time 445028214 ps
CPU time 9.13 seconds
Started Jul 16 06:31:42 PM PDT 24
Finished Jul 16 06:31:52 PM PDT 24
Peak memory 218084 kb
Host smart-ad9f667b-c87a-4825-8cb5-0e3019ed1ee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258942602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1258942602
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3594854422
Short name T51
Test name
Test status
Simulation time 414993522 ps
CPU time 8.69 seconds
Started Jul 16 06:31:45 PM PDT 24
Finished Jul 16 06:31:55 PM PDT 24
Peak memory 225904 kb
Host smart-66c17b2a-0af7-4002-882d-0800af23a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594854422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3594854422
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1896032941
Short name T582
Test name
Test status
Simulation time 20141641 ps
CPU time 1.44 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:31:45 PM PDT 24
Peak memory 213768 kb
Host smart-3d44388e-773b-4e7f-9bc9-159d477fe9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896032941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1896032941
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.548849357
Short name T709
Test name
Test status
Simulation time 5192295335 ps
CPU time 34.16 seconds
Started Jul 16 06:31:45 PM PDT 24
Finished Jul 16 06:32:20 PM PDT 24
Peak memory 247104 kb
Host smart-95fbd7d3-3fce-4d2b-bc3c-efffdb716c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548849357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.548849357
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.945369948
Short name T101
Test name
Test status
Simulation time 67546970 ps
CPU time 7.71 seconds
Started Jul 16 06:31:46 PM PDT 24
Finished Jul 16 06:31:55 PM PDT 24
Peak memory 250844 kb
Host smart-3ac14520-ba2b-4daf-87b6-eb56df78b358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945369948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.945369948
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2991475476
Short name T452
Test name
Test status
Simulation time 8319999628 ps
CPU time 166.33 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:34:31 PM PDT 24
Peak memory 267444 kb
Host smart-c3185985-9851-4507-a34b-c6b32dbea078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991475476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2991475476
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2230187152
Short name T296
Test name
Test status
Simulation time 14191289 ps
CPU time 1.13 seconds
Started Jul 16 06:31:44 PM PDT 24
Finished Jul 16 06:31:46 PM PDT 24
Peak memory 213104 kb
Host smart-ae9bf2d0-bd4d-40ad-b367-8c4b457a75c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230187152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2230187152
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1441159779
Short name T592
Test name
Test status
Simulation time 55845501 ps
CPU time 0.94 seconds
Started Jul 16 06:28:18 PM PDT 24
Finished Jul 16 06:28:20 PM PDT 24
Peak memory 208836 kb
Host smart-c183f2c5-4501-49c7-8ce4-43dd6e29f278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441159779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1441159779
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3802099205
Short name T666
Test name
Test status
Simulation time 229820459 ps
CPU time 8.71 seconds
Started Jul 16 06:28:08 PM PDT 24
Finished Jul 16 06:28:18 PM PDT 24
Peak memory 225988 kb
Host smart-7ac69c0e-88b8-4176-9e82-390518ec446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802099205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3802099205
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1363375861
Short name T367
Test name
Test status
Simulation time 440209545 ps
CPU time 6.54 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:15 PM PDT 24
Peak memory 216984 kb
Host smart-89b5eefe-81dc-4415-9047-9cd632037a7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363375861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1363375861
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1566313022
Short name T238
Test name
Test status
Simulation time 3460805475 ps
CPU time 33.48 seconds
Started Jul 16 06:28:09 PM PDT 24
Finished Jul 16 06:28:43 PM PDT 24
Peak memory 218796 kb
Host smart-e044be13-8f88-4e2d-8712-62c1690049a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566313022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1566313022
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.380620300
Short name T585
Test name
Test status
Simulation time 2008728522 ps
CPU time 9.44 seconds
Started Jul 16 06:28:16 PM PDT 24
Finished Jul 16 06:28:26 PM PDT 24
Peak memory 217660 kb
Host smart-9957434a-50fa-4c59-a620-1f71cb81d5a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380620300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.380620300
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4236075252
Short name T646
Test name
Test status
Simulation time 499329276 ps
CPU time 9.81 seconds
Started Jul 16 06:28:06 PM PDT 24
Finished Jul 16 06:28:17 PM PDT 24
Peak memory 218144 kb
Host smart-e1a4664f-c699-4d52-8ac0-aa21e264733d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236075252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4236075252
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.620694725
Short name T66
Test name
Test status
Simulation time 2863084566 ps
CPU time 20.45 seconds
Started Jul 16 06:28:18 PM PDT 24
Finished Jul 16 06:28:39 PM PDT 24
Peak memory 217640 kb
Host smart-5c7030ca-0d4d-4ad5-802d-9436e4767737
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620694725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.620694725
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3572145924
Short name T384
Test name
Test status
Simulation time 2578510349 ps
CPU time 8.73 seconds
Started Jul 16 06:28:09 PM PDT 24
Finished Jul 16 06:28:18 PM PDT 24
Peak memory 217648 kb
Host smart-84887dce-fd7e-46c8-b617-bd58fa687639
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572145924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3572145924
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3919585343
Short name T418
Test name
Test status
Simulation time 5451352574 ps
CPU time 52.51 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:29:01 PM PDT 24
Peak memory 283652 kb
Host smart-1214209f-a890-45ad-99ff-ec492df7620f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919585343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3919585343
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.50310230
Short name T279
Test name
Test status
Simulation time 466620379 ps
CPU time 10.93 seconds
Started Jul 16 06:28:08 PM PDT 24
Finished Jul 16 06:28:20 PM PDT 24
Peak memory 246512 kb
Host smart-882494ca-dd50-471e-a8c9-1a0110dbefcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50310230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt
ag_state_post_trans.50310230
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1167772131
Short name T313
Test name
Test status
Simulation time 61518104 ps
CPU time 3.55 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:12 PM PDT 24
Peak memory 218108 kb
Host smart-85c0ce22-aee9-44af-acba-7ecf3f2bbdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167772131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1167772131
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3106134498
Short name T513
Test name
Test status
Simulation time 1411889838 ps
CPU time 9.91 seconds
Started Jul 16 06:28:10 PM PDT 24
Finished Jul 16 06:28:20 PM PDT 24
Peak memory 217612 kb
Host smart-e59047a8-ef4b-4e1e-a939-774d595a3f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106134498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3106134498
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1184940321
Short name T52
Test name
Test status
Simulation time 831279740 ps
CPU time 25.02 seconds
Started Jul 16 06:28:18 PM PDT 24
Finished Jul 16 06:28:45 PM PDT 24
Peak memory 267516 kb
Host smart-e78e499a-4cd2-41ef-872d-413970741c0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184940321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1184940321
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2083520575
Short name T100
Test name
Test status
Simulation time 2349019055 ps
CPU time 13.4 seconds
Started Jul 16 06:28:18 PM PDT 24
Finished Jul 16 06:28:33 PM PDT 24
Peak memory 226112 kb
Host smart-a2dd9c21-625a-4cb4-95f8-7bbbc11d02e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083520575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2083520575
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1076145230
Short name T549
Test name
Test status
Simulation time 719303910 ps
CPU time 8.89 seconds
Started Jul 16 06:28:17 PM PDT 24
Finished Jul 16 06:28:28 PM PDT 24
Peak memory 225832 kb
Host smart-e2250003-9748-471c-9e63-90de75877824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076145230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1076145230
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.490209409
Short name T656
Test name
Test status
Simulation time 171804125 ps
CPU time 7.69 seconds
Started Jul 16 06:28:18 PM PDT 24
Finished Jul 16 06:28:27 PM PDT 24
Peak memory 225912 kb
Host smart-7345688c-f9cb-4101-86e4-f2cace0e8aaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490209409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.490209409
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2275750238
Short name T466
Test name
Test status
Simulation time 458410602 ps
CPU time 7.12 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:15 PM PDT 24
Peak memory 224644 kb
Host smart-774421a6-6569-46e7-84c0-ef15e2821ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275750238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2275750238
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3404813995
Short name T209
Test name
Test status
Simulation time 27690800 ps
CPU time 1.16 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:09 PM PDT 24
Peak memory 213548 kb
Host smart-b1541d10-a850-4365-89b0-a0420ef1b2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404813995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3404813995
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3417664837
Short name T237
Test name
Test status
Simulation time 983990347 ps
CPU time 28.06 seconds
Started Jul 16 06:28:08 PM PDT 24
Finished Jul 16 06:28:37 PM PDT 24
Peak memory 245428 kb
Host smart-adf007e6-86ef-40e9-b688-f54b4e2d66e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417664837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3417664837
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2271135876
Short name T320
Test name
Test status
Simulation time 217947336 ps
CPU time 6.41 seconds
Started Jul 16 06:28:07 PM PDT 24
Finished Jul 16 06:28:14 PM PDT 24
Peak memory 246448 kb
Host smart-92ac7bba-7fd8-4c50-bab3-a7b8b26c5ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271135876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2271135876
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.590629246
Short name T369
Test name
Test status
Simulation time 1103728166 ps
CPU time 19.55 seconds
Started Jul 16 06:28:17 PM PDT 24
Finished Jul 16 06:28:37 PM PDT 24
Peak memory 226020 kb
Host smart-83eb7670-5e74-4338-a3bd-81b906383e0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590629246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.590629246
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3147062859
Short name T181
Test name
Test status
Simulation time 15205361449 ps
CPU time 494.73 seconds
Started Jul 16 06:28:20 PM PDT 24
Finished Jul 16 06:36:36 PM PDT 24
Peak memory 422128 kb
Host smart-bf16b27e-46d0-4462-a2e6-a49131989ef8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3147062859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3147062859
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.298854604
Short name T345
Test name
Test status
Simulation time 25401687 ps
CPU time 0.9 seconds
Started Jul 16 06:28:08 PM PDT 24
Finished Jul 16 06:28:10 PM PDT 24
Peak memory 211652 kb
Host smart-1e435f1e-5c14-42df-b53d-bf0170a4b3ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298854604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.298854604
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4282621852
Short name T496
Test name
Test status
Simulation time 1217703639 ps
CPU time 17.48 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:32:02 PM PDT 24
Peak memory 218232 kb
Host smart-e8124a4f-3a72-4c07-81fc-29dcb505ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282621852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4282621852
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2867523777
Short name T735
Test name
Test status
Simulation time 968738697 ps
CPU time 16.92 seconds
Started Jul 16 06:31:42 PM PDT 24
Finished Jul 16 06:32:00 PM PDT 24
Peak memory 217236 kb
Host smart-563359c9-c48b-4268-9521-fbc74e893f76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867523777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2867523777
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3792989686
Short name T344
Test name
Test status
Simulation time 134454192 ps
CPU time 2.35 seconds
Started Jul 16 06:31:44 PM PDT 24
Finished Jul 16 06:31:48 PM PDT 24
Peak memory 222184 kb
Host smart-0fd51eac-5aae-4a32-b8e6-479a62cc6c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792989686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3792989686
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.604478944
Short name T353
Test name
Test status
Simulation time 367146480 ps
CPU time 11.03 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:31:56 PM PDT 24
Peak memory 218884 kb
Host smart-bc08ef29-f897-4e18-86f0-2febabf75d1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604478944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.604478944
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2885157821
Short name T785
Test name
Test status
Simulation time 1310931054 ps
CPU time 13.31 seconds
Started Jul 16 06:31:53 PM PDT 24
Finished Jul 16 06:32:07 PM PDT 24
Peak memory 225904 kb
Host smart-bc0d60d4-bfed-48fe-9214-571e71a0bd2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885157821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2885157821
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4275209539
Short name T422
Test name
Test status
Simulation time 630480437 ps
CPU time 8.26 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:32:06 PM PDT 24
Peak memory 225952 kb
Host smart-2aa85b1a-68e8-4d1d-becc-da27f73ceb3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275209539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4275209539
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.669206017
Short name T798
Test name
Test status
Simulation time 445049289 ps
CPU time 7.14 seconds
Started Jul 16 06:31:45 PM PDT 24
Finished Jul 16 06:31:54 PM PDT 24
Peak memory 218264 kb
Host smart-978c196d-1503-4c5e-9bce-568466245bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669206017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.669206017
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.782246928
Short name T252
Test name
Test status
Simulation time 60300733 ps
CPU time 1.51 seconds
Started Jul 16 06:31:44 PM PDT 24
Finished Jul 16 06:31:47 PM PDT 24
Peak memory 213828 kb
Host smart-3d3c567c-f73e-4f95-a666-db53a25c66f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782246928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.782246928
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2736198098
Short name T314
Test name
Test status
Simulation time 757102802 ps
CPU time 26.41 seconds
Started Jul 16 06:31:43 PM PDT 24
Finished Jul 16 06:32:10 PM PDT 24
Peak memory 250984 kb
Host smart-8bf32459-10ed-4f68-bf20-387c48969fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736198098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2736198098
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3314482475
Short name T686
Test name
Test status
Simulation time 52067009 ps
CPU time 2.86 seconds
Started Jul 16 06:31:47 PM PDT 24
Finished Jul 16 06:31:51 PM PDT 24
Peak memory 217440 kb
Host smart-59a58b81-db2f-4a48-ab13-09cb0a31da09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314482475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3314482475
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2514536008
Short name T547
Test name
Test status
Simulation time 5454053418 ps
CPU time 35.37 seconds
Started Jul 16 06:31:54 PM PDT 24
Finished Jul 16 06:32:30 PM PDT 24
Peak memory 226088 kb
Host smart-bda9b01f-55ac-4aec-857e-ca0ee009229a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514536008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2514536008
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1909605514
Short name T706
Test name
Test status
Simulation time 25446027 ps
CPU time 0.85 seconds
Started Jul 16 06:31:44 PM PDT 24
Finished Jul 16 06:31:47 PM PDT 24
Peak memory 211700 kb
Host smart-cbc7922d-c928-41fb-98f8-56cc839040c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909605514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1909605514
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.4025755822
Short name T572
Test name
Test status
Simulation time 18290109 ps
CPU time 0.99 seconds
Started Jul 16 06:31:57 PM PDT 24
Finished Jul 16 06:31:59 PM PDT 24
Peak memory 208756 kb
Host smart-9cec596f-fa3f-4f05-90ca-ffe18dde3a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025755822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.4025755822
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.4154665433
Short name T423
Test name
Test status
Simulation time 1210326764 ps
CPU time 15.09 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:32:13 PM PDT 24
Peak memory 218240 kb
Host smart-eb529053-8988-45cf-88cd-5be5d9486994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154665433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4154665433
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3381464295
Short name T27
Test name
Test status
Simulation time 170137693 ps
CPU time 3.79 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:32:02 PM PDT 24
Peak memory 217008 kb
Host smart-21fb047a-0288-43cf-a849-91c06fb02cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381464295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3381464295
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3879340851
Short name T727
Test name
Test status
Simulation time 144377848 ps
CPU time 2.92 seconds
Started Jul 16 06:31:54 PM PDT 24
Finished Jul 16 06:31:57 PM PDT 24
Peak memory 218160 kb
Host smart-0569ab29-6e9c-4195-ab9a-2c20a84fd0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879340851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3879340851
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.569842576
Short name T800
Test name
Test status
Simulation time 591166697 ps
CPU time 13.08 seconds
Started Jul 16 06:31:54 PM PDT 24
Finished Jul 16 06:32:08 PM PDT 24
Peak memory 225944 kb
Host smart-44ad59b2-6198-44e9-9a61-715f3434d857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569842576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.569842576
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2812220690
Short name T514
Test name
Test status
Simulation time 214296878 ps
CPU time 7.83 seconds
Started Jul 16 06:31:57 PM PDT 24
Finished Jul 16 06:32:06 PM PDT 24
Peak memory 225936 kb
Host smart-4081c437-89c2-4e9c-b7aa-a21ce7e710b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812220690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2812220690
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1171266781
Short name T387
Test name
Test status
Simulation time 1094007098 ps
CPU time 8.73 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:32:05 PM PDT 24
Peak memory 218160 kb
Host smart-7a697528-004c-4add-a8bd-1e3bada98a32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171266781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1171266781
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2592659922
Short name T596
Test name
Test status
Simulation time 414412451 ps
CPU time 9.59 seconds
Started Jul 16 06:31:54 PM PDT 24
Finished Jul 16 06:32:05 PM PDT 24
Peak memory 218240 kb
Host smart-98d53ce3-4307-4e7c-bec0-29eb744932d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592659922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2592659922
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2583131393
Short name T489
Test name
Test status
Simulation time 34237539 ps
CPU time 2.79 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:31:59 PM PDT 24
Peak memory 214700 kb
Host smart-f080b5a5-1d3f-4089-9121-0ee3eff7e96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583131393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2583131393
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.827973635
Short name T391
Test name
Test status
Simulation time 331618134 ps
CPU time 35.59 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:32:33 PM PDT 24
Peak memory 250984 kb
Host smart-3c33fbe1-21e2-464e-9c87-9e38f31dad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827973635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.827973635
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3775269475
Short name T655
Test name
Test status
Simulation time 53814953 ps
CPU time 3.07 seconds
Started Jul 16 06:31:54 PM PDT 24
Finished Jul 16 06:31:59 PM PDT 24
Peak memory 222228 kb
Host smart-6b2b3789-0584-4092-9899-d51d3f82906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775269475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3775269475
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.106792324
Short name T598
Test name
Test status
Simulation time 20464457599 ps
CPU time 780.5 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:44:57 PM PDT 24
Peak memory 268096 kb
Host smart-944c4606-9dac-423f-a9b7-229f49847812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106792324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.106792324
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3489869030
Short name T680
Test name
Test status
Simulation time 2640872549 ps
CPU time 79.42 seconds
Started Jul 16 06:32:01 PM PDT 24
Finished Jul 16 06:33:21 PM PDT 24
Peak memory 271708 kb
Host smart-c8122cd5-5f29-435f-9061-bab0ec956970
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3489869030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3489869030
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.172822121
Short name T167
Test name
Test status
Simulation time 14525506 ps
CPU time 0.87 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:31:59 PM PDT 24
Peak memory 212836 kb
Host smart-068b5edf-b0dc-4de1-a17b-778d4795dbf7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172822121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.172822121
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3653029413
Short name T597
Test name
Test status
Simulation time 30632657 ps
CPU time 1.39 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:31:58 PM PDT 24
Peak memory 208892 kb
Host smart-de3410c8-0974-4db2-8b27-c813a6d99225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653029413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3653029413
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1520388466
Short name T563
Test name
Test status
Simulation time 563726210 ps
CPU time 11.59 seconds
Started Jul 16 06:31:54 PM PDT 24
Finished Jul 16 06:32:07 PM PDT 24
Peak memory 218172 kb
Host smart-12caa659-408c-476b-a26a-28e092955eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520388466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1520388466
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4081093069
Short name T812
Test name
Test status
Simulation time 263565187 ps
CPU time 3.72 seconds
Started Jul 16 06:31:54 PM PDT 24
Finished Jul 16 06:31:58 PM PDT 24
Peak memory 217120 kb
Host smart-40b85083-3a28-4a0c-937e-2de7c860843b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081093069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4081093069
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2288490960
Short name T86
Test name
Test status
Simulation time 77699430 ps
CPU time 1.57 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:31:58 PM PDT 24
Peak memory 221576 kb
Host smart-3b11078f-41a2-4385-89e1-2f38d43ff0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288490960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2288490960
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3985646769
Short name T679
Test name
Test status
Simulation time 826276657 ps
CPU time 14.37 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:32:11 PM PDT 24
Peak memory 226004 kb
Host smart-57e5f600-f7de-434a-a048-a50087c88113
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985646769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3985646769
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3118937737
Short name T250
Test name
Test status
Simulation time 1392043424 ps
CPU time 10.98 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:32:09 PM PDT 24
Peak memory 225892 kb
Host smart-627a901c-9447-4d17-b7e5-428a0ac90f53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118937737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3118937737
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.366892019
Short name T561
Test name
Test status
Simulation time 207340355 ps
CPU time 8.62 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:32:06 PM PDT 24
Peak memory 218112 kb
Host smart-7b000ecf-ee91-4254-b485-2105a0f61b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366892019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.366892019
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2395109376
Short name T589
Test name
Test status
Simulation time 1051966911 ps
CPU time 10.9 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:32:07 PM PDT 24
Peak memory 225180 kb
Host smart-2c76d1eb-e44d-4e5c-b61e-d88590a3ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395109376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2395109376
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.254628986
Short name T632
Test name
Test status
Simulation time 87478710 ps
CPU time 1.33 seconds
Started Jul 16 06:32:02 PM PDT 24
Finished Jul 16 06:32:05 PM PDT 24
Peak memory 213564 kb
Host smart-54c981f6-b93e-4cb0-8eb1-de2ec35bec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254628986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.254628986
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4088696460
Short name T506
Test name
Test status
Simulation time 678758608 ps
CPU time 19.29 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:32:17 PM PDT 24
Peak memory 250952 kb
Host smart-afd01f44-3a26-4be2-a3b0-aae1828e27a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088696460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4088696460
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3840547712
Short name T467
Test name
Test status
Simulation time 75554860 ps
CPU time 6.84 seconds
Started Jul 16 06:32:01 PM PDT 24
Finished Jul 16 06:32:08 PM PDT 24
Peak memory 247412 kb
Host smart-2f9a82cc-7a5b-4bfe-9a53-90272e08cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840547712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3840547712
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.963520483
Short name T172
Test name
Test status
Simulation time 2103968855 ps
CPU time 63.09 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:32:59 PM PDT 24
Peak memory 275568 kb
Host smart-b7a7f9f8-0109-47ba-a661-8842275519a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963520483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.963520483
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.788853671
Short name T574
Test name
Test status
Simulation time 39553796 ps
CPU time 0.97 seconds
Started Jul 16 06:32:04 PM PDT 24
Finished Jul 16 06:32:07 PM PDT 24
Peak memory 211900 kb
Host smart-0fd1add6-66b4-4d0d-926f-76c60c33a3e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788853671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.788853671
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3422214404
Short name T274
Test name
Test status
Simulation time 73243297 ps
CPU time 1.18 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:12 PM PDT 24
Peak memory 208856 kb
Host smart-b9cd65e1-e5a3-415a-bc3a-b76d46b899bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422214404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3422214404
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2348954399
Short name T824
Test name
Test status
Simulation time 1190481504 ps
CPU time 19.07 seconds
Started Jul 16 06:32:04 PM PDT 24
Finished Jul 16 06:32:24 PM PDT 24
Peak memory 218216 kb
Host smart-7aac2dbe-4180-4d96-96f5-6f8d80a6ce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348954399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2348954399
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2991526730
Short name T786
Test name
Test status
Simulation time 411458469 ps
CPU time 1.6 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:31:58 PM PDT 24
Peak memory 217072 kb
Host smart-d0504c5f-213e-40a6-8469-2c2655687f46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991526730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2991526730
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2095156824
Short name T242
Test name
Test status
Simulation time 40885569 ps
CPU time 1.98 seconds
Started Jul 16 06:31:56 PM PDT 24
Finished Jul 16 06:32:00 PM PDT 24
Peak memory 218128 kb
Host smart-1337868a-3ce3-44c4-8e6d-12f306ad657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095156824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2095156824
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.8102325
Short name T325
Test name
Test status
Simulation time 579375759 ps
CPU time 12.91 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:23 PM PDT 24
Peak memory 225952 kb
Host smart-6a563254-1277-4010-b0a8-7dbb298e56d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8102325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_dige
st.8102325
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3264477029
Short name T720
Test name
Test status
Simulation time 289632078 ps
CPU time 10.41 seconds
Started Jul 16 06:32:09 PM PDT 24
Finished Jul 16 06:32:22 PM PDT 24
Peak memory 218068 kb
Host smart-6629581d-33e9-4eb9-aa97-f290a747b90d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264477029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3264477029
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.703071887
Short name T719
Test name
Test status
Simulation time 343569182 ps
CPU time 12.12 seconds
Started Jul 16 06:32:02 PM PDT 24
Finished Jul 16 06:32:15 PM PDT 24
Peak memory 218276 kb
Host smart-4eb8fc2c-a876-4cfa-a628-5e4a4be6d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703071887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.703071887
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.792587334
Short name T689
Test name
Test status
Simulation time 41575660 ps
CPU time 2.06 seconds
Started Jul 16 06:32:04 PM PDT 24
Finished Jul 16 06:32:08 PM PDT 24
Peak memory 217644 kb
Host smart-1a64c47d-21d4-4ef4-9ad8-8908852b333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792587334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.792587334
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2201485148
Short name T857
Test name
Test status
Simulation time 1212986648 ps
CPU time 33.33 seconds
Started Jul 16 06:31:58 PM PDT 24
Finished Jul 16 06:32:32 PM PDT 24
Peak memory 250940 kb
Host smart-7909ab22-4086-43d5-a689-3b2f79ae9abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201485148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2201485148
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.431502986
Short name T444
Test name
Test status
Simulation time 96498264 ps
CPU time 8.68 seconds
Started Jul 16 06:31:57 PM PDT 24
Finished Jul 16 06:32:07 PM PDT 24
Peak memory 250728 kb
Host smart-7676a6fa-0618-46d2-bac0-4e78faff6b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431502986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.431502986
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2109441958
Short name T81
Test name
Test status
Simulation time 24183319541 ps
CPU time 349.51 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:37:58 PM PDT 24
Peak memory 250920 kb
Host smart-418f8bc7-38d6-4ca6-aa10-5a4816b317f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109441958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2109441958
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1064392465
Short name T106
Test name
Test status
Simulation time 34015979568 ps
CPU time 562.84 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:41:33 PM PDT 24
Peak memory 283916 kb
Host smart-c760a69c-3ec6-41b3-8ee0-f68128158117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1064392465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1064392465
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2550995515
Short name T813
Test name
Test status
Simulation time 43737158 ps
CPU time 0.99 seconds
Started Jul 16 06:31:55 PM PDT 24
Finished Jul 16 06:31:58 PM PDT 24
Peak memory 211760 kb
Host smart-45f43c0c-2edc-4af8-b52c-ef88db5790e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550995515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2550995515
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1328432673
Short name T295
Test name
Test status
Simulation time 23680425 ps
CPU time 1.31 seconds
Started Jul 16 06:32:09 PM PDT 24
Finished Jul 16 06:32:13 PM PDT 24
Peak memory 208912 kb
Host smart-843d1ce9-6a29-4b8c-b61e-2d512ca08270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328432673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1328432673
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2294660276
Short name T789
Test name
Test status
Simulation time 885845078 ps
CPU time 16.9 seconds
Started Jul 16 06:32:09 PM PDT 24
Finished Jul 16 06:32:28 PM PDT 24
Peak memory 226036 kb
Host smart-cb2dd9f8-f857-4587-87e7-616bcc5997a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294660276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2294660276
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1550550014
Short name T836
Test name
Test status
Simulation time 1697777880 ps
CPU time 8.15 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:17 PM PDT 24
Peak memory 217296 kb
Host smart-8233a0e9-ef3f-42ad-ba79-31cf353406d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550550014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1550550014
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1267443655
Short name T445
Test name
Test status
Simulation time 37746106 ps
CPU time 1.62 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:12 PM PDT 24
Peak memory 218068 kb
Host smart-08ae7692-ff26-4bdd-91d1-e20de3ce830a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267443655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1267443655
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.894574489
Short name T460
Test name
Test status
Simulation time 407377565 ps
CPU time 12.24 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:23 PM PDT 24
Peak memory 225976 kb
Host smart-0ed096ff-be11-48b9-bedc-4c4c47ebde99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894574489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.894574489
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2460497139
Short name T357
Test name
Test status
Simulation time 1093296962 ps
CPU time 13.93 seconds
Started Jul 16 06:32:07 PM PDT 24
Finished Jul 16 06:32:23 PM PDT 24
Peak memory 225848 kb
Host smart-4c668ada-de28-4b76-863d-d69edd3f8a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460497139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2460497139
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4189188231
Short name T63
Test name
Test status
Simulation time 904406710 ps
CPU time 9.12 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:18 PM PDT 24
Peak memory 218120 kb
Host smart-15353a6e-1bbb-4848-90ee-d7232edf4495
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189188231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4189188231
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2480594774
Short name T219
Test name
Test status
Simulation time 378202346 ps
CPU time 14.18 seconds
Started Jul 16 06:32:09 PM PDT 24
Finished Jul 16 06:32:26 PM PDT 24
Peak memory 225956 kb
Host smart-20faa3ea-a5d4-4fff-8769-269ce846ca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480594774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2480594774
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.817148423
Short name T791
Test name
Test status
Simulation time 90377404 ps
CPU time 3.11 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:12 PM PDT 24
Peak memory 223404 kb
Host smart-5c2b53fb-0af8-4daa-a624-4e89e2c0630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817148423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.817148423
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.764800863
Short name T697
Test name
Test status
Simulation time 874698032 ps
CPU time 24.69 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:33 PM PDT 24
Peak memory 250996 kb
Host smart-a8cda0fa-f3cd-4174-b472-7b3dd9f3b32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764800863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.764800863
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1440839137
Short name T468
Test name
Test status
Simulation time 130758479 ps
CPU time 3.14 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:14 PM PDT 24
Peak memory 222568 kb
Host smart-a8e507a7-3a5c-461e-afa7-34aa1c1f1ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440839137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1440839137
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.549162496
Short name T340
Test name
Test status
Simulation time 3040802588 ps
CPU time 75.33 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:33:26 PM PDT 24
Peak memory 275876 kb
Host smart-5957e725-1db4-4e15-9957-795c7b0ecf21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549162496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.549162496
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1263840829
Short name T211
Test name
Test status
Simulation time 16502753 ps
CPU time 0.92 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:09 PM PDT 24
Peak memory 212828 kb
Host smart-834a6865-7761-401a-8318-feee53831b4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263840829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1263840829
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.514369947
Short name T316
Test name
Test status
Simulation time 64238185 ps
CPU time 1.5 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:12 PM PDT 24
Peak memory 209020 kb
Host smart-cc72e4c3-db39-4abd-b7da-b574aa96159b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514369947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.514369947
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.215566021
Short name T754
Test name
Test status
Simulation time 487482147 ps
CPU time 11.93 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:23 PM PDT 24
Peak memory 218224 kb
Host smart-021c726c-df27-4c30-b07a-2a1221743ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215566021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.215566021
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3790954680
Short name T731
Test name
Test status
Simulation time 337117521 ps
CPU time 2.33 seconds
Started Jul 16 06:32:07 PM PDT 24
Finished Jul 16 06:32:13 PM PDT 24
Peak memory 217000 kb
Host smart-a4e6aa2a-da23-4ee8-9785-1385e6c374ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790954680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3790954680
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3178475147
Short name T394
Test name
Test status
Simulation time 367723150 ps
CPU time 1.9 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:10 PM PDT 24
Peak memory 218204 kb
Host smart-be2ae4ae-cdd1-4c5a-9093-3a9810759fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178475147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3178475147
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2766725921
Short name T849
Test name
Test status
Simulation time 1453061864 ps
CPU time 11.44 seconds
Started Jul 16 06:32:10 PM PDT 24
Finished Jul 16 06:32:24 PM PDT 24
Peak memory 226016 kb
Host smart-c2e194bf-f5dc-4029-91de-1ce065297804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766725921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2766725921
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3742507721
Short name T525
Test name
Test status
Simulation time 297482772 ps
CPU time 11.71 seconds
Started Jul 16 06:32:09 PM PDT 24
Finished Jul 16 06:32:24 PM PDT 24
Peak memory 225892 kb
Host smart-7309034c-2188-48a4-8bbb-79f77eec8b04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742507721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3742507721
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2411513923
Short name T816
Test name
Test status
Simulation time 1267214260 ps
CPU time 16.46 seconds
Started Jul 16 06:32:09 PM PDT 24
Finished Jul 16 06:32:28 PM PDT 24
Peak memory 218128 kb
Host smart-9ce76c06-6f9d-45d9-8996-3ad0c8277048
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411513923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2411513923
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1174012564
Short name T860
Test name
Test status
Simulation time 269884102 ps
CPU time 12.22 seconds
Started Jul 16 06:32:07 PM PDT 24
Finished Jul 16 06:32:22 PM PDT 24
Peak memory 225984 kb
Host smart-56ac1721-7b0c-4905-a40a-f5db33f63728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174012564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1174012564
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2837679640
Short name T503
Test name
Test status
Simulation time 137468858 ps
CPU time 2.3 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:11 PM PDT 24
Peak memory 217656 kb
Host smart-e36c63b0-25a3-43e4-8c2c-2472c79cfeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837679640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2837679640
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2815469196
Short name T637
Test name
Test status
Simulation time 248187337 ps
CPU time 28.71 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:38 PM PDT 24
Peak memory 247844 kb
Host smart-2e781494-d9a5-4997-8e9e-0fa364ccb5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815469196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2815469196
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1514721274
Short name T848
Test name
Test status
Simulation time 129884759 ps
CPU time 6.75 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:18 PM PDT 24
Peak memory 250536 kb
Host smart-83f503ca-63b5-48a9-b2eb-ef6658923984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514721274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1514721274
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2623294793
Short name T548
Test name
Test status
Simulation time 5240741037 ps
CPU time 50.48 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:33:01 PM PDT 24
Peak memory 252704 kb
Host smart-5a65dd89-79ec-41ca-85b4-4276fc3a2e61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623294793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2623294793
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2001063816
Short name T112
Test name
Test status
Simulation time 129258978324 ps
CPU time 5109.15 seconds
Started Jul 16 06:32:10 PM PDT 24
Finished Jul 16 07:57:22 PM PDT 24
Peak memory 660728 kb
Host smart-c321915a-997f-491c-a55f-7f08d52331bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2001063816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2001063816
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1014774255
Short name T243
Test name
Test status
Simulation time 10953616 ps
CPU time 0.99 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:10 PM PDT 24
Peak memory 211876 kb
Host smart-90d83e75-4fd9-42c6-8bee-89c682d2d8e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014774255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1014774255
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1120935142
Short name T437
Test name
Test status
Simulation time 17434987 ps
CPU time 1.08 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:18 PM PDT 24
Peak memory 208912 kb
Host smart-d1b7e140-4b36-4c74-9cd9-20e332c363a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120935142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1120935142
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3776868124
Short name T270
Test name
Test status
Simulation time 1108697121 ps
CPU time 17.51 seconds
Started Jul 16 06:32:07 PM PDT 24
Finished Jul 16 06:32:27 PM PDT 24
Peak memory 226196 kb
Host smart-17c080ee-9a52-4f9f-b715-8720a0e5dccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776868124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3776868124
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.685218335
Short name T668
Test name
Test status
Simulation time 576348522 ps
CPU time 7.32 seconds
Started Jul 16 06:32:19 PM PDT 24
Finished Jul 16 06:32:27 PM PDT 24
Peak memory 217352 kb
Host smart-30f69a7a-db09-4ba5-987c-08d9b4318118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685218335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.685218335
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2480560441
Short name T276
Test name
Test status
Simulation time 722459732 ps
CPU time 5.43 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:16 PM PDT 24
Peak memory 218152 kb
Host smart-e6215458-8935-42ff-8c27-d09478631a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480560441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2480560441
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3528837012
Short name T777
Test name
Test status
Simulation time 510646221 ps
CPU time 10.71 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:28 PM PDT 24
Peak memory 218708 kb
Host smart-55cdb53e-119c-4804-98ae-11aa30ef84ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528837012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3528837012
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2640545957
Short name T11
Test name
Test status
Simulation time 1302068451 ps
CPU time 11.73 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:30 PM PDT 24
Peak memory 218044 kb
Host smart-2a4b291c-dfde-464e-9a76-def97c3161ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640545957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2640545957
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1308954166
Short name T493
Test name
Test status
Simulation time 567066643 ps
CPU time 7.38 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 06:32:27 PM PDT 24
Peak memory 218156 kb
Host smart-10a5e4c8-eb1a-4312-9984-17bfc859d4b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308954166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1308954166
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3615940785
Short name T542
Test name
Test status
Simulation time 1118694424 ps
CPU time 7.56 seconds
Started Jul 16 06:32:08 PM PDT 24
Finished Jul 16 06:32:18 PM PDT 24
Peak memory 218204 kb
Host smart-e8b2f717-27d6-4250-ad5e-57b232fb96f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615940785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3615940785
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1310672384
Short name T775
Test name
Test status
Simulation time 1272438960 ps
CPU time 3.97 seconds
Started Jul 16 06:32:07 PM PDT 24
Finished Jul 16 06:32:14 PM PDT 24
Peak memory 217652 kb
Host smart-0e8a474a-7379-4d28-a27a-09341833ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310672384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1310672384
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1297943836
Short name T392
Test name
Test status
Simulation time 387262000 ps
CPU time 20.86 seconds
Started Jul 16 06:32:09 PM PDT 24
Finished Jul 16 06:32:33 PM PDT 24
Peak memory 251020 kb
Host smart-24efcb51-1f10-4446-80d6-0f5898207e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297943836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1297943836
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.883610886
Short name T747
Test name
Test status
Simulation time 48947127 ps
CPU time 8.01 seconds
Started Jul 16 06:32:06 PM PDT 24
Finished Jul 16 06:32:17 PM PDT 24
Peak memory 250804 kb
Host smart-4bd0336e-f2aa-46b9-ad79-5a817a669c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883610886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.883610886
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2342640852
Short name T183
Test name
Test status
Simulation time 15449980222 ps
CPU time 129.92 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 06:34:30 PM PDT 24
Peak memory 247996 kb
Host smart-30358574-e314-4c13-9b0f-7162d5ef3662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342640852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2342640852
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4281290844
Short name T177
Test name
Test status
Simulation time 43824722 ps
CPU time 0.88 seconds
Started Jul 16 06:32:07 PM PDT 24
Finished Jul 16 06:32:10 PM PDT 24
Peak memory 217656 kb
Host smart-af2e847b-8a37-4ab4-bd25-d9bb5c99a7e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281290844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4281290844
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2273771195
Short name T73
Test name
Test status
Simulation time 14772612 ps
CPU time 1.04 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:18 PM PDT 24
Peak memory 208832 kb
Host smart-f55aeafd-d2a5-4c97-ad39-988fe9b8e355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273771195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2273771195
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1599471500
Short name T844
Test name
Test status
Simulation time 1074567387 ps
CPU time 12.09 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:30 PM PDT 24
Peak memory 218124 kb
Host smart-7c3529a5-5195-4731-b51b-296b49d19c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599471500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1599471500
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2738890255
Short name T169
Test name
Test status
Simulation time 5978895663 ps
CPU time 13.92 seconds
Started Jul 16 06:32:19 PM PDT 24
Finished Jul 16 06:32:35 PM PDT 24
Peak memory 217572 kb
Host smart-5b696404-0b72-421c-bb1d-15ae0fff068c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738890255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2738890255
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2386650212
Short name T566
Test name
Test status
Simulation time 31510970 ps
CPU time 1.44 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:19 PM PDT 24
Peak memory 218160 kb
Host smart-c4cb6838-db4c-477a-8291-4c19249e3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386650212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2386650212
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.546047839
Short name T769
Test name
Test status
Simulation time 1055907936 ps
CPU time 14.59 seconds
Started Jul 16 06:32:20 PM PDT 24
Finished Jul 16 06:32:36 PM PDT 24
Peak memory 225940 kb
Host smart-cda7915d-abf6-4c59-87e1-7ce3213888ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546047839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.546047839
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.649636447
Short name T650
Test name
Test status
Simulation time 1819100883 ps
CPU time 10.12 seconds
Started Jul 16 06:32:17 PM PDT 24
Finished Jul 16 06:32:29 PM PDT 24
Peak memory 225872 kb
Host smart-ed13b9a0-dd3a-4243-a389-377282664a5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649636447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.649636447
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2255327393
Short name T435
Test name
Test status
Simulation time 255001938 ps
CPU time 6.88 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 06:32:26 PM PDT 24
Peak memory 225944 kb
Host smart-ce22eb86-c6a3-4ffa-9862-5e8c5cffb52c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255327393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2255327393
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2281201178
Short name T739
Test name
Test status
Simulation time 198066773 ps
CPU time 1.99 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:19 PM PDT 24
Peak memory 214144 kb
Host smart-91848625-ede6-498d-aebc-b4b74c8c803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281201178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2281201178
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.423089085
Short name T89
Test name
Test status
Simulation time 665503588 ps
CPU time 31.61 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:48 PM PDT 24
Peak memory 250976 kb
Host smart-ff1ce795-9980-41c1-93dc-f5535b88b70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423089085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.423089085
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3312750249
Short name T166
Test name
Test status
Simulation time 475799212 ps
CPU time 7.77 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:26 PM PDT 24
Peak memory 246204 kb
Host smart-406b811e-10af-4907-a547-166dd2b2edb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312750249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3312750249
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4107149349
Short name T487
Test name
Test status
Simulation time 4454112840 ps
CPU time 119.7 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 06:34:19 PM PDT 24
Peak memory 268036 kb
Host smart-c94297fe-7ecc-495c-aed7-21047f7766fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107149349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4107149349
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1709941555
Short name T573
Test name
Test status
Simulation time 20094110 ps
CPU time 1.2 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:19 PM PDT 24
Peak memory 212864 kb
Host smart-d88c6fb8-490b-4126-a1e3-51483c248096
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709941555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1709941555
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1112675022
Short name T698
Test name
Test status
Simulation time 17863855 ps
CPU time 0.91 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:18 PM PDT 24
Peak memory 208752 kb
Host smart-6e115b87-e835-4661-8b67-9497cb86c9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112675022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1112675022
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3408660938
Short name T834
Test name
Test status
Simulation time 816334215 ps
CPU time 13.77 seconds
Started Jul 16 06:32:17 PM PDT 24
Finished Jul 16 06:32:32 PM PDT 24
Peak memory 218212 kb
Host smart-bd20eadf-bbf6-41d9-9f05-58e93035ff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408660938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3408660938
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.4277311981
Short name T415
Test name
Test status
Simulation time 807819023 ps
CPU time 9.82 seconds
Started Jul 16 06:32:20 PM PDT 24
Finished Jul 16 06:32:31 PM PDT 24
Peak memory 217248 kb
Host smart-ddfc9fab-b9de-46a8-9746-16ea940f4782
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277311981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4277311981
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3240955563
Short name T346
Test name
Test status
Simulation time 160783005 ps
CPU time 3.78 seconds
Started Jul 16 06:32:19 PM PDT 24
Finished Jul 16 06:32:24 PM PDT 24
Peak memory 218048 kb
Host smart-e49cc8eb-d214-4499-9d1e-dd3d6005b354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240955563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3240955563
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2563869277
Short name T174
Test name
Test status
Simulation time 1197223022 ps
CPU time 12.58 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 06:32:32 PM PDT 24
Peak memory 218884 kb
Host smart-16d6a120-8798-4c8f-a0b7-ea355fbfe97d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563869277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2563869277
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3176995066
Short name T318
Test name
Test status
Simulation time 1316771985 ps
CPU time 11.06 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:29 PM PDT 24
Peak memory 225944 kb
Host smart-cb5adeff-eefc-4a8d-b06d-fd7ebd1ff5b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176995066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3176995066
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2231602022
Short name T477
Test name
Test status
Simulation time 762206779 ps
CPU time 9.61 seconds
Started Jul 16 06:32:17 PM PDT 24
Finished Jul 16 06:32:28 PM PDT 24
Peak memory 218172 kb
Host smart-2d5a99eb-3fe4-45ef-85ca-da41bb48756f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231602022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2231602022
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1148856809
Short name T580
Test name
Test status
Simulation time 746790871 ps
CPU time 8.94 seconds
Started Jul 16 06:32:19 PM PDT 24
Finished Jul 16 06:32:29 PM PDT 24
Peak memory 218224 kb
Host smart-5a81637f-85d4-43e2-a943-331db5f5563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148856809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1148856809
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.438426034
Short name T401
Test name
Test status
Simulation time 35543767 ps
CPU time 1.09 seconds
Started Jul 16 06:32:19 PM PDT 24
Finished Jul 16 06:32:21 PM PDT 24
Peak memory 213672 kb
Host smart-6191b4c1-cf10-4f14-b03b-f322dee40cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438426034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.438426034
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3322010330
Short name T535
Test name
Test status
Simulation time 160074018 ps
CPU time 23.77 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 06:32:43 PM PDT 24
Peak memory 250972 kb
Host smart-1497f156-9e19-4c6a-a504-2824f9af417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322010330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3322010330
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.869424682
Short name T518
Test name
Test status
Simulation time 210480198 ps
CPU time 7.3 seconds
Started Jul 16 06:32:20 PM PDT 24
Finished Jul 16 06:32:28 PM PDT 24
Peak memory 250960 kb
Host smart-cbff53ba-e21f-492d-b5cc-395ba8925f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869424682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.869424682
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3071850719
Short name T96
Test name
Test status
Simulation time 5368431686 ps
CPU time 120.47 seconds
Started Jul 16 06:32:15 PM PDT 24
Finished Jul 16 06:34:17 PM PDT 24
Peak memory 253344 kb
Host smart-880d8254-8c70-47df-bcb0-67893e330d1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071850719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3071850719
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1116835005
Short name T821
Test name
Test status
Simulation time 15844839 ps
CPU time 0.89 seconds
Started Jul 16 06:32:18 PM PDT 24
Finished Jul 16 06:32:20 PM PDT 24
Peak memory 211976 kb
Host smart-0b0a507d-ec14-4359-a9ba-e57d6370f242
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116835005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1116835005
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3789443297
Short name T268
Test name
Test status
Simulation time 37650928 ps
CPU time 1.16 seconds
Started Jul 16 06:32:29 PM PDT 24
Finished Jul 16 06:32:30 PM PDT 24
Peak memory 208912 kb
Host smart-5304cf90-ff13-4061-8b77-43adeb368d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789443297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3789443297
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1062212637
Short name T501
Test name
Test status
Simulation time 227141850 ps
CPU time 11.47 seconds
Started Jul 16 06:32:27 PM PDT 24
Finished Jul 16 06:32:39 PM PDT 24
Peak memory 226048 kb
Host smart-2fd2b5ef-143f-4f9f-b8cb-b518644f5820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062212637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1062212637
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.660447644
Short name T782
Test name
Test status
Simulation time 1078173065 ps
CPU time 4.98 seconds
Started Jul 16 06:32:27 PM PDT 24
Finished Jul 16 06:32:33 PM PDT 24
Peak memory 217184 kb
Host smart-0f15f90f-f0ad-498a-a5f3-28a098fcaf53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660447644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.660447644
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2639897366
Short name T293
Test name
Test status
Simulation time 360572644 ps
CPU time 4.77 seconds
Started Jul 16 06:32:29 PM PDT 24
Finished Jul 16 06:32:35 PM PDT 24
Peak memory 218196 kb
Host smart-0c24e124-40f3-4d3e-a0eb-627b7075c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639897366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2639897366
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2907075613
Short name T453
Test name
Test status
Simulation time 360559212 ps
CPU time 16.3 seconds
Started Jul 16 06:32:30 PM PDT 24
Finished Jul 16 06:32:47 PM PDT 24
Peak memory 225912 kb
Host smart-50889006-7591-42d0-843e-4ea9133509e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907075613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2907075613
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1645986521
Short name T631
Test name
Test status
Simulation time 663923614 ps
CPU time 15.1 seconds
Started Jul 16 06:32:30 PM PDT 24
Finished Jul 16 06:32:45 PM PDT 24
Peak memory 225932 kb
Host smart-ddba8618-00a6-4032-bb8a-0ffaac0dde45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645986521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1645986521
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2667864303
Short name T248
Test name
Test status
Simulation time 671041440 ps
CPU time 13.97 seconds
Started Jul 16 06:32:27 PM PDT 24
Finished Jul 16 06:32:42 PM PDT 24
Peak memory 218160 kb
Host smart-d605f3fa-155a-4841-ba80-427a01959a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667864303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2667864303
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.460954049
Short name T540
Test name
Test status
Simulation time 293241072 ps
CPU time 9.72 seconds
Started Jul 16 06:32:27 PM PDT 24
Finished Jul 16 06:32:38 PM PDT 24
Peak memory 226064 kb
Host smart-033becb7-7523-4226-80c7-64539bd8251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460954049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.460954049
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1473811306
Short name T831
Test name
Test status
Simulation time 14383906 ps
CPU time 1.16 seconds
Started Jul 16 06:32:16 PM PDT 24
Finished Jul 16 06:32:19 PM PDT 24
Peak memory 211916 kb
Host smart-b1a0e7e7-3d23-4723-968a-3c9eb2322149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473811306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1473811306
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2042376107
Short name T104
Test name
Test status
Simulation time 267900652 ps
CPU time 19.22 seconds
Started Jul 16 06:32:28 PM PDT 24
Finished Jul 16 06:32:48 PM PDT 24
Peak memory 250964 kb
Host smart-9a7fcdde-d662-4704-87bd-3db3dc2df0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042376107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2042376107
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.4282549836
Short name T416
Test name
Test status
Simulation time 887215358 ps
CPU time 5.99 seconds
Started Jul 16 06:32:27 PM PDT 24
Finished Jul 16 06:32:34 PM PDT 24
Peak memory 246772 kb
Host smart-f1b8d74e-958d-4787-8514-8ba8934d9d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282549836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.4282549836
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2259469632
Short name T847
Test name
Test status
Simulation time 1614324096 ps
CPU time 37.46 seconds
Started Jul 16 06:32:31 PM PDT 24
Finished Jul 16 06:33:09 PM PDT 24
Peak memory 250892 kb
Host smart-aa3b63ba-559a-4aed-b765-c6ef68149150
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259469632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2259469632
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.41424139
Short name T711
Test name
Test status
Simulation time 34218409597 ps
CPU time 345.41 seconds
Started Jul 16 06:32:30 PM PDT 24
Finished Jul 16 06:38:16 PM PDT 24
Peak memory 272844 kb
Host smart-6c38939f-14dd-4201-8a96-faf6dcb7b47a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=41424139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.41424139
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1024668491
Short name T510
Test name
Test status
Simulation time 14288534 ps
CPU time 1.06 seconds
Started Jul 16 06:32:28 PM PDT 24
Finished Jul 16 06:32:30 PM PDT 24
Peak memory 211872 kb
Host smart-ec2bb507-f71d-42d5-99a0-e38578ac611c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024668491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1024668491
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1920700754
Short name T616
Test name
Test status
Simulation time 17791195 ps
CPU time 0.91 seconds
Started Jul 16 06:28:24 PM PDT 24
Finished Jul 16 06:28:25 PM PDT 24
Peak memory 208776 kb
Host smart-409521d1-684f-4a93-a279-554af71bc663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920700754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1920700754
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1485796869
Short name T178
Test name
Test status
Simulation time 24054094 ps
CPU time 0.8 seconds
Started Jul 16 06:28:19 PM PDT 24
Finished Jul 16 06:28:21 PM PDT 24
Peak memory 208832 kb
Host smart-7155e4c4-37ce-4fe8-9a3e-476136eb1436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485796869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1485796869
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2603017690
Short name T613
Test name
Test status
Simulation time 5732224083 ps
CPU time 9.16 seconds
Started Jul 16 06:28:22 PM PDT 24
Finished Jul 16 06:28:32 PM PDT 24
Peak memory 218404 kb
Host smart-8fbaccca-4d2f-4e74-a193-c526aa96fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603017690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2603017690
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1950630686
Short name T498
Test name
Test status
Simulation time 469848525 ps
CPU time 6.17 seconds
Started Jul 16 06:28:22 PM PDT 24
Finished Jul 16 06:28:30 PM PDT 24
Peak memory 217144 kb
Host smart-b9c4e2dd-63d5-4e99-87ee-32c3bb8ca7e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950630686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1950630686
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1057571217
Short name T425
Test name
Test status
Simulation time 1558648490 ps
CPU time 24.54 seconds
Started Jul 16 06:28:19 PM PDT 24
Finished Jul 16 06:28:45 PM PDT 24
Peak memory 218156 kb
Host smart-cda2c278-3d63-4e56-8704-89aa3052d37e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057571217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1057571217
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.490671829
Short name T682
Test name
Test status
Simulation time 1656834201 ps
CPU time 2.09 seconds
Started Jul 16 06:28:20 PM PDT 24
Finished Jul 16 06:28:23 PM PDT 24
Peak memory 217416 kb
Host smart-5ff926f7-3079-492f-9069-5f892c22f410
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490671829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.490671829
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3711108056
Short name T85
Test name
Test status
Simulation time 571928757 ps
CPU time 12.93 seconds
Started Jul 16 06:28:20 PM PDT 24
Finished Jul 16 06:28:34 PM PDT 24
Peak memory 218144 kb
Host smart-767b44d9-a525-4107-81ed-9208741a255c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711108056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3711108056
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1875149915
Short name T651
Test name
Test status
Simulation time 11698684383 ps
CPU time 11.31 seconds
Started Jul 16 06:28:24 PM PDT 24
Finished Jul 16 06:28:36 PM PDT 24
Peak memory 217612 kb
Host smart-1d2666b7-b26c-4cce-a757-e9ec29fcb018
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875149915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1875149915
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1848932951
Short name T309
Test name
Test status
Simulation time 93018900 ps
CPU time 3.15 seconds
Started Jul 16 06:28:22 PM PDT 24
Finished Jul 16 06:28:26 PM PDT 24
Peak memory 217460 kb
Host smart-4a9eb22b-1b14-480b-b3b4-c9ef9b602386
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848932951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1848932951
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3400903039
Short name T175
Test name
Test status
Simulation time 44041932612 ps
CPU time 65.79 seconds
Started Jul 16 06:28:24 PM PDT 24
Finished Jul 16 06:29:31 PM PDT 24
Peak memory 278916 kb
Host smart-dd1abcf9-4db3-4fca-abc8-ca1c07a413b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400903039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3400903039
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.972237880
Short name T492
Test name
Test status
Simulation time 6392081835 ps
CPU time 25.39 seconds
Started Jul 16 06:28:20 PM PDT 24
Finished Jul 16 06:28:47 PM PDT 24
Peak memory 250852 kb
Host smart-a8c937e2-3c0a-4698-b564-4e9818d62c82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972237880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.972237880
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.377649712
Short name T505
Test name
Test status
Simulation time 133686367 ps
CPU time 2.61 seconds
Started Jul 16 06:28:18 PM PDT 24
Finished Jul 16 06:28:22 PM PDT 24
Peak memory 218188 kb
Host smart-503ae110-2dc1-4e82-ae23-3297216da711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377649712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.377649712
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2316444716
Short name T184
Test name
Test status
Simulation time 1108909054 ps
CPU time 6.51 seconds
Started Jul 16 06:28:21 PM PDT 24
Finished Jul 16 06:28:29 PM PDT 24
Peak memory 214608 kb
Host smart-cf01edd2-6b2a-4835-8471-62904e7e9368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316444716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2316444716
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.496017287
Short name T236
Test name
Test status
Simulation time 544408753 ps
CPU time 13.77 seconds
Started Jul 16 06:28:24 PM PDT 24
Finished Jul 16 06:28:38 PM PDT 24
Peak memory 225876 kb
Host smart-5cee1682-d7d0-4af9-96d6-78efff2e0abf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496017287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.496017287
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1428937419
Short name T454
Test name
Test status
Simulation time 957876477 ps
CPU time 9.44 seconds
Started Jul 16 06:28:24 PM PDT 24
Finished Jul 16 06:28:34 PM PDT 24
Peak memory 218084 kb
Host smart-5c96d7f3-e243-43c0-8d39-d6c7aee723af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428937419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
428937419
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3384688935
Short name T221
Test name
Test status
Simulation time 376703598 ps
CPU time 14.1 seconds
Started Jul 16 06:28:19 PM PDT 24
Finished Jul 16 06:28:35 PM PDT 24
Peak memory 225980 kb
Host smart-9a10e67a-58f2-4b81-b265-89aa612f43c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384688935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3384688935
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.254423028
Short name T733
Test name
Test status
Simulation time 699222506 ps
CPU time 11.88 seconds
Started Jul 16 06:28:20 PM PDT 24
Finished Jul 16 06:28:33 PM PDT 24
Peak memory 223376 kb
Host smart-8ba13897-9156-4867-abb9-2265ae3bb876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254423028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.254423028
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.183191830
Short name T263
Test name
Test status
Simulation time 2349471979 ps
CPU time 33.89 seconds
Started Jul 16 06:28:19 PM PDT 24
Finished Jul 16 06:28:55 PM PDT 24
Peak memory 250924 kb
Host smart-80b2e03f-5756-42cf-866d-e5a7ee295a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183191830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.183191830
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3809607743
Short name T265
Test name
Test status
Simulation time 145076026 ps
CPU time 9.31 seconds
Started Jul 16 06:28:22 PM PDT 24
Finished Jul 16 06:28:32 PM PDT 24
Peak memory 250864 kb
Host smart-b2d92140-35b6-4735-8677-aeee70c0d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809607743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3809607743
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1429778290
Short name T361
Test name
Test status
Simulation time 20797063035 ps
CPU time 107.38 seconds
Started Jul 16 06:28:21 PM PDT 24
Finished Jul 16 06:30:10 PM PDT 24
Peak memory 226056 kb
Host smart-bd263aa2-c955-4883-a3f2-b02bf83569e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429778290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1429778290
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1469818162
Short name T438
Test name
Test status
Simulation time 19385736 ps
CPU time 0.96 seconds
Started Jul 16 06:28:18 PM PDT 24
Finished Jul 16 06:28:20 PM PDT 24
Peak memory 211772 kb
Host smart-8ca1db43-e717-4624-a7c7-c127866dba0a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469818162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1469818162
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1373298078
Short name T84
Test name
Test status
Simulation time 89524847 ps
CPU time 1.11 seconds
Started Jul 16 06:28:30 PM PDT 24
Finished Jul 16 06:28:33 PM PDT 24
Peak memory 208912 kb
Host smart-5b9223d9-7de2-4c76-b323-d5bf495c5f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373298078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1373298078
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.297365007
Short name T213
Test name
Test status
Simulation time 92974186 ps
CPU time 0.81 seconds
Started Jul 16 06:28:33 PM PDT 24
Finished Jul 16 06:28:35 PM PDT 24
Peak memory 208900 kb
Host smart-c4b6b108-7740-4d36-9e94-698794823cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297365007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.297365007
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4123093774
Short name T779
Test name
Test status
Simulation time 560841657 ps
CPU time 9.86 seconds
Started Jul 16 06:28:30 PM PDT 24
Finished Jul 16 06:28:41 PM PDT 24
Peak memory 218044 kb
Host smart-c293b23f-9e6d-45af-9adf-6da7ba4fe46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123093774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4123093774
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2925273711
Short name T29
Test name
Test status
Simulation time 1065671932 ps
CPU time 4.49 seconds
Started Jul 16 06:28:35 PM PDT 24
Finished Jul 16 06:28:41 PM PDT 24
Peak memory 217224 kb
Host smart-c9849818-2dba-47f6-ac6f-39c9e419cdb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925273711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2925273711
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.530917881
Short name T502
Test name
Test status
Simulation time 12466232559 ps
CPU time 30.67 seconds
Started Jul 16 06:28:29 PM PDT 24
Finished Jul 16 06:29:02 PM PDT 24
Peak memory 218156 kb
Host smart-a59c6ed1-b196-4c76-8401-d19659d44101
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530917881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.530917881
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3011941551
Short name T483
Test name
Test status
Simulation time 615847414 ps
CPU time 2.48 seconds
Started Jul 16 06:28:30 PM PDT 24
Finished Jul 16 06:28:34 PM PDT 24
Peak memory 217700 kb
Host smart-3c7b5d9c-c0f1-4044-9a3d-fda26e9cfb8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011941551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
011941551
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1674689401
Short name T838
Test name
Test status
Simulation time 398220511 ps
CPU time 11.49 seconds
Started Jul 16 06:28:36 PM PDT 24
Finished Jul 16 06:28:48 PM PDT 24
Peak memory 218056 kb
Host smart-0d2ff6cb-28bd-4072-a3eb-79d336b27097
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674689401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1674689401
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1738691293
Short name T24
Test name
Test status
Simulation time 909910234 ps
CPU time 25.79 seconds
Started Jul 16 06:28:31 PM PDT 24
Finished Jul 16 06:28:59 PM PDT 24
Peak memory 217524 kb
Host smart-001462b8-f1f5-4183-8d44-7ebc789fa2fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738691293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1738691293
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2660486640
Short name T823
Test name
Test status
Simulation time 713323599 ps
CPU time 3.5 seconds
Started Jul 16 06:28:29 PM PDT 24
Finished Jul 16 06:28:35 PM PDT 24
Peak memory 217588 kb
Host smart-1d9b2dbb-1cf9-4157-beef-76539e4a5981
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660486640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2660486640
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1206548383
Short name T22
Test name
Test status
Simulation time 27564020279 ps
CPU time 69.98 seconds
Started Jul 16 06:28:35 PM PDT 24
Finished Jul 16 06:29:46 PM PDT 24
Peak memory 282848 kb
Host smart-47e1e36f-94af-426b-8bf1-8baed617b83a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206548383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1206548383
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1550781859
Short name T321
Test name
Test status
Simulation time 601939637 ps
CPU time 16.26 seconds
Started Jul 16 06:28:35 PM PDT 24
Finished Jul 16 06:28:52 PM PDT 24
Peak memory 250788 kb
Host smart-d77f27d1-d4d4-4cc6-9bdf-4c820069c524
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550781859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1550781859
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2531585490
Short name T603
Test name
Test status
Simulation time 109196551 ps
CPU time 2.31 seconds
Started Jul 16 06:28:34 PM PDT 24
Finished Jul 16 06:28:38 PM PDT 24
Peak memory 218144 kb
Host smart-da80106d-e008-4e48-bd96-0b10bd1567e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531585490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2531585490
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.213121516
Short name T526
Test name
Test status
Simulation time 833064275 ps
CPU time 24.27 seconds
Started Jul 16 06:28:30 PM PDT 24
Finished Jul 16 06:28:56 PM PDT 24
Peak memory 217704 kb
Host smart-1c0f37c6-8c51-4077-b06c-b50b6d1c3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213121516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.213121516
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4258020920
Short name T291
Test name
Test status
Simulation time 1384547650 ps
CPU time 14.22 seconds
Started Jul 16 06:28:30 PM PDT 24
Finished Jul 16 06:28:46 PM PDT 24
Peak memory 225868 kb
Host smart-b2dd9f9b-46f8-455e-a97d-6575967f49ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258020920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4258020920
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1598793489
Short name T476
Test name
Test status
Simulation time 1191389720 ps
CPU time 10.09 seconds
Started Jul 16 06:28:32 PM PDT 24
Finished Jul 16 06:28:44 PM PDT 24
Peak memory 225892 kb
Host smart-2f12c04c-f205-41f0-913b-72f748dc7b9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598793489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
598793489
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1744822450
Short name T39
Test name
Test status
Simulation time 2133838975 ps
CPU time 8.19 seconds
Started Jul 16 06:28:31 PM PDT 24
Finished Jul 16 06:28:41 PM PDT 24
Peak memory 218276 kb
Host smart-3b817643-4fb1-4c4b-baa8-16725583a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744822450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1744822450
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3240125826
Short name T419
Test name
Test status
Simulation time 197027754 ps
CPU time 3.48 seconds
Started Jul 16 06:28:22 PM PDT 24
Finished Jul 16 06:28:27 PM PDT 24
Peak memory 214944 kb
Host smart-f291aab8-576c-4982-9356-dc882753d538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240125826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3240125826
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3665166430
Short name T297
Test name
Test status
Simulation time 2102874413 ps
CPU time 30.2 seconds
Started Jul 16 06:28:23 PM PDT 24
Finished Jul 16 06:28:54 PM PDT 24
Peak memory 250972 kb
Host smart-30d1803e-a734-47d8-8fdb-42e86f7ca100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665166430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3665166430
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3022753254
Short name T856
Test name
Test status
Simulation time 83232912 ps
CPU time 8.23 seconds
Started Jul 16 06:28:21 PM PDT 24
Finished Jul 16 06:28:30 PM PDT 24
Peak memory 250924 kb
Host smart-632be6de-df21-4702-90b6-e580e9116de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022753254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3022753254
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1267725203
Short name T568
Test name
Test status
Simulation time 20153906265 ps
CPU time 94.95 seconds
Started Jul 16 06:28:31 PM PDT 24
Finished Jul 16 06:30:08 PM PDT 24
Peak memory 278944 kb
Host smart-84372261-8de5-45a4-bfd7-6eab0b26cd7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267725203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1267725203
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2610997037
Short name T342
Test name
Test status
Simulation time 13332299 ps
CPU time 0.77 seconds
Started Jul 16 06:28:20 PM PDT 24
Finished Jul 16 06:28:22 PM PDT 24
Peak memory 208316 kb
Host smart-056dcd73-c056-44a7-af3f-75f236332099
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610997037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2610997037
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2516376511
Short name T408
Test name
Test status
Simulation time 31275049 ps
CPU time 1.35 seconds
Started Jul 16 06:28:42 PM PDT 24
Finished Jul 16 06:28:44 PM PDT 24
Peak memory 208924 kb
Host smart-d39dc573-b5e9-4b33-b418-5188db61e34a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516376511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2516376511
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1775923622
Short name T797
Test name
Test status
Simulation time 30296301 ps
CPU time 0.92 seconds
Started Jul 16 06:28:30 PM PDT 24
Finished Jul 16 06:28:33 PM PDT 24
Peak memory 208568 kb
Host smart-56a235e2-75bf-4b2b-99af-c3ae970c9538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775923622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1775923622
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3584588531
Short name T623
Test name
Test status
Simulation time 258239687 ps
CPU time 9.08 seconds
Started Jul 16 06:28:34 PM PDT 24
Finished Jul 16 06:28:44 PM PDT 24
Peak memory 225976 kb
Host smart-493fc6bb-286f-4f9d-820d-405f544da65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584588531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3584588531
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3239021197
Short name T774
Test name
Test status
Simulation time 856187200 ps
CPU time 5.71 seconds
Started Jul 16 06:28:40 PM PDT 24
Finished Jul 16 06:28:47 PM PDT 24
Peak memory 217376 kb
Host smart-3f416ce5-6368-414e-a47a-41be77506cfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239021197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3239021197
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4139191920
Short name T44
Test name
Test status
Simulation time 8177340998 ps
CPU time 109.14 seconds
Started Jul 16 06:28:38 PM PDT 24
Finished Jul 16 06:30:28 PM PDT 24
Peak memory 218804 kb
Host smart-a157247f-63c2-4222-b835-ca051cbda5cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139191920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4139191920
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.4108496866
Short name T23
Test name
Test status
Simulation time 2868754435 ps
CPU time 7.29 seconds
Started Jul 16 06:28:40 PM PDT 24
Finished Jul 16 06:28:48 PM PDT 24
Peak memory 217752 kb
Host smart-e9612210-89a2-4abe-8c6d-bd5090072704
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108496866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.4
108496866
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.617730104
Short name T426
Test name
Test status
Simulation time 980617401 ps
CPU time 8.04 seconds
Started Jul 16 06:28:42 PM PDT 24
Finished Jul 16 06:28:50 PM PDT 24
Peak memory 218068 kb
Host smart-191082ae-c8d3-4a86-8c34-01ec8757d135
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617730104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.617730104
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3533335347
Short name T593
Test name
Test status
Simulation time 2027440369 ps
CPU time 31.34 seconds
Started Jul 16 06:28:37 PM PDT 24
Finished Jul 16 06:29:09 PM PDT 24
Peak memory 217600 kb
Host smart-3a5a8d50-6e9c-4879-ba81-1c7f7fc08204
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533335347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3533335347
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1628838122
Short name T794
Test name
Test status
Simulation time 1351757597 ps
CPU time 1.46 seconds
Started Jul 16 06:28:27 PM PDT 24
Finished Jul 16 06:28:30 PM PDT 24
Peak memory 217656 kb
Host smart-7b85840c-9679-48f9-9bf7-309a05991449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628838122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1628838122
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3321733070
Short name T428
Test name
Test status
Simulation time 7081299903 ps
CPU time 79.14 seconds
Started Jul 16 06:28:34 PM PDT 24
Finished Jul 16 06:29:54 PM PDT 24
Peak memory 270780 kb
Host smart-db4301ff-062e-4a4d-867e-0ac2fc819dc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321733070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3321733070
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.621409250
Short name T329
Test name
Test status
Simulation time 711170040 ps
CPU time 11.9 seconds
Started Jul 16 06:28:36 PM PDT 24
Finished Jul 16 06:28:49 PM PDT 24
Peak memory 222960 kb
Host smart-91a5e025-c774-4595-afe5-961efe7bc98e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621409250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.621409250
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3144374858
Short name T155
Test name
Test status
Simulation time 51991001 ps
CPU time 2.45 seconds
Started Jul 16 06:28:30 PM PDT 24
Finished Jul 16 06:28:34 PM PDT 24
Peak memory 218120 kb
Host smart-347c05db-d169-488e-ae80-47b864ff426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144374858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3144374858
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3195847590
Short name T15
Test name
Test status
Simulation time 1092901268 ps
CPU time 7.62 seconds
Started Jul 16 06:28:31 PM PDT 24
Finished Jul 16 06:28:41 PM PDT 24
Peak memory 217604 kb
Host smart-26c56744-c2ef-43d2-8f24-d1f7215b426c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195847590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3195847590
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.743780771
Short name T234
Test name
Test status
Simulation time 221597642 ps
CPU time 8.95 seconds
Started Jul 16 06:28:38 PM PDT 24
Finished Jul 16 06:28:47 PM PDT 24
Peak memory 225972 kb
Host smart-2f33c8eb-c488-4e2b-9cc5-b033ffb3dbca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743780771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.743780771
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.103630164
Short name T292
Test name
Test status
Simulation time 1462649467 ps
CPU time 12.68 seconds
Started Jul 16 06:28:40 PM PDT 24
Finished Jul 16 06:28:54 PM PDT 24
Peak memory 218188 kb
Host smart-3a281351-bbff-4b58-a2c6-93fce07f21cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103630164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.103630164
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2568539255
Short name T863
Test name
Test status
Simulation time 1466389160 ps
CPU time 13.96 seconds
Started Jul 16 06:28:29 PM PDT 24
Finished Jul 16 06:28:45 PM PDT 24
Peak memory 218112 kb
Host smart-a59af2ca-5e78-49a8-a47f-39ee3e03a073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568539255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2568539255
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.476571431
Short name T335
Test name
Test status
Simulation time 117656082 ps
CPU time 4.51 seconds
Started Jul 16 06:28:29 PM PDT 24
Finished Jul 16 06:28:35 PM PDT 24
Peak memory 217560 kb
Host smart-fecf6f93-586c-4a8b-b59e-769ebc64074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476571431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.476571431
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1894156855
Short name T26
Test name
Test status
Simulation time 274899559 ps
CPU time 27.76 seconds
Started Jul 16 06:28:34 PM PDT 24
Finished Jul 16 06:29:02 PM PDT 24
Peak memory 250916 kb
Host smart-f612286d-48d9-49ea-b0d4-cbe8f4b54691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894156855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1894156855
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.963107252
Short name T472
Test name
Test status
Simulation time 329767629 ps
CPU time 6.77 seconds
Started Jul 16 06:28:35 PM PDT 24
Finished Jul 16 06:28:43 PM PDT 24
Peak memory 246616 kb
Host smart-0d3c38d8-25f8-4b87-be2c-fff6b0f7c893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963107252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.963107252
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1821187329
Short name T559
Test name
Test status
Simulation time 7170108291 ps
CPU time 158.95 seconds
Started Jul 16 06:28:40 PM PDT 24
Finished Jul 16 06:31:19 PM PDT 24
Peak memory 277220 kb
Host smart-316c73ca-9350-4fdc-a003-74fe388fe485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821187329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1821187329
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4228144835
Short name T171
Test name
Test status
Simulation time 41335537 ps
CPU time 0.82 seconds
Started Jul 16 06:28:35 PM PDT 24
Finished Jul 16 06:28:37 PM PDT 24
Peak memory 211760 kb
Host smart-f10d2afa-6953-4000-b595-4ddd171e7cde
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228144835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4228144835
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2341785181
Short name T95
Test name
Test status
Simulation time 14879038 ps
CPU time 1.04 seconds
Started Jul 16 06:28:51 PM PDT 24
Finished Jul 16 06:28:52 PM PDT 24
Peak memory 208816 kb
Host smart-3ddf1eb5-9639-4438-9e64-8a46cdbd13aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341785181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2341785181
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.698489601
Short name T225
Test name
Test status
Simulation time 402575905 ps
CPU time 10.1 seconds
Started Jul 16 06:28:41 PM PDT 24
Finished Jul 16 06:28:51 PM PDT 24
Peak memory 218208 kb
Host smart-e5692c9c-bc26-4dad-a56b-0d0eb9a8f5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698489601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.698489601
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1812326031
Short name T413
Test name
Test status
Simulation time 233696406 ps
CPU time 6.39 seconds
Started Jul 16 06:28:47 PM PDT 24
Finished Jul 16 06:28:54 PM PDT 24
Peak memory 217300 kb
Host smart-4f5b0d8f-37e1-4922-8c9b-28e918b0a2eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812326031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1812326031
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.978956169
Short name T504
Test name
Test status
Simulation time 12882557154 ps
CPU time 42.87 seconds
Started Jul 16 06:28:49 PM PDT 24
Finished Jul 16 06:29:33 PM PDT 24
Peak memory 225872 kb
Host smart-7e8af877-bc4d-4792-8543-14e44c7494f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978956169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.978956169
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1969244267
Short name T372
Test name
Test status
Simulation time 1228495044 ps
CPU time 5.53 seconds
Started Jul 16 06:28:48 PM PDT 24
Finished Jul 16 06:28:55 PM PDT 24
Peak memory 217656 kb
Host smart-586809ac-125b-4872-8892-6f3c57c5a353
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969244267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
969244267
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3179386696
Short name T749
Test name
Test status
Simulation time 284963074 ps
CPU time 5.53 seconds
Started Jul 16 06:28:49 PM PDT 24
Finished Jul 16 06:28:56 PM PDT 24
Peak memory 218172 kb
Host smart-e9f34eb2-0f6c-4416-97c7-e7d24f96e6c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179386696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3179386696
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1525483107
Short name T286
Test name
Test status
Simulation time 1803950874 ps
CPU time 35.7 seconds
Started Jul 16 06:28:49 PM PDT 24
Finished Jul 16 06:29:26 PM PDT 24
Peak memory 217460 kb
Host smart-3b3af0cc-67d7-4850-9ea0-1934c21af662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525483107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1525483107
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.759492441
Short name T390
Test name
Test status
Simulation time 376501095 ps
CPU time 2.21 seconds
Started Jul 16 06:28:47 PM PDT 24
Finished Jul 16 06:28:51 PM PDT 24
Peak memory 217572 kb
Host smart-e2a54f57-d1a4-415d-a1b4-19a7a0114444
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759492441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.759492441
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2457114558
Short name T640
Test name
Test status
Simulation time 3598431179 ps
CPU time 59.17 seconds
Started Jul 16 06:28:47 PM PDT 24
Finished Jul 16 06:29:48 PM PDT 24
Peak memory 283692 kb
Host smart-605bf287-4eed-49d7-b98f-aed8d668b691
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457114558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2457114558
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2917495321
Short name T759
Test name
Test status
Simulation time 729295836 ps
CPU time 10.72 seconds
Started Jul 16 06:28:48 PM PDT 24
Finished Jul 16 06:29:00 PM PDT 24
Peak memory 242692 kb
Host smart-16f2ee5c-7aed-4694-a46f-f68d5b934cef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917495321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2917495321
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1310340559
Short name T275
Test name
Test status
Simulation time 66654531 ps
CPU time 2.5 seconds
Started Jul 16 06:28:37 PM PDT 24
Finished Jul 16 06:28:40 PM PDT 24
Peak memory 218224 kb
Host smart-bce9e78c-70a4-4d47-b5ea-0cbd5fe1f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310340559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1310340559
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3426603279
Short name T742
Test name
Test status
Simulation time 1411129997 ps
CPU time 10.84 seconds
Started Jul 16 06:28:37 PM PDT 24
Finished Jul 16 06:28:48 PM PDT 24
Peak memory 214184 kb
Host smart-1baaa999-b238-4f63-b106-d4e192eb8560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426603279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3426603279
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.664386514
Short name T439
Test name
Test status
Simulation time 217861875 ps
CPU time 11.81 seconds
Started Jul 16 06:28:50 PM PDT 24
Finished Jul 16 06:29:03 PM PDT 24
Peak memory 226020 kb
Host smart-442e5916-7a40-4915-a73e-b8adac723e56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664386514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.664386514
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.329820503
Short name T474
Test name
Test status
Simulation time 1360537637 ps
CPU time 12.12 seconds
Started Jul 16 06:28:47 PM PDT 24
Finished Jul 16 06:29:00 PM PDT 24
Peak memory 226080 kb
Host smart-a9e383b4-0262-422d-95e8-4f2f27587471
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329820503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.329820503
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2601140544
Short name T721
Test name
Test status
Simulation time 458997850 ps
CPU time 10.89 seconds
Started Jul 16 06:28:36 PM PDT 24
Finished Jul 16 06:28:48 PM PDT 24
Peak memory 225988 kb
Host smart-53982a0a-bd02-402d-83ba-abdd7e315f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601140544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2601140544
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3666698888
Short name T569
Test name
Test status
Simulation time 174686727 ps
CPU time 4.64 seconds
Started Jul 16 06:28:41 PM PDT 24
Finished Jul 16 06:28:47 PM PDT 24
Peak memory 217680 kb
Host smart-6f8796ff-70bb-487f-b3a2-6ce144a6a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666698888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3666698888
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.927899750
Short name T99
Test name
Test status
Simulation time 264231858 ps
CPU time 30.1 seconds
Started Jul 16 06:28:38 PM PDT 24
Finished Jul 16 06:29:09 PM PDT 24
Peak memory 250888 kb
Host smart-a6c2c477-089d-4df7-ae39-8b283a700290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927899750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.927899750
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1385127388
Short name T790
Test name
Test status
Simulation time 158941859 ps
CPU time 4.56 seconds
Started Jul 16 06:28:38 PM PDT 24
Finished Jul 16 06:28:43 PM PDT 24
Peak memory 226396 kb
Host smart-e88c29f7-ddab-4b5a-a4d6-61e3e38efa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385127388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1385127388
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2833705103
Short name T647
Test name
Test status
Simulation time 30735344508 ps
CPU time 107.14 seconds
Started Jul 16 06:28:49 PM PDT 24
Finished Jul 16 06:30:37 PM PDT 24
Peak memory 283632 kb
Host smart-8e526297-c7c4-45ff-891c-7eaa58adb0b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833705103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2833705103
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1819066394
Short name T255
Test name
Test status
Simulation time 94413115 ps
CPU time 0.81 seconds
Started Jul 16 06:28:37 PM PDT 24
Finished Jul 16 06:28:39 PM PDT 24
Peak memory 211908 kb
Host smart-efffd9fa-b5d3-4d0a-a26e-d3d5cddb73f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819066394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1819066394
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3419057216
Short name T692
Test name
Test status
Simulation time 45328180 ps
CPU time 0.83 seconds
Started Jul 16 06:28:59 PM PDT 24
Finished Jul 16 06:29:01 PM PDT 24
Peak memory 208620 kb
Host smart-a785e613-5f31-4efc-b2e5-a040944e511a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419057216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3419057216
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1397463094
Short name T214
Test name
Test status
Simulation time 34658031 ps
CPU time 0.93 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:01 PM PDT 24
Peak memory 208720 kb
Host smart-63311232-4e1b-4f6e-bc48-fd218730da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397463094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1397463094
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3136467518
Short name T266
Test name
Test status
Simulation time 512998329 ps
CPU time 9.8 seconds
Started Jul 16 06:28:48 PM PDT 24
Finished Jul 16 06:28:59 PM PDT 24
Peak memory 218132 kb
Host smart-720531a2-90c5-49e5-9f9f-cb4f398c9dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136467518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3136467518
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3477295405
Short name T366
Test name
Test status
Simulation time 32250361 ps
CPU time 1.53 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:28:59 PM PDT 24
Peak memory 217156 kb
Host smart-e77e3a76-38dc-4bce-bad6-9bb8f8163f28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477295405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3477295405
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1174731047
Short name T21
Test name
Test status
Simulation time 3575007871 ps
CPU time 99.64 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:30:37 PM PDT 24
Peak memory 226004 kb
Host smart-eccde8ac-afca-49ec-a30e-3af3fc64eb7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174731047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1174731047
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.520118483
Short name T399
Test name
Test status
Simulation time 1177819435 ps
CPU time 4.57 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:05 PM PDT 24
Peak memory 217584 kb
Host smart-0bb03233-8416-47d4-ad09-5348070447d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520118483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.520118483
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1191867053
Short name T663
Test name
Test status
Simulation time 922436171 ps
CPU time 21.23 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:21 PM PDT 24
Peak memory 218772 kb
Host smart-2f99c424-b88c-481b-b0b4-9e37518e55f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191867053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1191867053
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3229316596
Short name T457
Test name
Test status
Simulation time 3708084264 ps
CPU time 16.53 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:16 PM PDT 24
Peak memory 217596 kb
Host smart-f0184485-2316-4b97-a94b-88012a2051df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229316596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3229316596
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.226661485
Short name T536
Test name
Test status
Simulation time 198633591 ps
CPU time 6.39 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:06 PM PDT 24
Peak memory 217496 kb
Host smart-9739467c-672e-4b53-addb-3b9d0eaba3e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226661485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.226661485
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1729353691
Short name T465
Test name
Test status
Simulation time 1052400499 ps
CPU time 38.31 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:37 PM PDT 24
Peak memory 250816 kb
Host smart-eefc5159-2417-44df-a51d-ef748469a0a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729353691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1729353691
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3508364941
Short name T758
Test name
Test status
Simulation time 1108368536 ps
CPU time 14.43 seconds
Started Jul 16 06:29:00 PM PDT 24
Finished Jul 16 06:29:15 PM PDT 24
Peak memory 224640 kb
Host smart-e0d68976-d04f-4f65-bf61-eec274eae117
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508364941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3508364941
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3261638983
Short name T407
Test name
Test status
Simulation time 19132636 ps
CPU time 1.55 seconds
Started Jul 16 06:28:48 PM PDT 24
Finished Jul 16 06:28:51 PM PDT 24
Peak memory 218168 kb
Host smart-c453cc0a-4b68-4952-b4bc-f75e43489b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261638983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3261638983
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.866347127
Short name T724
Test name
Test status
Simulation time 1540375640 ps
CPU time 8.15 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:06 PM PDT 24
Peak memory 217660 kb
Host smart-19a85648-e920-47d7-ac06-58ee13d8de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866347127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.866347127
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.239595894
Short name T434
Test name
Test status
Simulation time 553283445 ps
CPU time 13.14 seconds
Started Jul 16 06:28:59 PM PDT 24
Finished Jul 16 06:29:14 PM PDT 24
Peak memory 218884 kb
Host smart-bb0379c8-2d54-41ec-a455-93a8b114769e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239595894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.239595894
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2732657688
Short name T354
Test name
Test status
Simulation time 407674258 ps
CPU time 11.54 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:10 PM PDT 24
Peak memory 225920 kb
Host smart-e3f1b614-8c6b-4d0b-9e33-6dbfb0563e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732657688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2732657688
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.4257925161
Short name T541
Test name
Test status
Simulation time 1028484324 ps
CPU time 8.13 seconds
Started Jul 16 06:28:57 PM PDT 24
Finished Jul 16 06:29:07 PM PDT 24
Peak memory 225928 kb
Host smart-fe8af7d9-b363-4655-bc2d-53e72e392f78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257925161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.4
257925161
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1776671613
Short name T586
Test name
Test status
Simulation time 366428368 ps
CPU time 12.47 seconds
Started Jul 16 06:28:50 PM PDT 24
Finished Jul 16 06:29:04 PM PDT 24
Peak memory 218328 kb
Host smart-cb611a31-6a23-43ee-a676-0621970deb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776671613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1776671613
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3006777491
Short name T862
Test name
Test status
Simulation time 107797709 ps
CPU time 2.74 seconds
Started Jul 16 06:28:48 PM PDT 24
Finished Jul 16 06:28:52 PM PDT 24
Peak memory 217688 kb
Host smart-64740d7a-2128-4192-8a3f-e97db5d1a138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006777491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3006777491
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2773636724
Short name T87
Test name
Test status
Simulation time 210284082 ps
CPU time 22.33 seconds
Started Jul 16 06:28:48 PM PDT 24
Finished Jul 16 06:29:12 PM PDT 24
Peak memory 250928 kb
Host smart-1571c851-e29e-4e1a-ae15-ca2327b7e68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773636724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2773636724
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2133982152
Short name T365
Test name
Test status
Simulation time 78335741 ps
CPU time 6.5 seconds
Started Jul 16 06:28:49 PM PDT 24
Finished Jul 16 06:28:57 PM PDT 24
Peak memory 242472 kb
Host smart-af9726a1-97ce-48bf-83c4-3a4906b1da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133982152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2133982152
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.958183699
Short name T610
Test name
Test status
Simulation time 1907432896 ps
CPU time 47.95 seconds
Started Jul 16 06:28:58 PM PDT 24
Finished Jul 16 06:29:47 PM PDT 24
Peak memory 226036 kb
Host smart-dadd399f-c253-44a5-b375-f13588623e0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958183699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.958183699
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2485763699
Short name T277
Test name
Test status
Simulation time 36199184 ps
CPU time 0.83 seconds
Started Jul 16 06:28:48 PM PDT 24
Finished Jul 16 06:28:50 PM PDT 24
Peak memory 211704 kb
Host smart-c761ee33-882f-4ec3-b376-15e820c51ae9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485763699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2485763699
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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