Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52955 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1802 |
1 |
|
|
T11 |
10 |
|
T4 |
10 |
|
T16 |
13 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54114 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
643 |
1 |
|
|
T15 |
17 |
|
T63 |
16 |
|
T67 |
16 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52708 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
9 |
auto[1] |
2049 |
1 |
|
|
T3 |
1 |
|
T12 |
8 |
|
T27 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52724 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
2033 |
1 |
|
|
T12 |
9 |
|
T38 |
5 |
|
T46 |
4 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52686 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
2071 |
1 |
|
|
T12 |
3 |
|
T27 |
1 |
|
T38 |
7 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49427 |
1 |
|
|
T1 |
50 |
|
T3 |
5 |
|
T10 |
100 |
no_err_inj |
5330 |
1 |
|
|
T2 |
13 |
|
T3 |
5 |
|
T5 |
9 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52932 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1825 |
1 |
|
|
T11 |
11 |
|
T4 |
12 |
|
T16 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54103 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
654 |
1 |
|
|
T15 |
25 |
|
T63 |
14 |
|
T67 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37990 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[1] |
16767 |
1 |
|
|
T3 |
10 |
|
T4 |
91 |
|
T5 |
9 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52703 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
2054 |
1 |
|
|
T12 |
6 |
|
T27 |
1 |
|
T38 |
8 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52689 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
9 |
auto[1] |
2068 |
1 |
|
|
T3 |
1 |
|
T12 |
8 |
|
T27 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52750 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
2007 |
1 |
|
|
T12 |
7 |
|
T27 |
1 |
|
T38 |
4 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52929 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1828 |
1 |
|
|
T11 |
12 |
|
T4 |
20 |
|
T16 |
8 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52527 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
2230 |
1 |
|
|
T26 |
16 |
|
T66 |
14 |
|
T46 |
18 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54059 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
698 |
1 |
|
|
T15 |
15 |
|
T63 |
17 |
|
T67 |
15 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54109 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
648 |
1 |
|
|
T15 |
16 |
|
T63 |
20 |
|
T67 |
17 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54176 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
581 |
1 |
|
|
T15 |
14 |
|
T63 |
18 |
|
T67 |
9 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51965 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[1] |
2792 |
1 |
|
|
T3 |
10 |
|
T27 |
10 |
|
T46 |
66 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51081 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
3676 |
1 |
|
|
T10 |
100 |
|
T22 |
89 |
|
T17 |
60 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52769 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
9 |
auto[1] |
1988 |
1 |
|
|
T3 |
1 |
|
T12 |
10 |
|
T27 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52738 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
9 |
auto[1] |
2019 |
1 |
|
|
T3 |
1 |
|
T12 |
8 |
|
T27 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52728 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
9 |
auto[1] |
2029 |
1 |
|
|
T3 |
1 |
|
T12 |
5 |
|
T38 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52866 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1891 |
1 |
|
|
T11 |
10 |
|
T4 |
7 |
|
T16 |
13 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49227 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
5530 |
1 |
|
|
T11 |
16 |
|
T13 |
60 |
|
T25 |
85 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51062 |
1 |
|
|
T2 |
13 |
|
T3 |
10 |
|
T10 |
100 |
auto[1] |
3695 |
1 |
|
|
T1 |
50 |
|
T23 |
91 |
|
T19 |
78 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54757 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52940 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1817 |
1 |
|
|
T11 |
9 |
|
T4 |
5 |
|
T16 |
12 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52942 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1815 |
1 |
|
|
T11 |
6 |
|
T4 |
14 |
|
T16 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52981 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1776 |
1 |
|
|
T11 |
14 |
|
T4 |
11 |
|
T16 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48015 |
1 |
|
|
T1 |
50 |
|
T10 |
100 |
|
T11 |
88 |
auto[0] |
no_err_inj |
3950 |
1 |
|
|
T2 |
13 |
|
T5 |
9 |
|
T16 |
12 |
auto[1] |
err_inj |
1412 |
1 |
|
|
T3 |
5 |
|
T27 |
8 |
|
T46 |
33 |
auto[1] |
no_err_inj |
1380 |
1 |
|
|
T3 |
5 |
|
T27 |
2 |
|
T46 |
33 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50096 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1869 |
1 |
|
|
T12 |
8 |
|
T38 |
13 |
|
T93 |
12 |
auto[1] |
auto[0] |
2642 |
1 |
|
|
T3 |
9 |
|
T27 |
9 |
|
T46 |
64 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T3 |
1 |
|
T27 |
1 |
|
T46 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50065 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1900 |
1 |
|
|
T12 |
8 |
|
T38 |
5 |
|
T93 |
15 |
auto[1] |
auto[0] |
2624 |
1 |
|
|
T3 |
9 |
|
T27 |
8 |
|
T46 |
63 |
auto[1] |
auto[1] |
168 |
1 |
|
|
T3 |
1 |
|
T27 |
2 |
|
T46 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50080 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1885 |
1 |
|
|
T12 |
5 |
|
T38 |
1 |
|
T93 |
4 |
auto[1] |
auto[0] |
2648 |
1 |
|
|
T3 |
9 |
|
T27 |
10 |
|
T46 |
65 |
auto[1] |
auto[1] |
144 |
1 |
|
|
T3 |
1 |
|
T46 |
1 |
|
T87 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50095 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1870 |
1 |
|
|
T12 |
9 |
|
T38 |
5 |
|
T93 |
9 |
auto[1] |
auto[0] |
2629 |
1 |
|
|
T3 |
10 |
|
T27 |
10 |
|
T46 |
62 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T46 |
4 |
|
T88 |
1 |
|
T89 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50030 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1935 |
1 |
|
|
T12 |
3 |
|
T38 |
7 |
|
T93 |
6 |
auto[1] |
auto[0] |
2656 |
1 |
|
|
T3 |
10 |
|
T27 |
9 |
|
T46 |
62 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T27 |
1 |
|
T46 |
4 |
|
T87 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50071 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1894 |
1 |
|
|
T12 |
8 |
|
T38 |
6 |
|
T93 |
12 |
auto[1] |
auto[0] |
2637 |
1 |
|
|
T3 |
9 |
|
T27 |
9 |
|
T46 |
63 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T3 |
1 |
|
T27 |
1 |
|
T46 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36930 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1060 |
1 |
|
|
T11 |
10 |
|
T16 |
13 |
|
T43 |
12 |
auto[1] |
auto[0] |
16025 |
1 |
|
|
T3 |
10 |
|
T4 |
81 |
|
T5 |
9 |
auto[1] |
auto[1] |
742 |
1 |
|
|
T4 |
10 |
|
T46 |
5 |
|
T91 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36914 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1076 |
1 |
|
|
T11 |
11 |
|
T16 |
9 |
|
T43 |
13 |
auto[1] |
auto[0] |
16018 |
1 |
|
|
T3 |
10 |
|
T4 |
79 |
|
T5 |
9 |
auto[1] |
auto[1] |
749 |
1 |
|
|
T4 |
12 |
|
T46 |
10 |
|
T91 |
5 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36626 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1364 |
1 |
|
|
T66 |
14 |
|
T46 |
18 |
|
T195 |
17 |
auto[1] |
auto[0] |
15901 |
1 |
|
|
T3 |
10 |
|
T4 |
91 |
|
T5 |
9 |
auto[1] |
auto[1] |
866 |
1 |
|
|
T26 |
16 |
|
T196 |
4 |
|
T47 |
26 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36936 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1054 |
1 |
|
|
T11 |
12 |
|
T16 |
8 |
|
T43 |
16 |
auto[1] |
auto[0] |
15993 |
1 |
|
|
T3 |
10 |
|
T4 |
71 |
|
T5 |
9 |
auto[1] |
auto[1] |
774 |
1 |
|
|
T4 |
20 |
|
T46 |
17 |
|
T91 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33254 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
4736 |
1 |
|
|
T11 |
16 |
|
T13 |
60 |
|
T25 |
85 |
auto[1] |
auto[0] |
15973 |
1 |
|
|
T3 |
10 |
|
T4 |
79 |
|
T5 |
9 |
auto[1] |
auto[1] |
794 |
1 |
|
|
T4 |
12 |
|
T46 |
15 |
|
T91 |
5 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36741 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1249 |
1 |
|
|
T12 |
8 |
|
T38 |
13 |
|
T46 |
1 |
auto[1] |
auto[0] |
15997 |
1 |
|
|
T3 |
9 |
|
T4 |
91 |
|
T5 |
9 |
auto[1] |
auto[1] |
770 |
1 |
|
|
T3 |
1 |
|
T27 |
1 |
|
T46 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36798 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T12 |
10 |
|
T38 |
5 |
|
T46 |
4 |
auto[1] |
auto[0] |
15971 |
1 |
|
|
T3 |
9 |
|
T4 |
91 |
|
T5 |
9 |
auto[1] |
auto[1] |
796 |
1 |
|
|
T3 |
1 |
|
T27 |
1 |
|
T46 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36753 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1237 |
1 |
|
|
T12 |
8 |
|
T38 |
5 |
|
T87 |
2 |
auto[1] |
auto[0] |
15936 |
1 |
|
|
T3 |
9 |
|
T4 |
91 |
|
T5 |
9 |
auto[1] |
auto[1] |
831 |
1 |
|
|
T3 |
1 |
|
T27 |
2 |
|
T46 |
3 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36727 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1263 |
1 |
|
|
T12 |
6 |
|
T38 |
8 |
|
T46 |
6 |
auto[1] |
auto[0] |
15976 |
1 |
|
|
T3 |
10 |
|
T4 |
91 |
|
T5 |
9 |
auto[1] |
auto[1] |
791 |
1 |
|
|
T27 |
1 |
|
T46 |
2 |
|
T47 |
45 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36753 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1237 |
1 |
|
|
T12 |
9 |
|
T38 |
5 |
|
T46 |
4 |
auto[1] |
auto[0] |
15971 |
1 |
|
|
T3 |
10 |
|
T4 |
91 |
|
T5 |
9 |
auto[1] |
auto[1] |
796 |
1 |
|
|
T197 |
2 |
|
T47 |
50 |
|
T45 |
14 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36778 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1212 |
1 |
|
|
T12 |
8 |
|
T38 |
6 |
|
T46 |
3 |
auto[1] |
auto[0] |
15930 |
1 |
|
|
T3 |
9 |
|
T4 |
91 |
|
T5 |
9 |
auto[1] |
auto[1] |
837 |
1 |
|
|
T3 |
1 |
|
T27 |
1 |
|
T197 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36955 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1035 |
1 |
|
|
T11 |
14 |
|
T16 |
9 |
|
T43 |
6 |
auto[1] |
auto[0] |
16026 |
1 |
|
|
T3 |
10 |
|
T4 |
80 |
|
T5 |
9 |
auto[1] |
auto[1] |
741 |
1 |
|
|
T4 |
11 |
|
T46 |
12 |
|
T91 |
10 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36957 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1033 |
1 |
|
|
T11 |
6 |
|
T16 |
10 |
|
T43 |
13 |
auto[1] |
auto[0] |
15985 |
1 |
|
|
T3 |
10 |
|
T4 |
77 |
|
T5 |
9 |
auto[1] |
auto[1] |
782 |
1 |
|
|
T4 |
14 |
|
T46 |
14 |
|
T91 |
7 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36325 |
1 |
|
|
T1 |
50 |
|
T2 |
13 |
|
T10 |
100 |
auto[0] |
auto[1] |
1665 |
1 |
|
|
T46 |
38 |
|
T87 |
14 |
|
T88 |
13 |
auto[1] |
auto[0] |
15640 |
1 |
|
|
T4 |
91 |
|
T5 |
9 |
|
T26 |
16 |
auto[1] |
auto[1] |
1127 |
1 |
|
|
T3 |
10 |
|
T27 |
10 |
|
T46 |
28 |