Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105291760

1

T1

17967

T2

3953

T3

34230

auto[1]

1424474

1

T3

98

T10

11246

T11

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105319125

1

T1

17967

T2

3953

T3

34034

auto[1]

1397109

1

T3

294

T10

10492

T11

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7527836	1			T1	4446		T2	1168		T3	1036
auto[IdleSt]	22110061	1			T1	4493		T2	1032		T3	9401
auto[ClkMuxSt]	35421	1			T1	50		T2	12		T3	5
auto[CntIncrSt]	35191	1			T1	50		T2	12		T3	5
auto[CntProgSt]	1660836	1			T1	715		T2	459		T3	178
auto[TransCheckSt]	27520	1			T1	50		T2	12		T3	5
auto[TokenHashSt]	41861164	1			T1	486		T2	128		T3	2296
auto[FlashRmaSt]	35578	1			T1	57		T2	45		T3	29
auto[TokenCheck0St]	12916	1			T1	18		T2	12		T3	5
auto[TokenCheck1St]	9690	1			T1	6		T2	12		T3	5
auto[TransProgSt]	389016	1			T2	431		T3	156		T10	78
auto[PostTransSt]	13070095	1			T1	7596		T2	605		T3	10372
auto[ScrapSt]	248075	1			T2	25		T41	1855		T42	248
auto[EscalateSt]	7031609	1			T3	5004		T10	16464		T11	1442
auto[InvalidSt]	12659065	1			T3	5830		T12	3819		T15	2216

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2161	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12659065	1			T3	5830		T12	3819		T15	2216
EscalateSt	7031609	1			T3	5004		T10	16464		T11	1442
ScrapSt	248075	1			T2	25		T41	1855		T42	248
PostTransSt	13070095	1			T1	7596		T2	605		T3	10372
TransProgSt	389016	1			T2	431		T3	156		T10	78
TokenCheck1St	9690	1			T1	6		T2	12		T3	5
TokenCheck0St	12916	1			T1	18		T2	12		T3	5
FlashRmaSt	35578	1			T1	57		T2	45		T3	29
TokenHashSt	41861164	1			T1	486		T2	128		T3	2296
TransCheckSt	27520	1			T1	50		T2	12		T3	5
CntProgSt	1660836	1			T1	715		T2	459		T3	178
CntIncrSt	35191	1			T1	50		T2	12		T3	5
ClkMuxSt	35421	1			T1	50		T2	12		T3	5
IdleSt	22110061	1			T1	4493		T2	1032		T3	9401
ResetSt	7527836	1			T1	4446		T2	1168		T3	1036
arcs[ResetSt=>IdleSt]	55016	1			T1	51		T2	13		T3	11
arcs[IdleSt=>ScrapSt]	294	1			T2	1		T41	1		T42	3
arcs[IdleSt=>ClkMuxSt]	35249	1			T1	50		T2	12		T3	5
arcs[ClkMuxSt=>CntIncrSt]	35191	1			T1	50		T2	12		T3	5
arcs[CntIncrSt=>PostTransSt]	1817	1			T11	6		T4	14		T16	10
arcs[CntIncrSt=>CntProgSt]	33304	1			T1	50		T2	12		T3	5
arcs[CntProgSt=>PostTransSt]	4633	1			T11	7		T15	17		T4	10
arcs[CntProgSt=>TransCheckSt]	27520	1			T1	50		T2	12		T3	5
arcs[TransCheckSt=>PostTransSt]	3578	1			T1	27		T11	14		T4	11
arcs[TransCheckSt=>TokenHashSt]	23832	1			T1	23		T2	12		T3	5
arcs[TokenHashSt=>PostTransSt]	10145	1			T1	5		T11	35		T13	60
arcs[TokenHashSt=>FlashRmaSt]	13034	1			T1	18		T2	12		T3	5
arcs[FlashRmaSt=>TokenCheck0St]	12916	1			T1	18		T2	12		T3	5
arcs[TokenCheck0St=>PostTransSt]	3205	1			T1	12		T11	10		T15	23
arcs[TokenCheck0St=>TokenCheck1St]	9690	1			T1	6		T2	12		T3	5
arcs[TokenCheck1St=>PostTransSt]	633	1			T1	6		T11	1		T23	9
arcs[TransProgSt=>PostTransSt]	8176	1			T2	12		T3	5		T10	3
arcs[IdleSt=>EscalateSt]	140	1			T53	7		T54	6		T55	6
arcs[ClkMuxSt=>EscalateSt]	58	1			T10	2		T22	2		T52	1
arcs[CntIncrSt=>EscalateSt]	70	1			T10	5		T22	2		T17	2
arcs[CntProgSt=>EscalateSt]	1151	1			T10	29		T22	31		T17	2
arcs[TransCheckSt=>EscalateSt]	110	1			T10	5		T17	13		T52	7
arcs[TokenHashSt=>EscalateSt]	653	1			T10	20		T11	3		T22	17
arcs[FlashRmaSt=>EscalateSt]	118	1			T10	4		T22	5		T17	1
arcs[TokenCheck0St=>EscalateSt]	21	1			T22	1		T53	1		T61	1
arcs[TokenCheck1St=>EscalateSt]	156	1			T10	4		T22	4		T17	1
arcs[TransProgSt=>EscalateSt]	725	1			T10	25		T22	18		T17	8
arcs[PostTransSt=>EscalateSt]	4847	1			T10	3		T11	7		T15	17
arcs[InvalidSt=>EscalateSt]	14944	1			T3	4		T12	52		T15	16

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7527665	1			T1	4446		T2	1168		T3	1036
auto[0]	auto[IdleSt]	22109972	1			T1	4493		T2	1032		T3	9401
auto[0]	auto[ClkMuxSt]	35384	1			T1	50		T2	12		T3	5
auto[0]	auto[CntIncrSt]	35142	1			T1	50		T2	12		T3	5
auto[0]	auto[CntProgSt]	1660066	1			T1	715		T2	459		T3	178
auto[0]	auto[TransCheckSt]	27459	1			T1	50		T2	12		T3	5
auto[0]	auto[TokenHashSt]	41860743	1			T1	486		T2	128		T3	2296
auto[0]	auto[FlashRmaSt]	35491	1			T1	57		T2	45		T3	29
auto[0]	auto[TokenCheck0St]	12906	1			T1	18		T2	12		T3	5
auto[0]	auto[TokenCheck1St]	9585	1			T1	6		T2	12		T3	5
auto[0]	auto[TransProgSt]	388550	1			T2	431		T3	156		T10	61
auto[0]	auto[PostTransSt]	13067615	1			T1	7596		T2	605		T3	10372
auto[0]	auto[ScrapSt]	248043	1			T2	25		T41	1855		T42	248
auto[0]	auto[EscalateSt]	5619539	1			T3	4907		T10	5286		T11	854
auto[0]	auto[InvalidSt]	12651439	1			T3	5829		T12	3787		T15	2205
auto[1]	auto[ResetSt]	171	1			T10	2		T22	8		T17	8
auto[1]	auto[IdleSt]	89	1			T53	5		T54	2		T55	5
auto[1]	auto[ClkMuxSt]	37	1			T10	1		T22	2		T52	1
auto[1]	auto[CntIncrSt]	49	1			T10	3		T22	2		T17	2
auto[1]	auto[CntProgSt]	770	1			T10	19		T22	25		T17	1
auto[1]	auto[TransCheckSt]	61	1			T10	5		T17	5		T52	1
auto[1]	auto[TokenHashSt]	421	1			T10	14		T11	2		T22	13
auto[1]	auto[FlashRmaSt]	87	1			T10	4		T22	4		T17	1
auto[1]	auto[TokenCheck0St]	10	1			T22	1		T53	1		T61	1
auto[1]	auto[TokenCheck1St]	105	1			T10	1		T22	3		T17	1
auto[1]	auto[TransProgSt]	466	1			T10	17		T22	11		T17	6
auto[1]	auto[PostTransSt]	2480	1			T10	2		T11	4		T15	10
auto[1]	auto[ScrapSt]	32	1			T56	2		T57	1		T54	3
auto[1]	auto[EscalateSt]	1412070	1			T3	97		T10	11178		T11	588
auto[1]	auto[InvalidSt]	7626	1			T3	1		T12	32		T15	11

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7527666	1			T1	4446		T2	1168		T3	1036
auto[0]	auto[IdleSt]	22109975	1			T1	4493		T2	1032		T3	9401
auto[0]	auto[ClkMuxSt]	35380	1			T1	50		T2	12		T3	5
auto[0]	auto[CntIncrSt]	35144	1			T1	50		T2	12		T3	5
auto[0]	auto[CntProgSt]	1660066	1			T1	715		T2	459		T3	178
auto[0]	auto[TransCheckSt]	27435	1			T1	50		T2	12		T3	5
auto[0]	auto[TokenHashSt]	41860729	1			T1	486		T2	128		T3	2296
auto[0]	auto[FlashRmaSt]	35504	1			T1	57		T2	45		T3	29
auto[0]	auto[TokenCheck0St]	12902	1			T1	18		T2	12		T3	5
auto[0]	auto[TokenCheck1St]	9581	1			T1	6		T2	12		T3	5
auto[0]	auto[TransProgSt]	388531	1			T2	431		T3	156		T10	60
auto[0]	auto[PostTransSt]	13067670	1			T1	7596		T2	605		T3	10372
auto[0]	auto[ScrapSt]	248044	1			T2	25		T41	1855		T42	248
auto[0]	auto[EscalateSt]	5646590	1			T3	4713		T10	6035		T11	1050
auto[0]	auto[InvalidSt]	12651747	1			T3	5827		T12	3799		T15	2211
auto[1]	auto[ResetSt]	170	1			T10	2		T22	4		T17	7
auto[1]	auto[IdleSt]	86	1			T53	4		T54	5		T55	3
auto[1]	auto[ClkMuxSt]	41	1			T10	1		T22	1		T163	2
auto[1]	auto[CntIncrSt]	47	1			T10	4		T22	2		T17	1
auto[1]	auto[CntProgSt]	770	1			T10	21		T22	17		T17	2
auto[1]	auto[TransCheckSt]	85	1			T10	2		T17	11		T52	6
auto[1]	auto[TokenHashSt]	435	1			T10	9		T11	1		T22	7
auto[1]	auto[FlashRmaSt]	74	1			T10	2		T22	3		T163	1
auto[1]	auto[TokenCheck0St]	14	1			T53	1		T192	2		T193	1
auto[1]	auto[TokenCheck1St]	109	1			T10	3		T22	4		T52	2
auto[1]	auto[TransProgSt]	485	1			T10	18		T22	13		T17	5
auto[1]	auto[PostTransSt]	2425	1			T10	1		T11	3		T15	7
auto[1]	auto[ScrapSt]	31	1			T56	2		T194	1		T61	1
auto[1]	auto[EscalateSt]	1385019	1			T3	291		T10	10429		T11	392
auto[1]	auto[InvalidSt]	7318	1			T3	3		T12	20		T15	5