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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 97.92 96.03 93.40 100.00 98.52 98.51 96.29


Total test records in report: 997
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T812 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2873629037 Jul 17 07:45:29 PM PDT 24 Jul 17 07:45:39 PM PDT 24 263541214 ps
T813 /workspace/coverage/default/21.lc_ctrl_errors.721039413 Jul 17 07:45:58 PM PDT 24 Jul 17 07:46:16 PM PDT 24 520696531 ps
T156 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2468761156 Jul 17 07:45:22 PM PDT 24 Jul 17 07:50:51 PM PDT 24 61490114588 ps
T814 /workspace/coverage/default/40.lc_ctrl_errors.872451546 Jul 17 07:47:11 PM PDT 24 Jul 17 07:47:29 PM PDT 24 2070624102 ps
T188 /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.525969728 Jul 17 07:46:02 PM PDT 24 Jul 17 07:49:56 PM PDT 24 74786457848 ps
T157 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2027869021 Jul 17 07:45:58 PM PDT 24 Jul 17 08:02:30 PM PDT 24 31382296130 ps
T815 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2510420997 Jul 17 07:46:44 PM PDT 24 Jul 17 07:47:01 PM PDT 24 757051302 ps
T816 /workspace/coverage/default/7.lc_ctrl_sec_mubi.1280406995 Jul 17 07:47:58 PM PDT 24 Jul 17 07:48:08 PM PDT 24 255805981 ps
T817 /workspace/coverage/default/17.lc_ctrl_stress_all.686386828 Jul 17 07:45:29 PM PDT 24 Jul 17 07:46:27 PM PDT 24 5490575804 ps
T190 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.30569804 Jul 17 07:43:31 PM PDT 24 Jul 17 07:43:34 PM PDT 24 11994996 ps
T818 /workspace/coverage/default/4.lc_ctrl_smoke.483099502 Jul 17 07:43:26 PM PDT 24 Jul 17 07:43:28 PM PDT 24 39428202 ps
T819 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2021876251 Jul 17 07:47:31 PM PDT 24 Jul 17 07:47:44 PM PDT 24 258728723 ps
T820 /workspace/coverage/default/13.lc_ctrl_jtag_errors.2430881169 Jul 17 07:45:20 PM PDT 24 Jul 17 07:45:50 PM PDT 24 4599741865 ps
T821 /workspace/coverage/default/5.lc_ctrl_state_post_trans.4264927648 Jul 17 07:43:30 PM PDT 24 Jul 17 07:43:39 PM PDT 24 186440659 ps
T822 /workspace/coverage/default/8.lc_ctrl_prog_failure.2192061456 Jul 17 07:44:53 PM PDT 24 Jul 17 07:45:00 PM PDT 24 211201469 ps
T823 /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2637918870 Jul 17 07:47:37 PM PDT 24 Jul 17 07:47:40 PM PDT 24 20489846 ps
T824 /workspace/coverage/default/15.lc_ctrl_smoke.2063024508 Jul 17 07:45:27 PM PDT 24 Jul 17 07:45:32 PM PDT 24 41269253 ps
T825 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4003909575 Jul 17 07:42:47 PM PDT 24 Jul 17 07:43:39 PM PDT 24 8368109748 ps
T826 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.989106114 Jul 17 07:45:59 PM PDT 24 Jul 17 07:46:06 PM PDT 24 13212548 ps
T827 /workspace/coverage/default/38.lc_ctrl_state_post_trans.4135545701 Jul 17 07:47:09 PM PDT 24 Jul 17 07:47:21 PM PDT 24 305169687 ps
T95 /workspace/coverage/default/1.lc_ctrl_sec_cm.3254570789 Jul 17 07:42:41 PM PDT 24 Jul 17 07:43:07 PM PDT 24 276069805 ps
T828 /workspace/coverage/default/4.lc_ctrl_stress_all.2421859260 Jul 17 07:43:28 PM PDT 24 Jul 17 07:48:23 PM PDT 24 32090079044 ps
T829 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3026079144 Jul 17 07:45:33 PM PDT 24 Jul 17 07:45:44 PM PDT 24 194023523 ps
T830 /workspace/coverage/default/4.lc_ctrl_jtag_errors.1248287458 Jul 17 07:43:30 PM PDT 24 Jul 17 07:44:27 PM PDT 24 7752618295 ps
T831 /workspace/coverage/default/32.lc_ctrl_stress_all.3820427726 Jul 17 07:46:49 PM PDT 24 Jul 17 07:48:51 PM PDT 24 5433174874 ps
T832 /workspace/coverage/default/23.lc_ctrl_state_failure.3543466527 Jul 17 07:46:02 PM PDT 24 Jul 17 07:46:29 PM PDT 24 602535925 ps
T833 /workspace/coverage/default/33.lc_ctrl_jtag_access.1338248536 Jul 17 07:46:50 PM PDT 24 Jul 17 07:47:14 PM PDT 24 9783763462 ps
T834 /workspace/coverage/default/35.lc_ctrl_stress_all.899691209 Jul 17 07:47:06 PM PDT 24 Jul 17 07:48:57 PM PDT 24 4495152959 ps
T835 /workspace/coverage/default/17.lc_ctrl_prog_failure.1910541442 Jul 17 07:45:22 PM PDT 24 Jul 17 07:45:26 PM PDT 24 29616973 ps
T836 /workspace/coverage/default/20.lc_ctrl_security_escalation.449123044 Jul 17 07:45:58 PM PDT 24 Jul 17 07:46:13 PM PDT 24 3634251497 ps
T837 /workspace/coverage/default/33.lc_ctrl_security_escalation.2579885194 Jul 17 07:46:47 PM PDT 24 Jul 17 07:47:01 PM PDT 24 2886786382 ps
T838 /workspace/coverage/default/35.lc_ctrl_jtag_access.3225853390 Jul 17 07:46:45 PM PDT 24 Jul 17 07:46:49 PM PDT 24 74224395 ps
T839 /workspace/coverage/default/41.lc_ctrl_sec_mubi.3058476125 Jul 17 07:47:14 PM PDT 24 Jul 17 07:47:31 PM PDT 24 1135779537 ps
T840 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.947767626 Jul 17 07:42:56 PM PDT 24 Jul 17 07:43:02 PM PDT 24 605903036 ps
T841 /workspace/coverage/default/15.lc_ctrl_stress_all.955920984 Jul 17 07:45:33 PM PDT 24 Jul 17 07:49:09 PM PDT 24 147155598506 ps
T842 /workspace/coverage/default/5.lc_ctrl_jtag_priority.617351931 Jul 17 07:43:28 PM PDT 24 Jul 17 07:43:33 PM PDT 24 269919961 ps
T843 /workspace/coverage/default/26.lc_ctrl_errors.818066058 Jul 17 07:46:18 PM PDT 24 Jul 17 07:46:33 PM PDT 24 978420515 ps
T844 /workspace/coverage/default/29.lc_ctrl_jtag_access.1338049217 Jul 17 07:46:44 PM PDT 24 Jul 17 07:47:00 PM PDT 24 474925027 ps
T845 /workspace/coverage/default/33.lc_ctrl_errors.1864823345 Jul 17 07:46:47 PM PDT 24 Jul 17 07:47:06 PM PDT 24 433892179 ps
T846 /workspace/coverage/default/25.lc_ctrl_errors.2090325538 Jul 17 07:46:02 PM PDT 24 Jul 17 07:46:21 PM PDT 24 541849276 ps
T847 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.479569886 Jul 17 07:42:55 PM PDT 24 Jul 17 07:44:07 PM PDT 24 14119738184 ps
T848 /workspace/coverage/default/16.lc_ctrl_smoke.2135216531 Jul 17 07:45:33 PM PDT 24 Jul 17 07:45:37 PM PDT 24 11292197 ps
T849 /workspace/coverage/default/2.lc_ctrl_alert_test.1180289975 Jul 17 07:42:56 PM PDT 24 Jul 17 07:42:58 PM PDT 24 18850770 ps
T850 /workspace/coverage/default/10.lc_ctrl_smoke.1111857406 Jul 17 07:44:48 PM PDT 24 Jul 17 07:44:52 PM PDT 24 60840597 ps
T851 /workspace/coverage/default/12.lc_ctrl_state_post_trans.3074432404 Jul 17 07:44:56 PM PDT 24 Jul 17 07:45:03 PM PDT 24 78063271 ps
T852 /workspace/coverage/default/15.lc_ctrl_security_escalation.342950527 Jul 17 07:45:29 PM PDT 24 Jul 17 07:45:40 PM PDT 24 1154585087 ps
T853 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2028677716 Jul 17 07:44:51 PM PDT 24 Jul 17 07:45:04 PM PDT 24 1319003091 ps
T854 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3247104166 Jul 17 07:44:52 PM PDT 24 Jul 17 07:45:09 PM PDT 24 342473167 ps
T855 /workspace/coverage/default/7.lc_ctrl_prog_failure.2118138749 Jul 17 07:44:50 PM PDT 24 Jul 17 07:44:56 PM PDT 24 173273566 ps
T74 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2970163593 Jul 17 07:43:33 PM PDT 24 Jul 17 07:43:35 PM PDT 24 13539771 ps
T856 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3215675603 Jul 17 07:45:29 PM PDT 24 Jul 17 07:46:35 PM PDT 24 11901834617 ps
T857 /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2705382213 Jul 17 07:43:31 PM PDT 24 Jul 17 07:43:34 PM PDT 24 24530191 ps
T858 /workspace/coverage/default/17.lc_ctrl_jtag_errors.4186023369 Jul 17 07:45:27 PM PDT 24 Jul 17 07:45:55 PM PDT 24 16367569654 ps
T859 /workspace/coverage/default/1.lc_ctrl_stress_all.2597216246 Jul 17 07:42:55 PM PDT 24 Jul 17 07:44:27 PM PDT 24 17177535206 ps
T860 /workspace/coverage/default/21.lc_ctrl_smoke.661280004 Jul 17 07:45:58 PM PDT 24 Jul 17 07:46:05 PM PDT 24 63218306 ps
T861 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1727926131 Jul 17 07:47:26 PM PDT 24 Jul 17 07:47:37 PM PDT 24 360151084 ps
T862 /workspace/coverage/default/24.lc_ctrl_prog_failure.1022499329 Jul 17 07:45:57 PM PDT 24 Jul 17 07:46:05 PM PDT 24 166948516 ps
T863 /workspace/coverage/default/31.lc_ctrl_prog_failure.314798679 Jul 17 07:46:44 PM PDT 24 Jul 17 07:46:49 PM PDT 24 302786845 ps
T864 /workspace/coverage/default/2.lc_ctrl_sec_mubi.2321149035 Jul 17 07:42:54 PM PDT 24 Jul 17 07:43:08 PM PDT 24 707442543 ps
T865 /workspace/coverage/default/34.lc_ctrl_jtag_access.1309197359 Jul 17 07:46:47 PM PDT 24 Jul 17 07:46:57 PM PDT 24 886454922 ps
T866 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3875259932 Jul 17 07:45:59 PM PDT 24 Jul 17 07:46:56 PM PDT 24 20207579592 ps
T867 /workspace/coverage/default/14.lc_ctrl_security_escalation.2155325867 Jul 17 07:45:23 PM PDT 24 Jul 17 07:45:33 PM PDT 24 954555315 ps
T111 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1006293065 Jul 17 06:16:45 PM PDT 24 Jul 17 06:16:47 PM PDT 24 17360609 ps
T105 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3014489763 Jul 17 06:16:39 PM PDT 24 Jul 17 06:16:41 PM PDT 24 188008162 ps
T112 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3965059751 Jul 17 06:17:27 PM PDT 24 Jul 17 06:17:29 PM PDT 24 24149205 ps
T117 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3802829245 Jul 17 06:17:20 PM PDT 24 Jul 17 06:17:22 PM PDT 24 23006748 ps
T113 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1484280236 Jul 17 06:16:36 PM PDT 24 Jul 17 06:16:38 PM PDT 24 50328898 ps
T108 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.489785467 Jul 17 06:17:29 PM PDT 24 Jul 17 06:17:32 PM PDT 24 27363822 ps
T868 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1578899199 Jul 17 06:16:56 PM PDT 24 Jul 17 06:16:59 PM PDT 24 59832961 ps
T869 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2186632046 Jul 17 06:21:45 PM PDT 24 Jul 17 06:21:46 PM PDT 24 35677405 ps
T143 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3004992107 Jul 17 06:16:45 PM PDT 24 Jul 17 06:16:48 PM PDT 24 96570699 ps
T106 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1532152319 Jul 17 06:17:22 PM PDT 24 Jul 17 06:17:26 PM PDT 24 237419520 ps
T144 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2335373199 Jul 17 06:16:55 PM PDT 24 Jul 17 06:16:58 PM PDT 24 104667995 ps
T127 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2131998563 Jul 17 06:22:06 PM PDT 24 Jul 17 06:22:08 PM PDT 24 41187811 ps
T139 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2558244956 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:13 PM PDT 24 111423344 ps
T166 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2220137393 Jul 17 06:17:29 PM PDT 24 Jul 17 06:17:31 PM PDT 24 50371158 ps
T167 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1404920957 Jul 17 06:16:53 PM PDT 24 Jul 17 06:16:57 PM PDT 24 414065620 ps
T870 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3546694339 Jul 17 06:21:49 PM PDT 24 Jul 17 06:21:50 PM PDT 24 33177525 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.488324823 Jul 17 06:17:22 PM PDT 24 Jul 17 06:17:25 PM PDT 24 24075220 ps
T187 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2066552614 Jul 17 06:21:44 PM PDT 24 Jul 17 06:21:51 PM PDT 24 484960280 ps
T107 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1632250887 Jul 17 06:21:44 PM PDT 24 Jul 17 06:21:48 PM PDT 24 76540291 ps
T128 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1241513433 Jul 17 06:16:45 PM PDT 24 Jul 17 06:16:49 PM PDT 24 63656242 ps
T116 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1042138102 Jul 17 06:17:11 PM PDT 24 Jul 17 06:17:14 PM PDT 24 77013777 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4059005431 Jul 17 06:16:54 PM PDT 24 Jul 17 06:16:56 PM PDT 24 42521765 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.303469015 Jul 17 06:16:43 PM PDT 24 Jul 17 06:16:46 PM PDT 24 143029977 ps
T873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2466121916 Jul 17 06:16:54 PM PDT 24 Jul 17 06:17:07 PM PDT 24 1102552209 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1684698349 Jul 17 06:16:54 PM PDT 24 Jul 17 06:16:56 PM PDT 24 97503215 ps
T875 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2122163375 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:45 PM PDT 24 1940636202 ps
T876 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1639658058 Jul 17 06:17:06 PM PDT 24 Jul 17 06:17:07 PM PDT 24 42855533 ps
T179 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3096407200 Jul 17 06:16:38 PM PDT 24 Jul 17 06:16:40 PM PDT 24 75887476 ps
T158 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.703016908 Jul 17 06:17:16 PM PDT 24 Jul 17 06:17:19 PM PDT 24 34408149 ps
T180 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3813010525 Jul 17 06:16:49 PM PDT 24 Jul 17 06:16:50 PM PDT 24 70130462 ps
T877 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2573286591 Jul 17 06:21:30 PM PDT 24 Jul 17 06:21:32 PM PDT 24 37570148 ps
T109 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3472944519 Jul 17 06:16:43 PM PDT 24 Jul 17 06:16:47 PM PDT 24 447807350 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1891816058 Jul 17 06:21:45 PM PDT 24 Jul 17 06:21:46 PM PDT 24 20181306 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2049585626 Jul 17 06:21:49 PM PDT 24 Jul 17 06:21:52 PM PDT 24 107759692 ps
T140 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1256838930 Jul 17 06:22:14 PM PDT 24 Jul 17 06:22:17 PM PDT 24 1000918350 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4073454474 Jul 17 06:16:54 PM PDT 24 Jul 17 06:16:56 PM PDT 24 14777068 ps
T881 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3671965194 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:42 PM PDT 24 38138988 ps
T141 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1757803216 Jul 17 06:22:01 PM PDT 24 Jul 17 06:22:05 PM PDT 24 478675369 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3873225414 Jul 17 06:16:49 PM PDT 24 Jul 17 06:16:53 PM PDT 24 142795702 ps
T110 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2981868785 Jul 17 06:17:22 PM PDT 24 Jul 17 06:17:26 PM PDT 24 629331514 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1213403425 Jul 17 06:21:44 PM PDT 24 Jul 17 06:21:46 PM PDT 24 43438326 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3120680618 Jul 17 06:16:38 PM PDT 24 Jul 17 06:16:40 PM PDT 24 291428665 ps
T181 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1571810826 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:13 PM PDT 24 42860828 ps
T121 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2314928369 Jul 17 06:16:41 PM PDT 24 Jul 17 06:16:43 PM PDT 24 19732649 ps
T182 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.642483852 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:11 PM PDT 24 17971778 ps
T885 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4290379153 Jul 17 06:16:42 PM PDT 24 Jul 17 06:16:45 PM PDT 24 224448666 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3450883376 Jul 17 06:21:49 PM PDT 24 Jul 17 06:21:53 PM PDT 24 325494013 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1723559060 Jul 17 06:16:43 PM PDT 24 Jul 17 06:16:45 PM PDT 24 27621309 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.530847865 Jul 17 06:16:55 PM PDT 24 Jul 17 06:17:20 PM PDT 24 7206430641 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1405899088 Jul 17 06:16:38 PM PDT 24 Jul 17 06:16:40 PM PDT 24 118170099 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2849601521 Jul 17 06:16:43 PM PDT 24 Jul 17 06:16:45 PM PDT 24 125243436 ps
T174 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3036560453 Jul 17 06:16:36 PM PDT 24 Jul 17 06:16:37 PM PDT 24 40266673 ps
T183 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1979174749 Jul 17 06:23:06 PM PDT 24 Jul 17 06:23:09 PM PDT 24 97068241 ps
T184 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1776286371 Jul 17 06:16:49 PM PDT 24 Jul 17 06:16:51 PM PDT 24 87148348 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3938065991 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:16 PM PDT 24 107099394 ps
T185 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.227167819 Jul 17 06:17:22 PM PDT 24 Jul 17 06:17:24 PM PDT 24 13646823 ps
T892 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3063697543 Jul 17 06:17:30 PM PDT 24 Jul 17 06:17:32 PM PDT 24 16149820 ps
T114 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.256660934 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:16 PM PDT 24 302420457 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2510960779 Jul 17 06:16:49 PM PDT 24 Jul 17 06:16:50 PM PDT 24 14887658 ps
T894 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2427718675 Jul 17 06:16:41 PM PDT 24 Jul 17 06:16:44 PM PDT 24 29321856 ps
T895 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3979793942 Jul 17 06:17:16 PM PDT 24 Jul 17 06:17:19 PM PDT 24 100467987 ps
T896 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4122066124 Jul 17 06:16:42 PM PDT 24 Jul 17 06:16:45 PM PDT 24 154823513 ps
T130 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.136086107 Jul 17 06:17:07 PM PDT 24 Jul 17 06:17:12 PM PDT 24 425477109 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1782184156 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:00 PM PDT 24 67852035 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1751094897 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:14 PM PDT 24 89120072 ps
T898 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.495319032 Jul 17 06:17:08 PM PDT 24 Jul 17 06:17:11 PM PDT 24 21230791 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1449563422 Jul 17 06:22:13 PM PDT 24 Jul 17 06:22:15 PM PDT 24 401195584 ps
T900 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2484935005 Jul 17 06:17:08 PM PDT 24 Jul 17 06:17:14 PM PDT 24 356059241 ps
T901 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.674250633 Jul 17 06:16:56 PM PDT 24 Jul 17 06:17:12 PM PDT 24 2370918503 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2671520214 Jul 17 06:16:52 PM PDT 24 Jul 17 06:16:55 PM PDT 24 21548877 ps
T903 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.957099891 Jul 17 06:17:04 PM PDT 24 Jul 17 06:17:06 PM PDT 24 190916141 ps
T904 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4102493072 Jul 17 06:17:16 PM PDT 24 Jul 17 06:17:17 PM PDT 24 26925127 ps
T133 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.787650840 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:17 PM PDT 24 49376748 ps
T905 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.159609337 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:17 PM PDT 24 431349455 ps
T118 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2595963311 Jul 17 06:16:57 PM PDT 24 Jul 17 06:17:02 PM PDT 24 2121478403 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.618280583 Jul 17 06:16:56 PM PDT 24 Jul 17 06:16:59 PM PDT 24 31518393 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1443458099 Jul 17 06:22:06 PM PDT 24 Jul 17 06:22:08 PM PDT 24 211158585 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.566593516 Jul 17 06:16:49 PM PDT 24 Jul 17 06:16:51 PM PDT 24 23442425 ps
T909 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3020692492 Jul 17 06:17:18 PM PDT 24 Jul 17 06:17:20 PM PDT 24 25725714 ps
T910 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3639212491 Jul 17 06:21:49 PM PDT 24 Jul 17 06:21:52 PM PDT 24 694720325 ps
T125 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1913350823 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:14 PM PDT 24 206603931 ps
T137 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2681302271 Jul 17 06:17:15 PM PDT 24 Jul 17 06:17:20 PM PDT 24 470436922 ps
T175 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3723870757 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:42 PM PDT 24 21535091 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1207175563 Jul 17 06:16:38 PM PDT 24 Jul 17 06:16:40 PM PDT 24 92710005 ps
T132 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.986557084 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:15 PM PDT 24 93253878 ps
T912 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.564688713 Jul 17 06:17:04 PM PDT 24 Jul 17 06:17:06 PM PDT 24 50165826 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3646071937 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:46 PM PDT 24 357653908 ps
T914 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1904681702 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:17 PM PDT 24 24990839 ps
T915 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4001168330 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:13 PM PDT 24 78495785 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2433331860 Jul 17 06:22:12 PM PDT 24 Jul 17 06:22:16 PM PDT 24 507657254 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.367132678 Jul 17 06:16:55 PM PDT 24 Jul 17 06:16:59 PM PDT 24 224963770 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.262977240 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:13 PM PDT 24 45699642 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3883290196 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:12 PM PDT 24 24178077 ps
T920 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3162491606 Jul 17 06:16:52 PM PDT 24 Jul 17 06:17:07 PM PDT 24 517215350 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1924808422 Jul 17 06:22:06 PM PDT 24 Jul 17 06:22:09 PM PDT 24 160574056 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3693260654 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:04 PM PDT 24 2147373948 ps
T122 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.643787539 Jul 17 06:23:00 PM PDT 24 Jul 17 06:23:03 PM PDT 24 480056199 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2684995601 Jul 17 06:21:49 PM PDT 24 Jul 17 06:21:51 PM PDT 24 20984979 ps
T924 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3437360597 Jul 17 06:17:12 PM PDT 24 Jul 17 06:17:16 PM PDT 24 38133148 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2650535064 Jul 17 06:16:43 PM PDT 24 Jul 17 06:16:45 PM PDT 24 61213112 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3419969870 Jul 17 06:16:41 PM PDT 24 Jul 17 06:16:50 PM PDT 24 873600991 ps
T927 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3512715795 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:14 PM PDT 24 20026435 ps
T928 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.601951905 Jul 17 06:16:55 PM PDT 24 Jul 17 06:16:58 PM PDT 24 147593461 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2433176763 Jul 17 06:17:07 PM PDT 24 Jul 17 06:17:09 PM PDT 24 154887377 ps
T138 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1709768137 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:14 PM PDT 24 42728510 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4249029260 Jul 17 06:16:52 PM PDT 24 Jul 17 06:16:54 PM PDT 24 20247687 ps
T931 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.26361273 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:16 PM PDT 24 43166291 ps
T932 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1919189524 Jul 17 06:17:08 PM PDT 24 Jul 17 06:17:10 PM PDT 24 28336349 ps
T933 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1055779704 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:48 PM PDT 24 922645056 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2141919829 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:43 PM PDT 24 88462515 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1152813902 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:01 PM PDT 24 204998476 ps
T123 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.590710433 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:17 PM PDT 24 257065717 ps
T936 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1580280978 Jul 17 06:22:13 PM PDT 24 Jul 17 06:22:15 PM PDT 24 44237566 ps
T937 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3836119659 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:56 PM PDT 24 765346380 ps
T938 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2752325474 Jul 17 06:17:07 PM PDT 24 Jul 17 06:17:12 PM PDT 24 149592921 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3795828754 Jul 17 06:16:42 PM PDT 24 Jul 17 06:16:45 PM PDT 24 136658666 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1002128168 Jul 17 06:21:37 PM PDT 24 Jul 17 06:21:38 PM PDT 24 38168164 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1732270533 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:02 PM PDT 24 293813613 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1618302861 Jul 17 06:16:49 PM PDT 24 Jul 17 06:16:52 PM PDT 24 53196839 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2992075499 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:12 PM PDT 24 823381372 ps
T943 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3063161614 Jul 17 06:16:42 PM PDT 24 Jul 17 06:16:46 PM PDT 24 819601240 ps
T944 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1849063430 Jul 17 06:21:50 PM PDT 24 Jul 17 06:22:14 PM PDT 24 4459599002 ps
T945 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.804661465 Jul 17 06:17:21 PM PDT 24 Jul 17 06:17:24 PM PDT 24 56614456 ps
T119 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3836278349 Jul 17 06:21:46 PM PDT 24 Jul 17 06:21:50 PM PDT 24 76140497 ps
T176 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.356813516 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:13 PM PDT 24 12268461 ps
T135 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1397267660 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:43 PM PDT 24 238858032 ps
T946 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2713702789 Jul 17 06:17:16 PM PDT 24 Jul 17 06:17:21 PM PDT 24 486587456 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.482342247 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:03 PM PDT 24 233291777 ps
T948 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3531388479 Jul 17 06:19:48 PM PDT 24 Jul 17 06:19:50 PM PDT 24 48378739 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4116197122 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:12 PM PDT 24 42829521 ps
T950 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2809251002 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:11 PM PDT 24 89590131 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2458610378 Jul 17 06:23:18 PM PDT 24 Jul 17 06:23:20 PM PDT 24 21561972 ps
T952 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.52362072 Jul 17 06:16:37 PM PDT 24 Jul 17 06:16:40 PM PDT 24 296252018 ps
T953 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4162175572 Jul 17 06:16:54 PM PDT 24 Jul 17 06:16:55 PM PDT 24 46583606 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2817412217 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:12 PM PDT 24 12631312034 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2843546920 Jul 17 06:17:20 PM PDT 24 Jul 17 06:17:24 PM PDT 24 105728233 ps
T955 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.147333966 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:15 PM PDT 24 107321111 ps
T956 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1021000747 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:14 PM PDT 24 420572508 ps
T957 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.279405752 Jul 17 06:17:21 PM PDT 24 Jul 17 06:17:23 PM PDT 24 45989569 ps
T958 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1754966314 Jul 17 06:17:26 PM PDT 24 Jul 17 06:17:29 PM PDT 24 28362605 ps
T177 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1231643718 Jul 17 06:16:55 PM PDT 24 Jul 17 06:16:57 PM PDT 24 14157382 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1610502285 Jul 17 06:16:43 PM PDT 24 Jul 17 06:16:45 PM PDT 24 23855566 ps
T960 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3297898534 Jul 17 06:17:07 PM PDT 24 Jul 17 06:17:11 PM PDT 24 264220319 ps
T961 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4044497653 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:17 PM PDT 24 26646118 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3809909780 Jul 17 06:17:08 PM PDT 24 Jul 17 06:17:10 PM PDT 24 18610116 ps
T963 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3913342271 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:02 PM PDT 24 299049422 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3964012154 Jul 17 06:17:12 PM PDT 24 Jul 17 06:17:15 PM PDT 24 52147741 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3247822763 Jul 17 06:23:07 PM PDT 24 Jul 17 06:23:12 PM PDT 24 498945704 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.543036626 Jul 17 06:16:42 PM PDT 24 Jul 17 06:16:46 PM PDT 24 403581050 ps
T967 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.638170904 Jul 17 06:16:56 PM PDT 24 Jul 17 06:16:59 PM PDT 24 39811103 ps
T968 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1402871160 Jul 17 06:21:46 PM PDT 24 Jul 17 06:21:48 PM PDT 24 34013781 ps
T969 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.545587827 Jul 17 06:16:54 PM PDT 24 Jul 17 06:16:56 PM PDT 24 17572320 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3490215538 Jul 17 06:16:54 PM PDT 24 Jul 17 06:16:56 PM PDT 24 161820604 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.453213899 Jul 17 06:16:37 PM PDT 24 Jul 17 06:16:44 PM PDT 24 977399623 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1501574317 Jul 17 06:23:01 PM PDT 24 Jul 17 06:23:03 PM PDT 24 24969385 ps
T178 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1849498055 Jul 17 06:17:11 PM PDT 24 Jul 17 06:17:13 PM PDT 24 11709962 ps
T973 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3551953025 Jul 17 06:17:22 PM PDT 24 Jul 17 06:17:25 PM PDT 24 136163722 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2966093668 Jul 17 06:16:55 PM PDT 24 Jul 17 06:17:01 PM PDT 24 140542887 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.723375888 Jul 17 06:16:48 PM PDT 24 Jul 17 06:16:50 PM PDT 24 413144766 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1964052659 Jul 17 06:21:49 PM PDT 24 Jul 17 06:21:53 PM PDT 24 342922826 ps
T977 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2522019490 Jul 17 06:16:38 PM PDT 24 Jul 17 06:16:40 PM PDT 24 62808413 ps
T978 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1362408664 Jul 17 06:16:38 PM PDT 24 Jul 17 06:16:41 PM PDT 24 47689447 ps
T131 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3998660741 Jul 17 06:16:56 PM PDT 24 Jul 17 06:16:59 PM PDT 24 162676063 ps
T979 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.668216459 Jul 17 06:17:11 PM PDT 24 Jul 17 06:17:13 PM PDT 24 46721972 ps
T980 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1587341402 Jul 17 06:17:16 PM PDT 24 Jul 17 06:17:18 PM PDT 24 18132850 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2846929985 Jul 17 06:17:06 PM PDT 24 Jul 17 06:17:08 PM PDT 24 15282791 ps
T982 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3377582945 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:14 PM PDT 24 38685096 ps
T983 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1162396843 Jul 17 06:17:09 PM PDT 24 Jul 17 06:17:11 PM PDT 24 129289429 ps
T129 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3890224735 Jul 17 06:17:10 PM PDT 24 Jul 17 06:17:14 PM PDT 24 723228695 ps
T984 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.438245678 Jul 17 06:16:41 PM PDT 24 Jul 17 06:16:53 PM PDT 24 4267767489 ps
T985 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3956624528 Jul 17 06:17:07 PM PDT 24 Jul 17 06:17:14 PM PDT 24 375357098 ps
T986 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2161514583 Jul 17 06:21:46 PM PDT 24 Jul 17 06:21:48 PM PDT 24 160741679 ps
T126 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2124964680 Jul 17 06:17:12 PM PDT 24 Jul 17 06:17:17 PM PDT 24 231309372 ps
T987 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3526993255 Jul 17 06:21:58 PM PDT 24 Jul 17 06:22:01 PM PDT 24 64990672 ps
T988 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2788017201 Jul 17 06:17:23 PM PDT 24 Jul 17 06:17:27 PM PDT 24 135077209 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.661365479 Jul 17 06:17:05 PM PDT 24 Jul 17 06:17:07 PM PDT 24 89304443 ps
T990 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1472000642 Jul 17 06:22:14 PM PDT 24 Jul 17 06:22:34 PM PDT 24 4424661009 ps
T991 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4224648551 Jul 17 06:16:52 PM PDT 24 Jul 17 06:16:54 PM PDT 24 62533678 ps
T136 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.35451703 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:17 PM PDT 24 142441295 ps
T992 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1554174585 Jul 17 06:17:12 PM PDT 24 Jul 17 06:17:16 PM PDT 24 115394251 ps
T993 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1835410345 Jul 17 06:16:40 PM PDT 24 Jul 17 06:16:46 PM PDT 24 2050232901 ps
T994 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1525832478 Jul 17 06:17:13 PM PDT 24 Jul 17 06:17:16 PM PDT 24 98703401 ps
T995 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2640773156 Jul 17 06:22:11 PM PDT 24 Jul 17 06:22:13 PM PDT 24 20455952 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3339513773 Jul 17 06:16:55 PM PDT 24 Jul 17 06:16:57 PM PDT 24 26621630 ps
T997 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3894610960 Jul 17 06:16:39 PM PDT 24 Jul 17 06:16:42 PM PDT 24 58464554 ps

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1035592057
Short name T15
Test name
Test status
Simulation time 410116195 ps
CPU time 13.68 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:43:45 PM PDT 24
Peak memory 226016 kb
Host smart-659450c3-a528-4d0e-ab01-e56b14797d62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035592057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1035592057
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.707070630
Short name T4
Test name
Test status
Simulation time 7550920256 ps
CPU time 56.77 seconds
Started Jul 17 07:45:31 PM PDT 24
Finished Jul 17 07:46:31 PM PDT 24
Peak memory 226012 kb
Host smart-3052d9ca-a602-44b9-83d6-f95dee1459dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707070630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.707070630
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2245708519
Short name T17
Test name
Test status
Simulation time 853956417 ps
CPU time 6.12 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:09 PM PDT 24
Peak memory 218284 kb
Host smart-2d23a6a9-a8e3-4383-a5b5-fc97004fc8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245708519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2245708519
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4292776470
Short name T46
Test name
Test status
Simulation time 6069588612 ps
CPU time 190.09 seconds
Started Jul 17 07:47:34 PM PDT 24
Finished Jul 17 07:50:46 PM PDT 24
Peak memory 251032 kb
Host smart-d0c4bfc7-d891-44c9-a85e-08014eb381ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292776470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4292776470
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3476579334
Short name T45
Test name
Test status
Simulation time 46167699053 ps
CPU time 1566.43 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 08:12:56 PM PDT 24
Peak memory 314592 kb
Host smart-f886d951-28a7-4587-9053-491106809556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3476579334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3476579334
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3471185013
Short name T22
Test name
Test status
Simulation time 309539416 ps
CPU time 12.78 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:25 PM PDT 24
Peak memory 225816 kb
Host smart-68a1b702-3606-4137-9020-980ad63c3e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471185013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3471185013
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.489785467
Short name T108
Test name
Test status
Simulation time 27363822 ps
CPU time 1.75 seconds
Started Jul 17 06:17:29 PM PDT 24
Finished Jul 17 06:17:32 PM PDT 24
Peak memory 217344 kb
Host smart-0dee8e31-cc74-49ec-88ec-dd3948bdb0d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489785467 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.489785467
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3644778327
Short name T192
Test name
Test status
Simulation time 393348439 ps
CPU time 10.98 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:47:01 PM PDT 24
Peak memory 218112 kb
Host smart-f45d4f9c-af01-41c7-81e9-72bbee130b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644778327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3644778327
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1090564074
Short name T19
Test name
Test status
Simulation time 580156813 ps
CPU time 17.83 seconds
Started Jul 17 07:43:26 PM PDT 24
Finished Jul 17 07:43:45 PM PDT 24
Peak memory 218212 kb
Host smart-38b80e21-34f5-4c38-bc99-e1577f49775f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090564074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
090564074
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1517821937
Short name T59
Test name
Test status
Simulation time 1246641840 ps
CPU time 38.89 seconds
Started Jul 17 07:42:55 PM PDT 24
Finished Jul 17 07:43:35 PM PDT 24
Peak memory 283640 kb
Host smart-6c57f65b-afa9-4a01-9fe2-f24b4e70a2d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517821937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1517821937
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3924447172
Short name T8
Test name
Test status
Simulation time 1182648233 ps
CPU time 4.54 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 07:47:19 PM PDT 24
Peak memory 217420 kb
Host smart-e85c019d-2ac1-46d4-8393-7ade7562f280
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924447172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3924447172
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.805713855
Short name T16
Test name
Test status
Simulation time 2172875925 ps
CPU time 39.96 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 226044 kb
Host smart-aa42bd74-954c-4210-8e3e-af5d0d101707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805713855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.805713855
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1577820127
Short name T104
Test name
Test status
Simulation time 73348177261 ps
CPU time 749.18 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:59:42 PM PDT 24
Peak memory 405780 kb
Host smart-01a525f9-4a3d-45a4-a3b3-f1427519d50a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1577820127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1577820127
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.22970987
Short name T30
Test name
Test status
Simulation time 41184955 ps
CPU time 1.13 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:44:58 PM PDT 24
Peak memory 208860 kb
Host smart-941205ec-9547-4ba7-bc09-65f026bc96cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22970987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.22970987
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3472944519
Short name T109
Test name
Test status
Simulation time 447807350 ps
CPU time 2.69 seconds
Started Jul 17 06:16:43 PM PDT 24
Finished Jul 17 06:16:47 PM PDT 24
Peak memory 221876 kb
Host smart-1eb20888-b5c2-4d42-9a10-54e3965df5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472944519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3472944519
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.356813516
Short name T176
Test name
Test status
Simulation time 12268461 ps
CPU time 1 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:13 PM PDT 24
Peak memory 208944 kb
Host smart-071f28ea-f090-46f1-ab14-1668b808988d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356813516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.356813516
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2558244956
Short name T139
Test name
Test status
Simulation time 111423344 ps
CPU time 1.72 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:13 PM PDT 24
Peak memory 209036 kb
Host smart-7bf7c922-ea55-494e-b537-718c04c02e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558244956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2558244956
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.136086107
Short name T130
Test name
Test status
Simulation time 425477109 ps
CPU time 3.63 seconds
Started Jul 17 06:17:07 PM PDT 24
Finished Jul 17 06:17:12 PM PDT 24
Peak memory 221636 kb
Host smart-cae15346-cbad-413f-a5de-705923c711f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136086107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.136086107
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.947722107
Short name T20
Test name
Test status
Simulation time 23055503 ps
CPU time 0.85 seconds
Started Jul 17 07:45:19 PM PDT 24
Finished Jul 17 07:45:21 PM PDT 24
Peak memory 211928 kb
Host smart-37c10ddb-4b12-4e8e-91f4-6c1d337bb155
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947722107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.947722107
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1532152319
Short name T106
Test name
Test status
Simulation time 237419520 ps
CPU time 2.77 seconds
Started Jul 17 06:17:22 PM PDT 24
Finished Jul 17 06:17:26 PM PDT 24
Peak memory 217404 kb
Host smart-a6e842e2-73ac-4b9b-9977-9356f9f5ef2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532152319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1532152319
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.4084842923
Short name T49
Test name
Test status
Simulation time 67002048126 ps
CPU time 254.71 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:50:14 PM PDT 24
Peak memory 267452 kb
Host smart-09ad5e7e-eec3-43de-942e-de833b674c84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4084842923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.4084842923
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.643787539
Short name T122
Test name
Test status
Simulation time 480056199 ps
CPU time 2.91 seconds
Started Jul 17 06:23:00 PM PDT 24
Finished Jul 17 06:23:03 PM PDT 24
Peak memory 217208 kb
Host smart-9fb7840d-eeb3-41e4-8f00-43e25eb613a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643787539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.643787539
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1732270533
Short name T134
Test name
Test status
Simulation time 293813613 ps
CPU time 3.7 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:02 PM PDT 24
Peak memory 217212 kb
Host smart-103eb18a-7473-4963-abdd-eaabc5224bfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732270533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1732270533
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1632250887
Short name T107
Test name
Test status
Simulation time 76540291 ps
CPU time 3.33 seconds
Started Jul 17 06:21:44 PM PDT 24
Finished Jul 17 06:21:48 PM PDT 24
Peak memory 217168 kb
Host smart-ea0ed8cd-71cd-4efd-85a5-a886a2937426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632250887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1632250887
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3869981023
Short name T12
Test name
Test status
Simulation time 179905621 ps
CPU time 26.5 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:55 PM PDT 24
Peak memory 250968 kb
Host smart-0101f2bd-c749-48ac-8658-4941a0a04e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869981023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3869981023
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2124964680
Short name T126
Test name
Test status
Simulation time 231309372 ps
CPU time 3.13 seconds
Started Jul 17 06:17:12 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 222044 kb
Host smart-9a025b1d-05e2-4dbe-a15b-856ac001f818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124964680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2124964680
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2681302271
Short name T137
Test name
Test status
Simulation time 470436922 ps
CPU time 4.35 seconds
Started Jul 17 06:17:15 PM PDT 24
Finished Jul 17 06:17:20 PM PDT 24
Peak memory 217212 kb
Host smart-8a2eec0c-1325-487c-9787-43aec6acbd56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681302271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2681302271
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1776286371
Short name T184
Test name
Test status
Simulation time 87148348 ps
CPU time 1.16 seconds
Started Jul 17 06:16:49 PM PDT 24
Finished Jul 17 06:16:51 PM PDT 24
Peak memory 209060 kb
Host smart-52c2fb8e-43d8-4c3a-9c80-2c12ca4bfda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776286371 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1776286371
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1799714531
Short name T14
Test name
Test status
Simulation time 39901256 ps
CPU time 0.8 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:44:50 PM PDT 24
Peak memory 208836 kb
Host smart-944a42cb-0192-4d5e-8611-6e423bd68645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799714531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1799714531
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2829867517
Short name T191
Test name
Test status
Simulation time 11500517 ps
CPU time 0.81 seconds
Started Jul 17 07:42:46 PM PDT 24
Finished Jul 17 07:42:48 PM PDT 24
Peak memory 208736 kb
Host smart-ad1e06f8-204b-420d-8f1f-954392523ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829867517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2829867517
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.30569804
Short name T190
Test name
Test status
Simulation time 11994996 ps
CPU time 0.96 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 208828 kb
Host smart-05cc2b9f-e923-4b10-b69f-794fb163165b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30569804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.30569804
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2970163593
Short name T74
Test name
Test status
Simulation time 13539771 ps
CPU time 1.02 seconds
Started Jul 17 07:43:33 PM PDT 24
Finished Jul 17 07:43:35 PM PDT 24
Peak memory 208792 kb
Host smart-6da402af-4b67-45b9-a3e9-f82d2082958c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970163593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2970163593
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3890224735
Short name T129
Test name
Test status
Simulation time 723228695 ps
CPU time 2.36 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 221288 kb
Host smart-21e55cb3-0bf9-4b56-ab08-ecbac0eb6b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890224735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3890224735
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.590710433
Short name T123
Test name
Test status
Simulation time 257065717 ps
CPU time 2.06 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 221996 kb
Host smart-3e547841-4d7c-40fe-95fe-f15102f77815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590710433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.590710433
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.170700648
Short name T51
Test name
Test status
Simulation time 409079487 ps
CPU time 12.84 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:13 PM PDT 24
Peak memory 218388 kb
Host smart-a4d6ce02-cff2-4603-9f97-57b5cf102324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170700648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.170700648
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.621032142
Short name T25
Test name
Test status
Simulation time 1605782861 ps
CPU time 11.36 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 07:46:59 PM PDT 24
Peak memory 226000 kb
Host smart-e1cc8072-5664-45b1-b566-3d0606ad1a6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621032142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.621032142
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4122066124
Short name T896
Test name
Test status
Simulation time 154823513 ps
CPU time 1.47 seconds
Started Jul 17 06:16:42 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 208956 kb
Host smart-705cbc44-8c8b-4a74-a8e1-e0978bf7fc42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122066124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.4122066124
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1207175563
Short name T911
Test name
Test status
Simulation time 92710005 ps
CPU time 1.53 seconds
Started Jul 17 06:16:38 PM PDT 24
Finished Jul 17 06:16:40 PM PDT 24
Peak memory 208124 kb
Host smart-9130ffdc-939e-49dd-8ba7-83f592db247c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207175563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1207175563
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3723870757
Short name T175
Test name
Test status
Simulation time 21535091 ps
CPU time 1.04 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:42 PM PDT 24
Peak memory 210972 kb
Host smart-27435a01-2107-40b9-8a5d-28d4c1eb3df1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723870757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3723870757
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3120680618
Short name T884
Test name
Test status
Simulation time 291428665 ps
CPU time 1.22 seconds
Started Jul 17 06:16:38 PM PDT 24
Finished Jul 17 06:16:40 PM PDT 24
Peak memory 220876 kb
Host smart-32aeaffa-45a4-4672-9a7c-17f96e42fce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120680618 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3120680618
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1002128168
Short name T940
Test name
Test status
Simulation time 38168164 ps
CPU time 0.94 seconds
Started Jul 17 06:21:37 PM PDT 24
Finished Jul 17 06:21:38 PM PDT 24
Peak memory 208412 kb
Host smart-801b3f3d-8f92-42e0-95a2-508a5f5aff7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002128168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1002128168
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2650535064
Short name T925
Test name
Test status
Simulation time 61213112 ps
CPU time 0.91 seconds
Started Jul 17 06:16:43 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 208776 kb
Host smart-3fc95edf-0dff-421d-8625-4afdf86dc143
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650535064 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2650535064
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1835410345
Short name T993
Test name
Test status
Simulation time 2050232901 ps
CPU time 4.96 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:46 PM PDT 24
Peak memory 208664 kb
Host smart-265e59cf-4435-4dad-919c-1f021dd6b028
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835410345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1835410345
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.438245678
Short name T984
Test name
Test status
Simulation time 4267767489 ps
CPU time 10.53 seconds
Started Jul 17 06:16:41 PM PDT 24
Finished Jul 17 06:16:53 PM PDT 24
Peak memory 208968 kb
Host smart-0f8f20e9-e119-47c2-a907-d1f015a31653
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438245678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.438245678
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1405899088
Short name T889
Test name
Test status
Simulation time 118170099 ps
CPU time 1.58 seconds
Started Jul 17 06:16:38 PM PDT 24
Finished Jul 17 06:16:40 PM PDT 24
Peak memory 210312 kb
Host smart-73dad44f-c4a4-4aaa-8217-2a9bc1759a6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405899088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1405899088
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2141919829
Short name T934
Test name
Test status
Simulation time 88462515 ps
CPU time 1.46 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:43 PM PDT 24
Peak memory 217296 kb
Host smart-74787d16-08ab-427a-9ba1-f0f7d84ce183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214191
9829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2141919829
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.52362072
Short name T952
Test name
Test status
Simulation time 296252018 ps
CPU time 1.54 seconds
Started Jul 17 06:16:37 PM PDT 24
Finished Jul 17 06:16:40 PM PDT 24
Peak memory 208888 kb
Host smart-3b6b4d25-b51f-4cec-a0a8-87436822e082
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52362072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 0.lc_ctrl_jtag_csr_rw.52362072
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2427718675
Short name T894
Test name
Test status
Simulation time 29321856 ps
CPU time 1.55 seconds
Started Jul 17 06:16:41 PM PDT 24
Finished Jul 17 06:16:44 PM PDT 24
Peak memory 209032 kb
Host smart-3acc2693-2aa2-460e-a1b1-e690c149924f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427718675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2427718675
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1241513433
Short name T128
Test name
Test status
Simulation time 63656242 ps
CPU time 2.63 seconds
Started Jul 17 06:16:45 PM PDT 24
Finished Jul 17 06:16:49 PM PDT 24
Peak memory 217188 kb
Host smart-06a4009f-a44c-4a8e-be0b-04b0686a7c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241513433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1241513433
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1397267660
Short name T135
Test name
Test status
Simulation time 238858032 ps
CPU time 1.88 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:43 PM PDT 24
Peak memory 221236 kb
Host smart-4d587466-aa1b-4b9f-a08d-71c42f8a774f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397267660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1397267660
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1723559060
Short name T887
Test name
Test status
Simulation time 27621309 ps
CPU time 0.99 seconds
Started Jul 17 06:16:43 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 208920 kb
Host smart-f3e14910-4419-4e25-92b6-b4cc94d914c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723559060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1723559060
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1618302861
Short name T941
Test name
Test status
Simulation time 53196839 ps
CPU time 2.17 seconds
Started Jul 17 06:16:49 PM PDT 24
Finished Jul 17 06:16:52 PM PDT 24
Peak memory 208860 kb
Host smart-5e6854db-ab3e-4c3b-8627-bd2c3e67b920
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618302861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1618302861
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3546694339
Short name T870
Test name
Test status
Simulation time 33177525 ps
CPU time 1.09 seconds
Started Jul 17 06:21:49 PM PDT 24
Finished Jul 17 06:21:50 PM PDT 24
Peak memory 209636 kb
Host smart-60a24da7-771b-4741-8a23-a019e9063217
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546694339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3546694339
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.566593516
Short name T908
Test name
Test status
Simulation time 23442425 ps
CPU time 1.5 seconds
Started Jul 17 06:16:49 PM PDT 24
Finished Jul 17 06:16:51 PM PDT 24
Peak memory 219044 kb
Host smart-16ea4173-f0e5-46dc-af49-1bf947a3ae3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566593516 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.566593516
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1006293065
Short name T111
Test name
Test status
Simulation time 17360609 ps
CPU time 0.93 seconds
Started Jul 17 06:16:45 PM PDT 24
Finished Jul 17 06:16:47 PM PDT 24
Peak memory 208812 kb
Host smart-96434e79-4d8b-4062-ad3a-6f097cd97c0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006293065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1006293065
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.303469015
Short name T872
Test name
Test status
Simulation time 143029977 ps
CPU time 1.56 seconds
Started Jul 17 06:16:43 PM PDT 24
Finished Jul 17 06:16:46 PM PDT 24
Peak memory 208812 kb
Host smart-d444be3a-2c4d-4b35-b86b-5e7bb4c598da
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303469015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.303469015
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3063161614
Short name T943
Test name
Test status
Simulation time 819601240 ps
CPU time 2.77 seconds
Started Jul 17 06:16:42 PM PDT 24
Finished Jul 17 06:16:46 PM PDT 24
Peak memory 208748 kb
Host smart-5aef989d-8889-4a00-be0f-e7285cdd35c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063161614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3063161614
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3646071937
Short name T913
Test name
Test status
Simulation time 357653908 ps
CPU time 4.95 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:46 PM PDT 24
Peak memory 208716 kb
Host smart-688a7f53-8c59-4acb-b413-d67d8eaea6f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646071937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3646071937
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.723375888
Short name T975
Test name
Test status
Simulation time 413144766 ps
CPU time 1.75 seconds
Started Jul 17 06:16:48 PM PDT 24
Finished Jul 17 06:16:50 PM PDT 24
Peak memory 210296 kb
Host smart-324302b4-920a-4088-84c3-9a60ae70765e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723375888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.723375888
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3795828754
Short name T939
Test name
Test status
Simulation time 136658666 ps
CPU time 2.42 seconds
Started Jul 17 06:16:42 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 217368 kb
Host smart-6fcbce8b-af1c-4a39-89a3-c827b5bb1981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379582
8754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3795828754
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2849601521
Short name T890
Test name
Test status
Simulation time 125243436 ps
CPU time 1.08 seconds
Started Jul 17 06:16:43 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 208848 kb
Host smart-6fea2c27-d808-4cb2-858a-ca73e0fc70f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849601521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2849601521
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1610502285
Short name T959
Test name
Test status
Simulation time 23855566 ps
CPU time 1.31 seconds
Started Jul 17 06:16:43 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 209032 kb
Host smart-eea1814e-dfe0-470f-a488-d8c420af7857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610502285 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1610502285
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3096407200
Short name T179
Test name
Test status
Simulation time 75887476 ps
CPU time 1.02 seconds
Started Jul 17 06:16:38 PM PDT 24
Finished Jul 17 06:16:40 PM PDT 24
Peak memory 209108 kb
Host smart-e8bf8964-44bb-413c-a3cc-f1b67c5042e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096407200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3096407200
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3014489763
Short name T105
Test name
Test status
Simulation time 188008162 ps
CPU time 1.77 seconds
Started Jul 17 06:16:39 PM PDT 24
Finished Jul 17 06:16:41 PM PDT 24
Peak memory 217168 kb
Host smart-5866a729-307b-4cd6-8bcb-6e133935b459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014489763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3014489763
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1362408664
Short name T978
Test name
Test status
Simulation time 47689447 ps
CPU time 2.6 seconds
Started Jul 17 06:16:38 PM PDT 24
Finished Jul 17 06:16:41 PM PDT 24
Peak memory 221704 kb
Host smart-d746c856-6232-4da5-bbd4-e99f02652f85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362408664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1362408664
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1919189524
Short name T932
Test name
Test status
Simulation time 28336349 ps
CPU time 1.5 seconds
Started Jul 17 06:17:08 PM PDT 24
Finished Jul 17 06:17:10 PM PDT 24
Peak memory 217392 kb
Host smart-692c8b24-134f-4192-a123-b13cd0414d3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919189524 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1919189524
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2809251002
Short name T950
Test name
Test status
Simulation time 89590131 ps
CPU time 1.09 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:11 PM PDT 24
Peak memory 208896 kb
Host smart-0bad6ee3-2e85-4f00-96df-819fc9cb37a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809251002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2809251002
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3377582945
Short name T982
Test name
Test status
Simulation time 38685096 ps
CPU time 1.4 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 209020 kb
Host smart-72f3f11c-6b0a-4640-af66-e9be78ccabc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377582945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3377582945
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.957099891
Short name T903
Test name
Test status
Simulation time 190916141 ps
CPU time 2.31 seconds
Started Jul 17 06:17:04 PM PDT 24
Finished Jul 17 06:17:06 PM PDT 24
Peak memory 217228 kb
Host smart-8fe6394a-ea67-43b5-a9a9-99491ea34130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957099891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.957099891
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3437360597
Short name T924
Test name
Test status
Simulation time 38133148 ps
CPU time 2.29 seconds
Started Jul 17 06:17:12 PM PDT 24
Finished Jul 17 06:17:16 PM PDT 24
Peak memory 219028 kb
Host smart-5c8610b1-dca9-4857-a896-142352dd21fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437360597 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3437360597
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3979793942
Short name T895
Test name
Test status
Simulation time 100467987 ps
CPU time 2.03 seconds
Started Jul 17 06:17:16 PM PDT 24
Finished Jul 17 06:17:19 PM PDT 24
Peak memory 209016 kb
Host smart-49590fbb-889c-4863-a3c6-68ff2cbf7726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979793942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3979793942
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1904681702
Short name T914
Test name
Test status
Simulation time 24990839 ps
CPU time 1.83 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 217368 kb
Host smart-54d24635-b71f-4ceb-b17d-245132ffbf3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904681702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1904681702
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3512715795
Short name T927
Test name
Test status
Simulation time 20026435 ps
CPU time 1.68 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 219488 kb
Host smart-ff423a7d-e095-4fb6-a72b-297cc6a619f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512715795 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3512715795
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1849498055
Short name T178
Test name
Test status
Simulation time 11709962 ps
CPU time 0.84 seconds
Started Jul 17 06:17:11 PM PDT 24
Finished Jul 17 06:17:13 PM PDT 24
Peak memory 209032 kb
Host smart-a055050c-2136-44e8-93f1-a28de2c69ebb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849498055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1849498055
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1525832478
Short name T994
Test name
Test status
Simulation time 98703401 ps
CPU time 1.08 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:16 PM PDT 24
Peak memory 209228 kb
Host smart-22f036a3-7574-43f5-ab01-8e89b170f5f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525832478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1525832478
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.986557084
Short name T132
Test name
Test status
Simulation time 93253878 ps
CPU time 3.37 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:15 PM PDT 24
Peak memory 218208 kb
Host smart-014ee380-948f-4f64-a007-ffe4f5bf50f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986557084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.986557084
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.703016908
Short name T158
Test name
Test status
Simulation time 34408149 ps
CPU time 1.54 seconds
Started Jul 17 06:17:16 PM PDT 24
Finished Jul 17 06:17:19 PM PDT 24
Peak memory 222476 kb
Host smart-b033d3d0-04c7-400c-b3e2-1d12a49c7ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703016908 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.703016908
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4102493072
Short name T904
Test name
Test status
Simulation time 26925127 ps
CPU time 0.84 seconds
Started Jul 17 06:17:16 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 208948 kb
Host smart-e6aa681f-7e5c-4879-9328-df83ee6b855d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102493072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4102493072
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.26361273
Short name T931
Test name
Test status
Simulation time 43166291 ps
CPU time 0.97 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:16 PM PDT 24
Peak memory 209084 kb
Host smart-1eead3d8-b414-453b-8547-0b8ea963b98c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26361273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
same_csr_outstanding.26361273
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.256660934
Short name T114
Test name
Test status
Simulation time 302420457 ps
CPU time 3.66 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:16 PM PDT 24
Peak memory 217564 kb
Host smart-316cf097-0092-47e5-9d11-d06af0a6e7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256660934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.256660934
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1709768137
Short name T138
Test name
Test status
Simulation time 42728510 ps
CPU time 1.89 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 221468 kb
Host smart-14115eb4-01b6-4715-8022-04111f0dbe96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709768137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1709768137
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4044497653
Short name T961
Test name
Test status
Simulation time 26646118 ps
CPU time 2.1 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 217544 kb
Host smart-aa005933-d57d-48c9-a3e0-7984b567a0b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044497653 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4044497653
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.147333966
Short name T955
Test name
Test status
Simulation time 107321111 ps
CPU time 0.81 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:15 PM PDT 24
Peak memory 208192 kb
Host smart-f47a662b-42c5-416c-a6bc-a55987bcced0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147333966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.147333966
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1587341402
Short name T980
Test name
Test status
Simulation time 18132850 ps
CPU time 1.07 seconds
Started Jul 17 06:17:16 PM PDT 24
Finished Jul 17 06:17:18 PM PDT 24
Peak memory 209128 kb
Host smart-8d150ac2-162e-4e88-b38f-88a035ed6f19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587341402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1587341402
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2713702789
Short name T946
Test name
Test status
Simulation time 486587456 ps
CPU time 4.03 seconds
Started Jul 17 06:17:16 PM PDT 24
Finished Jul 17 06:17:21 PM PDT 24
Peak memory 217160 kb
Host smart-2988e5cd-5657-43e9-9de8-7bee3ddef611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713702789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2713702789
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2131998563
Short name T127
Test name
Test status
Simulation time 41187811 ps
CPU time 1.41 seconds
Started Jul 17 06:22:06 PM PDT 24
Finished Jul 17 06:22:08 PM PDT 24
Peak memory 217280 kb
Host smart-f4036c99-7dc4-40c8-932d-135d874855e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131998563 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2131998563
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.668216459
Short name T979
Test name
Test status
Simulation time 46721972 ps
CPU time 0.89 seconds
Started Jul 17 06:17:11 PM PDT 24
Finished Jul 17 06:17:13 PM PDT 24
Peak memory 208820 kb
Host smart-728f02db-d117-4171-b1dd-35ae1a3a8924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668216459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.668216459
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.279405752
Short name T957
Test name
Test status
Simulation time 45989569 ps
CPU time 1.88 seconds
Started Jul 17 06:17:21 PM PDT 24
Finished Jul 17 06:17:23 PM PDT 24
Peak memory 209132 kb
Host smart-ab038b71-5f3a-43ca-aa0d-aa5b08886f0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279405752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.279405752
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.787650840
Short name T133
Test name
Test status
Simulation time 49376748 ps
CPU time 2.09 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 217156 kb
Host smart-b1b9b476-f102-4686-9532-83c7c52c02c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787650840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.787650840
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.35451703
Short name T136
Test name
Test status
Simulation time 142441295 ps
CPU time 2.23 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 217212 kb
Host smart-c54f7208-dd16-4a7b-9431-d9cfb2960e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35451703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_e
rr.35451703
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.488324823
Short name T120
Test name
Test status
Simulation time 24075220 ps
CPU time 1.44 seconds
Started Jul 17 06:17:22 PM PDT 24
Finished Jul 17 06:17:25 PM PDT 24
Peak memory 219288 kb
Host smart-7ea94a31-abd8-45e1-aac4-e74cf2c12258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488324823 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.488324823
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2186632046
Short name T869
Test name
Test status
Simulation time 35677405 ps
CPU time 0.85 seconds
Started Jul 17 06:21:45 PM PDT 24
Finished Jul 17 06:21:46 PM PDT 24
Peak memory 208128 kb
Host smart-56b123e9-585c-4c05-b649-0e96abe180ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186632046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2186632046
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3802829245
Short name T117
Test name
Test status
Simulation time 23006748 ps
CPU time 1.21 seconds
Started Jul 17 06:17:20 PM PDT 24
Finished Jul 17 06:17:22 PM PDT 24
Peak memory 209152 kb
Host smart-4dd793e5-ab70-4a9e-ad87-8f301fa1c187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802829245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3802829245
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2788017201
Short name T988
Test name
Test status
Simulation time 135077209 ps
CPU time 2.62 seconds
Started Jul 17 06:17:23 PM PDT 24
Finished Jul 17 06:17:27 PM PDT 24
Peak memory 217156 kb
Host smart-6984b7f0-b15f-4d9a-a245-4676a8541851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788017201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2788017201
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2220137393
Short name T166
Test name
Test status
Simulation time 50371158 ps
CPU time 1.58 seconds
Started Jul 17 06:17:29 PM PDT 24
Finished Jul 17 06:17:31 PM PDT 24
Peak memory 217240 kb
Host smart-6fc671f1-7ed4-43e0-b141-e1c54266187f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220137393 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2220137393
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.227167819
Short name T185
Test name
Test status
Simulation time 13646823 ps
CPU time 1.1 seconds
Started Jul 17 06:17:22 PM PDT 24
Finished Jul 17 06:17:24 PM PDT 24
Peak memory 208624 kb
Host smart-e5bd6a57-f5f9-4bac-a2f4-273469b9bfcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227167819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.227167819
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1979174749
Short name T183
Test name
Test status
Simulation time 97068241 ps
CPU time 1.12 seconds
Started Jul 17 06:23:06 PM PDT 24
Finished Jul 17 06:23:09 PM PDT 24
Peak memory 209056 kb
Host smart-a69d86f4-a82b-4e81-9f9d-382fe4638a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979174749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1979174749
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3551953025
Short name T973
Test name
Test status
Simulation time 136163722 ps
CPU time 1.74 seconds
Started Jul 17 06:17:22 PM PDT 24
Finished Jul 17 06:17:25 PM PDT 24
Peak memory 218140 kb
Host smart-159ced0b-657f-47d5-9af6-5f029058eeab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551953025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3551953025
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3020692492
Short name T909
Test name
Test status
Simulation time 25725714 ps
CPU time 1.07 seconds
Started Jul 17 06:17:18 PM PDT 24
Finished Jul 17 06:17:20 PM PDT 24
Peak memory 208740 kb
Host smart-a7bfb2df-2123-4be5-bef7-a01a6dc7aea2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020692492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3020692492
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.804661465
Short name T945
Test name
Test status
Simulation time 56614456 ps
CPU time 1.54 seconds
Started Jul 17 06:17:21 PM PDT 24
Finished Jul 17 06:17:24 PM PDT 24
Peak memory 209020 kb
Host smart-c344026f-5604-4685-914c-2f54067af084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804661465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.804661465
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1754966314
Short name T958
Test name
Test status
Simulation time 28362605 ps
CPU time 1.93 seconds
Started Jul 17 06:17:26 PM PDT 24
Finished Jul 17 06:17:29 PM PDT 24
Peak memory 218148 kb
Host smart-94fb3916-6d09-4ae2-bb71-e4122f61b121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754966314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1754966314
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2981868785
Short name T110
Test name
Test status
Simulation time 629331514 ps
CPU time 1.94 seconds
Started Jul 17 06:17:22 PM PDT 24
Finished Jul 17 06:17:26 PM PDT 24
Peak memory 221764 kb
Host smart-64d4628f-841d-4fc4-907d-1a5eb1d2b76b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981868785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2981868785
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2640773156
Short name T995
Test name
Test status
Simulation time 20455952 ps
CPU time 1.06 seconds
Started Jul 17 06:22:11 PM PDT 24
Finished Jul 17 06:22:13 PM PDT 24
Peak memory 218372 kb
Host smart-dad51204-d1ff-4db5-a84f-af5aec6ab254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640773156 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2640773156
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3965059751
Short name T112
Test name
Test status
Simulation time 24149205 ps
CPU time 0.94 seconds
Started Jul 17 06:17:27 PM PDT 24
Finished Jul 17 06:17:29 PM PDT 24
Peak memory 208916 kb
Host smart-a8e61da1-50af-42d6-9db3-b31797965565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965059751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3965059751
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3063697543
Short name T892
Test name
Test status
Simulation time 16149820 ps
CPU time 1 seconds
Started Jul 17 06:17:30 PM PDT 24
Finished Jul 17 06:17:32 PM PDT 24
Peak memory 209092 kb
Host smart-247ed912-d0c9-4a28-8447-9bfa2da39638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063697543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3063697543
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1580280978
Short name T936
Test name
Test status
Simulation time 44237566 ps
CPU time 1.61 seconds
Started Jul 17 06:22:13 PM PDT 24
Finished Jul 17 06:22:15 PM PDT 24
Peak memory 220356 kb
Host smart-f8176053-6513-4311-a56b-728ae391fa89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580280978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1580280978
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2843546920
Short name T124
Test name
Test status
Simulation time 105728233 ps
CPU time 2.94 seconds
Started Jul 17 06:17:20 PM PDT 24
Finished Jul 17 06:17:24 PM PDT 24
Peak memory 222196 kb
Host smart-2fcc4651-236f-416b-843f-a7b7d55adc2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843546920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2843546920
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2510960779
Short name T893
Test name
Test status
Simulation time 14887658 ps
CPU time 1.19 seconds
Started Jul 17 06:16:49 PM PDT 24
Finished Jul 17 06:16:50 PM PDT 24
Peak memory 208412 kb
Host smart-ad5b2a48-e9f2-49a6-9ef3-c12654f66027
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510960779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2510960779
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3894610960
Short name T997
Test name
Test status
Simulation time 58464554 ps
CPU time 1.69 seconds
Started Jul 17 06:16:39 PM PDT 24
Finished Jul 17 06:16:42 PM PDT 24
Peak memory 208892 kb
Host smart-0157fe26-7c77-4208-8252-04406f51310b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894610960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3894610960
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2573286591
Short name T877
Test name
Test status
Simulation time 37570148 ps
CPU time 1.04 seconds
Started Jul 17 06:21:30 PM PDT 24
Finished Jul 17 06:21:32 PM PDT 24
Peak memory 209484 kb
Host smart-5315bf8b-349b-4d08-b083-b862162b2fea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573286591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2573286591
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2314928369
Short name T121
Test name
Test status
Simulation time 19732649 ps
CPU time 1.15 seconds
Started Jul 17 06:16:41 PM PDT 24
Finished Jul 17 06:16:43 PM PDT 24
Peak memory 217344 kb
Host smart-934f0f38-b094-4031-a522-138f0e0038fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314928369 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2314928369
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3036560453
Short name T174
Test name
Test status
Simulation time 40266673 ps
CPU time 0.96 seconds
Started Jul 17 06:16:36 PM PDT 24
Finished Jul 17 06:16:37 PM PDT 24
Peak memory 209044 kb
Host smart-8f0a61a0-5642-4741-a571-8b86bdd522a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036560453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3036560453
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2522019490
Short name T977
Test name
Test status
Simulation time 62808413 ps
CPU time 1.06 seconds
Started Jul 17 06:16:38 PM PDT 24
Finished Jul 17 06:16:40 PM PDT 24
Peak memory 209040 kb
Host smart-f5f51dd0-8dc3-4605-a129-96f891a12adc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522019490 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2522019490
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3419969870
Short name T926
Test name
Test status
Simulation time 873600991 ps
CPU time 8.23 seconds
Started Jul 17 06:16:41 PM PDT 24
Finished Jul 17 06:16:50 PM PDT 24
Peak memory 208608 kb
Host smart-63eee5e0-4b8b-41ad-8880-9069a8eeb4ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419969870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3419969870
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3836119659
Short name T937
Test name
Test status
Simulation time 765346380 ps
CPU time 14.42 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:56 PM PDT 24
Peak memory 208736 kb
Host smart-5db571ac-285c-4be8-b93e-f54cf4819b94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836119659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3836119659
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3873225414
Short name T882
Test name
Test status
Simulation time 142795702 ps
CPU time 3.65 seconds
Started Jul 17 06:16:49 PM PDT 24
Finished Jul 17 06:16:53 PM PDT 24
Peak memory 210040 kb
Host smart-e12ac498-d54f-42f7-a582-ba59a61de022
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873225414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3873225414
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4290379153
Short name T885
Test name
Test status
Simulation time 224448666 ps
CPU time 2.2 seconds
Started Jul 17 06:16:42 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 217624 kb
Host smart-22ea8621-9908-475e-97ef-36c2c90fb815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429037
9153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4290379153
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3671965194
Short name T881
Test name
Test status
Simulation time 38138988 ps
CPU time 1.19 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:42 PM PDT 24
Peak memory 208816 kb
Host smart-ef1b4201-16e2-48bf-a117-f281ef4c4f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671965194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3671965194
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1484280236
Short name T113
Test name
Test status
Simulation time 50328898 ps
CPU time 1.52 seconds
Started Jul 17 06:16:36 PM PDT 24
Finished Jul 17 06:16:38 PM PDT 24
Peak memory 209020 kb
Host smart-3e9c33e3-e2a9-4b41-b98b-a0bcf38ee894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484280236 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1484280236
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3813010525
Short name T180
Test name
Test status
Simulation time 70130462 ps
CPU time 1.18 seconds
Started Jul 17 06:16:49 PM PDT 24
Finished Jul 17 06:16:50 PM PDT 24
Peak memory 208300 kb
Host smart-dec5a4f9-2b41-4e5d-a245-2a8f2d901b9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813010525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3813010525
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.543036626
Short name T966
Test name
Test status
Simulation time 403581050 ps
CPU time 3.07 seconds
Started Jul 17 06:16:42 PM PDT 24
Finished Jul 17 06:16:46 PM PDT 24
Peak memory 217484 kb
Host smart-eb7e565d-3f3a-46a0-9abe-815ed761fc5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543036626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.543036626
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4073454474
Short name T880
Test name
Test status
Simulation time 14777068 ps
CPU time 0.93 seconds
Started Jul 17 06:16:54 PM PDT 24
Finished Jul 17 06:16:56 PM PDT 24
Peak memory 208936 kb
Host smart-d202ed57-b1be-4d7d-b0be-cbb855aec599
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073454474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4073454474
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1152813902
Short name T935
Test name
Test status
Simulation time 204998476 ps
CPU time 2.35 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:01 PM PDT 24
Peak memory 208108 kb
Host smart-91c1aa10-c646-4923-84fb-e3bf2de86af6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152813902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1152813902
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1891816058
Short name T878
Test name
Test status
Simulation time 20181306 ps
CPU time 1.07 seconds
Started Jul 17 06:21:45 PM PDT 24
Finished Jul 17 06:21:46 PM PDT 24
Peak memory 209544 kb
Host smart-bd759066-793c-4db8-a7cb-f0fc38de82ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891816058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1891816058
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.618280583
Short name T906
Test name
Test status
Simulation time 31518393 ps
CPU time 1.29 seconds
Started Jul 17 06:16:56 PM PDT 24
Finished Jul 17 06:16:59 PM PDT 24
Peak memory 217524 kb
Host smart-f3de4398-fb37-4927-aa68-0649703eaaa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618280583 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.618280583
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1213403425
Short name T883
Test name
Test status
Simulation time 43438326 ps
CPU time 0.89 seconds
Started Jul 17 06:21:44 PM PDT 24
Finished Jul 17 06:21:46 PM PDT 24
Peak memory 208824 kb
Host smart-ae8e7f94-0a5f-4e62-a761-238e7d549cd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213403425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1213403425
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3490215538
Short name T970
Test name
Test status
Simulation time 161820604 ps
CPU time 1.26 seconds
Started Jul 17 06:16:54 PM PDT 24
Finished Jul 17 06:16:56 PM PDT 24
Peak memory 208884 kb
Host smart-0f594770-a91e-485f-ae93-8ab111b59d62
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490215538 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3490215538
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2122163375
Short name T875
Test name
Test status
Simulation time 1940636202 ps
CPU time 4.05 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 208676 kb
Host smart-fe98c93e-51ae-4772-8d85-b4092439b48f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122163375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2122163375
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.453213899
Short name T971
Test name
Test status
Simulation time 977399623 ps
CPU time 5.5 seconds
Started Jul 17 06:16:37 PM PDT 24
Finished Jul 17 06:16:44 PM PDT 24
Peak memory 207592 kb
Host smart-32918e6c-311c-4994-b912-0a757f62a80a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453213899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.453213899
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3004992107
Short name T143
Test name
Test status
Simulation time 96570699 ps
CPU time 1.72 seconds
Started Jul 17 06:16:45 PM PDT 24
Finished Jul 17 06:16:48 PM PDT 24
Peak memory 210276 kb
Host smart-7bc53fae-244c-4c1a-9188-c4fd24cc85c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004992107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3004992107
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1055779704
Short name T933
Test name
Test status
Simulation time 922645056 ps
CPU time 7.12 seconds
Started Jul 17 06:16:40 PM PDT 24
Finished Jul 17 06:16:48 PM PDT 24
Peak memory 219032 kb
Host smart-8c61ac71-9517-4a38-92df-cbbe0463ce45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105577
9704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1055779704
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2049585626
Short name T879
Test name
Test status
Simulation time 107759692 ps
CPU time 2.18 seconds
Started Jul 17 06:21:49 PM PDT 24
Finished Jul 17 06:21:52 PM PDT 24
Peak memory 208884 kb
Host smart-222382da-fd5d-4395-a9a0-cd8db47c8ca7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049585626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2049585626
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2684995601
Short name T923
Test name
Test status
Simulation time 20984979 ps
CPU time 1.55 seconds
Started Jul 17 06:21:49 PM PDT 24
Finished Jul 17 06:21:51 PM PDT 24
Peak memory 217216 kb
Host smart-b45b32e6-951e-46b0-aef0-c114aea8f90b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684995601 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2684995601
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.601951905
Short name T928
Test name
Test status
Simulation time 147593461 ps
CPU time 1.34 seconds
Started Jul 17 06:16:55 PM PDT 24
Finished Jul 17 06:16:58 PM PDT 24
Peak memory 208976 kb
Host smart-bca85b61-dc8c-40c6-8e67-f36d3c1afb19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601951905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.601951905
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.367132678
Short name T917
Test name
Test status
Simulation time 224963770 ps
CPU time 2.32 seconds
Started Jul 17 06:16:55 PM PDT 24
Finished Jul 17 06:16:59 PM PDT 24
Peak memory 217120 kb
Host smart-743b9da5-cce7-4d41-8c24-d0745cb4c7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367132678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.367132678
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3998660741
Short name T131
Test name
Test status
Simulation time 162676063 ps
CPU time 1.81 seconds
Started Jul 17 06:16:56 PM PDT 24
Finished Jul 17 06:16:59 PM PDT 24
Peak memory 221052 kb
Host smart-c63ded30-ff01-4c9e-aa58-aab233d70805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998660741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3998660741
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2458610378
Short name T951
Test name
Test status
Simulation time 21561972 ps
CPU time 1.24 seconds
Started Jul 17 06:23:18 PM PDT 24
Finished Jul 17 06:23:20 PM PDT 24
Peak memory 208896 kb
Host smart-ae6777bb-ed73-43ba-8b8c-0810438d625f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458610378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2458610378
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1578899199
Short name T868
Test name
Test status
Simulation time 59832961 ps
CPU time 1.24 seconds
Started Jul 17 06:16:56 PM PDT 24
Finished Jul 17 06:16:59 PM PDT 24
Peak memory 208824 kb
Host smart-8a3ef4ce-ee75-4aba-90bf-69fdacbd379f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578899199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1578899199
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1231643718
Short name T177
Test name
Test status
Simulation time 14157382 ps
CPU time 0.96 seconds
Started Jul 17 06:16:55 PM PDT 24
Finished Jul 17 06:16:57 PM PDT 24
Peak memory 209508 kb
Host smart-3ccf4ff9-17d5-4229-a160-73d51450a987
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231643718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1231643718
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2161514583
Short name T986
Test name
Test status
Simulation time 160741679 ps
CPU time 1.43 seconds
Started Jul 17 06:21:46 PM PDT 24
Finished Jul 17 06:21:48 PM PDT 24
Peak memory 218424 kb
Host smart-150ad9df-efde-4e91-ba7f-b72e0fad9a6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161514583 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2161514583
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4249029260
Short name T930
Test name
Test status
Simulation time 20247687 ps
CPU time 0.88 seconds
Started Jul 17 06:16:52 PM PDT 24
Finished Jul 17 06:16:54 PM PDT 24
Peak memory 208800 kb
Host smart-2cd5a547-34b5-4fc9-b788-c59cac23114d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249029260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4249029260
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2966093668
Short name T974
Test name
Test status
Simulation time 140542887 ps
CPU time 3.65 seconds
Started Jul 17 06:16:55 PM PDT 24
Finished Jul 17 06:17:01 PM PDT 24
Peak memory 208692 kb
Host smart-fab92a71-ba41-40e6-93ec-98483beebcb9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966093668 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2966093668
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1849063430
Short name T944
Test name
Test status
Simulation time 4459599002 ps
CPU time 23.22 seconds
Started Jul 17 06:21:50 PM PDT 24
Finished Jul 17 06:22:14 PM PDT 24
Peak memory 208964 kb
Host smart-205ea511-0939-4f0c-b3d3-ee8a514c9c3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849063430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1849063430
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.530847865
Short name T888
Test name
Test status
Simulation time 7206430641 ps
CPU time 22.47 seconds
Started Jul 17 06:16:55 PM PDT 24
Finished Jul 17 06:17:20 PM PDT 24
Peak memory 209152 kb
Host smart-27cead3b-5259-45da-b4be-f8b7e43fd6af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530847865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.530847865
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3450883376
Short name T886
Test name
Test status
Simulation time 325494013 ps
CPU time 2.71 seconds
Started Jul 17 06:21:49 PM PDT 24
Finished Jul 17 06:21:53 PM PDT 24
Peak memory 210680 kb
Host smart-c25abf7e-24fa-409c-8509-32b3b95b39db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450883376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3450883376
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1757803216
Short name T141
Test name
Test status
Simulation time 478675369 ps
CPU time 3.86 seconds
Started Jul 17 06:22:01 PM PDT 24
Finished Jul 17 06:22:05 PM PDT 24
Peak memory 217476 kb
Host smart-3a6c9622-2505-47b4-a3cd-035eac2f977f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175780
3216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1757803216
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1684698349
Short name T874
Test name
Test status
Simulation time 97503215 ps
CPU time 1.69 seconds
Started Jul 17 06:16:54 PM PDT 24
Finished Jul 17 06:16:56 PM PDT 24
Peak memory 208880 kb
Host smart-7bf24606-5f84-4dde-bb05-084bda1bd838
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684698349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1684698349
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3531388479
Short name T948
Test name
Test status
Simulation time 48378739 ps
CPU time 1 seconds
Started Jul 17 06:19:48 PM PDT 24
Finished Jul 17 06:19:50 PM PDT 24
Peak memory 208944 kb
Host smart-9fe19521-4495-45c5-93c0-d45f443e8616
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531388479 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3531388479
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3339513773
Short name T996
Test name
Test status
Simulation time 26621630 ps
CPU time 1.14 seconds
Started Jul 17 06:16:55 PM PDT 24
Finished Jul 17 06:16:57 PM PDT 24
Peak memory 209036 kb
Host smart-7ea8cd74-b94a-4180-9949-8211e3dae2eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339513773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3339513773
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3247822763
Short name T965
Test name
Test status
Simulation time 498945704 ps
CPU time 3.75 seconds
Started Jul 17 06:23:07 PM PDT 24
Finished Jul 17 06:23:12 PM PDT 24
Peak memory 217164 kb
Host smart-901fa2cb-7934-40e3-973c-af1aa5b205be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247822763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3247822763
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2595963311
Short name T118
Test name
Test status
Simulation time 2121478403 ps
CPU time 3.09 seconds
Started Jul 17 06:16:57 PM PDT 24
Finished Jul 17 06:17:02 PM PDT 24
Peak memory 221868 kb
Host smart-1484ac3b-011a-4a31-8480-961aca03f57a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595963311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2595963311
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1782184156
Short name T897
Test name
Test status
Simulation time 67852035 ps
CPU time 1.06 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:00 PM PDT 24
Peak memory 218304 kb
Host smart-14666a70-7460-435f-9592-990eb00ed075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782184156 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1782184156
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4059005431
Short name T871
Test name
Test status
Simulation time 42521765 ps
CPU time 0.99 seconds
Started Jul 17 06:16:54 PM PDT 24
Finished Jul 17 06:16:56 PM PDT 24
Peak memory 208896 kb
Host smart-c27354ce-69a8-4f15-94fa-415be7b59717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059005431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.4059005431
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4162175572
Short name T953
Test name
Test status
Simulation time 46583606 ps
CPU time 0.8 seconds
Started Jul 17 06:16:54 PM PDT 24
Finished Jul 17 06:16:55 PM PDT 24
Peak memory 208744 kb
Host smart-ef27c614-664c-4dcd-af93-d70603249b61
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162175572 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4162175572
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3913342271
Short name T963
Test name
Test status
Simulation time 299049422 ps
CPU time 3.45 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:02 PM PDT 24
Peak memory 208696 kb
Host smart-aed62a32-fac7-405c-9349-078024b03f05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913342271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3913342271
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2466121916
Short name T873
Test name
Test status
Simulation time 1102552209 ps
CPU time 11.94 seconds
Started Jul 17 06:16:54 PM PDT 24
Finished Jul 17 06:17:07 PM PDT 24
Peak memory 208712 kb
Host smart-6a4a8e23-bd00-4745-8642-34cf7be98358
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466121916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2466121916
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1924808422
Short name T921
Test name
Test status
Simulation time 160574056 ps
CPU time 2.53 seconds
Started Jul 17 06:22:06 PM PDT 24
Finished Jul 17 06:22:09 PM PDT 24
Peak memory 210372 kb
Host smart-fcaf6f5b-a410-49c8-907e-04770971c94b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924808422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1924808422
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1404920957
Short name T167
Test name
Test status
Simulation time 414065620 ps
CPU time 3.22 seconds
Started Jul 17 06:16:53 PM PDT 24
Finished Jul 17 06:16:57 PM PDT 24
Peak memory 217320 kb
Host smart-205d30d1-b7e3-4f9f-a118-e7f08f897e92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140492
0957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1404920957
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3526993255
Short name T987
Test name
Test status
Simulation time 64990672 ps
CPU time 1.65 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:01 PM PDT 24
Peak memory 208872 kb
Host smart-31fa8a99-181e-4c46-a1d9-ec466c84f4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526993255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3526993255
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4224648551
Short name T991
Test name
Test status
Simulation time 62533678 ps
CPU time 1.02 seconds
Started Jul 17 06:16:52 PM PDT 24
Finished Jul 17 06:16:54 PM PDT 24
Peak memory 209024 kb
Host smart-a4cb46fd-ddeb-4600-96a6-f2c72a5534e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224648551 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4224648551
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2671520214
Short name T902
Test name
Test status
Simulation time 21548877 ps
CPU time 1.31 seconds
Started Jul 17 06:16:52 PM PDT 24
Finished Jul 17 06:16:55 PM PDT 24
Peak memory 217128 kb
Host smart-c7dfe01f-56cf-4dea-9322-f21b6429cf58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671520214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2671520214
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1964052659
Short name T976
Test name
Test status
Simulation time 342922826 ps
CPU time 3.89 seconds
Started Jul 17 06:21:49 PM PDT 24
Finished Jul 17 06:21:53 PM PDT 24
Peak memory 217232 kb
Host smart-11038d13-aba7-4c01-99bd-bd6ab15f4ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964052659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1964052659
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3836278349
Short name T119
Test name
Test status
Simulation time 76140497 ps
CPU time 3.47 seconds
Started Jul 17 06:21:46 PM PDT 24
Finished Jul 17 06:21:50 PM PDT 24
Peak memory 217176 kb
Host smart-2db6793e-d815-4d53-9437-a285d2dc183f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836278349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3836278349
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2433176763
Short name T929
Test name
Test status
Simulation time 154887377 ps
CPU time 1.13 seconds
Started Jul 17 06:17:07 PM PDT 24
Finished Jul 17 06:17:09 PM PDT 24
Peak memory 218832 kb
Host smart-25694c26-3313-4daf-b876-7deb1d1dc8d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433176763 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2433176763
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1639658058
Short name T876
Test name
Test status
Simulation time 42855533 ps
CPU time 1.13 seconds
Started Jul 17 06:17:06 PM PDT 24
Finished Jul 17 06:17:07 PM PDT 24
Peak memory 208800 kb
Host smart-5184abe0-a66d-4bb2-95ee-167555e27610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639658058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1639658058
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1402871160
Short name T968
Test name
Test status
Simulation time 34013781 ps
CPU time 1.25 seconds
Started Jul 17 06:21:46 PM PDT 24
Finished Jul 17 06:21:48 PM PDT 24
Peak memory 208812 kb
Host smart-71cdb0e5-58d7-4a3b-bae6-0c3491295c69
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402871160 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1402871160
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3162491606
Short name T920
Test name
Test status
Simulation time 517215350 ps
CPU time 13.48 seconds
Started Jul 17 06:16:52 PM PDT 24
Finished Jul 17 06:17:07 PM PDT 24
Peak memory 208704 kb
Host smart-0d9d05ff-071f-4663-94d3-f982134ee9d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162491606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3162491606
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.674250633
Short name T901
Test name
Test status
Simulation time 2370918503 ps
CPU time 14.55 seconds
Started Jul 17 06:16:56 PM PDT 24
Finished Jul 17 06:17:12 PM PDT 24
Peak memory 209152 kb
Host smart-cac0af87-2381-4d6b-bb9a-5b26639a36c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674250633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.674250633
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2335373199
Short name T144
Test name
Test status
Simulation time 104667995 ps
CPU time 1.42 seconds
Started Jul 17 06:16:55 PM PDT 24
Finished Jul 17 06:16:58 PM PDT 24
Peak memory 210336 kb
Host smart-1b379a15-3114-4332-812f-9236a076f465
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335373199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2335373199
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3639212491
Short name T910
Test name
Test status
Simulation time 694720325 ps
CPU time 2.8 seconds
Started Jul 17 06:21:49 PM PDT 24
Finished Jul 17 06:21:52 PM PDT 24
Peak memory 217272 kb
Host smart-e06a111b-18b0-49e1-b2cd-bf15677f75fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363921
2491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3639212491
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.638170904
Short name T967
Test name
Test status
Simulation time 39811103 ps
CPU time 1.2 seconds
Started Jul 17 06:16:56 PM PDT 24
Finished Jul 17 06:16:59 PM PDT 24
Peak memory 208276 kb
Host smart-f9bfb01a-afe9-41d5-9c5c-1e182471b347
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638170904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.638170904
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.545587827
Short name T969
Test name
Test status
Simulation time 17572320 ps
CPU time 1.2 seconds
Started Jul 17 06:16:54 PM PDT 24
Finished Jul 17 06:16:56 PM PDT 24
Peak memory 209068 kb
Host smart-f5bd9da7-1e02-41cc-aef2-4848b6a507e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545587827 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.545587827
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.642483852
Short name T182
Test name
Test status
Simulation time 17971778 ps
CPU time 1.21 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:11 PM PDT 24
Peak memory 209152 kb
Host smart-7eef3a9a-0226-4539-9265-7b5eba5d6a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642483852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.642483852
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1913350823
Short name T125
Test name
Test status
Simulation time 206603931 ps
CPU time 4.2 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 217196 kb
Host smart-09950d83-6215-4645-ad31-96556546d1be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913350823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1913350823
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3297898534
Short name T960
Test name
Test status
Simulation time 264220319 ps
CPU time 3.36 seconds
Started Jul 17 06:17:07 PM PDT 24
Finished Jul 17 06:17:11 PM PDT 24
Peak memory 217220 kb
Host smart-0d59f949-c8fd-406b-8a3a-e8e46276c1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297898534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3297898534
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1042138102
Short name T116
Test name
Test status
Simulation time 77013777 ps
CPU time 1.37 seconds
Started Jul 17 06:17:11 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 221092 kb
Host smart-01a79533-a582-4704-9f54-8b3a680280ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042138102 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1042138102
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2846929985
Short name T981
Test name
Test status
Simulation time 15282791 ps
CPU time 1.09 seconds
Started Jul 17 06:17:06 PM PDT 24
Finished Jul 17 06:17:08 PM PDT 24
Peak memory 208940 kb
Host smart-01285a37-ac3b-4ce8-bd77-35ea9e7ee9a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846929985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2846929985
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4001168330
Short name T915
Test name
Test status
Simulation time 78495785 ps
CPU time 2.45 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:13 PM PDT 24
Peak memory 208852 kb
Host smart-3b245100-9acb-405a-af5f-8782606debb3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001168330 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4001168330
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3693260654
Short name T922
Test name
Test status
Simulation time 2147373948 ps
CPU time 5.88 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:04 PM PDT 24
Peak memory 208160 kb
Host smart-8d105576-232b-40cc-ae14-ae78d5d28097
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693260654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3693260654
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1472000642
Short name T990
Test name
Test status
Simulation time 4424661009 ps
CPU time 19.84 seconds
Started Jul 17 06:22:14 PM PDT 24
Finished Jul 17 06:22:34 PM PDT 24
Peak memory 208956 kb
Host smart-431dbdd7-5e94-426c-9f66-fbd09de8a7bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472000642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1472000642
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1443458099
Short name T907
Test name
Test status
Simulation time 211158585 ps
CPU time 1.61 seconds
Started Jul 17 06:22:06 PM PDT 24
Finished Jul 17 06:22:08 PM PDT 24
Peak memory 210528 kb
Host smart-fc7d13eb-ec17-49f9-b52c-4014623eb54b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443458099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1443458099
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1021000747
Short name T956
Test name
Test status
Simulation time 420572508 ps
CPU time 3.26 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 218352 kb
Host smart-8949fc19-098f-4c9c-be7f-56246cef57d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102100
0747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1021000747
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2433331860
Short name T916
Test name
Test status
Simulation time 507657254 ps
CPU time 3.44 seconds
Started Jul 17 06:22:12 PM PDT 24
Finished Jul 17 06:22:16 PM PDT 24
Peak memory 208892 kb
Host smart-86612e36-7d25-4058-9d55-63465363c5d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433331860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2433331860
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4116197122
Short name T949
Test name
Test status
Simulation time 42829521 ps
CPU time 1.6 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:12 PM PDT 24
Peak memory 211240 kb
Host smart-62e8e9b7-8b6d-4dd8-a368-a5efc5b78adc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116197122 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4116197122
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3809909780
Short name T962
Test name
Test status
Simulation time 18610116 ps
CPU time 1.01 seconds
Started Jul 17 06:17:08 PM PDT 24
Finished Jul 17 06:17:10 PM PDT 24
Peak memory 209096 kb
Host smart-450dd48a-afc4-4065-9220-663924b96810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809909780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3809909780
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1554174585
Short name T992
Test name
Test status
Simulation time 115394251 ps
CPU time 1.62 seconds
Started Jul 17 06:17:12 PM PDT 24
Finished Jul 17 06:17:16 PM PDT 24
Peak memory 218676 kb
Host smart-5fa7b0bb-d62d-47bf-85db-abb6451f88ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554174585 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1554174585
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.262977240
Short name T918
Test name
Test status
Simulation time 45699642 ps
CPU time 0.96 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:13 PM PDT 24
Peak memory 208948 kb
Host smart-185f407a-eb3b-433c-abab-fbe827929c0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262977240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.262977240
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.564688713
Short name T912
Test name
Test status
Simulation time 50165826 ps
CPU time 1.3 seconds
Started Jul 17 06:17:04 PM PDT 24
Finished Jul 17 06:17:06 PM PDT 24
Peak memory 208864 kb
Host smart-89e586dd-e148-4db8-8da6-675f298d6e0d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564688713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.564688713
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3956624528
Short name T985
Test name
Test status
Simulation time 375357098 ps
CPU time 6.33 seconds
Started Jul 17 06:17:07 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 208784 kb
Host smart-4dc17177-b644-4a4d-a485-91b5fc5143ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956624528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3956624528
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2484935005
Short name T900
Test name
Test status
Simulation time 356059241 ps
CPU time 4.75 seconds
Started Jul 17 06:17:08 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 208136 kb
Host smart-58da912f-2500-4ac1-94cc-49a2422323de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484935005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2484935005
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.159609337
Short name T905
Test name
Test status
Simulation time 431349455 ps
CPU time 4.81 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:17 PM PDT 24
Peak memory 210816 kb
Host smart-c6cd069a-06b1-4244-982d-6465f939c8a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159609337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.159609337
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1256838930
Short name T140
Test name
Test status
Simulation time 1000918350 ps
CPU time 2.86 seconds
Started Jul 17 06:22:14 PM PDT 24
Finished Jul 17 06:22:17 PM PDT 24
Peak memory 218328 kb
Host smart-767aadb0-ee69-47f3-9b08-38965c518d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125683
8930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1256838930
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1501574317
Short name T972
Test name
Test status
Simulation time 24969385 ps
CPU time 1.15 seconds
Started Jul 17 06:23:01 PM PDT 24
Finished Jul 17 06:23:03 PM PDT 24
Peak memory 209052 kb
Host smart-d5f65a1f-7060-4ae4-a96a-19046d71d245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501574317 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1501574317
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1162396843
Short name T983
Test name
Test status
Simulation time 129289429 ps
CPU time 1.23 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:11 PM PDT 24
Peak memory 209032 kb
Host smart-d76cf5ee-0f16-4e67-8002-5721fc3043fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162396843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1162396843
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.482342247
Short name T947
Test name
Test status
Simulation time 233291777 ps
CPU time 3.56 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:03 PM PDT 24
Peak memory 217144 kb
Host smart-ba1a6166-81d6-45d0-82e7-ec7345a775e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482342247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.482342247
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.495319032
Short name T898
Test name
Test status
Simulation time 21230791 ps
CPU time 1.61 seconds
Started Jul 17 06:17:08 PM PDT 24
Finished Jul 17 06:17:11 PM PDT 24
Peak memory 217396 kb
Host smart-8969d235-28e7-41ef-97d1-0608268c1a3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495319032 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.495319032
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3964012154
Short name T964
Test name
Test status
Simulation time 52147741 ps
CPU time 1.02 seconds
Started Jul 17 06:17:12 PM PDT 24
Finished Jul 17 06:17:15 PM PDT 24
Peak memory 209028 kb
Host smart-ab498ad2-4252-4b5e-9dd6-fa8c1063d705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964012154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3964012154
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.661365479
Short name T989
Test name
Test status
Simulation time 89304443 ps
CPU time 1.86 seconds
Started Jul 17 06:17:05 PM PDT 24
Finished Jul 17 06:17:07 PM PDT 24
Peak memory 208880 kb
Host smart-435a4fe9-4238-4e0e-9267-9a7e8f213cde
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661365479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.661365479
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2817412217
Short name T954
Test name
Test status
Simulation time 12631312034 ps
CPU time 13.31 seconds
Started Jul 17 06:21:58 PM PDT 24
Finished Jul 17 06:22:12 PM PDT 24
Peak memory 208204 kb
Host smart-a0f00032-b623-444f-bcfa-6374267e05fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817412217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2817412217
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2066552614
Short name T187
Test name
Test status
Simulation time 484960280 ps
CPU time 5.79 seconds
Started Jul 17 06:21:44 PM PDT 24
Finished Jul 17 06:21:51 PM PDT 24
Peak memory 208656 kb
Host smart-5b651f1b-d377-49bd-8f2a-a4ef8c23fcbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066552614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2066552614
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3938065991
Short name T891
Test name
Test status
Simulation time 107099394 ps
CPU time 1.97 seconds
Started Jul 17 06:17:13 PM PDT 24
Finished Jul 17 06:17:16 PM PDT 24
Peak memory 210544 kb
Host smart-b594e6b5-6978-44ec-bfae-f848ad839900
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938065991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3938065991
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2752325474
Short name T938
Test name
Test status
Simulation time 149592921 ps
CPU time 4.4 seconds
Started Jul 17 06:17:07 PM PDT 24
Finished Jul 17 06:17:12 PM PDT 24
Peak memory 217284 kb
Host smart-0839dcf6-5f4c-4ce5-ad94-1ff91756d19a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275232
5474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2752325474
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1449563422
Short name T899
Test name
Test status
Simulation time 401195584 ps
CPU time 1.63 seconds
Started Jul 17 06:22:13 PM PDT 24
Finished Jul 17 06:22:15 PM PDT 24
Peak memory 208644 kb
Host smart-2adbaa7b-1de0-4504-8c62-624069a0cb35
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449563422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1449563422
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1571810826
Short name T181
Test name
Test status
Simulation time 42860828 ps
CPU time 1.22 seconds
Started Jul 17 06:17:10 PM PDT 24
Finished Jul 17 06:17:13 PM PDT 24
Peak memory 211172 kb
Host smart-2429436c-d232-4933-b41c-0eba42a108f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571810826 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1571810826
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3883290196
Short name T919
Test name
Test status
Simulation time 24178077 ps
CPU time 1.15 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:12 PM PDT 24
Peak memory 209040 kb
Host smart-910ea614-05f9-4650-9283-dd3005d66555
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883290196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3883290196
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2992075499
Short name T942
Test name
Test status
Simulation time 823381372 ps
CPU time 2.08 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:12 PM PDT 24
Peak memory 218124 kb
Host smart-9d7e2649-6b3b-4479-8830-2cb186493f3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992075499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2992075499
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1751094897
Short name T115
Test name
Test status
Simulation time 89120072 ps
CPU time 3.94 seconds
Started Jul 17 06:17:09 PM PDT 24
Finished Jul 17 06:17:14 PM PDT 24
Peak memory 222256 kb
Host smart-77f3439d-fe53-4753-95a9-dae688dd050c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751094897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1751094897
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1677226322
Short name T466
Test name
Test status
Simulation time 19926861 ps
CPU time 1.06 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:42:52 PM PDT 24
Peak memory 208908 kb
Host smart-2c9ffab3-6321-4624-8ad7-4da6e2ed1875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677226322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1677226322
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.714894718
Short name T329
Test name
Test status
Simulation time 10841925 ps
CPU time 0.78 seconds
Started Jul 17 07:42:39 PM PDT 24
Finished Jul 17 07:42:41 PM PDT 24
Peak memory 208964 kb
Host smart-791e780d-14c1-40f5-9afa-180be9f4846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714894718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.714894718
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1579856458
Short name T246
Test name
Test status
Simulation time 4840257542 ps
CPU time 10.38 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:53 PM PDT 24
Peak memory 226004 kb
Host smart-3c773d46-22b9-44a8-ad54-aba779f9d743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579856458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1579856458
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2197820858
Short name T654
Test name
Test status
Simulation time 415429392 ps
CPU time 2.41 seconds
Started Jul 17 07:42:45 PM PDT 24
Finished Jul 17 07:42:48 PM PDT 24
Peak memory 217156 kb
Host smart-900ec09a-aec1-429f-960b-62685278ce4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197820858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2197820858
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1621979823
Short name T517
Test name
Test status
Simulation time 2845699580 ps
CPU time 81.55 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:44:10 PM PDT 24
Peak memory 218872 kb
Host smart-746096f1-a666-4eb8-b026-8842d915c68c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621979823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1621979823
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.221169908
Short name T186
Test name
Test status
Simulation time 3379061550 ps
CPU time 10.41 seconds
Started Jul 17 07:42:55 PM PDT 24
Finished Jul 17 07:43:07 PM PDT 24
Peak memory 218008 kb
Host smart-2f58fd48-c2cb-41d0-9161-d2ed31cd1c18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221169908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.221169908
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2498610862
Short name T315
Test name
Test status
Simulation time 819372245 ps
CPU time 10.82 seconds
Started Jul 17 07:42:55 PM PDT 24
Finished Jul 17 07:43:07 PM PDT 24
Peak memory 218320 kb
Host smart-d7246308-77ee-44d7-bad4-e79c77932351
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498610862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2498610862
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2877011906
Short name T153
Test name
Test status
Simulation time 3279907882 ps
CPU time 23.08 seconds
Started Jul 17 07:42:50 PM PDT 24
Finished Jul 17 07:43:14 PM PDT 24
Peak memory 217700 kb
Host smart-bb5655c2-8333-4af8-9f17-9bee3e2b7fa9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877011906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2877011906
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1996732945
Short name T703
Test name
Test status
Simulation time 373715319 ps
CPU time 3.33 seconds
Started Jul 17 07:42:40 PM PDT 24
Finished Jul 17 07:42:44 PM PDT 24
Peak memory 217648 kb
Host smart-07622d28-4df4-4b01-bf93-0e126f610bff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996732945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1996732945
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.479569886
Short name T847
Test name
Test status
Simulation time 14119738184 ps
CPU time 70.74 seconds
Started Jul 17 07:42:55 PM PDT 24
Finished Jul 17 07:44:07 PM PDT 24
Peak memory 283888 kb
Host smart-387058cf-a8ba-44fa-a7c8-7ecd60ebac9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479569886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.479569886
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1781363650
Short name T430
Test name
Test status
Simulation time 590035261 ps
CPU time 11.81 seconds
Started Jul 17 07:42:45 PM PDT 24
Finished Jul 17 07:42:58 PM PDT 24
Peak memory 224112 kb
Host smart-97f0e8c1-3c3f-46a0-b66a-b01a90c3c2a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781363650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1781363650
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.272571453
Short name T769
Test name
Test status
Simulation time 75271187 ps
CPU time 1.72 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:43 PM PDT 24
Peak memory 218288 kb
Host smart-ddd6bbc7-ffbd-48b5-bf6f-5217fafaab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272571453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.272571453
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.818766616
Short name T484
Test name
Test status
Simulation time 331129491 ps
CPU time 13.29 seconds
Started Jul 17 07:42:40 PM PDT 24
Finished Jul 17 07:42:55 PM PDT 24
Peak memory 214796 kb
Host smart-a095d5ab-dc48-4378-a9ea-e97c66248f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818766616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.818766616
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1486305830
Short name T58
Test name
Test status
Simulation time 206671926 ps
CPU time 35.92 seconds
Started Jul 17 07:42:51 PM PDT 24
Finished Jul 17 07:43:29 PM PDT 24
Peak memory 282704 kb
Host smart-fbefc47a-88ae-4dc4-a8b7-2f6b0363fe16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486305830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1486305830
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2277381495
Short name T692
Test name
Test status
Simulation time 1748912343 ps
CPU time 8.62 seconds
Started Jul 17 07:42:50 PM PDT 24
Finished Jul 17 07:43:01 PM PDT 24
Peak memory 225996 kb
Host smart-59e56b7a-969a-475e-b68d-22b2563b6f8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277381495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2277381495
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.966674776
Short name T347
Test name
Test status
Simulation time 842223127 ps
CPU time 16.28 seconds
Started Jul 17 07:42:51 PM PDT 24
Finished Jul 17 07:43:10 PM PDT 24
Peak memory 225448 kb
Host smart-c47ce596-2020-446a-8ecb-772783a4fc7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966674776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.966674776
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3416438051
Short name T537
Test name
Test status
Simulation time 917479219 ps
CPU time 7.88 seconds
Started Jul 17 07:42:39 PM PDT 24
Finished Jul 17 07:42:48 PM PDT 24
Peak memory 226028 kb
Host smart-69bf84ea-1c5c-49ba-ada9-1dfa1e85be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416438051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3416438051
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1861069801
Short name T76
Test name
Test status
Simulation time 70606792 ps
CPU time 2.26 seconds
Started Jul 17 07:42:39 PM PDT 24
Finished Jul 17 07:42:42 PM PDT 24
Peak memory 217720 kb
Host smart-8eab6285-e72c-4577-81e2-62b1534645ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861069801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1861069801
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1419826366
Short name T748
Test name
Test status
Simulation time 231321896 ps
CPU time 23.97 seconds
Started Jul 17 07:42:42 PM PDT 24
Finished Jul 17 07:43:08 PM PDT 24
Peak memory 251252 kb
Host smart-7a2ab3ce-9e00-40a8-a1cf-eca79b60549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419826366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1419826366
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2473854594
Short name T225
Test name
Test status
Simulation time 308764873 ps
CPU time 7.32 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:49 PM PDT 24
Peak memory 250924 kb
Host smart-df453b08-a5a2-4009-8cbf-7f1909e48617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473854594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2473854594
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.673648867
Short name T557
Test name
Test status
Simulation time 12723898080 ps
CPU time 96.67 seconds
Started Jul 17 07:42:49 PM PDT 24
Finished Jul 17 07:44:27 PM PDT 24
Peak memory 274148 kb
Host smart-5f3eb4a1-1f6e-4e8a-994b-f8237df2679c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673648867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.673648867
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3555730509
Short name T9
Test name
Test status
Simulation time 12798111 ps
CPU time 0.92 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:44 PM PDT 24
Peak memory 208588 kb
Host smart-709c4127-e47f-4951-8766-07f9bd98271f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555730509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3555730509
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2732403539
Short name T289
Test name
Test status
Simulation time 84604050 ps
CPU time 1.23 seconds
Started Jul 17 07:42:45 PM PDT 24
Finished Jul 17 07:42:47 PM PDT 24
Peak memory 208984 kb
Host smart-82ecd74e-e8f6-40de-a026-e8b2818690e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732403539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2732403539
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2725617146
Short name T273
Test name
Test status
Simulation time 36556173 ps
CPU time 0.91 seconds
Started Jul 17 07:42:42 PM PDT 24
Finished Jul 17 07:42:44 PM PDT 24
Peak memory 208760 kb
Host smart-d3a5aae9-0195-43bd-b681-123a8f330f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725617146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2725617146
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3553982324
Short name T232
Test name
Test status
Simulation time 2879401837 ps
CPU time 21.22 seconds
Started Jul 17 07:42:43 PM PDT 24
Finished Jul 17 07:43:06 PM PDT 24
Peak memory 218224 kb
Host smart-95179860-4a5f-4d00-9387-a9af72989a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553982324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3553982324
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.791482951
Short name T173
Test name
Test status
Simulation time 1065851269 ps
CPU time 10.97 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:43:01 PM PDT 24
Peak memory 217444 kb
Host smart-4d23da3a-d0c0-4bc0-bde7-37067f0e9f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791482951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.791482951
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2197239034
Short name T91
Test name
Test status
Simulation time 2610162636 ps
CPU time 38.5 seconds
Started Jul 17 07:42:45 PM PDT 24
Finished Jul 17 07:43:24 PM PDT 24
Peak memory 218208 kb
Host smart-4d3e0cd7-606f-41b6-ad9a-82a9a043ea2b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197239034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2197239034
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1904490585
Short name T424
Test name
Test status
Simulation time 635030030 ps
CPU time 8.83 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:42:59 PM PDT 24
Peak memory 217776 kb
Host smart-eb95d09d-1c1b-4b1a-9290-03afc1561650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904490585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
904490585
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2972187975
Short name T629
Test name
Test status
Simulation time 164661614 ps
CPU time 6 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:42:55 PM PDT 24
Peak memory 218160 kb
Host smart-d48983c6-6459-4faf-aaba-dbae113fe805
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972187975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2972187975
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3271556170
Short name T77
Test name
Test status
Simulation time 2340076122 ps
CPU time 14.98 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:57 PM PDT 24
Peak memory 217704 kb
Host smart-bd23c0e6-1e92-40b2-ab54-414c1295da20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271556170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3271556170
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1553673864
Short name T643
Test name
Test status
Simulation time 454761811 ps
CPU time 7.19 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:49 PM PDT 24
Peak memory 217664 kb
Host smart-397125da-dd44-4f64-9603-9e51a6c19d93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553673864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1553673864
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2459966881
Short name T737
Test name
Test status
Simulation time 829900553 ps
CPU time 38.16 seconds
Started Jul 17 07:42:54 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 251088 kb
Host smart-e6aa8cdb-08f3-4f72-9ced-b0a8d790886d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459966881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2459966881
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2376267001
Short name T197
Test name
Test status
Simulation time 1027114604 ps
CPU time 11.4 seconds
Started Jul 17 07:42:55 PM PDT 24
Finished Jul 17 07:43:08 PM PDT 24
Peak memory 251112 kb
Host smart-12b35007-50b6-42c9-980e-a827de6427a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376267001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2376267001
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.647586556
Short name T717
Test name
Test status
Simulation time 289601235 ps
CPU time 3.48 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:46 PM PDT 24
Peak memory 222476 kb
Host smart-0946a2c8-6b61-4baf-a82a-ccd0e047b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647586556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.647586556
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1770527394
Short name T798
Test name
Test status
Simulation time 2767939154 ps
CPU time 8.03 seconds
Started Jul 17 07:42:42 PM PDT 24
Finished Jul 17 07:42:52 PM PDT 24
Peak memory 214064 kb
Host smart-5c64014a-81b5-4025-abae-937829b06353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770527394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1770527394
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3254570789
Short name T95
Test name
Test status
Simulation time 276069805 ps
CPU time 25.26 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:43:07 PM PDT 24
Peak memory 284472 kb
Host smart-64ea11ea-dfeb-400e-82f1-b6a3b3a09c8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254570789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3254570789
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1005790790
Short name T307
Test name
Test status
Simulation time 1347602335 ps
CPU time 11.88 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:43:02 PM PDT 24
Peak memory 218884 kb
Host smart-95f92d64-0eaa-461b-800a-7f81e91ced1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005790790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1005790790
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4109171324
Short name T372
Test name
Test status
Simulation time 1967835355 ps
CPU time 12.22 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:55 PM PDT 24
Peak memory 226012 kb
Host smart-b848a6f8-c4f4-48f3-8ec7-369aa4a29712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109171324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.4109171324
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1645353791
Short name T487
Test name
Test status
Simulation time 1044697476 ps
CPU time 10.87 seconds
Started Jul 17 07:42:33 PM PDT 24
Finished Jul 17 07:42:45 PM PDT 24
Peak memory 226160 kb
Host smart-b3cc2867-bcaa-44e7-a7f3-b03ee32b3d0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645353791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
645353791
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2977151153
Short name T394
Test name
Test status
Simulation time 313249017 ps
CPU time 12.01 seconds
Started Jul 17 07:42:42 PM PDT 24
Finished Jul 17 07:42:55 PM PDT 24
Peak memory 218476 kb
Host smart-a5a58da9-5ccb-4967-80f5-c4ed7dd773f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977151153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2977151153
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1620701195
Short name T69
Test name
Test status
Simulation time 38689246 ps
CPU time 0.85 seconds
Started Jul 17 07:42:40 PM PDT 24
Finished Jul 17 07:42:42 PM PDT 24
Peak memory 208748 kb
Host smart-d52ed20b-f0b1-43cd-aaa9-cd2cd5dbebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620701195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1620701195
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2566273407
Short name T149
Test name
Test status
Simulation time 1012352182 ps
CPU time 25.98 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:43:08 PM PDT 24
Peak memory 246996 kb
Host smart-88ff23b3-c7d0-4faf-a7b9-5a8faeebd7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566273407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2566273407
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2882854133
Short name T653
Test name
Test status
Simulation time 246230856 ps
CPU time 9.23 seconds
Started Jul 17 07:42:42 PM PDT 24
Finished Jul 17 07:42:53 PM PDT 24
Peak memory 244364 kb
Host smart-95ec54e7-64c1-47a0-bb5d-39601a4c711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882854133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2882854133
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2597216246
Short name T859
Test name
Test status
Simulation time 17177535206 ps
CPU time 90.47 seconds
Started Jul 17 07:42:55 PM PDT 24
Finished Jul 17 07:44:27 PM PDT 24
Peak memory 267596 kb
Host smart-201cd68d-da47-4aa3-9900-b011b436e1ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597216246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2597216246
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3647640287
Short name T580
Test name
Test status
Simulation time 13869045176 ps
CPU time 296.59 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:47:39 PM PDT 24
Peak memory 421752 kb
Host smart-c5b36074-425f-4a54-a280-632f0e4f9be9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3647640287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3647640287
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2533633579
Short name T37
Test name
Test status
Simulation time 14872995 ps
CPU time 0.91 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:44 PM PDT 24
Peak memory 211868 kb
Host smart-15d1a396-7aff-4e98-8244-f663b1ff978c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533633579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2533633579
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1571368126
Short name T527
Test name
Test status
Simulation time 1220261988 ps
CPU time 18.18 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:11 PM PDT 24
Peak memory 218216 kb
Host smart-c1d3dbf0-bc44-4e2d-bc62-a6eaaa469cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571368126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1571368126
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2613855212
Short name T31
Test name
Test status
Simulation time 3643372468 ps
CPU time 5.77 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:04 PM PDT 24
Peak memory 217764 kb
Host smart-ef0d6059-77a9-40e7-8f6b-e8178d1daedf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613855212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2613855212
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1339147817
Short name T788
Test name
Test status
Simulation time 4701578428 ps
CPU time 66.71 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:46:06 PM PDT 24
Peak memory 226040 kb
Host smart-2c874cde-be2d-45c2-9557-cec69693c5af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339147817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1339147817
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3299548654
Short name T26
Test name
Test status
Simulation time 1478865114 ps
CPU time 11.43 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:09 PM PDT 24
Peak memory 223116 kb
Host smart-0d0b3569-c41b-4d2a-be28-3ddd5918264b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299548654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3299548654
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2789320558
Short name T334
Test name
Test status
Simulation time 234908590 ps
CPU time 7.82 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:02 PM PDT 24
Peak memory 217640 kb
Host smart-b7fed135-5445-4760-a984-7c383a4a8ca5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789320558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2789320558
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1165366149
Short name T759
Test name
Test status
Simulation time 2973315247 ps
CPU time 49.38 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:44 PM PDT 24
Peak memory 275540 kb
Host smart-36428aa8-a869-45cf-89d1-6cd98ddf6f7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165366149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1165366149
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3045453713
Short name T695
Test name
Test status
Simulation time 554334948 ps
CPU time 9.56 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:07 PM PDT 24
Peak memory 218060 kb
Host smart-5807de33-6aca-4b08-b3d6-0ab34c1db3b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045453713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3045453713
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4294455968
Short name T336
Test name
Test status
Simulation time 99094395 ps
CPU time 3.11 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:44:55 PM PDT 24
Peak memory 218204 kb
Host smart-4578be12-170d-4e3c-8a1d-2dcc47e38559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294455968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4294455968
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3400818084
Short name T663
Test name
Test status
Simulation time 323539648 ps
CPU time 15.98 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:12 PM PDT 24
Peak memory 219472 kb
Host smart-a7fce0c5-5f4e-40dc-80cf-28976b08d79c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400818084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3400818084
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.719125428
Short name T744
Test name
Test status
Simulation time 1008226393 ps
CPU time 10.33 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:05 PM PDT 24
Peak memory 226016 kb
Host smart-88b239f7-be8f-4fbc-9a89-82b4dcddf14c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719125428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.719125428
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3760408928
Short name T356
Test name
Test status
Simulation time 580188363 ps
CPU time 7.34 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:05 PM PDT 24
Peak memory 218316 kb
Host smart-c6eccfd2-509c-42c0-97a0-176709d57b2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760408928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3760408928
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2106657660
Short name T496
Test name
Test status
Simulation time 242391172 ps
CPU time 10.03 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:05 PM PDT 24
Peak memory 226028 kb
Host smart-4a62a4f6-f218-4e31-9eb8-3d772a9b5f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106657660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2106657660
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1111857406
Short name T850
Test name
Test status
Simulation time 60840597 ps
CPU time 3.49 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:44:52 PM PDT 24
Peak memory 217708 kb
Host smart-194851b5-b35b-4072-b2c3-c3db769b6d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111857406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1111857406
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.4178226738
Short name T516
Test name
Test status
Simulation time 1048369389 ps
CPU time 23.63 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:45:15 PM PDT 24
Peak memory 244484 kb
Host smart-931ed59f-9729-4522-adb9-50f07ad8912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178226738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4178226738
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3082277372
Short name T732
Test name
Test status
Simulation time 271519731 ps
CPU time 6.1 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:04 PM PDT 24
Peak memory 246612 kb
Host smart-524f843f-aa56-4a8e-ba9d-94ccbf55de54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082277372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3082277372
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1039759362
Short name T396
Test name
Test status
Simulation time 40690099976 ps
CPU time 103.99 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:46:42 PM PDT 24
Peak memory 253348 kb
Host smart-5c70ac1d-d903-4522-9ee2-1ab862468184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039759362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1039759362
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2012081056
Short name T711
Test name
Test status
Simulation time 13020533 ps
CPU time 1.02 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:44:54 PM PDT 24
Peak memory 211896 kb
Host smart-ad1a22b9-d9e3-40af-b00a-7e11120cb7c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012081056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2012081056
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4056361702
Short name T103
Test name
Test status
Simulation time 22455741 ps
CPU time 1.01 seconds
Started Jul 17 07:44:54 PM PDT 24
Finished Jul 17 07:45:00 PM PDT 24
Peak memory 208864 kb
Host smart-e3e14615-e891-4050-b175-30658ea657d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056361702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4056361702
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3872769256
Short name T43
Test name
Test status
Simulation time 449166671 ps
CPU time 14.13 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:12 PM PDT 24
Peak memory 218212 kb
Host smart-b0c13275-f018-431a-b46d-1fcbaefe27cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872769256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3872769256
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3457918933
Short name T790
Test name
Test status
Simulation time 188692176 ps
CPU time 2.64 seconds
Started Jul 17 07:44:55 PM PDT 24
Finished Jul 17 07:45:01 PM PDT 24
Peak memory 217056 kb
Host smart-c0b7111b-2a59-4e94-b2b5-38178932f638
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457918933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3457918933
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3681177900
Short name T446
Test name
Test status
Simulation time 5248221241 ps
CPU time 34.56 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:32 PM PDT 24
Peak memory 225824 kb
Host smart-44eebc17-7dd1-4bf8-ad47-081e59094184
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681177900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3681177900
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.796740284
Short name T606
Test name
Test status
Simulation time 429511505 ps
CPU time 4.68 seconds
Started Jul 17 07:44:55 PM PDT 24
Finished Jul 17 07:45:03 PM PDT 24
Peak memory 222996 kb
Host smart-fa511058-b935-4b5b-9f9f-d66837e5466f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796740284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.796740284
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2105893549
Short name T784
Test name
Test status
Simulation time 3364649620 ps
CPU time 14.33 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:13 PM PDT 24
Peak memory 217780 kb
Host smart-02624600-9785-451f-b693-c2a2425e65cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105893549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2105893549
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2444348425
Short name T277
Test name
Test status
Simulation time 3305598064 ps
CPU time 76.22 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:46:14 PM PDT 24
Peak memory 267464 kb
Host smart-7960e80c-d458-4dd9-961a-1039e7f5515f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444348425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2444348425
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3561246620
Short name T27
Test name
Test status
Simulation time 1239395176 ps
CPU time 15.21 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:08 PM PDT 24
Peak memory 244188 kb
Host smart-aa08199e-1dfe-49da-a02b-e703683e9c40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561246620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3561246620
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2865665072
Short name T627
Test name
Test status
Simulation time 184053055 ps
CPU time 2.93 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:01 PM PDT 24
Peak memory 218200 kb
Host smart-7e426c89-991b-4506-8790-3d3e7239ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865665072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2865665072
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3019481996
Short name T13
Test name
Test status
Simulation time 948910266 ps
CPU time 9.8 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:45:09 PM PDT 24
Peak memory 225964 kb
Host smart-08602ae1-67cd-4257-8eaf-6300d62315a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019481996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3019481996
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3500053940
Short name T705
Test name
Test status
Simulation time 419526866 ps
CPU time 8.69 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:45:08 PM PDT 24
Peak memory 218236 kb
Host smart-f279e2fc-925a-4c99-bc5d-2b168f411ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500053940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3500053940
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1894788631
Short name T723
Test name
Test status
Simulation time 259920259 ps
CPU time 7.67 seconds
Started Jul 17 07:44:54 PM PDT 24
Finished Jul 17 07:45:06 PM PDT 24
Peak memory 218276 kb
Host smart-dd23c15a-a980-430a-a7e1-f2b2d1d0febc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894788631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1894788631
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.737845522
Short name T399
Test name
Test status
Simulation time 45314963 ps
CPU time 0.98 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 217696 kb
Host smart-05e77add-5204-4700-b283-fa87588a3b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737845522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.737845522
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1979335009
Short name T577
Test name
Test status
Simulation time 414411962 ps
CPU time 22.16 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:20 PM PDT 24
Peak memory 251016 kb
Host smart-26f477db-7acd-4454-8ec3-fb7ffc80ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979335009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1979335009
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1505448187
Short name T260
Test name
Test status
Simulation time 374218721 ps
CPU time 3.4 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:01 PM PDT 24
Peak memory 222144 kb
Host smart-2ca3fa1f-dc28-459a-8cd6-0fdc38fc66dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505448187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1505448187
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.545301748
Short name T597
Test name
Test status
Simulation time 45907936162 ps
CPU time 218.85 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:48:38 PM PDT 24
Peak memory 283716 kb
Host smart-0b302888-a8b4-4598-9d72-4f4ba2f4042d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545301748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.545301748
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3880092641
Short name T64
Test name
Test status
Simulation time 80379732036 ps
CPU time 691.08 seconds
Started Jul 17 07:44:55 PM PDT 24
Finished Jul 17 07:56:30 PM PDT 24
Peak memory 307380 kb
Host smart-83bea1a4-9fe7-4c26-b5d2-693d5e18459a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3880092641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3880092641
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2480581366
Short name T358
Test name
Test status
Simulation time 12224609 ps
CPU time 0.86 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 211804 kb
Host smart-8412de07-d299-482d-bd54-a3c145b71438
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480581366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2480581366
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2555836808
Short name T214
Test name
Test status
Simulation time 69264229 ps
CPU time 1.15 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:26 PM PDT 24
Peak memory 209024 kb
Host smart-1da1ba54-f37e-41be-968c-9e38e3650e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555836808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2555836808
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.949820831
Short name T623
Test name
Test status
Simulation time 1406433742 ps
CPU time 9.6 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:06 PM PDT 24
Peak memory 218016 kb
Host smart-f60dc3f6-d617-4972-94e7-a61e3e437135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949820831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.949820831
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1811687598
Short name T734
Test name
Test status
Simulation time 158265457 ps
CPU time 1.93 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:00 PM PDT 24
Peak memory 217076 kb
Host smart-ea2ef34a-9483-4407-ba56-0a0ab126c6e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811687598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1811687598
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1829650219
Short name T535
Test name
Test status
Simulation time 7463079050 ps
CPU time 28.11 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:24 PM PDT 24
Peak memory 218236 kb
Host smart-f7819c04-774e-4716-b926-86448e5928af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829650219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1829650219
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.899786646
Short name T514
Test name
Test status
Simulation time 494110429 ps
CPU time 7.91 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:04 PM PDT 24
Peak memory 218284 kb
Host smart-578021ce-a141-4aba-a95a-bafa4320984a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899786646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.899786646
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3805982678
Short name T83
Test name
Test status
Simulation time 154976690 ps
CPU time 3.24 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 217520 kb
Host smart-c52f85f2-48c5-408d-8cb6-52eca262ea27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805982678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3805982678
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3955840359
Short name T743
Test name
Test status
Simulation time 1838435503 ps
CPU time 40.89 seconds
Started Jul 17 07:44:54 PM PDT 24
Finished Jul 17 07:45:39 PM PDT 24
Peak memory 250908 kb
Host smart-e5e97356-2705-4c91-8a1b-44ead4e34a17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955840359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3955840359
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.556527574
Short name T544
Test name
Test status
Simulation time 381497619 ps
CPU time 9.14 seconds
Started Jul 17 07:44:54 PM PDT 24
Finished Jul 17 07:45:08 PM PDT 24
Peak memory 226324 kb
Host smart-42271fac-89fc-4a00-91e0-12e55beca32a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556527574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.556527574
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.749703292
Short name T674
Test name
Test status
Simulation time 151587843 ps
CPU time 2 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 218072 kb
Host smart-6239aee7-c572-4bab-8781-833a1bb3d21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749703292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.749703292
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3247104166
Short name T854
Test name
Test status
Simulation time 342473167 ps
CPU time 12.3 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:09 PM PDT 24
Peak memory 226084 kb
Host smart-f99f5fa5-0ca7-4e4b-a027-1a1db2fbf15d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247104166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3247104166
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.568022342
Short name T702
Test name
Test status
Simulation time 2316260277 ps
CPU time 12.73 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:09 PM PDT 24
Peak memory 226068 kb
Host smart-f31d70da-c2c5-433f-91fb-9381d74289e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568022342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.568022342
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.558617782
Short name T519
Test name
Test status
Simulation time 575127780 ps
CPU time 13.15 seconds
Started Jul 17 07:44:54 PM PDT 24
Finished Jul 17 07:45:12 PM PDT 24
Peak memory 218368 kb
Host smart-58269399-3da1-48ea-9aa1-903b2ecda0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558617782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.558617782
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2160624390
Short name T785
Test name
Test status
Simulation time 57615773 ps
CPU time 3.57 seconds
Started Jul 17 07:44:55 PM PDT 24
Finished Jul 17 07:45:02 PM PDT 24
Peak memory 217716 kb
Host smart-a3c668ed-8dfc-4656-b0b9-61793b856732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160624390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2160624390
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1640210662
Short name T314
Test name
Test status
Simulation time 423173914 ps
CPU time 22.1 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:45:22 PM PDT 24
Peak memory 247280 kb
Host smart-bfbbf20a-c40f-44bf-bb51-f04beed44b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640210662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1640210662
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3074432404
Short name T851
Test name
Test status
Simulation time 78063271 ps
CPU time 3.98 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:45:03 PM PDT 24
Peak memory 222696 kb
Host smart-ef64e823-f223-44d5-8f3d-7098d9c66665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074432404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3074432404
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2438567653
Short name T591
Test name
Test status
Simulation time 9184723931 ps
CPU time 63.87 seconds
Started Jul 17 07:45:15 PM PDT 24
Finished Jul 17 07:46:20 PM PDT 24
Peak memory 266764 kb
Host smart-0b7ff73b-1cd3-45d2-8d75-19338d31de67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438567653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2438567653
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.10756723
Short name T669
Test name
Test status
Simulation time 119059277082 ps
CPU time 2492.52 seconds
Started Jul 17 07:45:19 PM PDT 24
Finished Jul 17 08:26:53 PM PDT 24
Peak memory 1151136 kb
Host smart-6fc191f3-9a62-45f7-baa1-5b3eb147cd7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=10756723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.10756723
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1361283004
Short name T342
Test name
Test status
Simulation time 19416071 ps
CPU time 0.96 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 212956 kb
Host smart-2af523ce-d120-4ca1-aa87-b4beeec91c20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361283004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1361283004
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3599831589
Short name T204
Test name
Test status
Simulation time 13770711 ps
CPU time 1.01 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:25 PM PDT 24
Peak memory 208832 kb
Host smart-b48c0d70-1646-4dcd-841c-1798d442629e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599831589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3599831589
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.374493736
Short name T412
Test name
Test status
Simulation time 1564374059 ps
CPU time 14.51 seconds
Started Jul 17 07:45:27 PM PDT 24
Finished Jul 17 07:45:43 PM PDT 24
Peak memory 218288 kb
Host smart-5e5c6c31-8ea2-47ab-9cc8-d6c7c0dd8c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374493736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.374493736
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.822979107
Short name T374
Test name
Test status
Simulation time 265528163 ps
CPU time 7.34 seconds
Started Jul 17 07:45:16 PM PDT 24
Finished Jul 17 07:45:24 PM PDT 24
Peak memory 217340 kb
Host smart-26bd107d-7ac8-4b50-ad1b-e0603c5691bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822979107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.822979107
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2430881169
Short name T820
Test name
Test status
Simulation time 4599741865 ps
CPU time 29.39 seconds
Started Jul 17 07:45:20 PM PDT 24
Finished Jul 17 07:45:50 PM PDT 24
Peak memory 218228 kb
Host smart-8e8b670c-e57d-4535-bddf-f65255450667
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430881169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2430881169
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1199981879
Short name T196
Test name
Test status
Simulation time 250705785 ps
CPU time 4.07 seconds
Started Jul 17 07:45:15 PM PDT 24
Finished Jul 17 07:45:20 PM PDT 24
Peak memory 218176 kb
Host smart-27c5b330-b3b7-4709-9379-b691eee43b4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199981879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1199981879
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.34793659
Short name T86
Test name
Test status
Simulation time 746821228 ps
CPU time 10.85 seconds
Started Jul 17 07:45:18 PM PDT 24
Finished Jul 17 07:45:30 PM PDT 24
Peak memory 217644 kb
Host smart-463bd1ba-3f8e-4afb-81e4-e906553faff1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.34793659
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.819815851
Short name T98
Test name
Test status
Simulation time 3830424752 ps
CPU time 39.8 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:46:03 PM PDT 24
Peak memory 266460 kb
Host smart-0dafac90-e55a-4f3c-90e2-cab2b04806c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819815851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.819815851
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1401570846
Short name T386
Test name
Test status
Simulation time 579514602 ps
CPU time 16.43 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:45:40 PM PDT 24
Peak memory 242700 kb
Host smart-02ba1e7c-16e6-48d4-9635-4ffb13fb3cd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401570846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1401570846
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4119564075
Short name T355
Test name
Test status
Simulation time 73887695 ps
CPU time 2.82 seconds
Started Jul 17 07:45:25 PM PDT 24
Finished Jul 17 07:45:30 PM PDT 24
Peak memory 218276 kb
Host smart-51aa087b-0a9c-423c-a77b-6701a3aae22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119564075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4119564075
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.647573699
Short name T614
Test name
Test status
Simulation time 1161363884 ps
CPU time 11.68 seconds
Started Jul 17 07:45:25 PM PDT 24
Finished Jul 17 07:45:38 PM PDT 24
Peak memory 218300 kb
Host smart-0640a2f6-b9f1-40ea-ba34-af0afd4a69a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647573699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.647573699
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.4082812380
Short name T581
Test name
Test status
Simulation time 785361140 ps
CPU time 11.53 seconds
Started Jul 17 07:45:23 PM PDT 24
Finished Jul 17 07:45:37 PM PDT 24
Peak memory 226012 kb
Host smart-be697623-3cb5-47ed-938b-bd8dd99e5472
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082812380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.4082812380
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.364641755
Short name T665
Test name
Test status
Simulation time 808947002 ps
CPU time 6.49 seconds
Started Jul 17 07:45:18 PM PDT 24
Finished Jul 17 07:45:26 PM PDT 24
Peak memory 226020 kb
Host smart-973cfbe1-c6e7-4412-b603-e3e2bf99dc8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364641755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.364641755
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2218847152
Short name T453
Test name
Test status
Simulation time 476118321 ps
CPU time 6.43 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:30 PM PDT 24
Peak memory 226032 kb
Host smart-212abaa9-8d69-4333-a4d9-07ee36109ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218847152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2218847152
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2856015532
Short name T65
Test name
Test status
Simulation time 191040429 ps
CPU time 3.15 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:45:26 PM PDT 24
Peak memory 214848 kb
Host smart-bd294d3e-20c8-4152-8ff2-73f530507295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856015532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2856015532
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.95385723
Short name T561
Test name
Test status
Simulation time 302248023 ps
CPU time 22.37 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:45:45 PM PDT 24
Peak memory 249860 kb
Host smart-9de87dce-ec03-473b-82bb-20fca0fff893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95385723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.95385723
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.4192114280
Short name T456
Test name
Test status
Simulation time 164909813 ps
CPU time 3.66 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:27 PM PDT 24
Peak memory 221420 kb
Host smart-bf9ba399-18e1-434d-bc78-d3eab2a5987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192114280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.4192114280
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3887854919
Short name T638
Test name
Test status
Simulation time 11795119747 ps
CPU time 113.83 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:47:15 PM PDT 24
Peak memory 275764 kb
Host smart-6a72cbe6-7ad6-4e8f-b5af-d7ab0f02fc3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887854919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3887854919
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2468761156
Short name T156
Test name
Test status
Simulation time 61490114588 ps
CPU time 326.6 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:50:51 PM PDT 24
Peak memory 421304 kb
Host smart-b44ae43c-f211-4e90-8642-9fe12a4f2408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2468761156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2468761156
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2402365530
Short name T21
Test name
Test status
Simulation time 29054932 ps
CPU time 1.1 seconds
Started Jul 17 07:45:23 PM PDT 24
Finished Jul 17 07:45:26 PM PDT 24
Peak memory 213040 kb
Host smart-8933dbd9-3c7e-42d4-8c5c-1aad42bca4ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402365530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2402365530
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3167740990
Short name T672
Test name
Test status
Simulation time 15639052 ps
CPU time 0.86 seconds
Started Jul 17 07:45:27 PM PDT 24
Finished Jul 17 07:45:30 PM PDT 24
Peak memory 208744 kb
Host smart-9b8262e4-0f36-4cc6-9c2b-b250e352f708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167740990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3167740990
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.812118268
Short name T316
Test name
Test status
Simulation time 1398701694 ps
CPU time 13.42 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:38 PM PDT 24
Peak memory 218208 kb
Host smart-7e50cb67-dc94-4fc4-8290-e30afbc4e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812118268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.812118268
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1172371653
Short name T780
Test name
Test status
Simulation time 1063597611 ps
CPU time 9.12 seconds
Started Jul 17 07:45:15 PM PDT 24
Finished Jul 17 07:45:25 PM PDT 24
Peak memory 217320 kb
Host smart-d7767213-76be-4838-b52a-a1f6ec110a50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172371653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1172371653
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3738807974
Short name T404
Test name
Test status
Simulation time 3297828039 ps
CPU time 29.21 seconds
Started Jul 17 07:45:24 PM PDT 24
Finished Jul 17 07:45:55 PM PDT 24
Peak memory 218968 kb
Host smart-40862982-cbfb-4c71-9619-26fd13180ee2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738807974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3738807974
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1539871825
Short name T470
Test name
Test status
Simulation time 527382503 ps
CPU time 8.06 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:32 PM PDT 24
Peak memory 218144 kb
Host smart-27cc3baf-06e8-4c6e-a629-56a87513f974
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539871825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1539871825
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2918844175
Short name T238
Test name
Test status
Simulation time 2314525514 ps
CPU time 13.86 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:38 PM PDT 24
Peak memory 217760 kb
Host smart-8d6f5766-1113-4517-970e-92cf1f5e246f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918844175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2918844175
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3615050411
Short name T497
Test name
Test status
Simulation time 2624187499 ps
CPU time 71.72 seconds
Started Jul 17 07:45:25 PM PDT 24
Finished Jul 17 07:46:39 PM PDT 24
Peak memory 269116 kb
Host smart-629d6a32-2959-45d6-a6fa-4408698785c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615050411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3615050411
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.679325825
Short name T461
Test name
Test status
Simulation time 2909502781 ps
CPU time 11.22 seconds
Started Jul 17 07:45:17 PM PDT 24
Finished Jul 17 07:45:29 PM PDT 24
Peak memory 246436 kb
Host smart-51701e16-5487-403e-810f-c6e86fee1c30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679325825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.679325825
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.665571286
Short name T66
Test name
Test status
Simulation time 75071819 ps
CPU time 3.77 seconds
Started Jul 17 07:45:17 PM PDT 24
Finished Jul 17 07:45:22 PM PDT 24
Peak memory 222332 kb
Host smart-ba2cf9cc-6c4c-407a-b981-962b1d9c68cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665571286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.665571286
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2768801606
Short name T600
Test name
Test status
Simulation time 236510740 ps
CPU time 10.11 seconds
Started Jul 17 07:45:16 PM PDT 24
Finished Jul 17 07:45:28 PM PDT 24
Peak memory 226024 kb
Host smart-69d8bceb-6afe-4eca-b51a-d6e0e13d41a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768801606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2768801606
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1291966786
Short name T464
Test name
Test status
Simulation time 772781031 ps
CPU time 10.67 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:35 PM PDT 24
Peak memory 226028 kb
Host smart-65ae39e2-55eb-4319-943b-7c648af60168
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291966786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1291966786
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4098230693
Short name T311
Test name
Test status
Simulation time 237305506 ps
CPU time 9.56 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:34 PM PDT 24
Peak memory 226028 kb
Host smart-60d08780-d4f0-4163-a208-9bfebf667017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098230693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4098230693
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2155325867
Short name T867
Test name
Test status
Simulation time 954555315 ps
CPU time 7.87 seconds
Started Jul 17 07:45:23 PM PDT 24
Finished Jul 17 07:45:33 PM PDT 24
Peak memory 226092 kb
Host smart-ed7aecc3-bfe1-4357-a810-e3c30fb4da11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155325867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2155325867
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2071695709
Short name T645
Test name
Test status
Simulation time 47396011 ps
CPU time 1.11 seconds
Started Jul 17 07:45:24 PM PDT 24
Finished Jul 17 07:45:27 PM PDT 24
Peak memory 212016 kb
Host smart-9279d787-d802-409a-bf5b-0636efd69061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071695709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2071695709
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1106055857
Short name T97
Test name
Test status
Simulation time 847273749 ps
CPU time 26.14 seconds
Started Jul 17 07:45:16 PM PDT 24
Finished Jul 17 07:45:43 PM PDT 24
Peak memory 250928 kb
Host smart-0811b790-67bc-4c0f-9641-8b40e6d738bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106055857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1106055857
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3081269286
Short name T100
Test name
Test status
Simulation time 339865098 ps
CPU time 7.23 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:31 PM PDT 24
Peak memory 247448 kb
Host smart-5161bab9-6e8b-447d-8e1b-43376afc4b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081269286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3081269286
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3028480930
Short name T657
Test name
Test status
Simulation time 1868748249 ps
CPU time 72.53 seconds
Started Jul 17 07:45:17 PM PDT 24
Finished Jul 17 07:46:30 PM PDT 24
Peak memory 248420 kb
Host smart-663e45fe-62ef-450b-89fe-822eedb0caf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028480930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3028480930
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3404985733
Short name T688
Test name
Test status
Simulation time 11841439 ps
CPU time 1.02 seconds
Started Jul 17 07:45:16 PM PDT 24
Finished Jul 17 07:45:18 PM PDT 24
Peak memory 211920 kb
Host smart-e3b6448f-209d-4b8a-8b07-c1703ae0bf7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404985733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3404985733
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3230837432
Short name T208
Test name
Test status
Simulation time 64765145 ps
CPU time 1.11 seconds
Started Jul 17 07:45:30 PM PDT 24
Finished Jul 17 07:45:34 PM PDT 24
Peak memory 208940 kb
Host smart-b4a67bad-6b63-4567-8516-7c7d9b6d8895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230837432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3230837432
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.725897968
Short name T409
Test name
Test status
Simulation time 1623294219 ps
CPU time 13.52 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:45 PM PDT 24
Peak memory 218388 kb
Host smart-f85a2e1a-31ac-4446-a8d7-80b37c98c6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725897968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.725897968
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1875815732
Short name T7
Test name
Test status
Simulation time 737761362 ps
CPU time 2.44 seconds
Started Jul 17 07:45:32 PM PDT 24
Finished Jul 17 07:45:38 PM PDT 24
Peak memory 217100 kb
Host smart-7ca9008e-6bcd-4a14-b29b-84f78322133f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875815732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1875815732
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3225292758
Short name T160
Test name
Test status
Simulation time 292063633 ps
CPU time 9.11 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:41 PM PDT 24
Peak memory 218160 kb
Host smart-dd2643c1-da52-487d-a2eb-bfa418ae597c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225292758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3225292758
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2873629037
Short name T812
Test name
Test status
Simulation time 263541214 ps
CPU time 7.92 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:39 PM PDT 24
Peak memory 217644 kb
Host smart-ae9ef651-f433-4608-a862-8001b5bfdca4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873629037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2873629037
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3215675603
Short name T856
Test name
Test status
Simulation time 11901834617 ps
CPU time 63.26 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:46:35 PM PDT 24
Peak memory 283704 kb
Host smart-54918144-f125-420e-b2f8-fca46b30ebf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215675603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3215675603
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3526304317
Short name T441
Test name
Test status
Simulation time 292804863 ps
CPU time 10.69 seconds
Started Jul 17 07:45:26 PM PDT 24
Finished Jul 17 07:45:39 PM PDT 24
Peak memory 226324 kb
Host smart-3f25af06-9296-4547-a2d0-29a69d98f1f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526304317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3526304317
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.4068008550
Short name T391
Test name
Test status
Simulation time 64110928 ps
CPU time 1.9 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:33 PM PDT 24
Peak memory 222052 kb
Host smart-78d900d8-e365-4f5d-b4a3-5b93c4a7966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068008550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.4068008550
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2467007663
Short name T439
Test name
Test status
Simulation time 962217557 ps
CPU time 9.59 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:41 PM PDT 24
Peak memory 226040 kb
Host smart-56c4a526-2bac-4e11-b51d-c72b6914ec05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467007663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2467007663
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3251496002
Short name T554
Test name
Test status
Simulation time 1254842188 ps
CPU time 13.05 seconds
Started Jul 17 07:45:32 PM PDT 24
Finished Jul 17 07:45:48 PM PDT 24
Peak memory 226020 kb
Host smart-740043d9-b263-4d81-ac9a-4c6e936b5073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251496002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3251496002
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3026079144
Short name T829
Test name
Test status
Simulation time 194023523 ps
CPU time 7.88 seconds
Started Jul 17 07:45:33 PM PDT 24
Finished Jul 17 07:45:44 PM PDT 24
Peak memory 218220 kb
Host smart-25face6c-32e1-42ae-ba60-eac5dfc19599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026079144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3026079144
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.342950527
Short name T852
Test name
Test status
Simulation time 1154585087 ps
CPU time 8.39 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:40 PM PDT 24
Peak memory 218364 kb
Host smart-817d616f-6132-4ce1-917e-67a1bed52971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342950527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.342950527
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2063024508
Short name T824
Test name
Test status
Simulation time 41269253 ps
CPU time 2.61 seconds
Started Jul 17 07:45:27 PM PDT 24
Finished Jul 17 07:45:32 PM PDT 24
Peak memory 214420 kb
Host smart-152e993d-a4ad-48ba-aa76-95ac11fe3b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063024508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2063024508
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3152892767
Short name T741
Test name
Test status
Simulation time 696341048 ps
CPU time 17.29 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:49 PM PDT 24
Peak memory 251140 kb
Host smart-f1c88ad1-26f9-472b-b231-fb6b7118487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152892767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3152892767
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2969091356
Short name T224
Test name
Test status
Simulation time 566131305 ps
CPU time 8.28 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:39 PM PDT 24
Peak memory 251144 kb
Host smart-cfd5d8c2-8a94-4620-b26e-adae8a1f5731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969091356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2969091356
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.955920984
Short name T841
Test name
Test status
Simulation time 147155598506 ps
CPU time 213.09 seconds
Started Jul 17 07:45:33 PM PDT 24
Finished Jul 17 07:49:09 PM PDT 24
Peak memory 283796 kb
Host smart-5c545141-944d-441b-8670-b5ce8c4fa7b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955920984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.955920984
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.194757555
Short name T475
Test name
Test status
Simulation time 18551884 ps
CPU time 0.83 seconds
Started Jul 17 07:45:30 PM PDT 24
Finished Jul 17 07:45:33 PM PDT 24
Peak memory 212168 kb
Host smart-53dda72e-e9e4-4b14-b4ae-6dcae9bf167d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194757555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.194757555
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2202259578
Short name T479
Test name
Test status
Simulation time 14592898 ps
CPU time 0.78 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:45:23 PM PDT 24
Peak memory 208680 kb
Host smart-f779191f-63c5-480c-b08b-e156463a00d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202259578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2202259578
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2112057277
Short name T491
Test name
Test status
Simulation time 923564031 ps
CPU time 13.28 seconds
Started Jul 17 07:45:35 PM PDT 24
Finished Jul 17 07:45:50 PM PDT 24
Peak memory 218180 kb
Host smart-61212a91-a652-4354-85fa-38ef29347d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112057277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2112057277
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1634068972
Short name T310
Test name
Test status
Simulation time 577579602 ps
CPU time 4.03 seconds
Started Jul 17 07:45:34 PM PDT 24
Finished Jul 17 07:45:41 PM PDT 24
Peak memory 217064 kb
Host smart-30b4ece6-c1fc-4946-bd11-f613f9a38cf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634068972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1634068972
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2443113103
Short name T302
Test name
Test status
Simulation time 3537092563 ps
CPU time 49.15 seconds
Started Jul 17 07:45:31 PM PDT 24
Finished Jul 17 07:46:23 PM PDT 24
Peak memory 218736 kb
Host smart-35144eb3-7b02-43e0-bc08-42cad1e916eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443113103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2443113103
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3862123475
Short name T101
Test name
Test status
Simulation time 734807190 ps
CPU time 3.71 seconds
Started Jul 17 07:45:28 PM PDT 24
Finished Jul 17 07:45:34 PM PDT 24
Peak memory 218164 kb
Host smart-e1c465cb-8792-46ab-b31b-b55f832ef460
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862123475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3862123475
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3114543468
Short name T803
Test name
Test status
Simulation time 3970415402 ps
CPU time 8.11 seconds
Started Jul 17 07:45:34 PM PDT 24
Finished Jul 17 07:45:45 PM PDT 24
Peak memory 217664 kb
Host smart-ba9884df-d233-4146-bb89-50635f726ecf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114543468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3114543468
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2442814575
Short name T625
Test name
Test status
Simulation time 3932346751 ps
CPU time 37.98 seconds
Started Jul 17 07:45:34 PM PDT 24
Finished Jul 17 07:46:14 PM PDT 24
Peak memory 252036 kb
Host smart-1d2f1308-4dea-4073-bb0c-5a90152d1f60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442814575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2442814575
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3113537197
Short name T786
Test name
Test status
Simulation time 797215194 ps
CPU time 16.56 seconds
Started Jul 17 07:45:34 PM PDT 24
Finished Jul 17 07:45:53 PM PDT 24
Peak memory 248496 kb
Host smart-42243824-bcbb-4310-9640-2797e9ad5857
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113537197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3113537197
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.290483581
Short name T222
Test name
Test status
Simulation time 103662521 ps
CPU time 3.05 seconds
Started Jul 17 07:45:31 PM PDT 24
Finished Jul 17 07:45:38 PM PDT 24
Peak memory 222336 kb
Host smart-0668b5ad-e06f-4448-8d58-f295befdfdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290483581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.290483581
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.563367434
Short name T348
Test name
Test status
Simulation time 1517438891 ps
CPU time 11.69 seconds
Started Jul 17 07:45:35 PM PDT 24
Finished Jul 17 07:45:49 PM PDT 24
Peak memory 219888 kb
Host smart-7577c4c7-61ed-4f7a-b31f-4aac48ea78e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563367434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.563367434
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.691674751
Short name T264
Test name
Test status
Simulation time 685972065 ps
CPU time 8.69 seconds
Started Jul 17 07:45:35 PM PDT 24
Finished Jul 17 07:45:46 PM PDT 24
Peak memory 225996 kb
Host smart-8addc4d3-3fbd-4362-b116-354ca115fdc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691674751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.691674751
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3918339814
Short name T603
Test name
Test status
Simulation time 1449388089 ps
CPU time 8.96 seconds
Started Jul 17 07:45:35 PM PDT 24
Finished Jul 17 07:45:46 PM PDT 24
Peak memory 225996 kb
Host smart-1b1e4434-6244-43e1-8be0-55b9df6ed2a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918339814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3918339814
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.956151178
Short name T715
Test name
Test status
Simulation time 450652192 ps
CPU time 6.13 seconds
Started Jul 17 07:45:31 PM PDT 24
Finished Jul 17 07:45:39 PM PDT 24
Peak memory 224544 kb
Host smart-a61b7f00-7467-411c-8237-cf9395f54ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956151178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.956151178
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2135216531
Short name T848
Test name
Test status
Simulation time 11292197 ps
CPU time 1.1 seconds
Started Jul 17 07:45:33 PM PDT 24
Finished Jul 17 07:45:37 PM PDT 24
Peak memory 212248 kb
Host smart-be71cb4f-7993-4e10-aba3-99b1835420ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135216531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2135216531
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2202996503
Short name T313
Test name
Test status
Simulation time 312029487 ps
CPU time 24.64 seconds
Started Jul 17 07:45:34 PM PDT 24
Finished Jul 17 07:46:01 PM PDT 24
Peak memory 247472 kb
Host smart-d7c427bd-38b9-4f65-9878-ffd628752d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202996503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2202996503
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2642284096
Short name T90
Test name
Test status
Simulation time 116894301 ps
CPU time 6.41 seconds
Started Jul 17 07:45:30 PM PDT 24
Finished Jul 17 07:45:39 PM PDT 24
Peak memory 250532 kb
Host smart-b0f2aedd-c214-46ce-aa19-df4ba9a034aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642284096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2642284096
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1280931943
Short name T522
Test name
Test status
Simulation time 4679240986 ps
CPU time 156.55 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:47:58 PM PDT 24
Peak memory 282028 kb
Host smart-617a558e-6cd8-49a3-820a-07145ec0b2fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280931943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1280931943
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1905947322
Short name T806
Test name
Test status
Simulation time 92689813495 ps
CPU time 508.94 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:53:52 PM PDT 24
Peak memory 373136 kb
Host smart-910c15e7-080e-49e6-87ac-3e4538a138ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1905947322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1905947322
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1591026140
Short name T235
Test name
Test status
Simulation time 16379748 ps
CPU time 0.89 seconds
Started Jul 17 07:45:30 PM PDT 24
Finished Jul 17 07:45:34 PM PDT 24
Peak memory 211732 kb
Host smart-a04302d7-0b9a-4b56-8d66-fe010751d2f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591026140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1591026140
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2882479099
Short name T234
Test name
Test status
Simulation time 20868271 ps
CPU time 0.84 seconds
Started Jul 17 07:45:28 PM PDT 24
Finished Jul 17 07:45:32 PM PDT 24
Peak memory 208792 kb
Host smart-c1de2418-cc73-47be-b651-95f496676fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882479099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2882479099
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.355512620
Short name T239
Test name
Test status
Simulation time 384855728 ps
CPU time 8.58 seconds
Started Jul 17 07:45:23 PM PDT 24
Finished Jul 17 07:45:34 PM PDT 24
Peak memory 226008 kb
Host smart-3baabf09-fd20-4ed4-a1ec-4daa5587256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355512620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.355512620
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.674345784
Short name T168
Test name
Test status
Simulation time 73650924 ps
CPU time 2.58 seconds
Started Jul 17 07:45:27 PM PDT 24
Finished Jul 17 07:45:32 PM PDT 24
Peak memory 217056 kb
Host smart-439e1a3d-480b-4d02-b3a5-d6451c31b470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674345784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.674345784
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4186023369
Short name T858
Test name
Test status
Simulation time 16367569654 ps
CPU time 25.9 seconds
Started Jul 17 07:45:27 PM PDT 24
Finished Jul 17 07:45:55 PM PDT 24
Peak memory 225988 kb
Host smart-a9ff6573-c36a-4d1d-aa52-35387027e1a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186023369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4186023369
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.664276696
Short name T706
Test name
Test status
Simulation time 1094423062 ps
CPU time 15.52 seconds
Started Jul 17 07:45:27 PM PDT 24
Finished Jul 17 07:45:44 PM PDT 24
Peak memory 224004 kb
Host smart-d2143b8e-9741-4245-ade5-a2aa6303a77b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664276696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.664276696
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3976605921
Short name T370
Test name
Test status
Simulation time 131111964 ps
CPU time 2.81 seconds
Started Jul 17 07:45:21 PM PDT 24
Finished Jul 17 07:45:26 PM PDT 24
Peak memory 217520 kb
Host smart-5fc8a0b8-1162-4c5e-8b39-934f9510311f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976605921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3976605921
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1582222460
Short name T503
Test name
Test status
Simulation time 5704177516 ps
CPU time 55.6 seconds
Started Jul 17 07:45:24 PM PDT 24
Finished Jul 17 07:46:22 PM PDT 24
Peak memory 251256 kb
Host smart-f09633ce-56fc-402b-b81e-ae3779222f32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582222460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1582222460
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.382624144
Short name T729
Test name
Test status
Simulation time 3868313097 ps
CPU time 15.69 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:40 PM PDT 24
Peak memory 249504 kb
Host smart-918631e8-97f2-4483-aeae-3e82c3fd52bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382624144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.382624144
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1910541442
Short name T835
Test name
Test status
Simulation time 29616973 ps
CPU time 2.02 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:26 PM PDT 24
Peak memory 222040 kb
Host smart-e3b3f716-1b93-4295-8ffb-49b446f3a74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910541442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1910541442
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2056620186
Short name T534
Test name
Test status
Simulation time 329861019 ps
CPU time 12.65 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:44 PM PDT 24
Peak memory 226192 kb
Host smart-a831e618-11f9-467b-a4f0-35efd9782e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056620186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2056620186
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3290423961
Short name T383
Test name
Test status
Simulation time 4390342086 ps
CPU time 13.05 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:45:45 PM PDT 24
Peak memory 218456 kb
Host smart-c2751508-2f03-4a39-98e4-b7b143fd57c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290423961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3290423961
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.305205836
Short name T61
Test name
Test status
Simulation time 273644032 ps
CPU time 7.84 seconds
Started Jul 17 07:45:24 PM PDT 24
Finished Jul 17 07:45:33 PM PDT 24
Peak memory 218264 kb
Host smart-2c4716ee-5fbd-45a0-82c6-8a491b5299cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305205836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.305205836
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3879385519
Short name T668
Test name
Test status
Simulation time 390044543 ps
CPU time 3.14 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:28 PM PDT 24
Peak memory 217708 kb
Host smart-61fd0079-ac9c-4a7c-b5e8-db6afdda4066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879385519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3879385519
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.70583544
Short name T93
Test name
Test status
Simulation time 3984951153 ps
CPU time 30.53 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:54 PM PDT 24
Peak memory 250900 kb
Host smart-2c8537bc-e4b4-4a59-afec-652805efc7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70583544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.70583544
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3634083646
Short name T642
Test name
Test status
Simulation time 94626605 ps
CPU time 7.28 seconds
Started Jul 17 07:45:22 PM PDT 24
Finished Jul 17 07:45:31 PM PDT 24
Peak memory 250816 kb
Host smart-7167ac2d-a6cf-4c03-b5cc-f8ede72fabc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634083646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3634083646
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.686386828
Short name T817
Test name
Test status
Simulation time 5490575804 ps
CPU time 55.47 seconds
Started Jul 17 07:45:29 PM PDT 24
Finished Jul 17 07:46:27 PM PDT 24
Peak memory 251192 kb
Host smart-ab673e5c-339f-486c-8efb-7fb818441968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686386828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.686386828
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2893937605
Short name T330
Test name
Test status
Simulation time 37104917 ps
CPU time 0.95 seconds
Started Jul 17 07:45:55 PM PDT 24
Finished Jul 17 07:45:58 PM PDT 24
Peak memory 208768 kb
Host smart-c08c42b4-888a-46a1-9876-4d55bc6d2efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893937605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2893937605
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3669940090
Short name T469
Test name
Test status
Simulation time 1438049747 ps
CPU time 14.37 seconds
Started Jul 17 07:45:26 PM PDT 24
Finished Jul 17 07:45:43 PM PDT 24
Peak memory 218128 kb
Host smart-6756ae5e-db87-43ab-8951-a60ac9579686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669940090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3669940090
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1567146627
Short name T530
Test name
Test status
Simulation time 1430009996 ps
CPU time 14.3 seconds
Started Jul 17 07:45:55 PM PDT 24
Finished Jul 17 07:46:12 PM PDT 24
Peak memory 217656 kb
Host smart-a390fbf9-e57f-4646-9968-023a28d1578e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567146627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1567146627
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2956890332
Short name T807
Test name
Test status
Simulation time 10948512175 ps
CPU time 38.24 seconds
Started Jul 17 07:45:34 PM PDT 24
Finished Jul 17 07:46:15 PM PDT 24
Peak memory 218836 kb
Host smart-618448a2-e56b-46b4-ab11-ec2522cbc40f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956890332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2956890332
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2404533089
Short name T237
Test name
Test status
Simulation time 176842732 ps
CPU time 4.97 seconds
Started Jul 17 07:45:31 PM PDT 24
Finished Jul 17 07:45:40 PM PDT 24
Peak memory 218156 kb
Host smart-de69e472-ebcc-422c-9ba8-d8aad33d63d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404533089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2404533089
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1026734212
Short name T552
Test name
Test status
Simulation time 561166212 ps
CPU time 6.7 seconds
Started Jul 17 07:45:33 PM PDT 24
Finished Jul 17 07:45:43 PM PDT 24
Peak memory 217628 kb
Host smart-8a70b5a9-218d-416e-a2ac-d386e1d6aabd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026734212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1026734212
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1362175443
Short name T287
Test name
Test status
Simulation time 2564434933 ps
CPU time 41.11 seconds
Started Jul 17 07:45:32 PM PDT 24
Finished Jul 17 07:46:16 PM PDT 24
Peak memory 250960 kb
Host smart-9afd2dac-2164-43c8-aeb2-da5c31ddda44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362175443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1362175443
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1727990949
Short name T676
Test name
Test status
Simulation time 351854188 ps
CPU time 15.51 seconds
Started Jul 17 07:45:35 PM PDT 24
Finished Jul 17 07:45:53 PM PDT 24
Peak memory 250680 kb
Host smart-53b31574-92ce-4579-84b6-ce1bc4f401df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727990949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1727990949
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3996099021
Short name T390
Test name
Test status
Simulation time 149287518 ps
CPU time 3.68 seconds
Started Jul 17 07:45:25 PM PDT 24
Finished Jul 17 07:45:30 PM PDT 24
Peak memory 218116 kb
Host smart-1a3a494a-cad1-4656-afaf-29c9607a9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996099021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3996099021
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3956820937
Short name T698
Test name
Test status
Simulation time 1165589515 ps
CPU time 9.52 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:12 PM PDT 24
Peak memory 225992 kb
Host smart-be5f4e38-93cc-49e3-806c-f98f51607300
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956820937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3956820937
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1850016873
Short name T673
Test name
Test status
Simulation time 1970131223 ps
CPU time 11.51 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:15 PM PDT 24
Peak memory 226028 kb
Host smart-ab69dd4a-6496-42e3-8786-4f8e16535490
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850016873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1850016873
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1524688733
Short name T701
Test name
Test status
Simulation time 1580185445 ps
CPU time 12.89 seconds
Started Jul 17 07:45:54 PM PDT 24
Finished Jul 17 07:46:09 PM PDT 24
Peak memory 226020 kb
Host smart-97b92584-4239-4cb1-8af7-58627d126495
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524688733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1524688733
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2168400165
Short name T563
Test name
Test status
Simulation time 793067897 ps
CPU time 12.52 seconds
Started Jul 17 07:45:30 PM PDT 24
Finished Jul 17 07:45:44 PM PDT 24
Peak memory 225136 kb
Host smart-12a767ee-167f-4adc-9422-faef94badb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168400165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2168400165
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3929316331
Short name T82
Test name
Test status
Simulation time 81161161 ps
CPU time 2.74 seconds
Started Jul 17 07:45:32 PM PDT 24
Finished Jul 17 07:45:38 PM PDT 24
Peak memory 217784 kb
Host smart-34be6709-f479-4217-a88c-0cef1f65cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929316331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3929316331
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.105683823
Short name T763
Test name
Test status
Simulation time 302734009 ps
CPU time 22.08 seconds
Started Jul 17 07:45:26 PM PDT 24
Finished Jul 17 07:45:51 PM PDT 24
Peak memory 250948 kb
Host smart-05c6e846-9306-40b8-b32e-ad01588c09ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105683823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.105683823
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2174561854
Short name T488
Test name
Test status
Simulation time 65471142 ps
CPU time 3.52 seconds
Started Jul 17 07:45:33 PM PDT 24
Finished Jul 17 07:45:40 PM PDT 24
Peak memory 222500 kb
Host smart-9b659769-4abc-4fc3-a8ef-8ebcb4978c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174561854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2174561854
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.4136501098
Short name T613
Test name
Test status
Simulation time 7145092353 ps
CPU time 120.68 seconds
Started Jul 17 07:45:54 PM PDT 24
Finished Jul 17 07:47:57 PM PDT 24
Peak memory 226072 kb
Host smart-10adab23-4cb8-4d76-ab09-a1fd760c1eff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136501098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.4136501098
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2952781703
Short name T142
Test name
Test status
Simulation time 23037691095 ps
CPU time 275.88 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:50:36 PM PDT 24
Peak memory 277568 kb
Host smart-0b22f19c-a84c-449e-8b50-bfcdc7ab4252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2952781703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2952781703
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.689410803
Short name T407
Test name
Test status
Simulation time 57360224 ps
CPU time 0.83 seconds
Started Jul 17 07:45:26 PM PDT 24
Finished Jul 17 07:45:29 PM PDT 24
Peak memory 211904 kb
Host smart-ec39fcb9-58bc-4418-9cc3-162061dc7066
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689410803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.689410803
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3870741991
Short name T770
Test name
Test status
Simulation time 17064429 ps
CPU time 1.1 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:46:01 PM PDT 24
Peak memory 208856 kb
Host smart-71657814-52fa-410a-a798-efa06cd77b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870741991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3870741991
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.477775944
Short name T35
Test name
Test status
Simulation time 232942333 ps
CPU time 3.84 seconds
Started Jul 17 07:45:55 PM PDT 24
Finished Jul 17 07:46:00 PM PDT 24
Peak memory 217180 kb
Host smart-17d6e249-5924-4932-92e5-be56e4b21d2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477775944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.477775944
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3994287465
Short name T573
Test name
Test status
Simulation time 2483358837 ps
CPU time 70.46 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 225728 kb
Host smart-dc36712f-77e3-422a-acd4-053bff582ef2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994287465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3994287465
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4008543603
Short name T240
Test name
Test status
Simulation time 1570433202 ps
CPU time 7.64 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:46:07 PM PDT 24
Peak memory 218160 kb
Host smart-e4190cdc-3c17-4926-9652-4751ecf7f48c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008543603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4008543603
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2401792705
Short name T804
Test name
Test status
Simulation time 550473378 ps
CPU time 4.95 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:46:03 PM PDT 24
Peak memory 217584 kb
Host smart-f26d38ec-36de-4f50-a014-98652028676c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401792705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2401792705
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3875259932
Short name T866
Test name
Test status
Simulation time 20207579592 ps
CPU time 51.74 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:56 PM PDT 24
Peak memory 275604 kb
Host smart-8509a85e-10be-46bc-8abc-98674e222b6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875259932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3875259932
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3419283686
Short name T414
Test name
Test status
Simulation time 334664890 ps
CPU time 16.44 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:18 PM PDT 24
Peak memory 250908 kb
Host smart-6a4cd2e9-1f55-4fe4-a7f7-97aa995f9429
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419283686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3419283686
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.915540499
Short name T801
Test name
Test status
Simulation time 459151170 ps
CPU time 3.33 seconds
Started Jul 17 07:45:55 PM PDT 24
Finished Jul 17 07:46:01 PM PDT 24
Peak memory 218240 kb
Host smart-65e767de-71fd-46f2-99ff-35ef1deb8892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915540499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.915540499
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.756807096
Short name T440
Test name
Test status
Simulation time 694303741 ps
CPU time 14.42 seconds
Started Jul 17 07:45:54 PM PDT 24
Finished Jul 17 07:46:10 PM PDT 24
Peak memory 219448 kb
Host smart-b5595411-1043-4f06-800f-f234a0de02c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756807096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.756807096
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2944705566
Short name T200
Test name
Test status
Simulation time 407411885 ps
CPU time 11.05 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:15 PM PDT 24
Peak memory 226016 kb
Host smart-2cf6eb85-5451-4944-9072-121242ec3255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944705566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2944705566
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2577773892
Short name T579
Test name
Test status
Simulation time 2892369944 ps
CPU time 22.36 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:28 PM PDT 24
Peak memory 226088 kb
Host smart-641429d5-33d5-4a9d-8d17-2410092dfb0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577773892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2577773892
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.4144576553
Short name T758
Test name
Test status
Simulation time 1084129527 ps
CPU time 10.08 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:14 PM PDT 24
Peak memory 224996 kb
Host smart-3ed42011-ba02-47c6-8446-f8ce8bc03529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144576553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.4144576553
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3954101416
Short name T392
Test name
Test status
Simulation time 118529323 ps
CPU time 2.71 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:09 PM PDT 24
Peak memory 214780 kb
Host smart-07e2b05b-7d78-4ce2-91de-d2f3d028f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954101416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3954101416
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2861224529
Short name T401
Test name
Test status
Simulation time 230903485 ps
CPU time 25.49 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:46:24 PM PDT 24
Peak memory 247112 kb
Host smart-cc1d5f75-d6ec-45e7-a769-2a1f4d5dfbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861224529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2861224529
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3924338583
Short name T403
Test name
Test status
Simulation time 369352389 ps
CPU time 7.9 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:09 PM PDT 24
Peak memory 250808 kb
Host smart-bfee0d18-a4ff-4aeb-b3c7-20dddc1b0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924338583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3924338583
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1082152841
Short name T457
Test name
Test status
Simulation time 44923659255 ps
CPU time 348.76 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:51:50 PM PDT 24
Peak memory 279944 kb
Host smart-be4eb94a-91e2-4165-8147-65437b7d3acf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082152841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1082152841
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1050467589
Short name T740
Test name
Test status
Simulation time 41717863 ps
CPU time 0.97 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:01 PM PDT 24
Peak memory 211704 kb
Host smart-ee95e589-7c27-44ee-b1f2-717527c5a615
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050467589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1050467589
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1180289975
Short name T849
Test name
Test status
Simulation time 18850770 ps
CPU time 1.07 seconds
Started Jul 17 07:42:56 PM PDT 24
Finished Jul 17 07:42:58 PM PDT 24
Peak memory 208832 kb
Host smart-c35b071a-1ddb-4810-b1fe-143138d7f3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180289975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1180289975
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2677459679
Short name T359
Test name
Test status
Simulation time 18284328 ps
CPU time 0.89 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:42:49 PM PDT 24
Peak memory 208828 kb
Host smart-9511f541-337f-4de8-b627-5cd019228ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677459679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2677459679
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.518046628
Short name T44
Test name
Test status
Simulation time 782230966 ps
CPU time 10.9 seconds
Started Jul 17 07:42:50 PM PDT 24
Finished Jul 17 07:43:03 PM PDT 24
Peak memory 218188 kb
Host smart-396b6e33-80f8-44e6-9bdd-1b87587b1132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518046628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.518046628
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.4272579000
Short name T28
Test name
Test status
Simulation time 78246716 ps
CPU time 1.58 seconds
Started Jul 17 07:42:54 PM PDT 24
Finished Jul 17 07:42:57 PM PDT 24
Peak memory 217096 kb
Host smart-f9a235a4-9677-4bf9-b124-e4547c54792e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272579000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.4272579000
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1945272398
Short name T283
Test name
Test status
Simulation time 2922851276 ps
CPU time 46.31 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:43:37 PM PDT 24
Peak memory 219444 kb
Host smart-96d6a927-d46f-4d54-a90a-d830278b8343
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945272398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1945272398
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.147056069
Short name T295
Test name
Test status
Simulation time 1616567174 ps
CPU time 2.91 seconds
Started Jul 17 07:42:54 PM PDT 24
Finished Jul 17 07:42:58 PM PDT 24
Peak memory 217576 kb
Host smart-b2fff049-c3ca-4a6e-a157-d7fa61df6afb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147056069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.147056069
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2848555394
Short name T259
Test name
Test status
Simulation time 469172653 ps
CPU time 12.55 seconds
Started Jul 17 07:42:52 PM PDT 24
Finished Jul 17 07:43:06 PM PDT 24
Peak memory 218140 kb
Host smart-40ca1f07-58ae-4311-a644-9edde69f2ee9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848555394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2848555394
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3507221631
Short name T713
Test name
Test status
Simulation time 642856095 ps
CPU time 19.78 seconds
Started Jul 17 07:42:55 PM PDT 24
Finished Jul 17 07:43:16 PM PDT 24
Peak memory 217652 kb
Host smart-aad6c44d-9030-4d7a-a078-088b87ffbaea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507221631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3507221631
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1934525982
Short name T301
Test name
Test status
Simulation time 603238536 ps
CPU time 3 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:42:53 PM PDT 24
Peak memory 217648 kb
Host smart-d641cd01-65aa-4673-a405-f0844542bc5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934525982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1934525982
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4003909575
Short name T825
Test name
Test status
Simulation time 8368109748 ps
CPU time 51.38 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:43:39 PM PDT 24
Peak memory 276544 kb
Host smart-56fcb19a-c250-4471-847a-f2709ccefc1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003909575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4003909575
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.436456928
Short name T781
Test name
Test status
Simulation time 460289010 ps
CPU time 13.87 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:43:04 PM PDT 24
Peak memory 250920 kb
Host smart-3e759441-1539-406d-b717-04f8bde3ed94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436456928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.436456928
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.499423735
Short name T387
Test name
Test status
Simulation time 890812832 ps
CPU time 3.66 seconds
Started Jul 17 07:42:38 PM PDT 24
Finished Jul 17 07:42:42 PM PDT 24
Peak memory 218148 kb
Host smart-434453d0-379d-4b1f-8325-b34001ac21a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499423735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.499423735
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2527366797
Short name T377
Test name
Test status
Simulation time 1066802189 ps
CPU time 9.38 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:42:57 PM PDT 24
Peak memory 214548 kb
Host smart-f57e086b-c9b3-486b-97df-c8caa2bd4e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527366797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2527366797
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2321149035
Short name T864
Test name
Test status
Simulation time 707442543 ps
CPU time 13.77 seconds
Started Jul 17 07:42:54 PM PDT 24
Finished Jul 17 07:43:08 PM PDT 24
Peak memory 218224 kb
Host smart-a4c2bb5e-68fd-47e8-aa0d-6271723d3a2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321149035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2321149035
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3938274964
Short name T508
Test name
Test status
Simulation time 1638270574 ps
CPU time 22.74 seconds
Started Jul 17 07:42:54 PM PDT 24
Finished Jul 17 07:43:18 PM PDT 24
Peak memory 226008 kb
Host smart-06219e24-33a1-4b80-b50b-cc3810058deb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938274964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3938274964
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2233408533
Short name T380
Test name
Test status
Simulation time 349692887 ps
CPU time 12.79 seconds
Started Jul 17 07:42:54 PM PDT 24
Finished Jul 17 07:43:08 PM PDT 24
Peak memory 218216 kb
Host smart-69641b29-1ea4-4103-a517-4971e31cb349
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233408533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
233408533
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.5450331
Short name T679
Test name
Test status
Simulation time 614608381 ps
CPU time 11.29 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:42:54 PM PDT 24
Peak memory 226020 kb
Host smart-37cc38d2-289f-428b-9de8-c6fb50fc7b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5450331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.5450331
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1124311143
Short name T546
Test name
Test status
Simulation time 185737882 ps
CPU time 2.75 seconds
Started Jul 17 07:42:43 PM PDT 24
Finished Jul 17 07:42:47 PM PDT 24
Peak memory 217780 kb
Host smart-9b014249-33cd-4c8f-a79f-2dda4a6b9bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124311143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1124311143
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1040248032
Short name T431
Test name
Test status
Simulation time 5141389571 ps
CPU time 28.97 seconds
Started Jul 17 07:42:56 PM PDT 24
Finished Jul 17 07:43:26 PM PDT 24
Peak memory 251208 kb
Host smart-025d539a-e84e-4b30-bd97-34704b9da746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040248032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1040248032
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2400808402
Short name T565
Test name
Test status
Simulation time 125024059 ps
CPU time 8.68 seconds
Started Jul 17 07:42:48 PM PDT 24
Finished Jul 17 07:42:58 PM PDT 24
Peak memory 250972 kb
Host smart-28ceaa71-639e-476a-a538-8ce4fa660e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400808402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2400808402
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.885642731
Short name T575
Test name
Test status
Simulation time 11180225386 ps
CPU time 118.24 seconds
Started Jul 17 07:42:49 PM PDT 24
Finished Jul 17 07:44:49 PM PDT 24
Peak memory 251044 kb
Host smart-117a5e2d-d28c-4e5a-804e-7f26f84690bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885642731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.885642731
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.561483885
Short name T596
Test name
Test status
Simulation time 53296036 ps
CPU time 0.9 seconds
Started Jul 17 07:42:43 PM PDT 24
Finished Jul 17 07:42:45 PM PDT 24
Peak memory 217700 kb
Host smart-ce4a8ed5-f30c-4a67-934c-29a5f021141c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561483885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.561483885
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1843832587
Short name T720
Test name
Test status
Simulation time 16622005 ps
CPU time 1.08 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:05 PM PDT 24
Peak memory 208964 kb
Host smart-4e3e8a1b-d907-46fa-ad8c-2ad77982bbea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843832587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1843832587
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2632190223
Short name T520
Test name
Test status
Simulation time 357099769 ps
CPU time 9.94 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:11 PM PDT 24
Peak memory 226028 kb
Host smart-89eee408-0d64-4995-bc1f-58a8156bcedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632190223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2632190223
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.506908397
Short name T604
Test name
Test status
Simulation time 6213083190 ps
CPU time 6.18 seconds
Started Jul 17 07:45:55 PM PDT 24
Finished Jul 17 07:46:04 PM PDT 24
Peak memory 217744 kb
Host smart-76cbc38e-7c97-4672-a43c-a46f5b8c0d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506908397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.506908397
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.4040581523
Short name T485
Test name
Test status
Simulation time 94299797 ps
CPU time 2.82 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:04 PM PDT 24
Peak memory 218188 kb
Host smart-197e0054-391f-4508-aae1-2589136463ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040581523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.4040581523
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1319534574
Short name T651
Test name
Test status
Simulation time 1164438631 ps
CPU time 13.48 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:18 PM PDT 24
Peak memory 226140 kb
Host smart-4e019db7-8ee8-4e50-9cf7-3caa8308fad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319534574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1319534574
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3756043534
Short name T159
Test name
Test status
Simulation time 5002792380 ps
CPU time 15.81 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:17 PM PDT 24
Peak memory 225580 kb
Host smart-1868b79b-08c7-4060-bc74-3078a1692377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756043534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3756043534
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3571290855
Short name T521
Test name
Test status
Simulation time 2890707158 ps
CPU time 10.05 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:16 PM PDT 24
Peak memory 226080 kb
Host smart-4102ee31-086c-40b0-8821-8a9d929c0278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571290855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3571290855
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.449123044
Short name T836
Test name
Test status
Simulation time 3634251497 ps
CPU time 9.2 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:13 PM PDT 24
Peak memory 225368 kb
Host smart-ab18ed8e-c89c-4197-81ba-9a03a28241e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449123044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.449123044
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1429126566
Short name T757
Test name
Test status
Simulation time 481142758 ps
CPU time 3.9 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:46:02 PM PDT 24
Peak memory 217716 kb
Host smart-533f6ac6-685f-45c9-ab4b-d4b99c5de75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429126566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1429126566
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3897774511
Short name T38
Test name
Test status
Simulation time 646762961 ps
CPU time 18.64 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:46:16 PM PDT 24
Peak memory 250828 kb
Host smart-7ee77366-6473-41d2-a650-e54661a689de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897774511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3897774511
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4285387762
Short name T357
Test name
Test status
Simulation time 137469576 ps
CPU time 6.65 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:11 PM PDT 24
Peak memory 250512 kb
Host smart-4293dddf-8a43-4d0c-b6be-7675cb628727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285387762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4285387762
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.996823424
Short name T558
Test name
Test status
Simulation time 4568790612 ps
CPU time 65.45 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:47:10 PM PDT 24
Peak memory 268108 kb
Host smart-87bd39c2-5b76-4b91-b0ef-cfdcbbb06423
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996823424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.996823424
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2205564383
Short name T684
Test name
Test status
Simulation time 11236572 ps
CPU time 0.88 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:45:59 PM PDT 24
Peak memory 211908 kb
Host smart-2ac344c6-e519-4688-a724-097338799a2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205564383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2205564383
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3432770176
Short name T231
Test name
Test status
Simulation time 219993370 ps
CPU time 1.27 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:46:09 PM PDT 24
Peak memory 209028 kb
Host smart-8961c494-7b26-48a4-b0b0-d0585d04ad87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432770176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3432770176
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.721039413
Short name T813
Test name
Test status
Simulation time 520696531 ps
CPU time 13.13 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:16 PM PDT 24
Peak memory 218212 kb
Host smart-e36d363d-579c-432b-9dcd-6525e13b7be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721039413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.721039413
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.522617260
Short name T765
Test name
Test status
Simulation time 369988416 ps
CPU time 1.98 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:06 PM PDT 24
Peak memory 217060 kb
Host smart-74d6dcb7-1ae6-49de-87ed-fb4219edb586
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522617260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.522617260
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3969249795
Short name T539
Test name
Test status
Simulation time 185264740 ps
CPU time 1.59 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:04 PM PDT 24
Peak memory 222012 kb
Host smart-d413e404-9cd2-4dd2-bbd3-ea0ca10a810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969249795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3969249795
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1225071493
Short name T523
Test name
Test status
Simulation time 3305813019 ps
CPU time 16.78 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:21 PM PDT 24
Peak memory 219960 kb
Host smart-fe0f27e6-7c98-4069-a69b-1631f4a7fa04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225071493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1225071493
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1560883220
Short name T24
Test name
Test status
Simulation time 434347647 ps
CPU time 11.15 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:13 PM PDT 24
Peak memory 225964 kb
Host smart-3be5f6f8-1bc2-46db-803c-ad777dcf8988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560883220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1560883220
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1071465751
Short name T616
Test name
Test status
Simulation time 642278704 ps
CPU time 8.05 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:11 PM PDT 24
Peak memory 225060 kb
Host smart-7dc6aec8-43e6-4e62-8af7-c5022dfad875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071465751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1071465751
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.661280004
Short name T860
Test name
Test status
Simulation time 63218306 ps
CPU time 2.35 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:05 PM PDT 24
Peak memory 214244 kb
Host smart-cb6f8ea7-b7c9-4fd0-a1dc-3fd84ec05e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661280004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.661280004
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3954777606
Short name T388
Test name
Test status
Simulation time 3532248906 ps
CPU time 35.96 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:38 PM PDT 24
Peak memory 251024 kb
Host smart-45494f3b-0d3d-4e6b-a8a8-c09f11b35c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954777606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3954777606
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1778576787
Short name T343
Test name
Test status
Simulation time 51201185 ps
CPU time 2.95 seconds
Started Jul 17 07:46:03 PM PDT 24
Finished Jul 17 07:46:11 PM PDT 24
Peak memory 221852 kb
Host smart-31b77491-b0fd-4203-be66-99a5a0176d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778576787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1778576787
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3647409393
Short name T482
Test name
Test status
Simulation time 19329328159 ps
CPU time 184.59 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:49:10 PM PDT 24
Peak memory 279592 kb
Host smart-efbadf4b-9fd1-4fea-81df-119705045afd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647409393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3647409393
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.525969728
Short name T188
Test name
Test status
Simulation time 74786457848 ps
CPU time 227.78 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:49:56 PM PDT 24
Peak memory 259452 kb
Host smart-31eab3c8-574d-46cd-a8e8-8cdf01f76d02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=525969728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.525969728
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1370585027
Short name T408
Test name
Test status
Simulation time 29869046 ps
CPU time 0.99 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:03 PM PDT 24
Peak memory 217768 kb
Host smart-b5b5fd68-39a6-4c76-9378-d540459df9b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370585027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1370585027
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3996063585
Short name T257
Test name
Test status
Simulation time 231560216 ps
CPU time 0.94 seconds
Started Jul 17 07:46:01 PM PDT 24
Finished Jul 17 07:46:08 PM PDT 24
Peak memory 208828 kb
Host smart-3a95c397-2555-4002-997f-ccf005758d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996063585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3996063585
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2405140637
Short name T796
Test name
Test status
Simulation time 403018082 ps
CPU time 16.24 seconds
Started Jul 17 07:46:10 PM PDT 24
Finished Jul 17 07:46:27 PM PDT 24
Peak memory 218216 kb
Host smart-c17821d7-b14a-4fe1-9300-2ecc7989fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405140637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2405140637
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2368723831
Short name T34
Test name
Test status
Simulation time 329687991 ps
CPU time 1.6 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:06 PM PDT 24
Peak memory 217620 kb
Host smart-1cd48c30-8555-4f11-998c-52349d4289f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368723831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2368723831
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3431389218
Short name T154
Test name
Test status
Simulation time 49247697 ps
CPU time 2.88 seconds
Started Jul 17 07:46:01 PM PDT 24
Finished Jul 17 07:46:10 PM PDT 24
Peak memory 218200 kb
Host smart-b6e71297-a574-496f-aefb-53362a9e31f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431389218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3431389218
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4162142316
Short name T504
Test name
Test status
Simulation time 338871888 ps
CPU time 10.88 seconds
Started Jul 17 07:46:01 PM PDT 24
Finished Jul 17 07:46:18 PM PDT 24
Peak memory 218856 kb
Host smart-6751e1c9-311c-48ca-9128-1bcc7b7977ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162142316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4162142316
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2468311949
Short name T685
Test name
Test status
Simulation time 1538624457 ps
CPU time 15.21 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:21 PM PDT 24
Peak memory 226036 kb
Host smart-41fb7e20-8e7c-4ea1-af13-6e6fde8e76c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468311949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2468311949
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.803137416
Short name T498
Test name
Test status
Simulation time 397805161 ps
CPU time 8.4 seconds
Started Jul 17 07:45:56 PM PDT 24
Finished Jul 17 07:46:07 PM PDT 24
Peak memory 218208 kb
Host smart-efda23fc-ff26-450b-bdcd-bbf67b3244c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803137416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.803137416
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3333313256
Short name T494
Test name
Test status
Simulation time 4444305427 ps
CPU time 9.9 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:14 PM PDT 24
Peak memory 218296 kb
Host smart-72a5a9f4-c7e5-453d-9b0d-48ba426a732e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333313256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3333313256
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2817397742
Short name T81
Test name
Test status
Simulation time 24562527 ps
CPU time 1.38 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:05 PM PDT 24
Peak memory 213624 kb
Host smart-457bbe27-3577-4ef1-bb05-5bb89854fc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817397742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2817397742
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4071716890
Short name T637
Test name
Test status
Simulation time 916816906 ps
CPU time 23.04 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:27 PM PDT 24
Peak memory 250832 kb
Host smart-fe5a343e-f458-48fc-9d50-de7508605003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071716890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4071716890
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2714516886
Short name T210
Test name
Test status
Simulation time 50449586 ps
CPU time 3.26 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:06 PM PDT 24
Peak memory 224020 kb
Host smart-71958895-468a-43bd-a350-884541d1b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714516886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2714516886
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1405372235
Short name T526
Test name
Test status
Simulation time 2981166251 ps
CPU time 62.81 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:47:10 PM PDT 24
Peak memory 217812 kb
Host smart-fb0f0a44-2046-4a2b-8112-a7e72aa6b990
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405372235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1405372235
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1011493309
Short name T511
Test name
Test status
Simulation time 34249402 ps
CPU time 0.87 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:05 PM PDT 24
Peak memory 211792 kb
Host smart-e4dc6c82-dec1-42c7-b46d-1f0b71d17837
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011493309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1011493309
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1206181278
Short name T467
Test name
Test status
Simulation time 19072423 ps
CPU time 0.93 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:05 PM PDT 24
Peak memory 208808 kb
Host smart-cc2b324e-631a-4a0f-92be-da22b60a1208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206181278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1206181278
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.354431481
Short name T660
Test name
Test status
Simulation time 309236583 ps
CPU time 12.95 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:19 PM PDT 24
Peak memory 218184 kb
Host smart-845dbbec-4711-4bd0-8af7-f19765764445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354431481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.354431481
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1525088803
Short name T782
Test name
Test status
Simulation time 395424467 ps
CPU time 4.6 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:20 PM PDT 24
Peak memory 217260 kb
Host smart-4d147be1-d8d4-48b4-8524-577fa88cd8b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525088803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1525088803
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2829993161
Short name T361
Test name
Test status
Simulation time 865874487 ps
CPU time 3.93 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:46:12 PM PDT 24
Peak memory 218156 kb
Host smart-eadbcbd1-8c37-43d3-af15-d45b1fac6ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829993161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2829993161
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.452626986
Short name T349
Test name
Test status
Simulation time 1606256807 ps
CPU time 11.58 seconds
Started Jul 17 07:46:01 PM PDT 24
Finished Jul 17 07:46:19 PM PDT 24
Peak memory 225980 kb
Host smart-d2db2a83-8484-4631-aaf3-e3932988b0a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452626986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.452626986
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.4074853044
Short name T212
Test name
Test status
Simulation time 1264758322 ps
CPU time 14.28 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:20 PM PDT 24
Peak memory 226108 kb
Host smart-ed9cb5b5-7d52-44f5-84a8-3653d3e54674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074853044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.4074853044
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3943498203
Short name T772
Test name
Test status
Simulation time 798856046 ps
CPU time 6.04 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:12 PM PDT 24
Peak memory 218180 kb
Host smart-bad2a3c3-d96d-44b3-836f-ec6141fbd23c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943498203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3943498203
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2042478332
Short name T432
Test name
Test status
Simulation time 1313853884 ps
CPU time 8.35 seconds
Started Jul 17 07:46:00 PM PDT 24
Finished Jul 17 07:46:15 PM PDT 24
Peak memory 224668 kb
Host smart-aa51a485-75e2-4c05-9942-89395766bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042478332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2042478332
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2110351809
Short name T571
Test name
Test status
Simulation time 140954697 ps
CPU time 2.63 seconds
Started Jul 17 07:46:03 PM PDT 24
Finished Jul 17 07:46:11 PM PDT 24
Peak memory 217616 kb
Host smart-39b70d6b-fc07-49ca-a4b4-cf54cec5061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110351809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2110351809
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3543466527
Short name T832
Test name
Test status
Simulation time 602535925 ps
CPU time 21.27 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:46:29 PM PDT 24
Peak memory 250920 kb
Host smart-2d66c26d-fe7f-4bda-a4f8-96c95ad59893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543466527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3543466527
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2512487591
Short name T256
Test name
Test status
Simulation time 70225886 ps
CPU time 8.03 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:46:16 PM PDT 24
Peak memory 250912 kb
Host smart-cb21bc23-9cb7-4921-8013-d7d165055d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512487591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2512487591
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.886467896
Short name T450
Test name
Test status
Simulation time 6581067421 ps
CPU time 182.17 seconds
Started Jul 17 07:45:55 PM PDT 24
Finished Jul 17 07:49:00 PM PDT 24
Peak memory 422328 kb
Host smart-7f62e4e7-8bb5-4b05-ae89-e2459e92222f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886467896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.886467896
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2027869021
Short name T157
Test name
Test status
Simulation time 31382296130 ps
CPU time 987.5 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 08:02:30 PM PDT 24
Peak memory 333072 kb
Host smart-e7220118-db18-4af5-a25f-f04450f37f15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2027869021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2027869021
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3545680433
Short name T254
Test name
Test status
Simulation time 55554751 ps
CPU time 1.11 seconds
Started Jul 17 07:46:01 PM PDT 24
Finished Jul 17 07:46:08 PM PDT 24
Peak memory 213012 kb
Host smart-8db6aad5-dc62-414b-ad8d-7f676e8e45bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545680433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3545680433
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1063781314
Short name T266
Test name
Test status
Simulation time 21023152 ps
CPU time 1.23 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:04 PM PDT 24
Peak memory 208976 kb
Host smart-f25c2dc5-940b-4542-8acd-aa934e6a7234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063781314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1063781314
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2985918067
Short name T308
Test name
Test status
Simulation time 787840183 ps
CPU time 15.93 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:17 PM PDT 24
Peak memory 218188 kb
Host smart-ae02d2a6-8796-41b1-8286-cc228f00e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985918067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2985918067
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.4142169444
Short name T767
Test name
Test status
Simulation time 290563392 ps
CPU time 7.47 seconds
Started Jul 17 07:46:03 PM PDT 24
Finished Jul 17 07:46:16 PM PDT 24
Peak memory 217068 kb
Host smart-a0770498-5208-4fea-80a1-154e49a29d3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142169444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.4142169444
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1022499329
Short name T862
Test name
Test status
Simulation time 166948516 ps
CPU time 3.09 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:05 PM PDT 24
Peak memory 218208 kb
Host smart-595c8c82-db34-4bc6-b722-38295b078c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022499329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1022499329
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.748788900
Short name T588
Test name
Test status
Simulation time 5173640609 ps
CPU time 10.75 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:15 PM PDT 24
Peak memory 226084 kb
Host smart-2f8d7b6c-1094-41e3-96db-4f4fe7e95dec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748788900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.748788900
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4179547
Short name T693
Test name
Test status
Simulation time 984291576 ps
CPU time 12.26 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:17 PM PDT 24
Peak memory 226004 kb
Host smart-151875f1-e388-4d83-a1d5-235d16c31a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_dige
st.4179547
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1713329820
Short name T205
Test name
Test status
Simulation time 6438336755 ps
CPU time 14.8 seconds
Started Jul 17 07:45:58 PM PDT 24
Finished Jul 17 07:46:18 PM PDT 24
Peak memory 226084 kb
Host smart-8d53a919-75fc-4081-aa41-3ebd26f1ee48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713329820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1713329820
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.152046834
Short name T555
Test name
Test status
Simulation time 1102225631 ps
CPU time 11.31 seconds
Started Jul 17 07:45:57 PM PDT 24
Finished Jul 17 07:46:13 PM PDT 24
Peak memory 225996 kb
Host smart-f47eae48-a750-4afb-bd3a-48da1318ea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152046834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.152046834
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3287272799
Short name T422
Test name
Test status
Simulation time 157431701 ps
CPU time 2.49 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:07 PM PDT 24
Peak memory 217680 kb
Host smart-2db9b69a-166f-499d-b8e3-75a82ebca032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287272799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3287272799
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2386031535
Short name T593
Test name
Test status
Simulation time 217317634 ps
CPU time 22.1 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:26 PM PDT 24
Peak memory 250976 kb
Host smart-6b6784b4-db32-48ad-ad84-3ff7e6a53230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386031535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2386031535
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2713972258
Short name T88
Test name
Test status
Simulation time 53416073 ps
CPU time 6.13 seconds
Started Jul 17 07:45:55 PM PDT 24
Finished Jul 17 07:46:04 PM PDT 24
Peak memory 250648 kb
Host smart-914a6e7e-2cef-4a46-813b-6a462c8493e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713972258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2713972258
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2888860798
Short name T170
Test name
Test status
Simulation time 6213202649 ps
CPU time 190.29 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:49:14 PM PDT 24
Peak memory 222592 kb
Host smart-a586110a-d507-4e4a-92f2-41aefa1139be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888860798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2888860798
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.291994367
Short name T335
Test name
Test status
Simulation time 45754291 ps
CPU time 0.87 seconds
Started Jul 17 07:46:03 PM PDT 24
Finished Jul 17 07:46:09 PM PDT 24
Peak memory 211824 kb
Host smart-3872a9df-107a-41b0-8d10-e05448ff1120
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291994367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.291994367
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2161060586
Short name T271
Test name
Test status
Simulation time 35742154 ps
CPU time 0.82 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:19 PM PDT 24
Peak memory 208580 kb
Host smart-2ec3e42b-75ef-44c2-b12e-570c0d28e15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161060586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2161060586
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2090325538
Short name T846
Test name
Test status
Simulation time 541849276 ps
CPU time 13.41 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:46:21 PM PDT 24
Peak memory 218204 kb
Host smart-228292eb-8bf0-445b-bdd5-2783212f8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090325538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2090325538
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3253294054
Short name T459
Test name
Test status
Simulation time 2280176639 ps
CPU time 12.23 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:27 PM PDT 24
Peak memory 217632 kb
Host smart-40106a13-fbcc-4a2e-b897-72bc2010a12f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253294054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3253294054
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.919244477
Short name T562
Test name
Test status
Simulation time 168719311 ps
CPU time 3.96 seconds
Started Jul 17 07:46:02 PM PDT 24
Finished Jul 17 07:46:11 PM PDT 24
Peak memory 218192 kb
Host smart-1a977fbe-8375-4c1f-b823-29be5a9aee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919244477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.919244477
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1571469183
Short name T397
Test name
Test status
Simulation time 2701445380 ps
CPU time 16.35 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:34 PM PDT 24
Peak memory 226104 kb
Host smart-a472e397-09a0-4d0e-846b-18c7960016cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571469183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1571469183
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3478706403
Short name T363
Test name
Test status
Simulation time 1679470191 ps
CPU time 12.29 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:27 PM PDT 24
Peak memory 226028 kb
Host smart-c80a77f0-e2d1-4e44-ab24-889b4d531ca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478706403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3478706403
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.485598126
Short name T795
Test name
Test status
Simulation time 764876665 ps
CPU time 10.65 seconds
Started Jul 17 07:46:17 PM PDT 24
Finished Jul 17 07:46:30 PM PDT 24
Peak memory 226088 kb
Host smart-52c407ab-6ffb-4eb9-ad88-8cd8dff69283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485598126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.485598126
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1293411605
Short name T556
Test name
Test status
Simulation time 1132518276 ps
CPU time 8.38 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:12 PM PDT 24
Peak memory 225892 kb
Host smart-be21cc60-bd63-4ac2-8f74-1680fbaf8711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293411605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1293411605
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1980736413
Short name T42
Test name
Test status
Simulation time 51301358 ps
CPU time 2.69 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:07 PM PDT 24
Peak memory 222636 kb
Host smart-d90291e0-d08e-4fc0-8f38-d0b515840c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980736413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1980736413
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1002566194
Short name T293
Test name
Test status
Simulation time 212363722 ps
CPU time 28.63 seconds
Started Jul 17 07:46:01 PM PDT 24
Finished Jul 17 07:46:35 PM PDT 24
Peak memory 250980 kb
Host smart-98011138-009a-4aab-8a2f-2a11ebac1148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002566194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1002566194
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.413594228
Short name T284
Test name
Test status
Simulation time 518349442 ps
CPU time 6.69 seconds
Started Jul 17 07:46:01 PM PDT 24
Finished Jul 17 07:46:13 PM PDT 24
Peak memory 244440 kb
Host smart-4091586a-4044-4494-8e79-defc3ea988b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413594228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.413594228
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2675772664
Short name T274
Test name
Test status
Simulation time 10515541060 ps
CPU time 71.07 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:47:32 PM PDT 24
Peak memory 251404 kb
Host smart-ef2335c3-fe18-45eb-b6a9-b278e3d89d5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675772664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2675772664
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.989106114
Short name T826
Test name
Test status
Simulation time 13212548 ps
CPU time 0.93 seconds
Started Jul 17 07:45:59 PM PDT 24
Finished Jul 17 07:46:06 PM PDT 24
Peak memory 211848 kb
Host smart-8df77b7e-4a3a-499e-9993-4a9477cce0b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989106114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.989106114
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3885172395
Short name T421
Test name
Test status
Simulation time 18532863 ps
CPU time 0.92 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:19 PM PDT 24
Peak memory 208804 kb
Host smart-d5773618-766c-4c04-be2e-2bb5a31faf1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885172395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3885172395
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.818066058
Short name T843
Test name
Test status
Simulation time 978420515 ps
CPU time 12.55 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:33 PM PDT 24
Peak memory 218216 kb
Host smart-cd1db5bd-0d2c-4623-b495-adaf884040c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818066058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.818066058
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1258403375
Short name T6
Test name
Test status
Simulation time 279922043 ps
CPU time 4.3 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:25 PM PDT 24
Peak memory 217096 kb
Host smart-236e6d43-f74c-46df-8bb3-1fd6f013920b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258403375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1258403375
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2477836411
Short name T195
Test name
Test status
Simulation time 251337428 ps
CPU time 3.76 seconds
Started Jul 17 07:46:17 PM PDT 24
Finished Jul 17 07:46:23 PM PDT 24
Peak memory 222732 kb
Host smart-12e9b1e7-ea32-4b33-b8c5-e4e5f3fb3dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477836411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2477836411
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1080723843
Short name T67
Test name
Test status
Simulation time 329527512 ps
CPU time 14.37 seconds
Started Jul 17 07:46:19 PM PDT 24
Finished Jul 17 07:46:36 PM PDT 24
Peak memory 218876 kb
Host smart-3bb941d7-67ff-4961-be0d-904c41a5689c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080723843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1080723843
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.462912434
Short name T531
Test name
Test status
Simulation time 592033119 ps
CPU time 9.81 seconds
Started Jul 17 07:46:19 PM PDT 24
Finished Jul 17 07:46:31 PM PDT 24
Peak memory 226024 kb
Host smart-cc0ea4b5-fcf9-4775-93e5-47d0423fb955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462912434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.462912434
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.4173003517
Short name T435
Test name
Test status
Simulation time 1090406828 ps
CPU time 11.27 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:27 PM PDT 24
Peak memory 218224 kb
Host smart-4ea3f2bf-cd03-4478-966a-9733a6967cba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173003517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
4173003517
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3287548039
Short name T585
Test name
Test status
Simulation time 2420273041 ps
CPU time 9.55 seconds
Started Jul 17 07:46:15 PM PDT 24
Finished Jul 17 07:46:26 PM PDT 24
Peak memory 226176 kb
Host smart-aae1e59f-848a-4c82-a8c1-09e7c46b1dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287548039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3287548039
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3036196533
Short name T486
Test name
Test status
Simulation time 44937510 ps
CPU time 1.89 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:19 PM PDT 24
Peak memory 217708 kb
Host smart-1e8ef52e-529f-42c7-b16e-829849e1b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036196533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3036196533
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2252364892
Short name T276
Test name
Test status
Simulation time 211787002 ps
CPU time 23.6 seconds
Started Jul 17 07:46:17 PM PDT 24
Finished Jul 17 07:46:43 PM PDT 24
Peak memory 251088 kb
Host smart-24e60b8d-f80f-4fa1-adce-0d4369fff4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252364892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2252364892
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.129444900
Short name T787
Test name
Test status
Simulation time 308649300 ps
CPU time 7.58 seconds
Started Jul 17 07:46:13 PM PDT 24
Finished Jul 17 07:46:22 PM PDT 24
Peak memory 250984 kb
Host smart-c587075e-0f3c-4067-9938-2052d6512b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129444900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.129444900
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3826651703
Short name T285
Test name
Test status
Simulation time 9263485818 ps
CPU time 79.1 seconds
Started Jul 17 07:46:15 PM PDT 24
Finished Jul 17 07:47:36 PM PDT 24
Peak memory 226104 kb
Host smart-325e94f8-d6a5-4ef5-a15f-49d2df0cb94b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826651703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3826651703
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1651901863
Short name T751
Test name
Test status
Simulation time 22455399 ps
CPU time 1.51 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:20 PM PDT 24
Peak memory 217788 kb
Host smart-5c3ca407-3e84-4781-8953-d864f2c7fca3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651901863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1651901863
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4181193705
Short name T251
Test name
Test status
Simulation time 45150899 ps
CPU time 1.19 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:16 PM PDT 24
Peak memory 208972 kb
Host smart-450d8b22-f5e7-4d2b-806c-b4c43267c149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181193705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4181193705
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.4006556696
Short name T426
Test name
Test status
Simulation time 705962742 ps
CPU time 13.44 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:34 PM PDT 24
Peak memory 226020 kb
Host smart-eac034da-a498-47fa-84c5-e914e5e9c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006556696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.4006556696
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.347313282
Short name T320
Test name
Test status
Simulation time 790966563 ps
CPU time 2.74 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:21 PM PDT 24
Peak memory 217088 kb
Host smart-a23ee6a8-208b-40f8-b33e-009af070ea3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347313282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.347313282
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1667994846
Short name T351
Test name
Test status
Simulation time 106779364 ps
CPU time 1.72 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:17 PM PDT 24
Peak memory 218200 kb
Host smart-d2ea124c-9189-413d-a106-09bf1bb5ae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667994846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1667994846
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4032935001
Short name T199
Test name
Test status
Simulation time 1299455487 ps
CPU time 10.31 seconds
Started Jul 17 07:46:13 PM PDT 24
Finished Jul 17 07:46:24 PM PDT 24
Peak memory 226100 kb
Host smart-3b55001b-33a2-42a9-8d1f-aad2f316c25d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032935001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4032935001
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2973445031
Short name T505
Test name
Test status
Simulation time 412632962 ps
CPU time 7.13 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:28 PM PDT 24
Peak memory 218224 kb
Host smart-555eebf5-eaa8-4448-9f8d-2e6a88d1463f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973445031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2973445031
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1684195073
Short name T584
Test name
Test status
Simulation time 277025402 ps
CPU time 6.94 seconds
Started Jul 17 07:46:15 PM PDT 24
Finished Jul 17 07:46:24 PM PDT 24
Peak memory 225324 kb
Host smart-d194fb86-d39a-4143-b187-0dd37f2fe815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684195073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1684195073
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1304568816
Short name T2
Test name
Test status
Simulation time 164768514 ps
CPU time 2.67 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:18 PM PDT 24
Peak memory 217704 kb
Host smart-564088ab-ff0e-496e-901a-d94590432054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304568816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1304568816
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2898624757
Short name T417
Test name
Test status
Simulation time 206200956 ps
CPU time 27.73 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:49 PM PDT 24
Peak memory 250800 kb
Host smart-580d31d5-bae1-4126-93e4-5099a16f8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898624757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2898624757
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.223837009
Short name T509
Test name
Test status
Simulation time 137959392 ps
CPU time 3.36 seconds
Started Jul 17 07:46:21 PM PDT 24
Finished Jul 17 07:46:26 PM PDT 24
Peak memory 222272 kb
Host smart-96ba14b2-265d-4419-b344-371d9ec14b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223837009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.223837009
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3398696830
Short name T797
Test name
Test status
Simulation time 6155652386 ps
CPU time 223.09 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:50:01 PM PDT 24
Peak memory 283732 kb
Host smart-826226f8-44ed-4d0c-a514-82f5f084fca5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398696830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3398696830
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4200004092
Short name T341
Test name
Test status
Simulation time 25580802 ps
CPU time 0.91 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:22 PM PDT 24
Peak memory 212956 kb
Host smart-4ef5ae1c-c4cd-47a5-945f-5213d0f68a5f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200004092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4200004092
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1848822727
Short name T567
Test name
Test status
Simulation time 64918417 ps
CPU time 1.1 seconds
Started Jul 17 07:46:15 PM PDT 24
Finished Jul 17 07:46:18 PM PDT 24
Peak memory 208836 kb
Host smart-7969a79d-5d7f-4211-b3c4-0278591469d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848822727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1848822727
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3702016012
Short name T794
Test name
Test status
Simulation time 382396850 ps
CPU time 15.5 seconds
Started Jul 17 07:46:13 PM PDT 24
Finished Jul 17 07:46:30 PM PDT 24
Peak memory 218164 kb
Host smart-7676005e-a306-4cf3-b355-c90a0b96c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702016012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3702016012
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1381123504
Short name T411
Test name
Test status
Simulation time 411092720 ps
CPU time 5.27 seconds
Started Jul 17 07:46:19 PM PDT 24
Finished Jul 17 07:46:26 PM PDT 24
Peak memory 217164 kb
Host smart-6726674d-1316-4161-9607-c212f451e519
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381123504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1381123504
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1346516314
Short name T501
Test name
Test status
Simulation time 381525857 ps
CPU time 1.99 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:23 PM PDT 24
Peak memory 222128 kb
Host smart-74640b2c-18ad-4e17-8182-f5ce2b48f943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346516314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1346516314
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1236135213
Short name T778
Test name
Test status
Simulation time 236107280 ps
CPU time 12.6 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:34 PM PDT 24
Peak memory 218180 kb
Host smart-3f304737-8bbb-4fbb-ae8c-b71fe5104a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236135213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1236135213
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2606314608
Short name T252
Test name
Test status
Simulation time 676603570 ps
CPU time 7.89 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:28 PM PDT 24
Peak memory 226016 kb
Host smart-a05eb4d4-dc9a-4ab2-8d16-e73db6559938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606314608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2606314608
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3315082310
Short name T761
Test name
Test status
Simulation time 394908732 ps
CPU time 9.8 seconds
Started Jul 17 07:46:19 PM PDT 24
Finished Jul 17 07:46:31 PM PDT 24
Peak memory 218228 kb
Host smart-e9e04f76-8dab-4701-a02f-05f5dee99c93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315082310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3315082310
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1403422785
Short name T753
Test name
Test status
Simulation time 219798142 ps
CPU time 8.6 seconds
Started Jul 17 07:46:14 PM PDT 24
Finished Jul 17 07:46:24 PM PDT 24
Peak memory 224988 kb
Host smart-b045bf82-94b6-4402-9113-cc78940fc87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403422785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1403422785
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.324671538
Short name T405
Test name
Test status
Simulation time 49976259 ps
CPU time 1.43 seconds
Started Jul 17 07:46:19 PM PDT 24
Finished Jul 17 07:46:23 PM PDT 24
Peak memory 213852 kb
Host smart-e715cf47-4303-40f2-91ac-cd4e3d543b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324671538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.324671538
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3090036008
Short name T617
Test name
Test status
Simulation time 266287412 ps
CPU time 30.52 seconds
Started Jul 17 07:46:17 PM PDT 24
Finished Jul 17 07:46:50 PM PDT 24
Peak memory 250808 kb
Host smart-eab101cc-4721-45cf-b732-815ca7ce7678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090036008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3090036008
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1879533980
Short name T280
Test name
Test status
Simulation time 48557749 ps
CPU time 2.96 seconds
Started Jul 17 07:46:18 PM PDT 24
Finished Jul 17 07:46:23 PM PDT 24
Peak memory 218196 kb
Host smart-00cafcc3-0f10-4500-bbc9-9dd1c020d1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879533980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1879533980
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.45073184
Short name T84
Test name
Test status
Simulation time 22424198250 ps
CPU time 81.8 seconds
Started Jul 17 07:46:17 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 267740 kb
Host smart-a9cdb1bf-c49c-4378-a08e-e239dfeda931
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45073184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.lc_ctrl_stress_all.45073184
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1357194564
Short name T566
Test name
Test status
Simulation time 16349271 ps
CPU time 0.93 seconds
Started Jul 17 07:46:19 PM PDT 24
Finished Jul 17 07:46:22 PM PDT 24
Peak memory 212924 kb
Host smart-e9d48ae0-da66-4b86-ae9b-0c31e45b69d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357194564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1357194564
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2850216147
Short name T755
Test name
Test status
Simulation time 22226833 ps
CPU time 1.22 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 07:46:49 PM PDT 24
Peak memory 208932 kb
Host smart-65dd5ffc-04c4-42f4-8bc5-e634ffde61f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850216147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2850216147
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2445011624
Short name T712
Test name
Test status
Simulation time 1112727744 ps
CPU time 15.36 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:47:02 PM PDT 24
Peak memory 218216 kb
Host smart-5654d673-c081-493e-8dab-b930dcb898db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445011624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2445011624
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1338049217
Short name T844
Test name
Test status
Simulation time 474925027 ps
CPU time 12.76 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:47:00 PM PDT 24
Peak memory 217336 kb
Host smart-f484a33f-72a3-4c1e-92c0-da35b2c9f674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338049217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1338049217
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3477136557
Short name T493
Test name
Test status
Simulation time 1443098906 ps
CPU time 3.02 seconds
Started Jul 17 07:46:15 PM PDT 24
Finished Jul 17 07:46:20 PM PDT 24
Peak memory 222588 kb
Host smart-8b50d03d-cb56-4844-9c2c-20464ec64b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477136557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3477136557
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.64685069
Short name T724
Test name
Test status
Simulation time 581014586 ps
CPU time 11.77 seconds
Started Jul 17 07:46:42 PM PDT 24
Finished Jul 17 07:46:55 PM PDT 24
Peak memory 225956 kb
Host smart-cf07bdac-0dca-494a-b033-4579d61e8f26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64685069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.64685069
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1237045981
Short name T805
Test name
Test status
Simulation time 1051624224 ps
CPU time 9.51 seconds
Started Jul 17 07:46:52 PM PDT 24
Finished Jul 17 07:47:03 PM PDT 24
Peak memory 218192 kb
Host smart-23844c60-8e9f-4921-a22c-fab1db9860b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237045981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1237045981
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.703070052
Short name T583
Test name
Test status
Simulation time 455600497 ps
CPU time 8.83 seconds
Started Jul 17 07:46:52 PM PDT 24
Finished Jul 17 07:47:03 PM PDT 24
Peak memory 224592 kb
Host smart-3989c1a6-2d06-4ddc-bc04-e70c4f0b5a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703070052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.703070052
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2823937452
Short name T415
Test name
Test status
Simulation time 67238153 ps
CPU time 1.76 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:20 PM PDT 24
Peak memory 223420 kb
Host smart-f27211e6-ede7-444a-a207-45b8dabe2b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823937452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2823937452
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2800467959
Short name T376
Test name
Test status
Simulation time 255617855 ps
CPU time 29.8 seconds
Started Jul 17 07:46:16 PM PDT 24
Finished Jul 17 07:46:47 PM PDT 24
Peak memory 251040 kb
Host smart-39844e7f-7b2c-45ae-9269-fe905e85dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800467959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2800467959
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.496510613
Short name T792
Test name
Test status
Simulation time 1626928481 ps
CPU time 7.86 seconds
Started Jul 17 07:46:17 PM PDT 24
Finished Jul 17 07:46:27 PM PDT 24
Peak memory 246660 kb
Host smart-45a297b7-5c30-45b7-a184-279eb3227bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496510613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.496510613
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3374944344
Short name T172
Test name
Test status
Simulation time 3021083981 ps
CPU time 110.31 seconds
Started Jul 17 07:46:42 PM PDT 24
Finished Jul 17 07:48:34 PM PDT 24
Peak memory 268812 kb
Host smart-fa9ef532-9f51-4f96-9377-428fbde60ce1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374944344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3374944344
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1920229406
Short name T360
Test name
Test status
Simulation time 17618534 ps
CPU time 0.84 seconds
Started Jul 17 07:46:17 PM PDT 24
Finished Jul 17 07:46:20 PM PDT 24
Peak memory 212016 kb
Host smart-9db60ac1-7512-4f38-bc11-5c39b2b89af9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920229406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1920229406
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2963355735
Short name T202
Test name
Test status
Simulation time 37546908 ps
CPU time 0.98 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:43:33 PM PDT 24
Peak memory 208832 kb
Host smart-bc418ff3-8b8a-4b50-ae77-b31ed7f7a1a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963355735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2963355735
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3185029700
Short name T762
Test name
Test status
Simulation time 886281134 ps
CPU time 9.87 seconds
Started Jul 17 07:42:56 PM PDT 24
Finished Jul 17 07:43:07 PM PDT 24
Peak memory 226024 kb
Host smart-62601ed7-3b8c-4ad7-a24c-dc234cfc2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185029700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3185029700
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2956790313
Short name T480
Test name
Test status
Simulation time 117460757 ps
CPU time 1.05 seconds
Started Jul 17 07:42:57 PM PDT 24
Finished Jul 17 07:42:59 PM PDT 24
Peak memory 217056 kb
Host smart-8c6164d2-114b-4da2-a594-778365ee9996
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956790313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2956790313
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.4120688614
Short name T492
Test name
Test status
Simulation time 1855004354 ps
CPU time 49.81 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:43:38 PM PDT 24
Peak memory 226052 kb
Host smart-61a01112-a466-4ba7-8b70-c4790c0b0f58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120688614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.4120688614
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3005290343
Short name T96
Test name
Test status
Simulation time 3322217665 ps
CPU time 10.83 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:43:43 PM PDT 24
Peak memory 217828 kb
Host smart-8f8a65eb-0d42-417c-8ca7-52569c123e3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005290343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
005290343
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.947767626
Short name T840
Test name
Test status
Simulation time 605903036 ps
CPU time 4.62 seconds
Started Jul 17 07:42:56 PM PDT 24
Finished Jul 17 07:43:02 PM PDT 24
Peak memory 218140 kb
Host smart-6e5e9cd7-8b3c-4d7e-a445-745976f12190
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947767626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.947767626
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2767435576
Short name T227
Test name
Test status
Simulation time 2857315576 ps
CPU time 27.33 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:56 PM PDT 24
Peak memory 217704 kb
Host smart-69fb32d3-b639-46a3-a6f2-b0054e10b03c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767435576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2767435576
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.667814611
Short name T68
Test name
Test status
Simulation time 170277040 ps
CPU time 1.47 seconds
Started Jul 17 07:42:57 PM PDT 24
Finished Jul 17 07:43:00 PM PDT 24
Peak memory 217752 kb
Host smart-1ce748cd-d891-4874-8325-29b9c97962ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667814611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.667814611
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1654420815
Short name T263
Test name
Test status
Simulation time 4081270961 ps
CPU time 43.93 seconds
Started Jul 17 07:42:57 PM PDT 24
Finished Jul 17 07:43:43 PM PDT 24
Peak memory 251272 kb
Host smart-1165b132-4cbd-4526-9f45-47f6ace15ecb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654420815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1654420815
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1770967631
Short name T465
Test name
Test status
Simulation time 878210979 ps
CPU time 8.13 seconds
Started Jul 17 07:42:56 PM PDT 24
Finished Jul 17 07:43:06 PM PDT 24
Peak memory 222976 kb
Host smart-bbfa6487-6c96-40d2-8951-de3a44d75f63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770967631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1770967631
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1972113751
Short name T570
Test name
Test status
Simulation time 102740162 ps
CPU time 3.27 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:42:51 PM PDT 24
Peak memory 218288 kb
Host smart-e7e9f9fa-fbb9-4ea2-8b84-8229572b4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972113751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1972113751
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.617422105
Short name T730
Test name
Test status
Simulation time 425662050 ps
CPU time 8.85 seconds
Started Jul 17 07:42:57 PM PDT 24
Finished Jul 17 07:43:08 PM PDT 24
Peak memory 217780 kb
Host smart-fcc6d3e9-5f79-47a7-b8de-1cf919c8863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617422105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.617422105
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3025884885
Short name T92
Test name
Test status
Simulation time 702343792 ps
CPU time 35.86 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:44:06 PM PDT 24
Peak memory 284436 kb
Host smart-94c4e2b3-7fdc-4cd5-b3fa-eb9c69884fe8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025884885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3025884885
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3099494567
Short name T564
Test name
Test status
Simulation time 892139699 ps
CPU time 15.05 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:43:45 PM PDT 24
Peak memory 218960 kb
Host smart-13fde9d5-ff91-45ae-9a17-94e589d5ac0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099494567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3099494567
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.49305703
Short name T739
Test name
Test status
Simulation time 1041655665 ps
CPU time 11.41 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:43:41 PM PDT 24
Peak memory 226024 kb
Host smart-1c39dce6-38a5-444c-a494-03e5e1f5b0b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49305703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dige
st.49305703
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4093933660
Short name T323
Test name
Test status
Simulation time 1557582168 ps
CPU time 14.06 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:43:44 PM PDT 24
Peak memory 218200 kb
Host smart-f028f828-ae56-4631-8e01-2ea866700b24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093933660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
093933660
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3935911608
Short name T270
Test name
Test status
Simulation time 843962206 ps
CPU time 8.7 seconds
Started Jul 17 07:42:57 PM PDT 24
Finished Jul 17 07:43:08 PM PDT 24
Peak memory 224748 kb
Host smart-2aafb72c-7906-418f-8e42-773c09b12708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935911608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3935911608
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3761247358
Short name T675
Test name
Test status
Simulation time 841393832 ps
CPU time 4.39 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:42:53 PM PDT 24
Peak memory 217872 kb
Host smart-4fda2cbf-c02f-40e2-b20b-3871705976a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761247358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3761247358
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1738152936
Short name T646
Test name
Test status
Simulation time 839947050 ps
CPU time 24.08 seconds
Started Jul 17 07:42:41 PM PDT 24
Finished Jul 17 07:43:07 PM PDT 24
Peak memory 250968 kb
Host smart-31e50420-3a31-4d32-b0b9-9db566e7c042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738152936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1738152936
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1917716731
Short name T400
Test name
Test status
Simulation time 180794109 ps
CPU time 8.94 seconds
Started Jul 17 07:42:47 PM PDT 24
Finished Jul 17 07:42:58 PM PDT 24
Peak memory 242888 kb
Host smart-94e8ce6e-c7e6-4750-ab7d-d84f3b88bd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917716731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1917716731
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2504807572
Short name T578
Test name
Test status
Simulation time 15864311942 ps
CPU time 160.02 seconds
Started Jul 17 07:43:33 PM PDT 24
Finished Jul 17 07:46:14 PM PDT 24
Peak memory 283768 kb
Host smart-8337ddcf-677e-49aa-9ccf-1e41496be63c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504807572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2504807572
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3861672435
Short name T664
Test name
Test status
Simulation time 76445754630 ps
CPU time 673.28 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:54:45 PM PDT 24
Peak memory 512780 kb
Host smart-1da05b66-bc3f-473b-9d51-7a3966b2aafc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3861672435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3861672435
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1037600843
Short name T297
Test name
Test status
Simulation time 72603234 ps
CPU time 0.99 seconds
Started Jul 17 07:42:57 PM PDT 24
Finished Jul 17 07:43:00 PM PDT 24
Peak memory 212872 kb
Host smart-a76151be-20c4-4e1f-8903-1cd130ae2263
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037600843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1037600843
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1840573506
Short name T791
Test name
Test status
Simulation time 69752908 ps
CPU time 1.01 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:46:52 PM PDT 24
Peak memory 208852 kb
Host smart-a2f53b25-d57d-48e7-9992-699b299b2362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840573506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1840573506
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.863984245
Short name T545
Test name
Test status
Simulation time 390797517 ps
CPU time 13.62 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:59 PM PDT 24
Peak memory 218424 kb
Host smart-964e605e-d683-4c6b-9999-45508711877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863984245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.863984245
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3323408342
Short name T36
Test name
Test status
Simulation time 1840358577 ps
CPU time 5.75 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:50 PM PDT 24
Peak memory 217248 kb
Host smart-bdc311d2-ef0a-45cc-8df1-1cc9f33aaa49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323408342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3323408342
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1078395812
Short name T151
Test name
Test status
Simulation time 164401483 ps
CPU time 3.56 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:46:49 PM PDT 24
Peak memory 222620 kb
Host smart-c9f0d535-dd02-4a81-9220-b18adb04c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078395812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1078395812
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.625434925
Short name T725
Test name
Test status
Simulation time 2058125578 ps
CPU time 12.48 seconds
Started Jul 17 07:46:42 PM PDT 24
Finished Jul 17 07:46:55 PM PDT 24
Peak memory 226040 kb
Host smart-dc8d910f-caa2-4bec-ba79-1e3fab4e53a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625434925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.625434925
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2554552248
Short name T250
Test name
Test status
Simulation time 381501929 ps
CPU time 15.93 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 07:47:04 PM PDT 24
Peak memory 226032 kb
Host smart-12c0ac4c-960a-4701-8cd4-7adb7449f7aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554552248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2554552248
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3500993239
Short name T221
Test name
Test status
Simulation time 347406656 ps
CPU time 9.41 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:46:56 PM PDT 24
Peak memory 218232 kb
Host smart-ec4cfd14-0a07-490b-8662-2b3bcf8e8950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500993239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3500993239
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1729219977
Short name T53
Test name
Test status
Simulation time 818709834 ps
CPU time 12.22 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 07:46:59 PM PDT 24
Peak memory 218216 kb
Host smart-defe6f2b-9a57-45ad-88ed-234c5c1edfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729219977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1729219977
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.211006202
Short name T201
Test name
Test status
Simulation time 41017137 ps
CPU time 1.37 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:46:47 PM PDT 24
Peak memory 213700 kb
Host smart-7084f862-5e95-4da6-b74c-30c2edbbd926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211006202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.211006202
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.762036848
Short name T525
Test name
Test status
Simulation time 170362538 ps
CPU time 20.2 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:47:05 PM PDT 24
Peak memory 246200 kb
Host smart-a6d0df1a-a59a-4375-b9b0-2182b576762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762036848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.762036848
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3154257698
Short name T750
Test name
Test status
Simulation time 299482574 ps
CPU time 7.87 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 07:46:55 PM PDT 24
Peak memory 250444 kb
Host smart-48cf6abd-1e95-43df-b02a-982021fc68dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154257698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3154257698
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3737405340
Short name T460
Test name
Test status
Simulation time 7662949743 ps
CPU time 67.12 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 07:47:55 PM PDT 24
Peak memory 250760 kb
Host smart-9da341ba-8bbd-4826-8f69-0a7343a16857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737405340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3737405340
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2318275787
Short name T261
Test name
Test status
Simulation time 18332189 ps
CPU time 0.86 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:45 PM PDT 24
Peak memory 211852 kb
Host smart-05c6157c-9aba-431e-9c58-d006653346c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318275787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2318275787
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.220406453
Short name T73
Test name
Test status
Simulation time 16284658 ps
CPU time 0.9 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:46 PM PDT 24
Peak memory 208772 kb
Host smart-33bd0f4b-34b5-4666-b098-5cd68443f8df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220406453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.220406453
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1577677221
Short name T262
Test name
Test status
Simulation time 1453920022 ps
CPU time 16 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:47:02 PM PDT 24
Peak memory 218216 kb
Host smart-2554069b-ae6a-4bdf-bb28-472b0462f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577677221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1577677221
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3082132971
Short name T550
Test name
Test status
Simulation time 814039355 ps
CPU time 6.95 seconds
Started Jul 17 07:46:42 PM PDT 24
Finished Jul 17 07:46:51 PM PDT 24
Peak memory 217248 kb
Host smart-29ff820d-6cb0-461e-9368-f6184fc15245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082132971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3082132971
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.314798679
Short name T863
Test name
Test status
Simulation time 302786845 ps
CPU time 2.69 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:46:49 PM PDT 24
Peak memory 218212 kb
Host smart-44672afc-c48d-4ec8-b9f6-396d5ef536d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314798679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.314798679
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.214162854
Short name T278
Test name
Test status
Simulation time 1320222565 ps
CPU time 13.41 seconds
Started Jul 17 07:46:42 PM PDT 24
Finished Jul 17 07:46:57 PM PDT 24
Peak memory 218984 kb
Host smart-1b36dd5b-d82a-4528-8658-4cc96275bdfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214162854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.214162854
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2510420997
Short name T815
Test name
Test status
Simulation time 757051302 ps
CPU time 15.03 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:47:01 PM PDT 24
Peak memory 226040 kb
Host smart-0cea8b65-539b-42ac-b10c-8fac20abeba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510420997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2510420997
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3704861371
Short name T709
Test name
Test status
Simulation time 3229377777 ps
CPU time 12.27 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 07:47:00 PM PDT 24
Peak memory 226080 kb
Host smart-0a673db5-1115-41b2-98a4-100d70d94a15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704861371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3704861371
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1337415098
Short name T471
Test name
Test status
Simulation time 103856194 ps
CPU time 3.86 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 07:46:51 PM PDT 24
Peak memory 217684 kb
Host smart-8d055f1d-5553-4ac5-a04c-dd5303ba8770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337415098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1337415098
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2150335847
Short name T344
Test name
Test status
Simulation time 206816412 ps
CPU time 31.37 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:47:22 PM PDT 24
Peak memory 246712 kb
Host smart-4a7fa42e-8ca8-4ca0-959f-7eeee9c14c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150335847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2150335847
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3723844808
Short name T533
Test name
Test status
Simulation time 51691333 ps
CPU time 3.35 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:48 PM PDT 24
Peak memory 222436 kb
Host smart-48c9f8de-3a31-413a-889a-1dc8114e84a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723844808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3723844808
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.662390634
Short name T507
Test name
Test status
Simulation time 5355358795 ps
CPU time 184.98 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:49:50 PM PDT 24
Peak memory 268136 kb
Host smart-3d16106d-f9f4-47b4-b0db-9d4a103e22d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662390634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.662390634
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.4232860347
Short name T658
Test name
Test status
Simulation time 26022325986 ps
CPU time 853.34 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 08:01:01 PM PDT 24
Peak memory 277628 kb
Host smart-0119f08c-99ff-4499-bc47-0e39f0d15317
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4232860347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.4232860347
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4047960024
Short name T707
Test name
Test status
Simulation time 18413923 ps
CPU time 0.95 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 07:46:49 PM PDT 24
Peak memory 211876 kb
Host smart-4738eb7a-72a3-4662-9505-51581766f5c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047960024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.4047960024
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3005857889
Short name T362
Test name
Test status
Simulation time 93997152 ps
CPU time 0.93 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:46:53 PM PDT 24
Peak memory 208844 kb
Host smart-5b507356-ec0b-41a6-aed8-ff1a05e28ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005857889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3005857889
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.718889867
Short name T594
Test name
Test status
Simulation time 771391016 ps
CPU time 14.49 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:59 PM PDT 24
Peak memory 218204 kb
Host smart-23676938-b8ff-467b-bbd8-631f2d4f4218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718889867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.718889867
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.544688786
Short name T631
Test name
Test status
Simulation time 417028497 ps
CPU time 11.68 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 07:47:00 PM PDT 24
Peak memory 217512 kb
Host smart-c82d2992-8efc-42db-9f8e-b5cfc1bcf39d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544688786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.544688786
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1046798994
Short name T312
Test name
Test status
Simulation time 105297751 ps
CPU time 3.49 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:46:49 PM PDT 24
Peak memory 218200 kb
Host smart-d477160c-4bdb-4761-91b1-2af534b27992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046798994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1046798994
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2370393279
Short name T63
Test name
Test status
Simulation time 1023353295 ps
CPU time 12.98 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:47:00 PM PDT 24
Peak memory 218940 kb
Host smart-3e4710a8-0d72-4fb0-9f56-110582305c22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370393279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2370393279
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3560678784
Short name T395
Test name
Test status
Simulation time 2461009490 ps
CPU time 8.64 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:46:59 PM PDT 24
Peak memory 226088 kb
Host smart-ef94a82d-3b1a-4d27-8395-f7a01b932543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560678784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3560678784
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.163511827
Short name T207
Test name
Test status
Simulation time 319670438 ps
CPU time 7.55 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:46:57 PM PDT 24
Peak memory 226032 kb
Host smart-b6cfd885-89a2-43a4-9d0e-ce6dfccca979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163511827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.163511827
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.638055380
Short name T718
Test name
Test status
Simulation time 393601571 ps
CPU time 14.97 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:47:02 PM PDT 24
Peak memory 218280 kb
Host smart-a5923784-327f-4244-a991-0e7d7bbe6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638055380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.638055380
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2264616532
Short name T647
Test name
Test status
Simulation time 17219533 ps
CPU time 1.26 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:46:51 PM PDT 24
Peak memory 217584 kb
Host smart-0aba56fb-a05b-426b-bab6-d8aef6aa92f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264616532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2264616532
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1331897416
Short name T230
Test name
Test status
Simulation time 1143120969 ps
CPU time 13.74 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:46:59 PM PDT 24
Peak memory 250940 kb
Host smart-e5d884dc-aea2-48b2-8b5f-a458d8fdcba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331897416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1331897416
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.4182975092
Short name T438
Test name
Test status
Simulation time 111254255 ps
CPU time 6.99 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:46:58 PM PDT 24
Peak memory 246972 kb
Host smart-8905d733-7dfc-4339-8849-b72841d28509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182975092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4182975092
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3820427726
Short name T831
Test name
Test status
Simulation time 5433174874 ps
CPU time 119.17 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:48:51 PM PDT 24
Peak memory 271548 kb
Host smart-9c56a1fe-cdfb-4df2-a80b-ea68e247cf45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820427726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3820427726
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1853966093
Short name T147
Test name
Test status
Simulation time 28715114480 ps
CPU time 402.42 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 07:53:31 PM PDT 24
Peak memory 333020 kb
Host smart-85fcca87-7648-4ccc-98c3-b207c5168170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1853966093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1853966093
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.600213714
Short name T443
Test name
Test status
Simulation time 24529351 ps
CPU time 1.16 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:46 PM PDT 24
Peak memory 217980 kb
Host smart-ca356256-1dad-4ed9-917e-4f2a37efe430
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600213714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.600213714
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3643230100
Short name T536
Test name
Test status
Simulation time 18134943 ps
CPU time 0.91 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:46:52 PM PDT 24
Peak memory 208824 kb
Host smart-6b40160d-84ea-4fb7-a868-9a2bab760333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643230100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3643230100
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1864823345
Short name T845
Test name
Test status
Simulation time 433892179 ps
CPU time 17.21 seconds
Started Jul 17 07:46:47 PM PDT 24
Finished Jul 17 07:47:06 PM PDT 24
Peak memory 217996 kb
Host smart-0c325b2d-5cbe-4b5d-b826-286f487279c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864823345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1864823345
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1338248536
Short name T833
Test name
Test status
Simulation time 9783763462 ps
CPU time 21.89 seconds
Started Jul 17 07:46:50 PM PDT 24
Finished Jul 17 07:47:14 PM PDT 24
Peak memory 217872 kb
Host smart-04fb91df-3dad-431e-a36c-7c102868e6ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338248536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1338248536
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3212517365
Short name T242
Test name
Test status
Simulation time 372942620 ps
CPU time 4.45 seconds
Started Jul 17 07:46:44 PM PDT 24
Finished Jul 17 07:46:50 PM PDT 24
Peak memory 218200 kb
Host smart-09b6ba24-e59e-491d-827f-710eafab26f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212517365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3212517365
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.4000123037
Short name T367
Test name
Test status
Simulation time 1401056123 ps
CPU time 15.04 seconds
Started Jul 17 07:46:52 PM PDT 24
Finished Jul 17 07:47:09 PM PDT 24
Peak memory 226016 kb
Host smart-f2a93b0f-48a7-4ded-96a6-859086709905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000123037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.4000123037
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2087984444
Short name T272
Test name
Test status
Simulation time 1977800036 ps
CPU time 8.24 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:46:59 PM PDT 24
Peak memory 225980 kb
Host smart-3ec356ed-a17e-4dbe-86e9-3aa95809e431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087984444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2087984444
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.116979915
Short name T524
Test name
Test status
Simulation time 1267419912 ps
CPU time 12.18 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:47:04 PM PDT 24
Peak memory 218220 kb
Host smart-ee81887c-ac8f-46d7-bff6-e1855b813a76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116979915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.116979915
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2579885194
Short name T837
Test name
Test status
Simulation time 2886786382 ps
CPU time 12.06 seconds
Started Jul 17 07:46:47 PM PDT 24
Finished Jul 17 07:47:01 PM PDT 24
Peak memory 225900 kb
Host smart-0a6a2448-0f57-4d95-8c4d-e92bbaa69fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579885194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2579885194
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3866268623
Short name T275
Test name
Test status
Simulation time 93800283 ps
CPU time 2.81 seconds
Started Jul 17 07:46:52 PM PDT 24
Finished Jul 17 07:46:57 PM PDT 24
Peak memory 214568 kb
Host smart-c8149693-58d1-4e90-bb3b-a5a061f72910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866268623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3866268623
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2213609333
Short name T382
Test name
Test status
Simulation time 253478383 ps
CPU time 25.35 seconds
Started Jul 17 07:46:47 PM PDT 24
Finished Jul 17 07:47:14 PM PDT 24
Peak memory 251040 kb
Host smart-56aedf72-a948-4f32-bc66-1cb23ecac754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213609333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2213609333
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3004433333
Short name T218
Test name
Test status
Simulation time 1361446047 ps
CPU time 7.96 seconds
Started Jul 17 07:46:43 PM PDT 24
Finished Jul 17 07:46:53 PM PDT 24
Peak memory 250968 kb
Host smart-b92ce956-b4c3-4b31-afa1-d19180d471a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004433333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3004433333
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1107350469
Short name T595
Test name
Test status
Simulation time 4719962392 ps
CPU time 144.41 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:49:16 PM PDT 24
Peak memory 267156 kb
Host smart-bc5e71c6-dd4d-4044-982b-a1610cd7cb03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107350469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1107350469
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3097510566
Short name T248
Test name
Test status
Simulation time 28533602 ps
CPU time 1.11 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:46:51 PM PDT 24
Peak memory 212928 kb
Host smart-64f7cad8-71d1-4ad7-996e-30b62a0def14
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097510566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3097510566
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.87588398
Short name T568
Test name
Test status
Simulation time 79860543 ps
CPU time 1.18 seconds
Started Jul 17 07:46:50 PM PDT 24
Finished Jul 17 07:46:54 PM PDT 24
Peak memory 209000 kb
Host smart-f195d6f3-f350-44a9-ae57-ac5d656aaae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87588398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.87588398
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.968579911
Short name T811
Test name
Test status
Simulation time 233690149 ps
CPU time 8.01 seconds
Started Jul 17 07:46:53 PM PDT 24
Finished Jul 17 07:47:03 PM PDT 24
Peak memory 218244 kb
Host smart-6e259602-dc5f-4862-9a79-2fd4aa40ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968579911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.968579911
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1309197359
Short name T865
Test name
Test status
Simulation time 886454922 ps
CPU time 8.19 seconds
Started Jul 17 07:46:47 PM PDT 24
Finished Jul 17 07:46:57 PM PDT 24
Peak memory 217368 kb
Host smart-3710179b-9e54-4f1a-92a9-e8b7a0d319ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309197359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1309197359
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1856740524
Short name T694
Test name
Test status
Simulation time 112353385 ps
CPU time 2.22 seconds
Started Jul 17 07:46:50 PM PDT 24
Finished Jul 17 07:46:54 PM PDT 24
Peak memory 218216 kb
Host smart-105aaf96-edbe-4559-bdf4-4103bd7ee397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856740524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1856740524
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2026107899
Short name T253
Test name
Test status
Simulation time 5846136922 ps
CPU time 17.82 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 07:47:06 PM PDT 24
Peak memory 219976 kb
Host smart-245c4391-6423-4c11-9deb-0ab3bc650b29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026107899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2026107899
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.10494754
Short name T733
Test name
Test status
Simulation time 8315505726 ps
CPU time 16.62 seconds
Started Jul 17 07:46:53 PM PDT 24
Finished Jul 17 07:47:11 PM PDT 24
Peak memory 226080 kb
Host smart-4173bad1-4e97-4a78-85c9-159fd695b9bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_dig
est.10494754
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.134352275
Short name T445
Test name
Test status
Simulation time 1438798178 ps
CPU time 8.01 seconds
Started Jul 17 07:46:53 PM PDT 24
Finished Jul 17 07:47:02 PM PDT 24
Peak memory 218316 kb
Host smart-a32f27e2-c950-4904-a9ff-2df0dba92732
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134352275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.134352275
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2572847935
Short name T57
Test name
Test status
Simulation time 245212899 ps
CPU time 10.54 seconds
Started Jul 17 07:46:50 PM PDT 24
Finished Jul 17 07:47:03 PM PDT 24
Peak memory 225884 kb
Host smart-c143397c-2e4e-4ebe-a479-46e126b65e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572847935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2572847935
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1619004359
Short name T607
Test name
Test status
Simulation time 39262244 ps
CPU time 1.66 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:46:53 PM PDT 24
Peak memory 217708 kb
Host smart-bffc3995-ce28-42b1-892e-0a67b7308891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619004359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1619004359
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.274195261
Short name T489
Test name
Test status
Simulation time 873843398 ps
CPU time 33.76 seconds
Started Jul 17 07:46:46 PM PDT 24
Finished Jul 17 07:47:22 PM PDT 24
Peak memory 250980 kb
Host smart-94a6ae21-665e-4a5b-a4e7-bdc395490b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274195261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.274195261
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1128574252
Short name T532
Test name
Test status
Simulation time 1074163491 ps
CPU time 9.66 seconds
Started Jul 17 07:46:53 PM PDT 24
Finished Jul 17 07:47:05 PM PDT 24
Peak memory 250984 kb
Host smart-92041dcc-3762-4efe-b6e6-656a3fcb9dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128574252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1128574252
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.166158878
Short name T80
Test name
Test status
Simulation time 15407105264 ps
CPU time 210.27 seconds
Started Jul 17 07:46:40 PM PDT 24
Finished Jul 17 07:50:10 PM PDT 24
Peak memory 251032 kb
Host smart-9bb69148-e4b8-4f7b-90ec-5db68427fe0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166158878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.166158878
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1233252257
Short name T500
Test name
Test status
Simulation time 12402399 ps
CPU time 0.88 seconds
Started Jul 17 07:46:53 PM PDT 24
Finished Jul 17 07:46:55 PM PDT 24
Peak memory 211900 kb
Host smart-d5b12247-e3a6-4cdc-9416-31c912903b04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233252257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1233252257
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.119240168
Short name T41
Test name
Test status
Simulation time 20391594 ps
CPU time 0.92 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:47:14 PM PDT 24
Peak memory 208756 kb
Host smart-2be2d52f-bcde-4f40-b35a-ccaf44edf2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119240168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.119240168
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3578261938
Short name T418
Test name
Test status
Simulation time 301589494 ps
CPU time 12.19 seconds
Started Jul 17 07:46:55 PM PDT 24
Finished Jul 17 07:47:08 PM PDT 24
Peak memory 218192 kb
Host smart-46510e9f-ed3d-4193-ae65-ce1be005ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578261938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3578261938
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3225853390
Short name T838
Test name
Test status
Simulation time 74224395 ps
CPU time 1.14 seconds
Started Jul 17 07:46:45 PM PDT 24
Finished Jul 17 07:46:49 PM PDT 24
Peak memory 217088 kb
Host smart-7ff88745-cba6-4a58-aef1-7f932c9b256f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225853390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3225853390
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1528797961
Short name T615
Test name
Test status
Simulation time 260348829 ps
CPU time 3.44 seconds
Started Jul 17 07:46:51 PM PDT 24
Finished Jul 17 07:46:57 PM PDT 24
Peak memory 218212 kb
Host smart-7c0d3fd3-c11f-4a04-a667-49a942f59734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528797961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1528797961
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.232368350
Short name T560
Test name
Test status
Simulation time 337758787 ps
CPU time 11.05 seconds
Started Jul 17 07:46:49 PM PDT 24
Finished Jul 17 07:47:03 PM PDT 24
Peak memory 226012 kb
Host smart-d82e668a-ca45-4e45-be39-559099109415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232368350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.232368350
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1073138379
Short name T472
Test name
Test status
Simulation time 224053329 ps
CPU time 8.05 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:17 PM PDT 24
Peak memory 226144 kb
Host smart-416f3d06-919e-4e30-8723-04d31e1d99b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073138379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1073138379
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4015807040
Short name T1
Test name
Test status
Simulation time 781249211 ps
CPU time 7.38 seconds
Started Jul 17 07:46:48 PM PDT 24
Finished Jul 17 07:46:58 PM PDT 24
Peak memory 224792 kb
Host smart-7cb2a6c4-b152-4478-b83b-7ee0ae7533ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015807040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4015807040
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2712505350
Short name T726
Test name
Test status
Simulation time 532205554 ps
CPU time 11 seconds
Started Jul 17 07:46:50 PM PDT 24
Finished Jul 17 07:47:03 PM PDT 24
Peak memory 226040 kb
Host smart-45dd17c7-1ec8-45e3-9d30-394874d25543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712505350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2712505350
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3267702103
Short name T719
Test name
Test status
Simulation time 104321214 ps
CPU time 1.75 seconds
Started Jul 17 07:46:55 PM PDT 24
Finished Jul 17 07:46:58 PM PDT 24
Peak memory 222968 kb
Host smart-e3921af8-933f-4b10-9c10-d159be394315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267702103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3267702103
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.436255460
Short name T281
Test name
Test status
Simulation time 346455587 ps
CPU time 28.8 seconds
Started Jul 17 07:46:50 PM PDT 24
Finished Jul 17 07:47:21 PM PDT 24
Peak memory 250968 kb
Host smart-3df12c49-95c5-46ea-813a-fc8635829ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436255460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.436255460
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.634816376
Short name T215
Test name
Test status
Simulation time 111722315 ps
CPU time 8.16 seconds
Started Jul 17 07:46:52 PM PDT 24
Finished Jul 17 07:47:02 PM PDT 24
Peak memory 250860 kb
Host smart-4ab3dbdb-c6de-4566-9eeb-d0e7774b76e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634816376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.634816376
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.899691209
Short name T834
Test name
Test status
Simulation time 4495152959 ps
CPU time 110.32 seconds
Started Jul 17 07:47:06 PM PDT 24
Finished Jul 17 07:48:57 PM PDT 24
Peak memory 283248 kb
Host smart-92fdc586-0e8f-460c-adb7-1f3c378247fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899691209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.899691209
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1154044279
Short name T145
Test name
Test status
Simulation time 104496989409 ps
CPU time 913.22 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 08:02:22 PM PDT 24
Peak memory 405736 kb
Host smart-25d51b23-19e8-4f85-a1f3-1e181010426c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1154044279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1154044279
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2904565414
Short name T434
Test name
Test status
Simulation time 30754474 ps
CPU time 0.91 seconds
Started Jul 17 07:46:50 PM PDT 24
Finished Jul 17 07:46:53 PM PDT 24
Peak memory 211880 kb
Host smart-1af5b94c-bace-4a76-b615-6ad69ffc5d83
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904565414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2904565414
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2019014290
Short name T708
Test name
Test status
Simulation time 24018486 ps
CPU time 1.3 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 209004 kb
Host smart-9c2514b8-52ac-429f-8ffa-0ca92abed823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019014290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2019014290
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3927354502
Short name T268
Test name
Test status
Simulation time 440592574 ps
CPU time 18.01 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:31 PM PDT 24
Peak memory 218204 kb
Host smart-b8c60035-961b-4f6e-bff2-43cdaea04cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927354502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3927354502
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3430822186
Short name T605
Test name
Test status
Simulation time 175597663 ps
CPU time 2.59 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 217184 kb
Host smart-b9f4166f-1ca8-493b-92d9-a4a043bb89b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430822186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3430822186
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.679479557
Short name T716
Test name
Test status
Simulation time 21381145 ps
CPU time 1.84 seconds
Started Jul 17 07:47:06 PM PDT 24
Finished Jul 17 07:47:09 PM PDT 24
Peak memory 218044 kb
Host smart-94ae453b-90fa-4b96-9b80-7c632e562c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679479557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.679479557
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3181041879
Short name T379
Test name
Test status
Simulation time 1636452537 ps
CPU time 12.7 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 07:47:26 PM PDT 24
Peak memory 226020 kb
Host smart-5bf0af2c-0aa0-4ea9-a08c-8aa8ef658d25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181041879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3181041879
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2275058186
Short name T325
Test name
Test status
Simulation time 3086593223 ps
CPU time 21.16 seconds
Started Jul 17 07:47:05 PM PDT 24
Finished Jul 17 07:47:27 PM PDT 24
Peak memory 226032 kb
Host smart-0d498fe7-e978-4263-88ba-550b3fa60ca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275058186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2275058186
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2549746345
Short name T499
Test name
Test status
Simulation time 247612925 ps
CPU time 9.9 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:18 PM PDT 24
Peak memory 218240 kb
Host smart-87655270-e460-4e7e-b671-48a190af14b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549746345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2549746345
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4058638888
Short name T163
Test name
Test status
Simulation time 4614082294 ps
CPU time 9.2 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:21 PM PDT 24
Peak memory 225468 kb
Host smart-8d638bc9-8a17-4fab-aa50-786aaf1624d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058638888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4058638888
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1710266228
Short name T317
Test name
Test status
Simulation time 61784840 ps
CPU time 1.64 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:47:15 PM PDT 24
Peak memory 213968 kb
Host smart-f76a911d-d250-48f0-94f2-bad7bdb171a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710266228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1710266228
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3725219833
Short name T776
Test name
Test status
Simulation time 1426643315 ps
CPU time 32.84 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:42 PM PDT 24
Peak memory 246188 kb
Host smart-83ec71e5-9fc6-41f6-9a8b-0fb0e8098159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725219833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3725219833
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2674392553
Short name T247
Test name
Test status
Simulation time 239051628 ps
CPU time 10.89 seconds
Started Jul 17 07:47:05 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 244220 kb
Host smart-a04960fd-58ed-4803-ba7a-ea550b50cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674392553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2674392553
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3305661493
Short name T624
Test name
Test status
Simulation time 47192535 ps
CPU time 0.88 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 212020 kb
Host smart-ee78f858-7d68-4cc8-b079-1fb72f2a0915
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305661493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3305661493
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3478668313
Short name T656
Test name
Test status
Simulation time 39585114 ps
CPU time 0.98 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 208836 kb
Host smart-a3a44374-6659-4b4e-972c-980ff2f546bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478668313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3478668313
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1508377215
Short name T678
Test name
Test status
Simulation time 2356409186 ps
CPU time 13.1 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:23 PM PDT 24
Peak memory 218228 kb
Host smart-8b70c57c-3a88-4545-8258-fc50abb326fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508377215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1508377215
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2823621983
Short name T659
Test name
Test status
Simulation time 270094374 ps
CPU time 3.73 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:15 PM PDT 24
Peak memory 217380 kb
Host smart-7b177a8e-2c12-4b38-b01d-05675f41304d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823621983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2823621983
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3103045010
Short name T590
Test name
Test status
Simulation time 65742233 ps
CPU time 2.33 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 218204 kb
Host smart-31a5c6b4-b8b8-41a0-9071-71f777890f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103045010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3103045010
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.242125222
Short name T305
Test name
Test status
Simulation time 295031846 ps
CPU time 15.65 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:26 PM PDT 24
Peak memory 218936 kb
Host smart-d55bb35b-16ce-45f1-8c70-a9282dfd797f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242125222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.242125222
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2539150848
Short name T670
Test name
Test status
Simulation time 1246976214 ps
CPU time 9.67 seconds
Started Jul 17 07:47:05 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 225948 kb
Host smart-34c8d640-662e-4823-9691-0821ab3ec5fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539150848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2539150848
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2398287506
Short name T385
Test name
Test status
Simulation time 913864488 ps
CPU time 6.96 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:14 PM PDT 24
Peak memory 218168 kb
Host smart-3b23d988-7318-47da-8a64-15c2057a632f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398287506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2398287506
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3334600249
Short name T529
Test name
Test status
Simulation time 137980418 ps
CPU time 2.36 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 214656 kb
Host smart-5f79e0a0-4ef0-4293-90b7-91036aa161c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334600249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3334600249
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2090064482
Short name T515
Test name
Test status
Simulation time 3875664351 ps
CPU time 20.91 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:47:34 PM PDT 24
Peak memory 247704 kb
Host smart-9ce3dbc6-2d03-485d-843b-064ef1b6431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090064482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2090064482
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2063503289
Short name T87
Test name
Test status
Simulation time 107692306 ps
CPU time 6.82 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:47:20 PM PDT 24
Peak memory 247048 kb
Host smart-e24305e8-76f8-475d-88aa-023b017c6cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063503289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2063503289
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2913154935
Short name T326
Test name
Test status
Simulation time 7011011420 ps
CPU time 36.75 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:45 PM PDT 24
Peak memory 251076 kb
Host smart-301eb027-55e6-4cbb-90b7-b2088ef9407c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913154935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2913154935
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3779589323
Short name T368
Test name
Test status
Simulation time 37374589 ps
CPU time 0.93 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 211968 kb
Host smart-7985f220-0f8a-46ab-89cf-1193f6b80294
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779589323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3779589323
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3818731775
Short name T365
Test name
Test status
Simulation time 45450741 ps
CPU time 1.09 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:11 PM PDT 24
Peak memory 208900 kb
Host smart-13aebbaf-156a-436b-81b3-d5bfe2cab12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818731775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3818731775
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3614498211
Short name T327
Test name
Test status
Simulation time 351899954 ps
CPU time 15.05 seconds
Started Jul 17 07:47:05 PM PDT 24
Finished Jul 17 07:47:21 PM PDT 24
Peak memory 226052 kb
Host smart-2b8cb3ed-8074-4143-8453-afabcb581f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614498211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3614498211
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3951139964
Short name T506
Test name
Test status
Simulation time 131736803 ps
CPU time 3.87 seconds
Started Jul 17 07:47:06 PM PDT 24
Finished Jul 17 07:47:10 PM PDT 24
Peak memory 217680 kb
Host smart-60b309ee-318d-4a83-94d4-5afd57d4dcae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951139964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3951139964
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.403187845
Short name T420
Test name
Test status
Simulation time 33654083 ps
CPU time 1.53 seconds
Started Jul 17 07:47:06 PM PDT 24
Finished Jul 17 07:47:09 PM PDT 24
Peak memory 218212 kb
Host smart-394040ed-93ad-40a5-8d44-715bd26da78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403187845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.403187845
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2830922496
Short name T800
Test name
Test status
Simulation time 427311203 ps
CPU time 9.19 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:17 PM PDT 24
Peak memory 218228 kb
Host smart-8c35cc8b-f044-441f-a594-fd985066b904
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830922496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2830922496
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4187737919
Short name T650
Test name
Test status
Simulation time 1960437061 ps
CPU time 13.1 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:21 PM PDT 24
Peak memory 226028 kb
Host smart-db5f6110-fcd3-4f17-ad5f-91c9b964e9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187737919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4187737919
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1853681681
Short name T559
Test name
Test status
Simulation time 518377320 ps
CPU time 6.64 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:18 PM PDT 24
Peak memory 226040 kb
Host smart-b9be1dc1-a0c4-4d1d-95ca-90f08dbf691a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853681681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1853681681
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3621603810
Short name T576
Test name
Test status
Simulation time 408524850 ps
CPU time 14.35 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:22 PM PDT 24
Peak memory 226028 kb
Host smart-991e26a0-dfe8-448c-a501-9f2af0f4217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621603810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3621603810
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.493220947
Short name T728
Test name
Test status
Simulation time 45517265 ps
CPU time 2.82 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:13 PM PDT 24
Peak memory 217784 kb
Host smart-8157b423-3e9d-4d36-a58f-76da530495cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493220947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.493220947
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2978744917
Short name T402
Test name
Test status
Simulation time 960330794 ps
CPU time 19.23 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:27 PM PDT 24
Peak memory 250952 kb
Host smart-87e57bc2-2395-47ba-967d-a5647dd68d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978744917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2978744917
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.4135545701
Short name T827
Test name
Test status
Simulation time 305169687 ps
CPU time 8.87 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:21 PM PDT 24
Peak memory 250960 kb
Host smart-f1c1f162-5dd7-4ba8-ba48-86217dfc3a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135545701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.4135545701
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1691780042
Short name T714
Test name
Test status
Simulation time 12074725769 ps
CPU time 204.35 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:50:36 PM PDT 24
Peak memory 250956 kb
Host smart-efd9b031-d5c7-404f-a97e-933f982b3dd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691780042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1691780042
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4195458274
Short name T164
Test name
Test status
Simulation time 77639105615 ps
CPU time 658.34 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 295072 kb
Host smart-a152c11e-56b1-49e2-b987-8e34d610f59b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4195458274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.4195458274
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1987098280
Short name T476
Test name
Test status
Simulation time 105110193 ps
CPU time 1.09 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:47:14 PM PDT 24
Peak memory 212928 kb
Host smart-abb06af4-de8e-4407-b8d3-45a5647e87ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987098280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1987098280
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2999680577
Short name T636
Test name
Test status
Simulation time 259758651 ps
CPU time 1.2 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 208952 kb
Host smart-016f3765-a175-4965-9529-a09933db6a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999680577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2999680577
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1742782053
Short name T474
Test name
Test status
Simulation time 1067594047 ps
CPU time 15.76 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:27 PM PDT 24
Peak memory 218140 kb
Host smart-a7c78e4e-02fc-4314-9710-02d53a2ef538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742782053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1742782053
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2799535489
Short name T303
Test name
Test status
Simulation time 482821663 ps
CPU time 12.58 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 07:47:27 PM PDT 24
Peak memory 217692 kb
Host smart-9265e780-2d24-45c4-b3df-18c244b73a2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799535489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2799535489
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.346025564
Short name T630
Test name
Test status
Simulation time 56767675 ps
CPU time 1.89 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:13 PM PDT 24
Peak memory 218216 kb
Host smart-38f68509-95be-4270-9c48-699830080191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346025564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.346025564
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2156075857
Short name T618
Test name
Test status
Simulation time 581729076 ps
CPU time 9.14 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:21 PM PDT 24
Peak memory 218876 kb
Host smart-1ef1d74b-782c-4ed8-8dfc-56c1cf2ab587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156075857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2156075857
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3119875801
Short name T209
Test name
Test status
Simulation time 1599710710 ps
CPU time 10.8 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 07:47:24 PM PDT 24
Peak memory 226008 kb
Host smart-fb859edf-6069-412e-89a4-6be446d0e219
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119875801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3119875801
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.47681167
Short name T775
Test name
Test status
Simulation time 286263078 ps
CPU time 11.47 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:24 PM PDT 24
Peak memory 218216 kb
Host smart-e9266c67-6fc2-492c-bff2-8d756cac662c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47681167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.47681167
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.573944582
Short name T436
Test name
Test status
Simulation time 529693158 ps
CPU time 8.9 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:20 PM PDT 24
Peak memory 218360 kb
Host smart-e643e1e9-29f2-4505-b17f-85bf5be2ccc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573944582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.573944582
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2950681576
Short name T321
Test name
Test status
Simulation time 54005485 ps
CPU time 1.78 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:12 PM PDT 24
Peak memory 214024 kb
Host smart-86c9743a-e21b-4008-ab03-921dccbba2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950681576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2950681576
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2466243245
Short name T152
Test name
Test status
Simulation time 641132026 ps
CPU time 21.14 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:30 PM PDT 24
Peak memory 250980 kb
Host smart-f42a8732-de02-4da4-a4ef-ba96ff794580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466243245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2466243245
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.939414286
Short name T518
Test name
Test status
Simulation time 95746308 ps
CPU time 3.28 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:15 PM PDT 24
Peak memory 222176 kb
Host smart-64ab9bd8-9f38-4cac-89e9-b5df184858a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939414286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.939414286
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1505118511
Short name T799
Test name
Test status
Simulation time 2406752860 ps
CPU time 53.54 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:48:04 PM PDT 24
Peak memory 267408 kb
Host smart-c09e2a67-ec25-412b-bf57-c2e00d187cae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505118511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1505118511
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1328744006
Short name T699
Test name
Test status
Simulation time 13518326 ps
CPU time 1.06 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:09 PM PDT 24
Peak memory 211896 kb
Host smart-e73ff821-5bc4-4801-afca-541de3d44dd8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328744006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1328744006
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1440441893
Short name T473
Test name
Test status
Simulation time 21750470 ps
CPU time 1.06 seconds
Started Jul 17 07:43:26 PM PDT 24
Finished Jul 17 07:43:29 PM PDT 24
Peak memory 208904 kb
Host smart-3710d8ca-854f-4620-adb3-000ee54bc950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440441893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1440441893
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3326332133
Short name T213
Test name
Test status
Simulation time 1578980081 ps
CPU time 16.83 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:45 PM PDT 24
Peak memory 218216 kb
Host smart-49787759-037e-4834-8281-0e8f48f6bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326332133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3326332133
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.597871533
Short name T169
Test name
Test status
Simulation time 464815584 ps
CPU time 10.73 seconds
Started Jul 17 07:43:32 PM PDT 24
Finished Jul 17 07:43:44 PM PDT 24
Peak memory 217224 kb
Host smart-a864bdb4-6923-4009-9495-3180538e1ba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597871533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.597871533
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1248287458
Short name T830
Test name
Test status
Simulation time 7752618295 ps
CPU time 55.99 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:44:27 PM PDT 24
Peak memory 218876 kb
Host smart-7b59dffa-4df1-44b9-b525-69e5bb8e23d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248287458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1248287458
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2224680947
Short name T211
Test name
Test status
Simulation time 3418575157 ps
CPU time 9.37 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:43:41 PM PDT 24
Peak memory 217828 kb
Host smart-8abd6476-a365-4b77-af9f-4d7ab5d2db2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224680947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
224680947
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4155765899
Short name T609
Test name
Test status
Simulation time 234002557 ps
CPU time 2.84 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:43:35 PM PDT 24
Peak memory 218192 kb
Host smart-36b6ea8e-7f00-43c2-90e4-e834dbd8b2ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155765899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4155765899
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1527466201
Short name T746
Test name
Test status
Simulation time 1316875113 ps
CPU time 37.92 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:44:07 PM PDT 24
Peak memory 217628 kb
Host smart-ccdbc417-d4e8-416a-9ed7-dca52f67d15e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527466201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1527466201
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4111451447
Short name T72
Test name
Test status
Simulation time 340023124 ps
CPU time 9.63 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:38 PM PDT 24
Peak memory 217544 kb
Host smart-3644f365-5540-40bf-ae2b-f4071d530697
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111451447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4111451447
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.332135
Short name T309
Test name
Test status
Simulation time 873198701 ps
CPU time 41.5 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:44:13 PM PDT 24
Peak memory 250908 kb
Host smart-2d977518-bd42-49eb-8d6b-98a893e3f5b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sta
te_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_st
ate_failure.332135
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3478572412
Short name T3
Test name
Test status
Simulation time 2860724913 ps
CPU time 11.39 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:44 PM PDT 24
Peak memory 250968 kb
Host smart-77ac2f6c-a5da-441a-a520-4acaaff60a53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478572412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3478572412
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.825584226
Short name T661
Test name
Test status
Simulation time 151277557 ps
CPU time 3.09 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 218072 kb
Host smart-4909032f-22bd-4c03-b3e0-645726286a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825584226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.825584226
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4110044965
Short name T697
Test name
Test status
Simulation time 1536193823 ps
CPU time 11.39 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:43:41 PM PDT 24
Peak memory 214724 kb
Host smart-a4e0c909-6649-4b17-a113-ba6ef22e12e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110044965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4110044965
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3109806515
Short name T60
Test name
Test status
Simulation time 402348928 ps
CPU time 36.62 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:44:06 PM PDT 24
Peak memory 268652 kb
Host smart-6a926c59-89b1-479a-a52e-80afb802aa62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109806515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3109806515
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3149298283
Short name T749
Test name
Test status
Simulation time 1290741477 ps
CPU time 26.04 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:58 PM PDT 24
Peak memory 226004 kb
Host smart-d9c79c52-87b3-454e-b3ae-5d249d0ff539
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149298283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3149298283
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.371634300
Short name T687
Test name
Test status
Simulation time 1917755457 ps
CPU time 12.73 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:42 PM PDT 24
Peak memory 226020 kb
Host smart-2ac386ab-e75b-4469-bf4b-f7f087a1a54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371634300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.371634300
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.483099502
Short name T818
Test name
Test status
Simulation time 39428202 ps
CPU time 1.76 seconds
Started Jul 17 07:43:26 PM PDT 24
Finished Jul 17 07:43:28 PM PDT 24
Peak memory 213972 kb
Host smart-ab221505-dd0f-4af7-8a9e-1b9599dc7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483099502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.483099502
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3383501582
Short name T319
Test name
Test status
Simulation time 76949818 ps
CPU time 8.48 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:43:39 PM PDT 24
Peak memory 250912 kb
Host smart-b30cc6c5-e80b-4117-b13e-d004fdc228d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383501582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3383501582
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2421859260
Short name T828
Test name
Test status
Simulation time 32090079044 ps
CPU time 294.04 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:48:23 PM PDT 24
Peak memory 332968 kb
Host smart-78d16da7-34ac-4c4b-8722-21bd2904ecb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421859260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2421859260
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.4137685573
Short name T610
Test name
Test status
Simulation time 56920484011 ps
CPU time 826.64 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:57:16 PM PDT 24
Peak memory 259320 kb
Host smart-12781b7c-8ab9-4587-84cc-3e3b3b93376e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4137685573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.4137685573
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2705382213
Short name T857
Test name
Test status
Simulation time 24530191 ps
CPU time 1.01 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 211864 kb
Host smart-244b2e97-0526-44be-a7bc-2ccf0039eac1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705382213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2705382213
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.384783207
Short name T217
Test name
Test status
Simulation time 49657046 ps
CPU time 1 seconds
Started Jul 17 07:47:12 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 208796 kb
Host smart-edd2baa1-87ad-40ee-83bb-4bbdd02f5bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384783207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.384783207
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.872451546
Short name T814
Test name
Test status
Simulation time 2070624102 ps
CPU time 15.01 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 07:47:29 PM PDT 24
Peak memory 218208 kb
Host smart-a3ca987c-aac0-4aae-8d60-2f395bf2f431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872451546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.872451546
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2978689109
Short name T574
Test name
Test status
Simulation time 64654445 ps
CPU time 2.87 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 218196 kb
Host smart-b66fad71-9419-4656-a831-829289a806a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978689109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2978689109
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3549082896
Short name T490
Test name
Test status
Simulation time 688961361 ps
CPU time 16.71 seconds
Started Jul 17 07:46:57 PM PDT 24
Finished Jul 17 07:47:14 PM PDT 24
Peak memory 226036 kb
Host smart-a7cd1629-df52-42fd-9cf9-a8de4ff87861
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549082896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3549082896
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3612220502
Short name T760
Test name
Test status
Simulation time 368600237 ps
CPU time 13.13 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:25 PM PDT 24
Peak memory 226016 kb
Host smart-6810c3fe-59c0-48dc-aec1-0336aa793b36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612220502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3612220502
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.966713221
Short name T700
Test name
Test status
Simulation time 3272444062 ps
CPU time 6.74 seconds
Started Jul 17 07:47:10 PM PDT 24
Finished Jul 17 07:47:20 PM PDT 24
Peak memory 218376 kb
Host smart-f0336261-b45c-4f7c-a354-207b9fe0d4bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966713221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.966713221
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2284658146
Short name T696
Test name
Test status
Simulation time 314986521 ps
CPU time 8.87 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:19 PM PDT 24
Peak memory 226008 kb
Host smart-be3637ea-77fa-443f-98cb-67b63d6d466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284658146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2284658146
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.12265122
Short name T582
Test name
Test status
Simulation time 253464923 ps
CPU time 2.46 seconds
Started Jul 17 07:47:07 PM PDT 24
Finished Jul 17 07:47:11 PM PDT 24
Peak memory 217696 kb
Host smart-3cf5b265-2554-4f00-9ea2-ad12869dc86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12265122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.12265122
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.4023747578
Short name T94
Test name
Test status
Simulation time 907589117 ps
CPU time 27.14 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 245912 kb
Host smart-f6eae891-178a-4038-bc20-4df3b1de18a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023747578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4023747578
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3318845656
Short name T495
Test name
Test status
Simulation time 157017635 ps
CPU time 6.59 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:18 PM PDT 24
Peak memory 250964 kb
Host smart-9f7a82bf-60ac-4f36-82a0-680df05a5640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318845656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3318845656
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1423897701
Short name T384
Test name
Test status
Simulation time 6979758638 ps
CPU time 166.27 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:49:58 PM PDT 24
Peak memory 283848 kb
Host smart-f372edab-1bcb-4ae5-a1f0-20ed319e7574
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423897701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1423897701
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1723758772
Short name T165
Test name
Test status
Simulation time 33802297873 ps
CPU time 1213.18 seconds
Started Jul 17 07:47:11 PM PDT 24
Finished Jul 17 08:07:27 PM PDT 24
Peak memory 677100 kb
Host smart-e19a38d9-b579-4e3f-872c-60c2b27aff05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1723758772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1723758772
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2942573833
Short name T738
Test name
Test status
Simulation time 34445849 ps
CPU time 0.89 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:11 PM PDT 24
Peak memory 211920 kb
Host smart-45441aec-ba58-49fc-af37-86a9db1ed73d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942573833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2942573833
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.850236354
Short name T375
Test name
Test status
Simulation time 93196521 ps
CPU time 0.86 seconds
Started Jul 17 07:47:13 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 208660 kb
Host smart-4f7290b8-9f76-4c5f-a948-61afdc2454c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850236354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.850236354
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.383143956
Short name T680
Test name
Test status
Simulation time 821007314 ps
CPU time 10.57 seconds
Started Jul 17 07:47:08 PM PDT 24
Finished Jul 17 07:47:21 PM PDT 24
Peak memory 218152 kb
Host smart-ab4c02dc-eb30-4acf-bf8f-de3e052b7c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383143956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.383143956
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1430425917
Short name T29
Test name
Test status
Simulation time 1429058094 ps
CPU time 4.75 seconds
Started Jul 17 07:47:15 PM PDT 24
Finished Jul 17 07:47:22 PM PDT 24
Peak memory 217104 kb
Host smart-255919f9-764f-4691-9c80-f1ac9ae0b6d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430425917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1430425917
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2569833952
Short name T454
Test name
Test status
Simulation time 20661877 ps
CPU time 1.72 seconds
Started Jul 17 07:47:15 PM PDT 24
Finished Jul 17 07:47:19 PM PDT 24
Peak memory 221640 kb
Host smart-f3d49588-c854-4025-bfc3-63a5b9db19c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569833952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2569833952
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3058476125
Short name T839
Test name
Test status
Simulation time 1135779537 ps
CPU time 14.34 seconds
Started Jul 17 07:47:14 PM PDT 24
Finished Jul 17 07:47:31 PM PDT 24
Peak memory 226008 kb
Host smart-c6cc21e7-2360-4b3e-96ad-459b0e7b6c0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058476125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3058476125
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.865967050
Short name T279
Test name
Test status
Simulation time 415203147 ps
CPU time 10.38 seconds
Started Jul 17 07:47:13 PM PDT 24
Finished Jul 17 07:47:26 PM PDT 24
Peak memory 226012 kb
Host smart-873a922b-e581-45c5-9e2c-faf9974adc7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865967050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.865967050
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3536659770
Short name T258
Test name
Test status
Simulation time 9225048072 ps
CPU time 13.45 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:25 PM PDT 24
Peak memory 218296 kb
Host smart-e9f402a9-b983-4375-8a73-19311df78649
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536659770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3536659770
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1445304362
Short name T55
Test name
Test status
Simulation time 678090454 ps
CPU time 12.91 seconds
Started Jul 17 07:47:15 PM PDT 24
Finished Jul 17 07:47:30 PM PDT 24
Peak memory 218352 kb
Host smart-53293d1c-a117-43e5-a487-6ce6f08a8872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445304362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1445304362
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.524135386
Short name T766
Test name
Test status
Simulation time 189394526 ps
CPU time 3.77 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:16 PM PDT 24
Peak memory 215072 kb
Host smart-d35083cc-743d-4dde-b255-f5ecaf683988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524135386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.524135386
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.294684113
Short name T671
Test name
Test status
Simulation time 777296324 ps
CPU time 22.48 seconds
Started Jul 17 07:47:15 PM PDT 24
Finished Jul 17 07:47:40 PM PDT 24
Peak memory 250972 kb
Host smart-211cdb8c-fba3-4e64-b5e3-2835ff434d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294684113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.294684113
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.406966408
Short name T350
Test name
Test status
Simulation time 80353452 ps
CPU time 8.8 seconds
Started Jul 17 07:47:13 PM PDT 24
Finished Jul 17 07:47:24 PM PDT 24
Peak memory 250968 kb
Host smart-fd3f6d7e-c47b-4052-9fe5-241c8269f5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406966408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.406966408
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1019477229
Short name T102
Test name
Test status
Simulation time 1689666266 ps
CPU time 73.64 seconds
Started Jul 17 07:47:13 PM PDT 24
Finished Jul 17 07:48:29 PM PDT 24
Peak memory 250948 kb
Host smart-a36ca5e5-9812-4c53-9759-edfff3c09d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019477229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1019477229
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1102225420
Short name T148
Test name
Test status
Simulation time 162255879104 ps
CPU time 632.59 seconds
Started Jul 17 07:47:13 PM PDT 24
Finished Jul 17 07:57:48 PM PDT 24
Peak memory 283816 kb
Host smart-371a3b5f-69d3-4952-8c1e-0b8f91ec1ef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1102225420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1102225420
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4237945716
Short name T481
Test name
Test status
Simulation time 11431547 ps
CPU time 0.93 seconds
Started Jul 17 07:47:13 PM PDT 24
Finished Jul 17 07:47:17 PM PDT 24
Peak memory 211936 kb
Host smart-1acbda72-e233-436b-9be2-83720319ccd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237945716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4237945716
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1732345042
Short name T338
Test name
Test status
Simulation time 18605820 ps
CPU time 0.93 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:29 PM PDT 24
Peak memory 208828 kb
Host smart-29419f80-d847-44d3-9187-4b6694abb9f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732345042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1732345042
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3577755946
Short name T655
Test name
Test status
Simulation time 960611824 ps
CPU time 20.16 seconds
Started Jul 17 07:47:14 PM PDT 24
Finished Jul 17 07:47:37 PM PDT 24
Peak memory 218168 kb
Host smart-f62ef640-da68-47ac-9d2d-d6df8cd51eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577755946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3577755946
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3038071261
Short name T406
Test name
Test status
Simulation time 1219558354 ps
CPU time 3.98 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:33 PM PDT 24
Peak memory 217100 kb
Host smart-f0dba204-dfc4-44e6-ba22-7686bd060643
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038071261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3038071261
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.4168533756
Short name T727
Test name
Test status
Simulation time 289103962 ps
CPU time 3.86 seconds
Started Jul 17 07:47:15 PM PDT 24
Finished Jul 17 07:47:22 PM PDT 24
Peak memory 218200 kb
Host smart-cc533cc6-5649-401a-aa37-3d930b95ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168533756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.4168533756
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3688499445
Short name T621
Test name
Test status
Simulation time 1235887086 ps
CPU time 14.33 seconds
Started Jul 17 07:47:26 PM PDT 24
Finished Jul 17 07:47:42 PM PDT 24
Peak memory 218444 kb
Host smart-6c885fad-c2c3-4754-8b04-b9c3863e514c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688499445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3688499445
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1000505876
Short name T433
Test name
Test status
Simulation time 541147188 ps
CPU time 9.34 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:47:48 PM PDT 24
Peak memory 226020 kb
Host smart-28e4cc3b-abfb-4a32-8b8a-26b8009f6ec1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000505876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1000505876
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1727926131
Short name T861
Test name
Test status
Simulation time 360151084 ps
CPU time 9.86 seconds
Started Jul 17 07:47:26 PM PDT 24
Finished Jul 17 07:47:37 PM PDT 24
Peak memory 218232 kb
Host smart-fdf31413-3ded-44bf-9f23-6a41bd033a48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727926131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1727926131
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1600992777
Short name T648
Test name
Test status
Simulation time 699067062 ps
CPU time 11.1 seconds
Started Jul 17 07:47:14 PM PDT 24
Finished Jul 17 07:47:28 PM PDT 24
Peak memory 226020 kb
Host smart-96909312-8250-4924-b331-7f967aa1b22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600992777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1600992777
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1086066379
Short name T75
Test name
Test status
Simulation time 110231862 ps
CPU time 3.18 seconds
Started Jul 17 07:47:14 PM PDT 24
Finished Jul 17 07:47:20 PM PDT 24
Peak memory 217708 kb
Host smart-c04a252e-c6a9-4a64-999f-a8e05e6d1b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086066379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1086066379
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3582800500
Short name T451
Test name
Test status
Simulation time 2975877054 ps
CPU time 30.52 seconds
Started Jul 17 07:47:09 PM PDT 24
Finished Jul 17 07:47:42 PM PDT 24
Peak memory 251100 kb
Host smart-f8de9e2e-3c91-41eb-a110-6da087014105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582800500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3582800500
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3950905485
Short name T298
Test name
Test status
Simulation time 71805502 ps
CPU time 2.67 seconds
Started Jul 17 07:47:14 PM PDT 24
Finished Jul 17 07:47:20 PM PDT 24
Peak memory 222532 kb
Host smart-57c595bd-8492-452c-8cf4-4c0907c4a715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950905485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3950905485
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3568987238
Short name T345
Test name
Test status
Simulation time 2681977497 ps
CPU time 18.41 seconds
Started Jul 17 07:47:32 PM PDT 24
Finished Jul 17 07:47:52 PM PDT 24
Peak memory 251028 kb
Host smart-d3da71d3-cfc0-44a4-93f2-a71a2bb73ec2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568987238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3568987238
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1971026243
Short name T294
Test name
Test status
Simulation time 25395994 ps
CPU time 1.09 seconds
Started Jul 17 07:47:13 PM PDT 24
Finished Jul 17 07:47:17 PM PDT 24
Peak memory 211900 kb
Host smart-01ec8d47-2292-4f8e-80b4-dbc65a8e757d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971026243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1971026243
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2481871570
Short name T789
Test name
Test status
Simulation time 59962491 ps
CPU time 1.15 seconds
Started Jul 17 07:47:24 PM PDT 24
Finished Jul 17 07:47:26 PM PDT 24
Peak memory 208980 kb
Host smart-04786507-092d-498f-98ae-ca36298dc683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481871570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2481871570
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3135952207
Short name T690
Test name
Test status
Simulation time 432353847 ps
CPU time 19.05 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:47 PM PDT 24
Peak memory 218292 kb
Host smart-78df2df4-8d18-4958-a7d9-b8dc11263df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135952207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3135952207
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.86674025
Short name T547
Test name
Test status
Simulation time 3979191575 ps
CPU time 8.7 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 217716 kb
Host smart-c64efb64-67a8-4e76-81c7-c79db463ce46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86674025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.86674025
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3667490677
Short name T783
Test name
Test status
Simulation time 783778772 ps
CPU time 2.99 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:31 PM PDT 24
Peak memory 222500 kb
Host smart-06daa7f6-74f2-4524-b2b6-216e155b1ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667490677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3667490677
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.181894282
Short name T468
Test name
Test status
Simulation time 1325488061 ps
CPU time 15.05 seconds
Started Jul 17 07:47:26 PM PDT 24
Finished Jul 17 07:47:43 PM PDT 24
Peak memory 226024 kb
Host smart-f5fc2c6d-c832-45c6-ae0e-0f74089751e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181894282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.181894282
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3613564089
Short name T62
Test name
Test status
Simulation time 2982763786 ps
CPU time 12.2 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 226092 kb
Host smart-56e88d84-e326-46af-9d3e-a23967fd3709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613564089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3613564089
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1847230758
Short name T322
Test name
Test status
Simulation time 671512640 ps
CPU time 12.35 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:45 PM PDT 24
Peak memory 226008 kb
Host smart-869269af-5c18-4273-9cd9-ed302a0c994a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847230758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1847230758
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.684953451
Short name T742
Test name
Test status
Simulation time 344982153 ps
CPU time 8.93 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:39 PM PDT 24
Peak memory 218276 kb
Host smart-81c79564-91be-4dee-8fa4-cb0688e4cd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684953451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.684953451
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.4057591444
Short name T70
Test name
Test status
Simulation time 117440590 ps
CPU time 3.15 seconds
Started Jul 17 07:47:28 PM PDT 24
Finished Jul 17 07:47:33 PM PDT 24
Peak memory 214860 kb
Host smart-eeddab40-ea7e-44ad-82d9-8c55ca9ec628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057591444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.4057591444
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1480427473
Short name T328
Test name
Test status
Simulation time 280295055 ps
CPU time 23.7 seconds
Started Jul 17 07:47:28 PM PDT 24
Finished Jul 17 07:47:54 PM PDT 24
Peak memory 250852 kb
Host smart-d57e1f73-837a-47d2-ae0f-9aa19606867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480427473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1480427473
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2547642598
Short name T89
Test name
Test status
Simulation time 492498259 ps
CPU time 6.86 seconds
Started Jul 17 07:47:26 PM PDT 24
Finished Jul 17 07:47:34 PM PDT 24
Peak memory 246676 kb
Host smart-4b172181-4d4b-49d3-ae07-7a63f630afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547642598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2547642598
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3033236538
Short name T233
Test name
Test status
Simulation time 14727345255 ps
CPU time 129.85 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:49:39 PM PDT 24
Peak memory 283768 kb
Host smart-bd8fb8bc-3c0c-4eac-ac97-0b0fd874f41a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033236538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3033236538
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.4158518218
Short name T458
Test name
Test status
Simulation time 19778568 ps
CPU time 0.84 seconds
Started Jul 17 07:47:26 PM PDT 24
Finished Jul 17 07:47:27 PM PDT 24
Peak memory 211872 kb
Host smart-84de3a4f-28ee-4a7c-b197-c11c122a04f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158518218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.4158518218
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.887833095
Short name T324
Test name
Test status
Simulation time 17628592 ps
CPU time 0.89 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:32 PM PDT 24
Peak memory 208732 kb
Host smart-0a75cc02-5c40-466e-81ab-d60163ab9603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887833095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.887833095
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1117180318
Short name T549
Test name
Test status
Simulation time 664969017 ps
CPU time 9 seconds
Started Jul 17 07:47:26 PM PDT 24
Finished Jul 17 07:47:35 PM PDT 24
Peak memory 218220 kb
Host smart-8d6bf99c-d447-4741-9ade-78f718368db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117180318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1117180318
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3148947356
Short name T455
Test name
Test status
Simulation time 240145825 ps
CPU time 2.17 seconds
Started Jul 17 07:47:26 PM PDT 24
Finished Jul 17 07:47:30 PM PDT 24
Peak memory 217104 kb
Host smart-97899b2f-0a19-420e-b292-e35d95fc793f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148947356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3148947356
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2380628230
Short name T691
Test name
Test status
Simulation time 53635193 ps
CPU time 2.41 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:35 PM PDT 24
Peak memory 218204 kb
Host smart-0f930362-1744-489e-8dd7-37600bb34ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380628230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2380628230
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.631424386
Short name T586
Test name
Test status
Simulation time 1910282606 ps
CPU time 21.09 seconds
Started Jul 17 07:47:31 PM PDT 24
Finished Jul 17 07:47:54 PM PDT 24
Peak memory 226100 kb
Host smart-7fe8ea7c-a72f-402f-a459-728471612918
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631424386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.631424386
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3003295758
Short name T318
Test name
Test status
Simulation time 1677279371 ps
CPU time 10.83 seconds
Started Jul 17 07:47:33 PM PDT 24
Finished Jul 17 07:47:45 PM PDT 24
Peak memory 226020 kb
Host smart-d75ee9b5-b10c-40f1-8c37-e1e281476e9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003295758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3003295758
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4082726081
Short name T477
Test name
Test status
Simulation time 230111064 ps
CPU time 6.02 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:35 PM PDT 24
Peak memory 224672 kb
Host smart-d0507e3d-96bd-4efa-b922-def2c2e83a81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082726081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4082726081
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.985997197
Short name T773
Test name
Test status
Simulation time 389683886 ps
CPU time 8.35 seconds
Started Jul 17 07:47:25 PM PDT 24
Finished Jul 17 07:47:34 PM PDT 24
Peak memory 218296 kb
Host smart-2f0cb6b0-80f2-41f1-b039-850f78090e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985997197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.985997197
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2453366045
Short name T587
Test name
Test status
Simulation time 39240448 ps
CPU time 2.35 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:34 PM PDT 24
Peak memory 217660 kb
Host smart-e7532592-e874-4c6b-8da9-f64cc17b6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453366045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2453366045
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3765796847
Short name T427
Test name
Test status
Simulation time 1790318871 ps
CPU time 30.32 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:48:02 PM PDT 24
Peak memory 245556 kb
Host smart-19272fcf-51c1-4182-921e-1677336ced74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765796847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3765796847
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.392565979
Short name T292
Test name
Test status
Simulation time 89007897 ps
CPU time 8.13 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:39 PM PDT 24
Peak memory 250456 kb
Host smart-aa52b7b8-2430-4164-b0d5-064d34ad5cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392565979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.392565979
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2598285591
Short name T155
Test name
Test status
Simulation time 124118981989 ps
CPU time 992.03 seconds
Started Jul 17 07:47:28 PM PDT 24
Finished Jul 17 08:04:02 PM PDT 24
Peak memory 422088 kb
Host smart-5e6d5131-af1c-4e66-8602-70a940ecccc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2598285591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2598285591
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1365168750
Short name T18
Test name
Test status
Simulation time 19137081 ps
CPU time 0.87 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:29 PM PDT 24
Peak memory 213008 kb
Host smart-311dc82d-db86-4678-9647-e21bb7b8f548
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365168750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1365168750
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.362142049
Short name T162
Test name
Test status
Simulation time 48811953 ps
CPU time 0.94 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:47:39 PM PDT 24
Peak memory 208880 kb
Host smart-69b2056a-47d5-4cc1-8dc5-e6f32b9ff43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362142049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.362142049
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1386164627
Short name T569
Test name
Test status
Simulation time 1506563516 ps
CPU time 14.42 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:46 PM PDT 24
Peak memory 218228 kb
Host smart-21f621cb-c418-4010-8837-40fec45f1771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386164627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1386164627
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2742486857
Short name T33
Test name
Test status
Simulation time 417772162 ps
CPU time 11.54 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 217480 kb
Host smart-9f437c70-0c83-49b2-8c06-add3b6ec948c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742486857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2742486857
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2167144353
Short name T449
Test name
Test status
Simulation time 134975853 ps
CPU time 2.76 seconds
Started Jul 17 07:47:31 PM PDT 24
Finished Jul 17 07:47:36 PM PDT 24
Peak memory 218216 kb
Host smart-fa83b680-4a66-45f4-8f06-2c25095b2b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167144353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2167144353
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.790910436
Short name T198
Test name
Test status
Simulation time 299766582 ps
CPU time 8.78 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 218872 kb
Host smart-4b82f05c-9a08-4d5b-bea6-cdc7291d19e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790910436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.790910436
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1949203446
Short name T619
Test name
Test status
Simulation time 811541187 ps
CPU time 8.58 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:47:47 PM PDT 24
Peak memory 225700 kb
Host smart-2ffb3910-ea28-4dd8-a1ae-475d058faa6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949203446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1949203446
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3359504449
Short name T601
Test name
Test status
Simulation time 1477766703 ps
CPU time 13.25 seconds
Started Jul 17 07:47:34 PM PDT 24
Finished Jul 17 07:47:49 PM PDT 24
Peak memory 218216 kb
Host smart-c6731a0b-ec98-4f68-8f3e-ebfa0fab7b2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359504449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3359504449
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.4189211257
Short name T10
Test name
Test status
Simulation time 337283420 ps
CPU time 10.02 seconds
Started Jul 17 07:47:37 PM PDT 24
Finished Jul 17 07:47:49 PM PDT 24
Peak memory 226024 kb
Host smart-4f42d692-328b-441f-b832-06b5a30e1aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189211257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.4189211257
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2792007102
Short name T463
Test name
Test status
Simulation time 36952665 ps
CPU time 2.52 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:35 PM PDT 24
Peak memory 217704 kb
Host smart-93111655-c9a1-442a-a247-95d2781a8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792007102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2792007102
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.483741347
Short name T243
Test name
Test status
Simulation time 1197372613 ps
CPU time 27.23 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:59 PM PDT 24
Peak memory 249792 kb
Host smart-80f5542b-b245-4559-93a9-dcc39eeacd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483741347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.483741347
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2968150331
Short name T219
Test name
Test status
Simulation time 216910493 ps
CPU time 3.3 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 226384 kb
Host smart-8b59d93a-11ee-476e-933a-2821f942e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968150331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2968150331
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2069744710
Short name T429
Test name
Test status
Simulation time 48256660778 ps
CPU time 467.58 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:55:25 PM PDT 24
Peak memory 283708 kb
Host smart-bed0db39-9ca8-4b10-8294-62fed6076c1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069744710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2069744710
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.4023347983
Short name T146
Test name
Test status
Simulation time 83708042940 ps
CPU time 3364.95 seconds
Started Jul 17 07:47:33 PM PDT 24
Finished Jul 17 08:43:40 PM PDT 24
Peak memory 644344 kb
Host smart-958d8d5a-7418-4b6e-b8d8-88fccf5b760d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4023347983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.4023347983
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.972452991
Short name T291
Test name
Test status
Simulation time 11175192 ps
CPU time 0.99 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:32 PM PDT 24
Peak memory 211800 kb
Host smart-c268a804-f4eb-4f0b-9082-a75a67a5a27c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972452991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.972452991
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.762257553
Short name T85
Test name
Test status
Simulation time 88958288 ps
CPU time 1.06 seconds
Started Jul 17 07:47:38 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 208708 kb
Host smart-0e23ff05-886e-473c-a8bc-af5e563fe1e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762257553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.762257553
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3477382212
Short name T340
Test name
Test status
Simulation time 250499700 ps
CPU time 12.16 seconds
Started Jul 17 07:47:28 PM PDT 24
Finished Jul 17 07:47:42 PM PDT 24
Peak memory 218212 kb
Host smart-30f5a95d-5656-496f-8c41-85cdbfdb52af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477382212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3477382212
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.4223939958
Short name T543
Test name
Test status
Simulation time 2842599722 ps
CPU time 7.24 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:36 PM PDT 24
Peak memory 217604 kb
Host smart-34bbbe00-ff03-4e5b-8959-e68e5e7eed61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223939958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4223939958
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2720434550
Short name T296
Test name
Test status
Simulation time 261309584 ps
CPU time 3.4 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:33 PM PDT 24
Peak memory 222200 kb
Host smart-d49e6fae-86bf-4202-93f2-4af615e673d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720434550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2720434550
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3339640305
Short name T602
Test name
Test status
Simulation time 4022542456 ps
CPU time 21.01 seconds
Started Jul 17 07:47:41 PM PDT 24
Finished Jul 17 07:48:04 PM PDT 24
Peak memory 226084 kb
Host smart-cb989e78-cb94-44a4-8658-c5876b32a6a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339640305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3339640305
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.921276218
Short name T809
Test name
Test status
Simulation time 707065615 ps
CPU time 17.59 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:48 PM PDT 24
Peak memory 225996 kb
Host smart-e59c78ca-0ba2-46d8-b2f2-63361d538725
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921276218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.921276218
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3978399463
Short name T150
Test name
Test status
Simulation time 630097328 ps
CPU time 7.13 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:38 PM PDT 24
Peak memory 218312 kb
Host smart-4dc00f1c-bcd5-4e4f-a65c-4acb0714a965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978399463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3978399463
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1176614272
Short name T194
Test name
Test status
Simulation time 338608582 ps
CPU time 8.58 seconds
Started Jul 17 07:47:35 PM PDT 24
Finished Jul 17 07:47:46 PM PDT 24
Peak memory 225452 kb
Host smart-fb9d365c-9ce0-4d41-8d3e-769f0a6bcff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176614272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1176614272
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1119602824
Short name T78
Test name
Test status
Simulation time 82473294 ps
CPU time 1.83 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:47:32 PM PDT 24
Peak memory 214152 kb
Host smart-f59ef5e5-485a-4f3c-8742-9d7c2f9d801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119602824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1119602824
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2401097289
Short name T389
Test name
Test status
Simulation time 254517011 ps
CPU time 26.02 seconds
Started Jul 17 07:47:35 PM PDT 24
Finished Jul 17 07:48:03 PM PDT 24
Peak memory 250976 kb
Host smart-c406a711-dd31-4d5b-a5d6-fb7e513c0a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401097289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2401097289
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3834480622
Short name T721
Test name
Test status
Simulation time 184912351 ps
CPU time 6.45 seconds
Started Jul 17 07:47:35 PM PDT 24
Finished Jul 17 07:47:44 PM PDT 24
Peak memory 248616 kb
Host smart-6345d920-323f-4dee-a81e-5904fc3d0b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834480622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3834480622
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2861318670
Short name T48
Test name
Test status
Simulation time 38230916811 ps
CPU time 149.16 seconds
Started Jul 17 07:47:29 PM PDT 24
Finished Jul 17 07:50:01 PM PDT 24
Peak memory 267552 kb
Host smart-d89d38b5-b53e-4f8d-a528-97da73814f5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861318670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2861318670
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1813130058
Short name T710
Test name
Test status
Simulation time 12517859 ps
CPU time 1 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:47:39 PM PDT 24
Peak memory 211960 kb
Host smart-d856f067-ec69-4eba-8ed0-ef85be3950aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813130058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1813130058
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1808947165
Short name T304
Test name
Test status
Simulation time 18275656 ps
CPU time 1.08 seconds
Started Jul 17 07:47:28 PM PDT 24
Finished Jul 17 07:47:31 PM PDT 24
Peak memory 208868 kb
Host smart-113d3056-ce60-4cb7-b5a9-2dc948e72f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808947165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1808947165
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3058801220
Short name T282
Test name
Test status
Simulation time 1256214856 ps
CPU time 16.09 seconds
Started Jul 17 07:47:41 PM PDT 24
Finished Jul 17 07:47:58 PM PDT 24
Peak memory 226020 kb
Host smart-4ee4d897-fe42-4339-9fcc-946955ead2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058801220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3058801220
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.270043416
Short name T353
Test name
Test status
Simulation time 810109134 ps
CPU time 3.29 seconds
Started Jul 17 07:47:38 PM PDT 24
Finished Jul 17 07:47:43 PM PDT 24
Peak memory 216940 kb
Host smart-7c94026b-a8a7-4ba8-adfd-5e8ea1f2e301
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270043416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.270043416
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3890408004
Short name T220
Test name
Test status
Simulation time 536113283 ps
CPU time 3.58 seconds
Started Jul 17 07:47:41 PM PDT 24
Finished Jul 17 07:47:46 PM PDT 24
Peak memory 222564 kb
Host smart-f8cc6801-03f7-46af-bef8-ece9165751b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890408004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3890408004
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3405168754
Short name T620
Test name
Test status
Simulation time 4656476710 ps
CPU time 24.76 seconds
Started Jul 17 07:47:38 PM PDT 24
Finished Jul 17 07:48:04 PM PDT 24
Peak memory 225956 kb
Host smart-b765eaa9-752f-46d0-abfc-c40133612022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405168754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3405168754
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1017143426
Short name T611
Test name
Test status
Simulation time 240241588 ps
CPU time 9.61 seconds
Started Jul 17 07:47:40 PM PDT 24
Finished Jul 17 07:47:52 PM PDT 24
Peak memory 226020 kb
Host smart-e11bdfb9-67b7-449b-b1a4-fcbfe3dff697
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017143426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1017143426
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2784827840
Short name T428
Test name
Test status
Simulation time 558031479 ps
CPU time 10.7 seconds
Started Jul 17 07:47:38 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 218096 kb
Host smart-b11c69ad-9a76-4703-b56e-e74cb2865298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784827840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2784827840
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3468530469
Short name T735
Test name
Test status
Simulation time 346384532 ps
CPU time 13.66 seconds
Started Jul 17 07:47:40 PM PDT 24
Finished Jul 17 07:47:55 PM PDT 24
Peak memory 226024 kb
Host smart-87be4e43-8b8d-4dd9-9837-8097fb8dbb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468530469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3468530469
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2653389104
Short name T540
Test name
Test status
Simulation time 98789316 ps
CPU time 1.02 seconds
Started Jul 17 07:47:27 PM PDT 24
Finished Jul 17 07:47:30 PM PDT 24
Peak memory 217732 kb
Host smart-f96f6056-a019-4e74-8e7a-3eb11eaa2432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653389104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2653389104
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1990193676
Short name T802
Test name
Test status
Simulation time 253251390 ps
CPU time 23.19 seconds
Started Jul 17 07:47:41 PM PDT 24
Finished Jul 17 07:48:05 PM PDT 24
Peak memory 245296 kb
Host smart-d7ad0c24-8213-4622-a2f2-e62a373dbfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990193676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1990193676
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1482252518
Short name T226
Test name
Test status
Simulation time 305697341 ps
CPU time 7.59 seconds
Started Jul 17 07:47:40 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 251084 kb
Host smart-2fcdf9d3-089a-4e8f-ac02-b43349ac5163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482252518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1482252518
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2475596603
Short name T677
Test name
Test status
Simulation time 18617060903 ps
CPU time 563.02 seconds
Started Jul 17 07:47:38 PM PDT 24
Finished Jul 17 07:57:03 PM PDT 24
Peak memory 221644 kb
Host smart-504c8960-b5ad-4b1f-8659-9afea926a5a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475596603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2475596603
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.947849357
Short name T686
Test name
Test status
Simulation time 98824908 ps
CPU time 0.86 seconds
Started Jul 17 07:47:41 PM PDT 24
Finished Jul 17 07:47:43 PM PDT 24
Peak memory 211544 kb
Host smart-1472f1f1-08e3-4c67-9b68-08663be6811b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947849357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.947849357
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1085954407
Short name T71
Test name
Test status
Simulation time 26334265 ps
CPU time 1.04 seconds
Started Jul 17 07:47:38 PM PDT 24
Finished Jul 17 07:47:40 PM PDT 24
Peak memory 208820 kb
Host smart-2a102787-cfc1-4fc6-86bc-375ce4a19d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085954407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1085954407
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1927822585
Short name T366
Test name
Test status
Simulation time 308577430 ps
CPU time 9.27 seconds
Started Jul 17 07:47:28 PM PDT 24
Finished Jul 17 07:47:39 PM PDT 24
Peak memory 218208 kb
Host smart-ff5170fa-764f-4e05-bf39-b583a7c03d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927822585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1927822585
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.240724292
Short name T667
Test name
Test status
Simulation time 1627609821 ps
CPU time 8.67 seconds
Started Jul 17 07:47:34 PM PDT 24
Finished Jul 17 07:47:44 PM PDT 24
Peak memory 217328 kb
Host smart-3ec2a786-f604-4d24-bc8a-faa33b6c96c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240724292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.240724292
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3803673428
Short name T299
Test name
Test status
Simulation time 59521862 ps
CPU time 2.38 seconds
Started Jul 17 07:47:38 PM PDT 24
Finished Jul 17 07:47:42 PM PDT 24
Peak memory 218200 kb
Host smart-db1d4466-cb67-4b5d-ba36-89226962eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803673428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3803673428
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2021876251
Short name T819
Test name
Test status
Simulation time 258728723 ps
CPU time 10.56 seconds
Started Jul 17 07:47:31 PM PDT 24
Finished Jul 17 07:47:44 PM PDT 24
Peak memory 226028 kb
Host smart-250d8fb0-2e3e-4ea4-b7d6-95ea1209626d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021876251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2021876251
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.4146571965
Short name T290
Test name
Test status
Simulation time 1132105273 ps
CPU time 7.35 seconds
Started Jul 17 07:47:33 PM PDT 24
Finished Jul 17 07:47:42 PM PDT 24
Peak memory 218232 kb
Host smart-a25f5f43-d9fe-4669-848c-37b53c20e99b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146571965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
4146571965
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1040781407
Short name T52
Test name
Test status
Simulation time 217968498 ps
CPU time 8.18 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 226028 kb
Host smart-c705ae2a-febc-4d69-8ab5-927ee455e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040781407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1040781407
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2015794527
Short name T337
Test name
Test status
Simulation time 133207221 ps
CPU time 1.53 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:33 PM PDT 24
Peak memory 217700 kb
Host smart-bad7f219-5c55-466f-b956-35db3d01705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015794527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2015794527
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1006085047
Short name T419
Test name
Test status
Simulation time 570681257 ps
CPU time 20.37 seconds
Started Jul 17 07:47:30 PM PDT 24
Finished Jul 17 07:47:52 PM PDT 24
Peak memory 245980 kb
Host smart-bed2484a-79a3-48d8-b781-c8beb36c5b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006085047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1006085047
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1333891761
Short name T286
Test name
Test status
Simulation time 283048278 ps
CPU time 10.52 seconds
Started Jul 17 07:47:34 PM PDT 24
Finished Jul 17 07:47:46 PM PDT 24
Peak memory 250956 kb
Host smart-4495f982-40b8-42d4-9281-670448f532d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333891761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1333891761
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3555212110
Short name T306
Test name
Test status
Simulation time 26408159255 ps
CPU time 180.26 seconds
Started Jul 17 07:47:37 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 283776 kb
Host smart-26967ccc-7876-497e-b247-798eb800f3b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555212110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3555212110
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2145527413
Short name T689
Test name
Test status
Simulation time 24168821 ps
CPU time 0.94 seconds
Started Jul 17 07:47:33 PM PDT 24
Finished Jul 17 07:47:35 PM PDT 24
Peak memory 211876 kb
Host smart-7036d1c5-e4ce-4a0a-95a5-2c91a86f2b08
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145527413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2145527413
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2285633467
Short name T634
Test name
Test status
Simulation time 51954330 ps
CPU time 0.82 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:47:53 PM PDT 24
Peak memory 208572 kb
Host smart-2b6b2106-4a84-4235-a821-cbdd2bddcd62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285633467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2285633467
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.4014017861
Short name T793
Test name
Test status
Simulation time 550373125 ps
CPU time 16.28 seconds
Started Jul 17 07:47:28 PM PDT 24
Finished Jul 17 07:47:46 PM PDT 24
Peak memory 226024 kb
Host smart-9dc3d677-6682-43fa-bfbc-0b82e0284092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014017861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4014017861
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.750212246
Short name T442
Test name
Test status
Simulation time 2663267833 ps
CPU time 8.91 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:48:01 PM PDT 24
Peak memory 217720 kb
Host smart-91709b26-a725-4c8a-8a9d-635a3aa170fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750212246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.750212246
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2816244468
Short name T249
Test name
Test status
Simulation time 30251786 ps
CPU time 2.09 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:47:40 PM PDT 24
Peak memory 218204 kb
Host smart-2b3f4aec-e0bf-4624-a17b-fdf3f2c3061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816244468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2816244468
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.264837425
Short name T682
Test name
Test status
Simulation time 408416228 ps
CPU time 13.03 seconds
Started Jul 17 07:47:47 PM PDT 24
Finished Jul 17 07:48:02 PM PDT 24
Peak memory 225940 kb
Host smart-e1c1ed34-47c2-41c2-abd3-343c6ccdc22e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264837425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.264837425
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.791397543
Short name T269
Test name
Test status
Simulation time 1545515064 ps
CPU time 8.55 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:47:59 PM PDT 24
Peak memory 226148 kb
Host smart-c3b2ba76-091f-4987-a01d-c74023b4f091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791397543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.791397543
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1462427744
Short name T331
Test name
Test status
Simulation time 676802072 ps
CPU time 10.93 seconds
Started Jul 17 07:47:49 PM PDT 24
Finished Jul 17 07:48:02 PM PDT 24
Peak memory 218236 kb
Host smart-97d61527-6b20-4c5c-8170-3eb4ad6c8cf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462427744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1462427744
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3593496685
Short name T193
Test name
Test status
Simulation time 1338095676 ps
CPU time 9.2 seconds
Started Jul 17 07:47:37 PM PDT 24
Finished Jul 17 07:47:48 PM PDT 24
Peak memory 218192 kb
Host smart-3ffa80e2-31e6-4489-a8c2-88b5ab04b8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593496685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3593496685
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2910241980
Short name T300
Test name
Test status
Simulation time 93753708 ps
CPU time 3.07 seconds
Started Jul 17 07:47:35 PM PDT 24
Finished Jul 17 07:47:41 PM PDT 24
Peak memory 215268 kb
Host smart-ad4197d1-d4bb-4526-a112-a4dad74425c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910241980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2910241980
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.391514548
Short name T369
Test name
Test status
Simulation time 668167887 ps
CPU time 25.49 seconds
Started Jul 17 07:47:36 PM PDT 24
Finished Jul 17 07:48:04 PM PDT 24
Peak memory 250652 kb
Host smart-7d573c2e-ce3a-4a76-865f-364e8cf8a085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391514548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.391514548
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3835880033
Short name T223
Test name
Test status
Simulation time 305204625 ps
CPU time 8.25 seconds
Started Jul 17 07:47:35 PM PDT 24
Finished Jul 17 07:47:45 PM PDT 24
Peak memory 250968 kb
Host smart-600800f2-e744-432f-b8ea-51dc83c22565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835880033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3835880033
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.90853881
Short name T641
Test name
Test status
Simulation time 853178814 ps
CPU time 36.97 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:48:24 PM PDT 24
Peak memory 226024 kb
Host smart-59f897db-31df-45d6-be92-f99a9cd352ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90853881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.lc_ctrl_stress_all.90853881
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.428822183
Short name T50
Test name
Test status
Simulation time 40777363950 ps
CPU time 1353.64 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 08:10:24 PM PDT 24
Peak memory 529720 kb
Host smart-cb2a5c9f-fe55-4aec-ad85-b3043a84f930
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=428822183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.428822183
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2637918870
Short name T823
Test name
Test status
Simulation time 20489846 ps
CPU time 0.84 seconds
Started Jul 17 07:47:37 PM PDT 24
Finished Jul 17 07:47:40 PM PDT 24
Peak memory 211852 kb
Host smart-2c948902-a2d8-4b12-aebc-cf413fdc2ba2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637918870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2637918870
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2154883977
Short name T364
Test name
Test status
Simulation time 17795001 ps
CPU time 0.93 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 208836 kb
Host smart-c5df818e-cadd-4a10-b35a-6056a169e5f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154883977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2154883977
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2975402671
Short name T189
Test name
Test status
Simulation time 15601120 ps
CPU time 0.88 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:29 PM PDT 24
Peak memory 208636 kb
Host smart-f6c6e1c5-cd9a-4d15-b6f0-dde03c33c650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975402671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2975402671
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2499639128
Short name T413
Test name
Test status
Simulation time 3242602108 ps
CPU time 8.21 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:37 PM PDT 24
Peak memory 219048 kb
Host smart-f9235aee-2240-4f02-8db8-fd2088318b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499639128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2499639128
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2845462860
Short name T462
Test name
Test status
Simulation time 1329955594 ps
CPU time 5.64 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:35 PM PDT 24
Peak memory 217404 kb
Host smart-3f82369c-4cd5-42d0-a2e2-d3e305882e90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845462860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2845462860
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2698383498
Short name T245
Test name
Test status
Simulation time 8381641302 ps
CPU time 60.59 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:44:30 PM PDT 24
Peak memory 218864 kb
Host smart-7ab0256c-e648-44e4-93f0-b778b71cb8b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698383498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2698383498
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.617351931
Short name T842
Test name
Test status
Simulation time 269919961 ps
CPU time 2.74 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:43:33 PM PDT 24
Peak memory 217736 kb
Host smart-ec43ca38-9890-4894-87ab-f4010870be0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617351931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.617351931
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.4281099829
Short name T736
Test name
Test status
Simulation time 1113677110 ps
CPU time 8.11 seconds
Started Jul 17 07:43:33 PM PDT 24
Finished Jul 17 07:43:42 PM PDT 24
Peak memory 218160 kb
Host smart-03263234-7ecc-453e-b156-84bab4abab3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281099829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.4281099829
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.286407605
Short name T5
Test name
Test status
Simulation time 5061106177 ps
CPU time 18.88 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:43:51 PM PDT 24
Peak memory 217708 kb
Host smart-c1950f11-59db-484d-b0db-9c32e3d65209
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286407605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.286407605
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3880819460
Short name T764
Test name
Test status
Simulation time 570433071 ps
CPU time 7.71 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:43:37 PM PDT 24
Peak memory 217600 kb
Host smart-1b7d1357-f488-417b-b1d1-16b04a409f1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880819460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3880819460
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2172150832
Short name T416
Test name
Test status
Simulation time 9038026845 ps
CPU time 79.74 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:44:49 PM PDT 24
Peak memory 271860 kb
Host smart-d1e9d281-65ef-4db1-9d95-eb751ad000cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172150832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2172150832
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1732892015
Short name T410
Test name
Test status
Simulation time 1802147099 ps
CPU time 17.35 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:46 PM PDT 24
Peak memory 250376 kb
Host smart-c73544e1-63b9-4b0d-a2cb-373f5e73217f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732892015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1732892015
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.595881403
Short name T425
Test name
Test status
Simulation time 61492745 ps
CPU time 1.47 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:30 PM PDT 24
Peak memory 218208 kb
Host smart-c299282d-97a2-41b8-9a7b-1768bd28f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595881403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.595881403
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2938919412
Short name T754
Test name
Test status
Simulation time 272235660 ps
CPU time 15.41 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:44 PM PDT 24
Peak memory 214756 kb
Host smart-6893194a-47fd-4885-9e13-b43e9c9bf351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938919412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2938919412
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.10264453
Short name T40
Test name
Test status
Simulation time 407481850 ps
CPU time 15.83 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:48 PM PDT 24
Peak memory 226024 kb
Host smart-fe2594e2-0d9f-42cf-8e9c-8308bc6eeb2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dige
st.10264453
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2910575149
Short name T774
Test name
Test status
Simulation time 892228422 ps
CPU time 9.09 seconds
Started Jul 17 07:43:32 PM PDT 24
Finished Jul 17 07:43:42 PM PDT 24
Peak memory 218212 kb
Host smart-049d2ffe-40df-460b-9575-64432c9bd879
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910575149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
910575149
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3936040630
Short name T56
Test name
Test status
Simulation time 526140035 ps
CPU time 12.69 seconds
Started Jul 17 07:43:27 PM PDT 24
Finished Jul 17 07:43:41 PM PDT 24
Peak memory 225980 kb
Host smart-19513ff5-15a7-48cd-bc1c-436eadbe2b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936040630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3936040630
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2195321773
Short name T265
Test name
Test status
Simulation time 56224756 ps
CPU time 1.88 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:35 PM PDT 24
Peak memory 217708 kb
Host smart-c6d0732d-777b-446b-bad7-5fc3a56a6227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195321773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2195321773
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1550011962
Short name T810
Test name
Test status
Simulation time 1669518496 ps
CPU time 22.38 seconds
Started Jul 17 07:43:32 PM PDT 24
Finished Jul 17 07:43:56 PM PDT 24
Peak memory 250376 kb
Host smart-b84f75d0-95c4-4098-8332-4b401e1c99d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550011962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1550011962
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4264927648
Short name T821
Test name
Test status
Simulation time 186440659 ps
CPU time 7.54 seconds
Started Jul 17 07:43:30 PM PDT 24
Finished Jul 17 07:43:39 PM PDT 24
Peak memory 250140 kb
Host smart-d77e868f-b984-46a0-8afa-46817dbad92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264927648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4264927648
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2344876611
Short name T652
Test name
Test status
Simulation time 11729401098 ps
CPU time 107.12 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:45:18 PM PDT 24
Peak memory 267412 kb
Host smart-0b654816-cd4d-4131-bfb0-d6fac6c0c895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344876611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2344876611
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1976332889
Short name T662
Test name
Test status
Simulation time 8967321479 ps
CPU time 182.03 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:46:32 PM PDT 24
Peak memory 277056 kb
Host smart-bccdc5a0-3c0a-4bbc-b77e-8174bfab6e0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1976332889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1976332889
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3418853725
Short name T423
Test name
Test status
Simulation time 12031597 ps
CPU time 1.04 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:43:31 PM PDT 24
Peak memory 211844 kb
Host smart-902a9c12-f2ab-49b7-8649-2d3cf6bc1e13
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418853725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3418853725
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3695273982
Short name T39
Test name
Test status
Simulation time 51124365 ps
CPU time 0.89 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:44:57 PM PDT 24
Peak memory 208768 kb
Host smart-21e5dcb7-d8a9-4cab-b837-d72d75eb4512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695273982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3695273982
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4231002184
Short name T553
Test name
Test status
Simulation time 934470865 ps
CPU time 9.66 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:42 PM PDT 24
Peak memory 218152 kb
Host smart-44548281-d221-4e5b-8684-3276c044dbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231002184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4231002184
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2297016538
Short name T216
Test name
Test status
Simulation time 63598633 ps
CPU time 1.44 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:44:57 PM PDT 24
Peak memory 217064 kb
Host smart-570569d6-9cb4-4d33-9993-95ca8692d324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297016538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2297016538
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2672990822
Short name T608
Test name
Test status
Simulation time 1735302579 ps
CPU time 27.68 seconds
Started Jul 17 07:43:32 PM PDT 24
Finished Jul 17 07:44:01 PM PDT 24
Peak memory 218156 kb
Host smart-32028366-c7a1-4f12-bd98-b077f5c41331
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672990822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2672990822
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3083399486
Short name T512
Test name
Test status
Simulation time 213313768 ps
CPU time 1.96 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:44:53 PM PDT 24
Peak memory 217920 kb
Host smart-669a60aa-1123-4c02-9c94-c0e30530911e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083399486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
083399486
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2747641008
Short name T161
Test name
Test status
Simulation time 151957174 ps
CPU time 3.08 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 218088 kb
Host smart-c99e92db-f411-4e33-9bd4-232e5c43bef0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747641008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2747641008
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1014933834
Short name T626
Test name
Test status
Simulation time 5894479663 ps
CPU time 38.88 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:45:29 PM PDT 24
Peak memory 217704 kb
Host smart-fe08aaf9-c46f-48f1-b1ab-2a2203c8bb05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014933834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1014933834
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3005686034
Short name T599
Test name
Test status
Simulation time 179311397 ps
CPU time 3.1 seconds
Started Jul 17 07:43:33 PM PDT 24
Finished Jul 17 07:43:37 PM PDT 24
Peak memory 217656 kb
Host smart-bdb4f7cd-bbfb-4cac-944e-653bc880341a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005686034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3005686034
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.279083543
Short name T752
Test name
Test status
Simulation time 1152049184 ps
CPU time 37.79 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:44:10 PM PDT 24
Peak memory 275488 kb
Host smart-c9576004-ca3b-47fd-acd3-57bede636bd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279083543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.279083543
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2794057748
Short name T612
Test name
Test status
Simulation time 3274870297 ps
CPU time 32.65 seconds
Started Jul 17 07:43:33 PM PDT 24
Finished Jul 17 07:44:07 PM PDT 24
Peak memory 249580 kb
Host smart-a78336d3-d5af-490d-8f19-b1b93332ea1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794057748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2794057748
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2744298112
Short name T639
Test name
Test status
Simulation time 213369674 ps
CPU time 2.5 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:43:34 PM PDT 24
Peak memory 218200 kb
Host smart-a98ee6fc-5994-4d5d-ac27-5810e9cf8421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744298112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2744298112
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3341171055
Short name T79
Test name
Test status
Simulation time 1742977147 ps
CPU time 16.82 seconds
Started Jul 17 07:43:32 PM PDT 24
Finished Jul 17 07:43:50 PM PDT 24
Peak memory 217776 kb
Host smart-95cf3b02-6474-4d17-9fd0-f777b3f9554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341171055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3341171055
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1298518402
Short name T378
Test name
Test status
Simulation time 2056439568 ps
CPU time 14.64 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:45:03 PM PDT 24
Peak memory 226020 kb
Host smart-7083ce2f-aee0-43e2-9bf7-afd90c463152
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298518402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1298518402
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4134328294
Short name T747
Test name
Test status
Simulation time 5378997773 ps
CPU time 12.93 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:06 PM PDT 24
Peak memory 226088 kb
Host smart-b31b3b0a-30d7-4d47-b348-e84ec27e7aee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134328294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4134328294
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3512167796
Short name T23
Test name
Test status
Simulation time 713785551 ps
CPU time 12.06 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:45:03 PM PDT 24
Peak memory 218112 kb
Host smart-b1037122-560e-4af5-9222-271dc480c0b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512167796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
512167796
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3656201198
Short name T502
Test name
Test status
Simulation time 358038825 ps
CPU time 7.69 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:41 PM PDT 24
Peak memory 224752 kb
Host smart-7a4d6e69-efed-4b8f-91ab-0f866bc7dc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656201198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3656201198
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3031795284
Short name T510
Test name
Test status
Simulation time 183101673 ps
CPU time 2.45 seconds
Started Jul 17 07:43:28 PM PDT 24
Finished Jul 17 07:43:32 PM PDT 24
Peak memory 217676 kb
Host smart-2983adaf-cb77-419b-9651-1a2d695d7e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031795284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3031795284
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2313929600
Short name T548
Test name
Test status
Simulation time 301329230 ps
CPU time 20.15 seconds
Started Jul 17 07:43:32 PM PDT 24
Finished Jul 17 07:43:53 PM PDT 24
Peak memory 250956 kb
Host smart-caebc7a6-75ba-4e8c-b66f-7ae55086def2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313929600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2313929600
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3594029752
Short name T666
Test name
Test status
Simulation time 91673866 ps
CPU time 6.75 seconds
Started Jul 17 07:43:31 PM PDT 24
Finished Jul 17 07:43:40 PM PDT 24
Peak memory 246892 kb
Host smart-e13f2f31-b948-43c1-97da-4f821bcbaac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594029752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3594029752
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.598026798
Short name T373
Test name
Test status
Simulation time 16196234804 ps
CPU time 237.17 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:48:50 PM PDT 24
Peak memory 256788 kb
Host smart-00a90a6e-ba55-41a5-aa26-59eb5825fde1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598026798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.598026798
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.977368803
Short name T538
Test name
Test status
Simulation time 40594212 ps
CPU time 0.87 seconds
Started Jul 17 07:43:29 PM PDT 24
Finished Jul 17 07:43:32 PM PDT 24
Peak memory 211928 kb
Host smart-6b2aad03-8e71-4f9b-84b0-c51f21971737
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977368803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.977368803
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1905643946
Short name T649
Test name
Test status
Simulation time 17564112 ps
CPU time 1.08 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:44:51 PM PDT 24
Peak memory 208912 kb
Host smart-63ca511c-f631-4b75-8805-fa2939ecb39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905643946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1905643946
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2092858682
Short name T598
Test name
Test status
Simulation time 172418911 ps
CPU time 0.91 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:44:57 PM PDT 24
Peak memory 208788 kb
Host smart-a688a9d4-2b1c-47ee-a5e4-474d5d6871b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092858682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2092858682
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1303895638
Short name T589
Test name
Test status
Simulation time 397915787 ps
CPU time 17.37 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:15 PM PDT 24
Peak memory 226028 kb
Host smart-8194ad29-8e43-48a9-a9b1-e0abfd42230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303895638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1303895638
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2210170049
Short name T32
Test name
Test status
Simulation time 647772839 ps
CPU time 9.15 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 217092 kb
Host smart-72018adf-eb46-4658-841d-4e211f7e135a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210170049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2210170049
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2643820406
Short name T437
Test name
Test status
Simulation time 13356127355 ps
CPU time 53.12 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:46 PM PDT 24
Peak memory 218860 kb
Host smart-8b0f3667-cb34-4175-86e7-369d73169ceb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643820406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2643820406
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1559524291
Short name T398
Test name
Test status
Simulation time 229135272 ps
CPU time 4.12 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:44:53 PM PDT 24
Peak memory 217732 kb
Host smart-7a71fb3e-fb96-41fc-a2ba-67ba860e59b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559524291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
559524291
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1901624995
Short name T255
Test name
Test status
Simulation time 1990517149 ps
CPU time 7.6 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:01 PM PDT 24
Peak memory 218144 kb
Host smart-108574e2-be73-4b82-8287-9f4ad0cc1c8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901624995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1901624995
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2670001705
Short name T206
Test name
Test status
Simulation time 2114057720 ps
CPU time 10.44 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:06 PM PDT 24
Peak memory 217648 kb
Host smart-d7c51b3e-18d7-444d-b893-07cd437df1a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670001705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2670001705
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1363676375
Short name T444
Test name
Test status
Simulation time 4064557819 ps
CPU time 9.79 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:06 PM PDT 24
Peak memory 217700 kb
Host smart-62e9785d-ce45-4a5b-a4ca-c2adf8af1ac8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363676375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1363676375
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2238196389
Short name T779
Test name
Test status
Simulation time 8094559180 ps
CPU time 83.36 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:46:13 PM PDT 24
Peak memory 278412 kb
Host smart-a90f64bf-809c-498a-af90-72f220c4073e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238196389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2238196389
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2676047616
Short name T731
Test name
Test status
Simulation time 3757715115 ps
CPU time 29.59 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:45:20 PM PDT 24
Peak memory 250924 kb
Host smart-89036611-89c0-401a-88f7-d35c40fd41a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676047616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2676047616
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2118138749
Short name T855
Test name
Test status
Simulation time 173273566 ps
CPU time 2.74 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:44:56 PM PDT 24
Peak memory 218216 kb
Host smart-72dd874a-4de2-48bf-babe-5d811b45e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118138749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2118138749
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4008044609
Short name T333
Test name
Test status
Simulation time 355482947 ps
CPU time 10.61 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:08 PM PDT 24
Peak memory 214776 kb
Host smart-46b83e81-f98e-4482-86c7-cdfcb4b44cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008044609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4008044609
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1280406995
Short name T816
Test name
Test status
Simulation time 255805981 ps
CPU time 8.77 seconds
Started Jul 17 07:47:58 PM PDT 24
Finished Jul 17 07:48:08 PM PDT 24
Peak memory 226092 kb
Host smart-f5d167f4-5ea5-411e-b68a-0f8e0c9b5d3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280406995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1280406995
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2405654200
Short name T447
Test name
Test status
Simulation time 468308710 ps
CPU time 13.19 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:45:04 PM PDT 24
Peak memory 226004 kb
Host smart-a544d29d-28ec-4029-81d7-626c3385514d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405654200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2405654200
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2355074249
Short name T203
Test name
Test status
Simulation time 1391846162 ps
CPU time 9.83 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:44:58 PM PDT 24
Peak memory 218204 kb
Host smart-d9153fa5-4476-421d-972a-34a83fd82f77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355074249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
355074249
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1773799811
Short name T478
Test name
Test status
Simulation time 403805442 ps
CPU time 9.49 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:02 PM PDT 24
Peak memory 218232 kb
Host smart-0ba87c03-b149-40b3-9138-90cf6a772590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773799811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1773799811
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1194133485
Short name T771
Test name
Test status
Simulation time 51379681 ps
CPU time 1.05 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:44:48 PM PDT 24
Peak memory 217692 kb
Host smart-7ac4f0e5-a29b-4454-a4a1-7ea2d133a082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194133485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1194133485
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1669442809
Short name T551
Test name
Test status
Simulation time 1651711657 ps
CPU time 26.08 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:45:15 PM PDT 24
Peak memory 246208 kb
Host smart-3dbf28a6-3c30-4531-97a4-4a8b515fa4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669442809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1669442809
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2659153496
Short name T267
Test name
Test status
Simulation time 65445281 ps
CPU time 9.93 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:02 PM PDT 24
Peak memory 251092 kb
Host smart-f111fefe-18b3-4572-82bb-268789d4d3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659153496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2659153496
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.421674461
Short name T683
Test name
Test status
Simulation time 7621227058 ps
CPU time 177.77 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:47:48 PM PDT 24
Peak memory 275252 kb
Host smart-6f93fe2a-9f73-4b13-81ce-3ecb9a096039
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421674461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.421674461
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.522171806
Short name T745
Test name
Test status
Simulation time 14616352 ps
CPU time 0.99 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:44:49 PM PDT 24
Peak memory 211880 kb
Host smart-b6f6564c-2c66-46c6-be3c-4d7d5176b0c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522171806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.522171806
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2038228711
Short name T722
Test name
Test status
Simulation time 20891983 ps
CPU time 0.96 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:44:52 PM PDT 24
Peak memory 208828 kb
Host smart-204c5a14-c11b-409e-b21d-8e45ab3e4073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038228711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2038228711
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2754020539
Short name T11
Test name
Test status
Simulation time 880809708 ps
CPU time 13.38 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:08 PM PDT 24
Peak memory 218216 kb
Host smart-de53bed9-c331-4bc8-ba2f-07d3191d9df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754020539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2754020539
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1017389928
Short name T541
Test name
Test status
Simulation time 235985966 ps
CPU time 6.5 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:00 PM PDT 24
Peak memory 217296 kb
Host smart-508c1162-44d3-475d-8542-2f090f9ccda0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017389928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1017389928
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3232977047
Short name T483
Test name
Test status
Simulation time 5946080855 ps
CPU time 47.03 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:43 PM PDT 24
Peak memory 218228 kb
Host smart-7ddfb309-c27d-47a4-bab6-9c2522602a3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232977047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3232977047
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2963156017
Short name T777
Test name
Test status
Simulation time 423513961 ps
CPU time 11.48 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 217680 kb
Host smart-9fd0eb2c-deb9-48ac-9746-667f26150cc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963156017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
963156017
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2921942008
Short name T640
Test name
Test status
Simulation time 352572576 ps
CPU time 7.68 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:44:59 PM PDT 24
Peak memory 218116 kb
Host smart-7b3c1c78-94ea-4b71-9ef6-ce4af8355dda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921942008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2921942008
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3737064361
Short name T352
Test name
Test status
Simulation time 835667408 ps
CPU time 16.05 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:09 PM PDT 24
Peak memory 217644 kb
Host smart-e61808db-07a4-48c8-b374-db4fbaedd2ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737064361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3737064361
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2144077895
Short name T99
Test name
Test status
Simulation time 82809806 ps
CPU time 1.84 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:00 PM PDT 24
Peak memory 217632 kb
Host smart-149ce475-a405-481e-8896-5eb69b8c6b91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144077895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2144077895
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3283110473
Short name T572
Test name
Test status
Simulation time 1365154920 ps
CPU time 52.79 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:45:41 PM PDT 24
Peak memory 250900 kb
Host smart-be36adbd-3b8c-4da2-b345-0c38c1e14bd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283110473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3283110473
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.189497567
Short name T448
Test name
Test status
Simulation time 460653797 ps
CPU time 22.33 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:15 PM PDT 24
Peak memory 250920 kb
Host smart-63170a3d-6957-4943-b932-b1b072eecd5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189497567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.189497567
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2192061456
Short name T822
Test name
Test status
Simulation time 211201469 ps
CPU time 2.65 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:00 PM PDT 24
Peak memory 218208 kb
Host smart-deadbab6-e379-4fd4-9f06-55e8485f0d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192061456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2192061456
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2480970408
Short name T528
Test name
Test status
Simulation time 368551672 ps
CPU time 11.82 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:45:02 PM PDT 24
Peak memory 217684 kb
Host smart-76f02ba8-b7ef-40f0-a6e3-ee5977fc8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480970408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2480970408
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4280081611
Short name T592
Test name
Test status
Simulation time 366593460 ps
CPU time 12.94 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:11 PM PDT 24
Peak memory 226024 kb
Host smart-3aba2f9b-dec2-42b3-b058-11efd08a2cba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280081611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4280081611
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.324385017
Short name T542
Test name
Test status
Simulation time 616244948 ps
CPU time 15.08 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:12 PM PDT 24
Peak memory 225976 kb
Host smart-efb679a9-da97-44fb-aa12-e538f086d222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324385017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.324385017
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.454434906
Short name T633
Test name
Test status
Simulation time 961106814 ps
CPU time 16.15 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:13 PM PDT 24
Peak memory 226016 kb
Host smart-46083374-4dd5-47ed-8673-8f3cfa07f419
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454434906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.454434906
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1353887176
Short name T54
Test name
Test status
Simulation time 2253527193 ps
CPU time 11.99 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:10 PM PDT 24
Peak memory 225204 kb
Host smart-e1c8929b-8c3d-4875-b294-497897f6d837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353887176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1353887176
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1428452304
Short name T244
Test name
Test status
Simulation time 75905810 ps
CPU time 1.55 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:44:50 PM PDT 24
Peak memory 213984 kb
Host smart-8d636cfa-54a7-4729-8247-359e430309ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428452304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1428452304
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2517862205
Short name T288
Test name
Test status
Simulation time 1567454919 ps
CPU time 28.69 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:45:19 PM PDT 24
Peak memory 250940 kb
Host smart-61e18ded-8ce2-4856-b281-ef77b3189355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517862205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2517862205
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.863065231
Short name T241
Test name
Test status
Simulation time 299948423 ps
CPU time 3.15 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:44:55 PM PDT 24
Peak memory 222608 kb
Host smart-31c993ea-eaf4-4541-81e0-91b8fab8f2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863065231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.863065231
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3722765304
Short name T171
Test name
Test status
Simulation time 17518044998 ps
CPU time 131.61 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:47:09 PM PDT 24
Peak memory 281244 kb
Host smart-2c30db22-2cf4-4a7c-9e93-fd6d030206b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722765304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3722765304
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4199931039
Short name T47
Test name
Test status
Simulation time 29732724756 ps
CPU time 9965.81 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 10:31:04 PM PDT 24
Peak memory 791832 kb
Host smart-1a33e79d-2bc3-4baf-825b-e16771b913d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4199931039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.4199931039
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3632681707
Short name T354
Test name
Test status
Simulation time 21114050 ps
CPU time 0.81 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:44:54 PM PDT 24
Peak memory 208192 kb
Host smart-a31efa49-ff8d-47f9-af9d-1f798817dac0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632681707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3632681707
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.58015158
Short name T681
Test name
Test status
Simulation time 17550412 ps
CPU time 0.93 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:44:56 PM PDT 24
Peak memory 208772 kb
Host smart-9ec9b77d-e5db-4875-aac5-316e5a48b8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58015158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.58015158
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3672058105
Short name T632
Test name
Test status
Simulation time 18376480 ps
CPU time 0.79 seconds
Started Jul 17 07:44:47 PM PDT 24
Finished Jul 17 07:44:49 PM PDT 24
Peak memory 208964 kb
Host smart-7e51a0e2-57cd-437e-8bbf-3c73ab58da69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672058105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3672058105
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.368804174
Short name T236
Test name
Test status
Simulation time 685703660 ps
CPU time 16.27 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:10 PM PDT 24
Peak memory 218220 kb
Host smart-80fd6870-2dfb-440e-92a4-fb638fc742ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368804174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.368804174
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1148789168
Short name T229
Test name
Test status
Simulation time 116217074 ps
CPU time 1.66 seconds
Started Jul 17 07:44:55 PM PDT 24
Finished Jul 17 07:45:00 PM PDT 24
Peak memory 217072 kb
Host smart-23467981-a09d-46f8-911b-751b85d2809f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148789168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1148789168
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4145231977
Short name T635
Test name
Test status
Simulation time 14119623398 ps
CPU time 51.48 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:49 PM PDT 24
Peak memory 219616 kb
Host smart-a78c417e-55e1-4a8d-904a-93a6eef3d77c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145231977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4145231977
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2483072857
Short name T704
Test name
Test status
Simulation time 440808655 ps
CPU time 3.36 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:45:02 PM PDT 24
Peak memory 217724 kb
Host smart-8b422650-6a02-4ac4-aedd-aff8a8143758
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483072857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
483072857
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2258125900
Short name T622
Test name
Test status
Simulation time 478363752 ps
CPU time 9.94 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:06 PM PDT 24
Peak memory 223144 kb
Host smart-d75fd502-2a9d-4a71-9ec7-9540ffa0ea8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258125900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2258125900
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2289863147
Short name T756
Test name
Test status
Simulation time 5299060268 ps
CPU time 39.47 seconds
Started Jul 17 07:44:56 PM PDT 24
Finished Jul 17 07:45:39 PM PDT 24
Peak memory 217728 kb
Host smart-bb0740fd-a48c-4435-9008-436ade5c45b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289863147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2289863147
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2028677716
Short name T853
Test name
Test status
Simulation time 1319003091 ps
CPU time 8.67 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:04 PM PDT 24
Peak memory 217640 kb
Host smart-5899b843-fbb6-4f77-8f9a-145632efaf8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028677716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2028677716
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2300412264
Short name T768
Test name
Test status
Simulation time 1485732008 ps
CPU time 55.86 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:54 PM PDT 24
Peak memory 250772 kb
Host smart-c7ba77cc-7f3e-4fe2-a06e-c2b0af867354
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300412264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2300412264
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1221822522
Short name T644
Test name
Test status
Simulation time 1225986699 ps
CPU time 22.03 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:17 PM PDT 24
Peak memory 247192 kb
Host smart-1e6625cc-ae3a-415d-b715-dd88f0136538
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221822522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1221822522
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1599711022
Short name T513
Test name
Test status
Simulation time 61401353 ps
CPU time 1.43 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:44:50 PM PDT 24
Peak memory 221600 kb
Host smart-cce37461-7466-4079-bdbc-fc93489aabc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599711022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1599711022
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2867427154
Short name T228
Test name
Test status
Simulation time 1231655184 ps
CPU time 18.79 seconds
Started Jul 17 07:44:48 PM PDT 24
Finished Jul 17 07:45:08 PM PDT 24
Peak memory 214796 kb
Host smart-7da0a621-dc18-47ac-9fed-0c4087851bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867427154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2867427154
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3815056345
Short name T808
Test name
Test status
Simulation time 197290194 ps
CPU time 7.76 seconds
Started Jul 17 07:44:51 PM PDT 24
Finished Jul 17 07:45:02 PM PDT 24
Peak memory 226024 kb
Host smart-8d40ef7a-76d6-4f10-9f54-9eb83fdc0394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815056345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3815056345
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2405735757
Short name T332
Test name
Test status
Simulation time 1811986955 ps
CPU time 12.71 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:11 PM PDT 24
Peak memory 226020 kb
Host smart-2a613b6d-d92b-4096-a493-1c663f0a9634
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405735757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2405735757
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3530547574
Short name T452
Test name
Test status
Simulation time 776039142 ps
CPU time 8.44 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:06 PM PDT 24
Peak memory 218308 kb
Host smart-8593bea0-5569-4150-a033-31b3f41d18db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530547574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
530547574
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2868764367
Short name T628
Test name
Test status
Simulation time 4494572824 ps
CPU time 12.34 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:09 PM PDT 24
Peak memory 226104 kb
Host smart-eb397ad9-62b7-4798-abfb-677a68499277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868764367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2868764367
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3495996391
Short name T381
Test name
Test status
Simulation time 215888292 ps
CPU time 6.17 seconds
Started Jul 17 07:44:53 PM PDT 24
Finished Jul 17 07:45:04 PM PDT 24
Peak memory 217700 kb
Host smart-59bffa21-c07c-4f1b-a2aa-4a64734cd2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495996391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3495996391
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2507760878
Short name T371
Test name
Test status
Simulation time 904838293 ps
CPU time 26.48 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:22 PM PDT 24
Peak memory 250956 kb
Host smart-f3ca6b58-4307-46a6-9f7b-cdf3875a8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507760878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2507760878
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3235897335
Short name T393
Test name
Test status
Simulation time 367236161 ps
CPU time 7.99 seconds
Started Jul 17 07:44:50 PM PDT 24
Finished Jul 17 07:45:01 PM PDT 24
Peak memory 250968 kb
Host smart-d51723b1-b3f7-4b98-bbe9-3fc468093fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235897335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3235897335
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2712976551
Short name T339
Test name
Test status
Simulation time 4943433318 ps
CPU time 48.05 seconds
Started Jul 17 07:44:52 PM PDT 24
Finished Jul 17 07:45:45 PM PDT 24
Peak memory 251020 kb
Host smart-6760e888-58ce-4e4f-a26f-eb23a95fde8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712976551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2712976551
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.872950508
Short name T346
Test name
Test status
Simulation time 20939332 ps
CPU time 0.85 seconds
Started Jul 17 07:44:49 PM PDT 24
Finished Jul 17 07:44:52 PM PDT 24
Peak memory 211856 kb
Host smart-9a0c2aa5-3a3a-4c2a-99c5-9fc2b380a1ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872950508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.872950508
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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