Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2128856	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2350722

1

T1

81

T2

26

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4128713	1			T1	79		T2	36		T3	2
values[0x0]	174941	1			T1	32		T2	6		T3	3
values[0x1]	175924	1			T1	35		T2	10		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1692387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2787191

1

T1

99

T2

32

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14051	1			T12	4		T18	1		T7	2
valid_sources[0x01]	14057	1			T12	1		T19	3		T18	4
valid_sources[0x02]	13356	1			T1	3		T12	9		T19	2
valid_sources[0x03]	14124	1			T1	5		T12	8		T19	1
valid_sources[0x04]	14155	1			T18	6		T7	1		T22	17
valid_sources[0x05]	13775	1			T12	13		T19	2		T73	1
valid_sources[0x06]	13755	1			T12	8		T19	2		T22	9
valid_sources[0x07]	13969	1			T19	2		T18	2		T7	4
valid_sources[0x08]	17643	1			T12	11		T7	1		T13	125
valid_sources[0x09]	13430	1			T1	1		T12	5		T19	2
valid_sources[0x0a]	13438	1			T12	5		T18	1		T22	4
valid_sources[0x0b]	15141	1			T12	2		T19	2		T18	2
valid_sources[0x0c]	17648	1			T7	3		T13	149		T34	1
valid_sources[0x0d]	115761	1			T7	2		T22	8		T13	115
valid_sources[0x0e]	15367	1			T12	3		T19	1		T18	1
valid_sources[0x0f]	13855	1			T19	2		T18	2		T7	1
valid_sources[0x10]	15709	1			T12	5		T18	2		T7	5
valid_sources[0x11]	20925	1			T12	2		T19	2		T18	3
valid_sources[0x12]	13640	1			T9	1		T12	13		T19	5
valid_sources[0x13]	30902	1			T12	3		T19	2		T73	1
valid_sources[0x14]	14193	1			T12	1		T22	15		T13	177
valid_sources[0x15]	14223	1			T1	1		T12	4		T19	1
valid_sources[0x16]	13978	1			T1	9		T12	8		T7	2
valid_sources[0x17]	13729	1			T12	4		T73	1		T18	1
valid_sources[0x18]	14298	1			T18	1		T13	182		T8	1
valid_sources[0x19]	14113	1			T12	6		T19	2		T7	3
valid_sources[0x1a]	16006	1			T12	1		T19	1		T7	1
valid_sources[0x1b]	16599	1			T12	10		T19	1		T18	2
valid_sources[0x1c]	15130	1			T12	10		T19	1		T7	2
valid_sources[0x1d]	13658	1			T12	15		T7	1		T13	106
valid_sources[0x1e]	14094	1			T12	1		T19	5		T18	2
valid_sources[0x1f]	14966	1			T12	7		T19	1		T7	2
valid_sources[0x20]	13745	1			T7	2		T22	13		T13	141
valid_sources[0x21]	13615	1			T9	1		T12	2		T19	1
valid_sources[0x22]	15155	1			T1	11		T12	4		T19	1
valid_sources[0x23]	13633	1			T12	5		T7	1		T22	2
valid_sources[0x24]	32043	1			T12	2		T19	1		T22	1
valid_sources[0x25]	13903	1			T2	52		T12	4		T19	5
valid_sources[0x26]	13831	1			T12	2		T19	2		T18	4
valid_sources[0x27]	49326	1			T12	4		T19	1		T7	1
valid_sources[0x28]	15391	1			T12	4		T7	1		T13	119
valid_sources[0x29]	14060	1			T12	2		T19	2		T73	1
valid_sources[0x2a]	43830	1			T12	3		T19	1		T7	2
valid_sources[0x2b]	17474	1			T12	5		T19	2		T18	4
valid_sources[0x2c]	16695	1			T12	2		T19	1		T18	4
valid_sources[0x2d]	13815	1			T12	7		T19	2		T18	4
valid_sources[0x2e]	13958	1			T12	6		T7	3		T22	9
valid_sources[0x2f]	14056	1			T12	7		T19	2		T73	1
valid_sources[0x30]	16988	1			T12	4		T19	2		T7	3
valid_sources[0x31]	13925	1			T12	6		T18	3		T22	7
valid_sources[0x32]	15854	1			T12	3		T19	2		T73	1
valid_sources[0x33]	16388	1			T1	3		T12	9		T19	3
valid_sources[0x34]	13234	1			T12	2		T19	3		T7	2
valid_sources[0x35]	15484	1			T12	1		T18	5		T7	4
valid_sources[0x36]	41803	1			T9	1		T12	6		T19	2
valid_sources[0x37]	13778	1			T12	5		T18	2		T7	1
valid_sources[0x38]	13763	1			T12	4		T19	1		T18	1
valid_sources[0x39]	13642	1			T12	7		T19	1		T18	1
valid_sources[0x3a]	15897	1			T12	4		T19	3		T13	124
valid_sources[0x3b]	14397	1			T12	4		T19	1		T18	4
valid_sources[0x3c]	14708	1			T12	4		T19	2		T7	4
valid_sources[0x3d]	14911	1			T12	2		T19	1		T7	2
valid_sources[0x3e]	13534	1			T12	3		T18	1		T7	2
valid_sources[0x3f]	15116	1			T12	7		T19	1		T22	1
valid_sources[0x40]	13939	1			T12	6		T19	4		T18	1
valid_sources[0x41]	14282	1			T12	9		T19	1		T7	1
valid_sources[0x42]	14415	1			T1	3		T12	12		T19	1
valid_sources[0x43]	14588	1			T12	4		T7	2		T22	2
valid_sources[0x44]	15077	1			T1	2		T12	3		T7	2
valid_sources[0x45]	13761	1			T12	2		T19	5		T22	4
valid_sources[0x46]	13558	1			T12	4		T18	1		T7	2
valid_sources[0x47]	14033	1			T1	2		T12	16		T19	1
valid_sources[0x48]	14091	1			T12	6		T19	1		T18	5
valid_sources[0x49]	13660	1			T19	1		T7	4		T13	174
valid_sources[0x4a]	13503	1			T1	22		T12	6		T22	8
valid_sources[0x4b]	16226	1			T12	7		T19	1		T18	1
valid_sources[0x4c]	13907	1			T10	1		T12	3		T19	5
valid_sources[0x4d]	13626	1			T10	2		T18	2		T7	2
valid_sources[0x4e]	13546	1			T12	8		T19	1		T73	1
valid_sources[0x4f]	13731	1			T12	4		T19	3		T18	2
valid_sources[0x50]	13569	1			T12	4		T19	1		T7	3
valid_sources[0x51]	30939	1			T19	2		T13	134		T34	6
valid_sources[0x52]	15703	1			T12	4		T19	4		T18	1
valid_sources[0x53]	13706	1			T12	5		T19	2		T18	2
valid_sources[0x54]	13776	1			T12	4		T19	2		T18	2
valid_sources[0x55]	16873	1			T12	6		T7	1		T13	111
valid_sources[0x56]	13790	1			T12	8		T18	1		T7	2
valid_sources[0x57]	15521	1			T12	9		T19	2		T7	2
valid_sources[0x58]	13466	1			T12	2		T19	1		T18	3
valid_sources[0x59]	15258	1			T12	1		T19	1		T18	2
valid_sources[0x5a]	14971	1			T12	7		T19	1		T18	2
valid_sources[0x5b]	13137	1			T1	10		T12	4		T18	1
valid_sources[0x5c]	14148	1			T12	4		T19	4		T18	2
valid_sources[0x5d]	16198	1			T12	2		T19	1		T7	4
valid_sources[0x5e]	63962	1			T12	1		T19	2		T18	1
valid_sources[0x5f]	13624	1			T12	7		T19	2		T7	2
valid_sources[0x60]	14058	1			T12	9		T18	1		T22	5
valid_sources[0x61]	15573	1			T11	1828		T12	5		T19	3
valid_sources[0x62]	13841	1			T12	2		T73	1		T18	1
valid_sources[0x63]	17896	1			T12	6		T19	1		T18	2
valid_sources[0x64]	26357	1			T12	6		T19	1		T18	1
valid_sources[0x65]	13468	1			T12	6		T18	1		T7	2
valid_sources[0x66]	13874	1			T12	10		T19	1		T18	3
valid_sources[0x67]	16663	1			T1	1		T12	3		T19	1
valid_sources[0x68]	14690	1			T12	1		T19	1		T73	1
valid_sources[0x69]	13758	1			T19	2		T18	1		T7	1
valid_sources[0x6a]	13212	1			T12	3		T19	1		T7	1
valid_sources[0x6b]	14143	1			T12	3		T19	1		T73	1
valid_sources[0x6c]	13892	1			T12	4		T19	1		T18	2
valid_sources[0x6d]	14088	1			T12	2		T19	3		T7	1
valid_sources[0x6e]	14499	1			T12	7		T19	1		T7	1
valid_sources[0x6f]	15037	1			T12	2		T19	6		T18	6
valid_sources[0x70]	14833	1			T12	2		T19	1		T73	1
valid_sources[0x71]	13304	1			T12	3		T19	1		T22	5
valid_sources[0x72]	13567	1			T10	1		T12	2		T19	1
valid_sources[0x73]	34034	1			T12	3		T19	1		T7	1
valid_sources[0x74]	13992	1			T12	5		T13	118		T34	2
valid_sources[0x75]	14134	1			T12	3		T18	2		T7	3
valid_sources[0x76]	13942	1			T19	1		T73	3		T18	1
valid_sources[0x77]	14078	1			T12	4		T19	5		T18	5
valid_sources[0x78]	14079	1			T12	5		T19	1		T18	2
valid_sources[0x79]	13448	1			T12	8		T7	1		T13	139
valid_sources[0x7a]	13832	1			T19	2		T13	124		T34	9
valid_sources[0x7b]	14860	1			T12	6		T19	2		T73	1
valid_sources[0x7c]	14652	1			T19	2		T18	3		T7	2
valid_sources[0x7d]	13396	1			T12	4		T19	2		T18	1
valid_sources[0x7e]	13902	1			T7	6		T13	114		T8	15
valid_sources[0x7f]	16746	1			T12	1		T19	1		T18	1
valid_sources[0x80]	13948	1			T12	8		T19	3		T73	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2047837

1

T1

31

T2

13

T5

210

values[0x0]

all_enables

biggest_size

151784

1

T1

27

T2

4

T3

2

values[0x1]

all_enables

biggest_size

151101

1

T1

23

T2

9

T3

4