Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114984419	14431	0	0
claim_transition_if_regwen_rd_A	114984419	1223	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114984419	14431	0	0
T8	132353	0	0	0
T13	146974	2	0	0
T24	19679	0	0	0
T34	27994	0	0	0
T40	0	16	0	0
T54	4232	0	0	0
T58	0	5	0	0
T62	24693	0	0	0
T63	21073	0	0	0
T72	10849	0	0	0
T85	0	4	0	0
T86	1125	0	0	0
T87	25917	0	0	0
T105	0	12	0	0
T138	0	2	0	0
T139	0	5	0	0
T140	0	3	0	0
T141	0	11	0	0
T142	0	8	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114984419	1223	0	0
T106	0	90	0	0
T110	0	6	0	0
T120	0	33	0	0
T121	0	16	0	0
T122	0	57	0	0
T130	0	36	0	0
T143	568189	4	0	0
T144	217200	1	0	0
T145	0	4	0	0
T146	0	14	0	0
T147	1660	0	0	0
T148	37044	0	0	0
T149	6332	0	0	0
T150	25185	0	0	0
T151	14721	0	0	0
T152	30053	0	0	0
T153	6524	0	0	0
T154	45773	0	0	0