Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1793764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2002703

1

T1

76

T2

1226

T3

884

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3468050	1			T1	99		T2	1214		T3	878
values[0x0]	163784	1			T1	43		T2	373		T3	256
values[0x1]	164633	1			T1	54		T2	363		T3	288

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1425306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2371161

1

T1

88

T2

1368

T3

1006

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11069	1			T2	10		T3	2		T6	2
valid_sources[0x01]	11121	1			T2	3		T3	8		T21	1
valid_sources[0x02]	132176	1			T2	4		T3	7		T15	357
valid_sources[0x03]	10720	1			T2	8		T3	9		T11	2
valid_sources[0x04]	12666	1			T2	13		T3	4		T14	2
valid_sources[0x05]	11358	1			T2	8		T3	2		T6	1
valid_sources[0x06]	145053	1			T2	10		T3	1		T21	1
valid_sources[0x07]	10920	1			T2	8		T3	10		T6	2
valid_sources[0x08]	10566	1			T2	6		T3	8		T6	2
valid_sources[0x09]	11136	1			T2	9		T3	7		T14	1
valid_sources[0x0a]	10936	1			T2	9		T3	4		T10	1
valid_sources[0x0b]	10959	1			T2	13		T3	3		T14	1
valid_sources[0x0c]	10901	1			T1	3		T2	2		T3	5
valid_sources[0x0d]	11550	1			T2	10		T3	4		T14	2
valid_sources[0x0e]	10552	1			T2	3		T3	11		T33	1
valid_sources[0x0f]	13143	1			T2	7		T3	4		T15	304
valid_sources[0x10]	10946	1			T1	1		T2	1		T3	6
valid_sources[0x11]	10823	1			T2	6		T3	9		T11	1
valid_sources[0x12]	11827	1			T2	13		T3	7		T11	1
valid_sources[0x13]	11029	1			T2	10		T3	4		T21	1
valid_sources[0x14]	13288	1			T2	8		T3	5		T15	321
valid_sources[0x15]	12793	1			T1	1		T2	4		T3	3
valid_sources[0x16]	10457	1			T2	10		T3	2		T5	3
valid_sources[0x17]	10974	1			T2	8		T3	7		T6	1
valid_sources[0x18]	11140	1			T2	9		T3	6		T6	1
valid_sources[0x19]	10853	1			T2	5		T3	3		T15	320
valid_sources[0x1a]	15774	1			T2	7		T3	6		T21	1
valid_sources[0x1b]	11329	1			T1	2		T2	8		T3	8
valid_sources[0x1c]	11301	1			T1	2		T2	9		T3	8
valid_sources[0x1d]	10840	1			T2	11		T3	6		T14	2
valid_sources[0x1e]	38170	1			T1	2		T2	5		T3	5
valid_sources[0x1f]	10924	1			T2	9		T3	5		T11	1
valid_sources[0x20]	10595	1			T2	9		T3	3		T33	1
valid_sources[0x21]	10869	1			T2	8		T3	5		T15	355
valid_sources[0x22]	11072	1			T2	5		T3	4		T14	1
valid_sources[0x23]	22948	1			T1	1		T2	4		T3	8
valid_sources[0x24]	10754	1			T2	7		T3	6		T5	1
valid_sources[0x25]	17694	1			T2	5		T3	5		T15	315
valid_sources[0x26]	11345	1			T1	4		T2	5		T3	10
valid_sources[0x27]	11681	1			T2	8		T3	5		T15	283
valid_sources[0x28]	10552	1			T1	1		T2	7		T3	7
valid_sources[0x29]	11863	1			T1	5		T2	10		T3	8
valid_sources[0x2a]	11062	1			T2	6		T3	3		T15	318
valid_sources[0x2b]	10819	1			T1	1		T2	9		T3	4
valid_sources[0x2c]	10433	1			T2	5		T3	4		T21	1
valid_sources[0x2d]	13810	1			T2	9		T3	7		T14	1
valid_sources[0x2e]	11490	1			T2	8		T3	5		T14	3
valid_sources[0x2f]	10598	1			T2	6		T3	5		T14	1
valid_sources[0x30]	11249	1			T2	5		T3	2		T21	1
valid_sources[0x31]	10678	1			T2	5		T3	5		T11	1
valid_sources[0x32]	10661	1			T2	6		T3	4		T6	1
valid_sources[0x33]	13016	1			T2	8		T3	8		T6	4
valid_sources[0x34]	11081	1			T2	5		T3	3		T6	2
valid_sources[0x35]	17250	1			T2	7		T3	6		T14	1
valid_sources[0x36]	10613	1			T2	7		T3	5		T15	348
valid_sources[0x37]	12214	1			T1	4		T2	10		T3	4
valid_sources[0x38]	10901	1			T2	8		T3	7		T11	1
valid_sources[0x39]	10931	1			T1	1		T2	10		T3	4
valid_sources[0x3a]	14352	1			T1	4		T2	9		T3	4
valid_sources[0x3b]	10595	1			T1	1		T2	12		T3	2
valid_sources[0x3c]	10899	1			T2	11		T3	3		T6	10
valid_sources[0x3d]	10568	1			T2	6		T3	9		T6	3
valid_sources[0x3e]	44238	1			T2	10		T3	7		T14	3
valid_sources[0x3f]	10790	1			T1	3		T2	8		T3	7
valid_sources[0x40]	13294	1			T2	5		T3	5		T12	2502
valid_sources[0x41]	13444	1			T2	6		T3	7		T15	307
valid_sources[0x42]	10636	1			T1	1		T2	4		T3	4
valid_sources[0x43]	13689	1			T2	7		T3	4		T14	2
valid_sources[0x44]	10753	1			T2	10		T3	3		T14	1
valid_sources[0x45]	83399	1			T1	1		T2	21		T3	7
valid_sources[0x46]	10396	1			T1	4		T2	13		T3	8
valid_sources[0x47]	13250	1			T2	5		T3	7		T15	295
valid_sources[0x48]	12269	1			T2	6		T3	4		T20	1589
valid_sources[0x49]	10957	1			T1	2		T2	5		T3	4
valid_sources[0x4a]	10829	1			T1	3		T2	4		T3	9
valid_sources[0x4b]	11026	1			T1	2		T2	4		T3	4
valid_sources[0x4c]	10768	1			T1	1		T2	6		T3	5
valid_sources[0x4d]	11228	1			T1	2		T2	6		T3	7
valid_sources[0x4e]	10929	1			T1	1		T2	9		T3	8
valid_sources[0x4f]	12227	1			T2	10		T3	3		T6	1
valid_sources[0x50]	12573	1			T2	8		T3	4		T21	1
valid_sources[0x51]	11807	1			T1	1		T2	4		T3	8
valid_sources[0x52]	11121	1			T2	10		T3	5		T6	1
valid_sources[0x53]	13161	1			T2	8		T3	5		T11	1
valid_sources[0x54]	24404	1			T1	2		T2	8		T3	7
valid_sources[0x55]	67712	1			T1	1		T2	7		T3	8
valid_sources[0x56]	12332	1			T2	11		T3	2		T14	1
valid_sources[0x57]	11046	1			T1	2		T2	5		T3	4
valid_sources[0x58]	10733	1			T3	6		T21	1		T15	335
valid_sources[0x59]	10616	1			T2	10		T3	7		T21	3
valid_sources[0x5a]	10874	1			T2	9		T3	7		T11	1
valid_sources[0x5b]	10751	1			T2	5		T3	3		T14	1
valid_sources[0x5c]	12394	1			T2	5		T3	11		T5	1
valid_sources[0x5d]	11404	1			T1	4		T2	5		T3	9
valid_sources[0x5e]	11106	1			T2	2		T3	4		T14	2
valid_sources[0x5f]	84258	1			T1	10		T2	10		T3	11
valid_sources[0x60]	24028	1			T2	14		T3	8		T14	2
valid_sources[0x61]	11774	1			T1	3		T2	8		T3	8
valid_sources[0x62]	11698	1			T2	7		T3	7		T14	1
valid_sources[0x63]	10526	1			T1	1		T2	7		T3	12
valid_sources[0x64]	10781	1			T2	11		T3	6		T6	1
valid_sources[0x65]	10731	1			T2	9		T3	8		T14	2
valid_sources[0x66]	10388	1			T1	1		T2	4		T3	3
valid_sources[0x67]	10780	1			T1	1		T2	11		T3	3
valid_sources[0x68]	12302	1			T2	6		T3	14		T5	1
valid_sources[0x69]	11103	1			T2	7		T3	6		T21	1
valid_sources[0x6a]	11017	1			T1	2		T2	5		T3	6
valid_sources[0x6b]	10895	1			T2	5		T3	5		T15	330
valid_sources[0x6c]	10750	1			T2	7		T3	6		T5	1
valid_sources[0x6d]	10820	1			T2	6		T3	7		T6	2
valid_sources[0x6e]	10932	1			T2	12		T3	3		T14	1
valid_sources[0x6f]	11283	1			T2	6		T3	4		T11	1
valid_sources[0x70]	13487	1			T1	1		T2	9		T3	4
valid_sources[0x71]	11326	1			T1	1		T2	11		T3	5
valid_sources[0x72]	11037	1			T2	3		T3	8		T5	1
valid_sources[0x73]	10866	1			T2	7		T3	6		T6	2
valid_sources[0x74]	11125	1			T2	7		T3	3		T10	17
valid_sources[0x75]	11562	1			T2	13		T3	9		T15	307
valid_sources[0x76]	14684	1			T1	2		T2	10		T3	1
valid_sources[0x77]	13226	1			T2	3		T3	10		T15	338
valid_sources[0x78]	10784	1			T1	2		T2	9		T3	7
valid_sources[0x79]	11796	1			T2	4		T3	7		T6	1
valid_sources[0x7a]	11656	1			T1	1		T2	8		T3	4
valid_sources[0x7b]	12242	1			T1	3		T2	13		T3	4
valid_sources[0x7c]	10674	1			T2	10		T3	2		T14	3
valid_sources[0x7d]	11795	1			T2	8		T3	4		T14	1
valid_sources[0x7e]	10742	1			T1	1		T2	12		T3	8
valid_sources[0x7f]	10974	1			T2	7		T3	3		T14	1
valid_sources[0x80]	10913	1			T2	11		T3	4		T15	340

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1720250

1

T1

48

T2

571

T3

418

values[0x0]

all_enables

biggest_size

141765

1

T1

12

T2

339

T3

219

values[0x1]

all_enables

biggest_size

140688

1

T1

16

T2

316

T3

247