Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	101987881	12751	0	0
claim_transition_if_regwen_rd_A	101987881	1348	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101987881	12751	0	0
T15	284646	5	0	0
T18	27807	0	0	0
T22	437258	0	0	0
T23	149859	0	0	0
T25	0	8	0	0
T46	0	6	0	0
T47	6366	0	0	0
T61	29430	0	0	0
T71	0	2	0	0
T72	3647	0	0	0
T73	20301	0	0	0
T78	1307	0	0	0
T97	0	13	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	5	0	0
T134	0	21	0	0
T135	0	5	0	0
T136	1404	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101987881	1348	0	0
T38	28190	0	0	0
T94	0	3	0	0
T96	0	5	0	0
T126	0	20	0	0
T133	312846	8	0	0
T134	182870	0	0	0
T137	0	4	0	0
T138	0	1	0	0
T139	0	5	0	0
T140	0	10	0	0
T141	0	3	0	0
T142	0	31	0	0
T143	31150	0	0	0
T144	27857	0	0	0
T145	606393	0	0	0
T146	853	0	0	0
T147	26867	0	0	0
T148	66074	0	0	0
T149	8959	0	0	0