Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1895216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2118497

1

T1

131

T2

63

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3659788	1			T1	112		T2	74		T3	3
values[0x0]	176888	1			T1	45		T2	23		T3	3
values[0x1]	177037	1			T1	43		T2	20		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1506197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2507516

1

T1

146

T2

73

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15184	1			T1	1		T4	1		T14	2
valid_sources[0x01]	41685	1			T4	1		T14	6		T15	1
valid_sources[0x02]	45197	1			T4	1		T14	10		T15	5
valid_sources[0x03]	11847	1			T14	5		T7	1		T15	2
valid_sources[0x04]	11850	1			T4	4		T14	1		T26	5
valid_sources[0x05]	11963	1			T1	1		T14	1		T26	4
valid_sources[0x06]	11843	1			T4	1		T14	1		T7	1
valid_sources[0x07]	11887	1			T4	3		T14	1		T6	4
valid_sources[0x08]	11761	1			T4	3		T14	5		T6	1
valid_sources[0x09]	12898	1			T4	2		T13	4		T14	2
valid_sources[0x0a]	11646	1			T4	1		T14	4		T15	5
valid_sources[0x0b]	11689	1			T1	3		T4	1		T14	4
valid_sources[0x0c]	11604	1			T14	7		T20	1		T15	8
valid_sources[0x0d]	11861	1			T14	6		T20	1		T15	1
valid_sources[0x0e]	11698	1			T4	2		T14	5		T15	5
valid_sources[0x0f]	11936	1			T4	3		T14	6		T15	9
valid_sources[0x10]	11663	1			T4	1		T14	4		T15	4
valid_sources[0x11]	12761	1			T4	4		T7	1		T15	6
valid_sources[0x12]	11984	1			T1	1		T4	1		T14	1
valid_sources[0x13]	12015	1			T13	1		T14	6		T15	6
valid_sources[0x14]	11726	1			T1	1		T6	9		T15	3
valid_sources[0x15]	12054	1			T4	2		T14	8		T6	5
valid_sources[0x16]	12259	1			T4	4		T14	3		T15	2
valid_sources[0x17]	11817	1			T14	1		T15	1		T26	3
valid_sources[0x18]	14343	1			T1	2		T4	2		T14	9
valid_sources[0x19]	32309	1			T4	3		T14	9		T15	2
valid_sources[0x1a]	11972	1			T4	4		T14	11		T6	6
valid_sources[0x1b]	12045	1			T4	3		T14	4		T15	13
valid_sources[0x1c]	11680	1			T4	1		T14	6		T15	8
valid_sources[0x1d]	11626	1			T1	3		T14	2		T6	5
valid_sources[0x1e]	11691	1			T1	1		T4	1		T14	14
valid_sources[0x1f]	13125	1			T1	1		T4	3		T14	8
valid_sources[0x20]	11786	1			T15	4		T26	3		T33	2
valid_sources[0x21]	16692	1			T1	1		T13	1		T14	1
valid_sources[0x22]	12524	1			T1	1		T7	2		T15	6
valid_sources[0x23]	11740	1			T4	1		T15	6		T33	5
valid_sources[0x24]	11489	1			T14	5		T15	4		T26	9
valid_sources[0x25]	11844	1			T1	1		T14	5		T7	1
valid_sources[0x26]	11853	1			T1	1		T14	2		T15	11
valid_sources[0x27]	14170	1			T14	4		T6	5		T33	5
valid_sources[0x28]	11988	1			T4	1		T14	3		T15	2
valid_sources[0x29]	13536	1			T4	2		T14	10		T15	4
valid_sources[0x2a]	12543	1			T1	1		T4	2		T14	6
valid_sources[0x2b]	11611	1			T14	4		T6	6		T15	5
valid_sources[0x2c]	11979	1			T10	26		T4	1		T13	3
valid_sources[0x2d]	11994	1			T4	4		T14	8		T15	6
valid_sources[0x2e]	12538	1			T1	1		T4	3		T14	3
valid_sources[0x2f]	12147	1			T1	3		T4	2		T14	9
valid_sources[0x30]	11501	1			T4	1		T14	4		T6	6
valid_sources[0x31]	13112	1			T1	2		T6	1		T15	5
valid_sources[0x32]	13580	1			T1	1		T4	1		T11	1769
valid_sources[0x33]	11921	1			T1	1		T4	1		T14	2
valid_sources[0x34]	12176	1			T4	2		T14	5		T6	2
valid_sources[0x35]	11963	1			T4	1		T14	7		T15	3
valid_sources[0x36]	12204	1			T4	1		T6	4		T15	17
valid_sources[0x37]	13737	1			T1	1		T4	2		T14	2
valid_sources[0x38]	14564	1			T1	2		T4	2		T14	7
valid_sources[0x39]	11982	1			T4	2		T14	1		T7	1
valid_sources[0x3a]	11946	1			T4	1		T14	2		T15	9
valid_sources[0x3b]	12758	1			T4	1		T14	4		T6	1
valid_sources[0x3c]	111230	1			T4	2		T15	2		T26	3
valid_sources[0x3d]	200094	1			T4	2		T15	13		T26	2
valid_sources[0x3e]	11698	1			T4	2		T14	2		T15	1
valid_sources[0x3f]	11912	1			T1	2		T4	1		T14	6
valid_sources[0x40]	15160	1			T1	2		T14	6		T6	3
valid_sources[0x41]	11982	1			T1	2		T4	2		T14	5
valid_sources[0x42]	79796	1			T4	2		T14	2		T15	3
valid_sources[0x43]	100494	1			T4	5		T14	3		T15	4
valid_sources[0x44]	12178	1			T4	4		T14	14		T7	4
valid_sources[0x45]	12071	1			T4	2		T14	9		T15	2
valid_sources[0x46]	13839	1			T1	1		T13	3		T14	2
valid_sources[0x47]	22284	1			T4	4		T14	12		T20	1
valid_sources[0x48]	12268	1			T1	1		T14	2		T7	1
valid_sources[0x49]	13741	1			T4	2		T14	3		T15	1
valid_sources[0x4a]	11573	1			T4	1		T14	9		T15	5
valid_sources[0x4b]	13065	1			T1	2		T14	1		T15	4
valid_sources[0x4c]	11903	1			T1	1		T4	2		T14	10
valid_sources[0x4d]	11796	1			T4	3		T14	16		T15	12
valid_sources[0x4e]	11912	1			T4	1		T14	8		T7	1
valid_sources[0x4f]	12003	1			T1	3		T14	4		T7	1
valid_sources[0x50]	12074	1			T14	5		T6	1		T15	10
valid_sources[0x51]	12092	1			T4	3		T14	2		T6	5
valid_sources[0x52]	11593	1			T14	3		T15	2		T26	7
valid_sources[0x53]	11719	1			T4	1		T14	14		T6	7
valid_sources[0x54]	12012	1			T1	1		T4	2		T14	5
valid_sources[0x55]	12066	1			T1	1		T4	2		T14	1
valid_sources[0x56]	27614	1			T14	2		T15	8		T26	1
valid_sources[0x57]	11738	1			T1	2		T4	1		T14	7
valid_sources[0x58]	18225	1			T1	1		T14	2		T31	18
valid_sources[0x59]	14986	1			T1	2		T4	5		T14	3
valid_sources[0x5a]	11928	1			T4	3		T14	8		T15	2
valid_sources[0x5b]	12105	1			T14	9		T15	4		T26	6
valid_sources[0x5c]	12165	1			T1	2		T4	1		T14	10
valid_sources[0x5d]	11584	1			T1	1		T4	1		T14	3
valid_sources[0x5e]	11572	1			T14	6		T6	1		T15	11
valid_sources[0x5f]	13973	1			T4	3		T14	2		T6	3
valid_sources[0x60]	13406	1			T4	4		T14	8		T20	2
valid_sources[0x61]	11685	1			T4	4		T14	10		T6	2
valid_sources[0x62]	13946	1			T4	1		T14	6		T15	9
valid_sources[0x63]	14359	1			T1	2		T4	3		T14	12
valid_sources[0x64]	11939	1			T14	3		T6	1		T7	1
valid_sources[0x65]	12000	1			T14	2		T15	7		T26	1
valid_sources[0x66]	14626	1			T1	5		T4	1		T14	1
valid_sources[0x67]	11905	1			T1	1		T14	17		T6	3
valid_sources[0x68]	19344	1			T4	2		T13	2		T14	9
valid_sources[0x69]	11426	1			T4	2		T14	1		T6	4
valid_sources[0x6a]	12240	1			T15	4		T33	5		T21	11
valid_sources[0x6b]	12708	1			T4	3		T14	7		T7	1
valid_sources[0x6c]	11712	1			T1	1		T4	1		T14	2
valid_sources[0x6d]	11617	1			T14	4		T15	10		T26	3
valid_sources[0x6e]	11908	1			T1	1		T4	2		T14	6
valid_sources[0x6f]	13442	1			T13	9		T14	8		T15	11
valid_sources[0x70]	20148	1			T4	1		T14	1		T15	1
valid_sources[0x71]	14243	1			T4	2		T14	10		T15	5
valid_sources[0x72]	11969	1			T1	1		T4	1		T14	1
valid_sources[0x73]	11389	1			T4	2		T14	3		T15	1
valid_sources[0x74]	11665	1			T14	10		T26	1		T33	5
valid_sources[0x75]	11566	1			T3	11		T14	5		T6	5
valid_sources[0x76]	11901	1			T1	1		T4	4		T14	1
valid_sources[0x77]	11594	1			T4	2		T14	8		T7	2
valid_sources[0x78]	11983	1			T4	3		T14	10		T7	1
valid_sources[0x79]	12844	1			T4	2		T14	6		T15	2
valid_sources[0x7a]	13021	1			T1	4		T4	1		T14	2
valid_sources[0x7b]	25043	1			T14	6		T7	1		T15	6
valid_sources[0x7c]	11623	1			T1	1		T14	12		T15	5
valid_sources[0x7d]	12063	1			T1	1		T14	13		T6	4
valid_sources[0x7e]	12054	1			T4	1		T14	6		T15	9
valid_sources[0x7f]	14052	1			T14	6		T7	2		T15	5
valid_sources[0x80]	11623	1			T4	1		T14	1		T15	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1813405

1

T1

52

T2

27

T4

140

values[0x0]

all_enables

biggest_size

153217

1

T1

42

T2

19

T3

3

values[0x1]

all_enables

biggest_size

151875

1

T1

37

T2

17

T3

3