Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	121389486	15834	0	0
claim_transition_if_regwen_rd_A	121389486	2154	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121389486	15834	0	0
T46	247684	2	0	0
T48	404688	8	0	0
T50	0	3	0	0
T54	20843	0	0	0
T57	297176	2	0	0
T58	0	10	0	0
T97	0	1	0	0
T140	0	2	0	0
T141	0	6	0	0
T142	0	4	0	0
T143	0	1	0	0
T144	1446	0	0	0
T145	83775	0	0	0
T146	66907	0	0	0
T147	4949	0	0	0
T148	6974	0	0	0
T149	149020	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121389486	2154	0	0
T57	297176	5	0	0
T71	726503	0	0	0
T106	0	26	0	0
T110	0	43	0	0
T111	0	4	0	0
T146	66907	0	0	0
T147	4949	0	0	0
T148	6974	0	0	0
T149	149020	0	0	0
T150	0	7	0	0
T151	0	15	0	0
T152	0	12	0	0
T153	0	25	0	0
T154	0	8	0	0
T155	0	36	0	0
T156	189361	0	0	0
T157	31115	0	0	0
T158	7548	0	0	0
T159	17716	0	0	0