Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1560855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1772607

1

T1

1346

T2

797

T3

458

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3005865	1			T1	1506		T2	752		T3	408
values[0x0]	163380	1			T1	342		T2	240		T3	179
values[0x1]	164217	1			T1	338		T2	256		T3	197

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1239504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2093958

1

T1

1523

T2

910

T3

524

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	44639	1			T2	1		T3	2		T10	2
valid_sources[0x01]	9605	1			T2	15		T3	2		T9	2
valid_sources[0x02]	10654	1			T3	4		T11	5		T12	2
valid_sources[0x03]	11179	1			T2	4		T3	4		T10	1
valid_sources[0x04]	9589	1			T2	14		T3	6		T9	1
valid_sources[0x05]	9441	1			T2	3		T3	4		T10	4
valid_sources[0x06]	9105	1			T2	2		T3	1		T10	2
valid_sources[0x07]	10004	1			T2	4		T3	1		T10	1
valid_sources[0x08]	9749	1			T2	2		T3	3		T9	1
valid_sources[0x09]	11506	1			T2	7		T3	2		T9	2
valid_sources[0x0a]	9848	1			T2	3		T3	2		T9	1
valid_sources[0x0b]	11132	1			T2	12		T3	4		T9	1
valid_sources[0x0c]	10617	1			T2	1		T3	5		T9	3
valid_sources[0x0d]	10161	1			T2	4		T10	1		T11	4
valid_sources[0x0e]	9248	1			T2	1		T3	3		T10	9
valid_sources[0x0f]	9489	1			T2	9		T3	3		T11	1
valid_sources[0x10]	9860	1			T2	8		T9	2		T11	2
valid_sources[0x11]	9681	1			T2	2		T3	3		T9	4
valid_sources[0x12]	9408	1			T2	3		T3	5		T9	3
valid_sources[0x13]	9680	1			T2	4		T3	4		T9	4
valid_sources[0x14]	12180	1			T2	7		T3	3		T10	9
valid_sources[0x15]	9711	1			T2	9		T3	1		T12	11
valid_sources[0x16]	10177	1			T2	5		T3	4		T12	6
valid_sources[0x17]	10691	1			T2	9		T10	5		T11	4
valid_sources[0x18]	12127	1			T2	8		T3	2		T11	1
valid_sources[0x19]	9443	1			T2	1		T3	8		T9	6
valid_sources[0x1a]	9461	1			T2	2		T3	3		T9	4
valid_sources[0x1b]	12429	1			T3	3		T11	2		T12	11
valid_sources[0x1c]	26516	1			T2	9		T3	2		T10	2
valid_sources[0x1d]	10017	1			T2	9		T3	1		T9	2
valid_sources[0x1e]	9473	1			T2	2		T11	5		T12	1
valid_sources[0x1f]	9714	1			T2	6		T3	3		T9	7
valid_sources[0x20]	9553	1			T2	2		T3	7		T11	1
valid_sources[0x21]	10799	1			T2	3		T3	1		T9	3
valid_sources[0x22]	9800	1			T2	4		T3	1		T10	7
valid_sources[0x23]	10890	1			T2	1		T3	2		T9	1
valid_sources[0x24]	10389	1			T2	6		T3	2		T9	1
valid_sources[0x25]	10974	1			T2	3		T3	8		T9	1
valid_sources[0x26]	13873	1			T2	2		T3	2		T9	1
valid_sources[0x27]	9597	1			T2	9		T3	2		T11	2
valid_sources[0x28]	9421	1			T2	5		T3	4		T10	2
valid_sources[0x29]	9761	1			T2	6		T3	2		T11	1
valid_sources[0x2a]	10448	1			T2	10		T3	5		T9	1
valid_sources[0x2b]	9482	1			T2	1		T3	1		T10	2
valid_sources[0x2c]	9674	1			T2	6		T3	3		T9	2
valid_sources[0x2d]	9373	1			T2	1		T3	3		T9	1
valid_sources[0x2e]	9357	1			T2	2		T3	4		T9	1
valid_sources[0x2f]	9820	1			T2	10		T3	4		T9	3
valid_sources[0x30]	9548	1			T2	3		T3	4		T10	4
valid_sources[0x31]	11664	1			T1	2186		T2	2		T3	4
valid_sources[0x32]	9485	1			T2	6		T10	6		T11	1
valid_sources[0x33]	11386	1			T2	3		T3	2		T9	1
valid_sources[0x34]	10577	1			T2	9		T3	3		T10	1
valid_sources[0x35]	9415	1			T2	4		T3	4		T9	3
valid_sources[0x36]	29175	1			T2	6		T3	1		T11	2
valid_sources[0x37]	9779	1			T3	6		T10	8		T11	1
valid_sources[0x38]	9014	1			T3	4		T10	10		T11	4
valid_sources[0x39]	11589	1			T2	1		T3	1		T12	8
valid_sources[0x3a]	9756	1			T2	10		T3	4		T9	3
valid_sources[0x3b]	9337	1			T2	1		T3	3		T10	10
valid_sources[0x3c]	9362	1			T2	7		T3	4		T11	2
valid_sources[0x3d]	11151	1			T2	5		T3	6		T10	9
valid_sources[0x3e]	9514	1			T2	1		T3	2		T10	8
valid_sources[0x3f]	11316	1			T2	5		T3	1		T10	1
valid_sources[0x40]	21981	1			T2	2		T3	3		T9	1
valid_sources[0x41]	9937	1			T2	3		T3	4		T10	3
valid_sources[0x42]	9657	1			T2	3		T10	8		T11	1
valid_sources[0x43]	57337	1			T2	3		T3	5		T12	2
valid_sources[0x44]	9775	1			T2	6		T3	4		T9	3
valid_sources[0x45]	9437	1			T2	11		T3	2		T9	2
valid_sources[0x46]	10739	1			T2	5		T3	5		T10	1
valid_sources[0x47]	9288	1			T2	3		T3	3		T10	7
valid_sources[0x48]	35438	1			T2	3		T3	3		T10	2
valid_sources[0x49]	9198	1			T2	3		T3	5		T10	13
valid_sources[0x4a]	10451	1			T2	3		T3	2		T9	3
valid_sources[0x4b]	9571	1			T3	4		T10	2		T11	2
valid_sources[0x4c]	10029	1			T2	6		T3	5		T10	7
valid_sources[0x4d]	9390	1			T2	1		T3	2		T10	15
valid_sources[0x4e]	47679	1			T2	10		T3	6		T10	2
valid_sources[0x4f]	11532	1			T2	5		T3	1		T9	1
valid_sources[0x50]	9867	1			T2	7		T3	3		T12	5
valid_sources[0x51]	9305	1			T2	3		T3	3		T9	2
valid_sources[0x52]	9665	1			T2	6		T3	5		T10	5
valid_sources[0x53]	18251	1			T2	3		T3	2		T9	2
valid_sources[0x54]	10033	1			T2	6		T3	4		T10	4
valid_sources[0x55]	10376	1			T2	7		T3	3		T9	2
valid_sources[0x56]	37181	1			T2	6		T3	3		T9	2
valid_sources[0x57]	9653	1			T2	5		T3	6		T12	1
valid_sources[0x58]	9599	1			T2	6		T3	1		T11	1
valid_sources[0x59]	9683	1			T2	1		T3	4		T9	1
valid_sources[0x5a]	9402	1			T2	4		T3	8		T9	2
valid_sources[0x5b]	9021	1			T2	6		T3	5		T10	3
valid_sources[0x5c]	42425	1			T2	1		T3	14		T11	1
valid_sources[0x5d]	9603	1			T2	8		T3	5		T10	4
valid_sources[0x5e]	10410	1			T2	2		T3	2		T10	12
valid_sources[0x5f]	11932	1			T2	1		T9	2		T10	1
valid_sources[0x60]	9909	1			T2	10		T3	3		T9	6
valid_sources[0x61]	9986	1			T2	7		T3	1		T10	11
valid_sources[0x62]	9670	1			T2	3		T3	2		T10	2
valid_sources[0x63]	9780	1			T2	2		T3	2		T10	23
valid_sources[0x64]	9536	1			T2	11		T3	1		T9	2
valid_sources[0x65]	12765	1			T2	4		T3	5		T11	1
valid_sources[0x66]	9737	1			T9	1		T10	8		T12	5
valid_sources[0x67]	9761	1			T2	4		T3	5		T9	2
valid_sources[0x68]	9413	1			T2	6		T3	2		T10	4
valid_sources[0x69]	9757	1			T2	5		T3	4		T9	1
valid_sources[0x6a]	10263	1			T2	8		T3	3		T9	1
valid_sources[0x6b]	9841	1			T2	3		T3	2		T10	1
valid_sources[0x6c]	11721	1			T2	7		T3	2		T12	10
valid_sources[0x6d]	9967	1			T10	2		T11	1		T12	7
valid_sources[0x6e]	10069	1			T2	6		T3	2		T9	5
valid_sources[0x6f]	10220	1			T2	11		T3	4		T9	1
valid_sources[0x70]	9604	1			T2	8		T3	3		T10	3
valid_sources[0x71]	15604	1			T2	2		T3	1		T10	1
valid_sources[0x72]	9419	1			T2	2		T3	2		T9	1
valid_sources[0x73]	9491	1			T2	11		T3	3		T9	1
valid_sources[0x74]	10980	1			T3	4		T9	1		T11	1
valid_sources[0x75]	10780	1			T2	3		T9	1		T10	1
valid_sources[0x76]	12851	1			T2	3		T3	2		T10	4
valid_sources[0x77]	14588	1			T2	2		T3	3		T11	4
valid_sources[0x78]	9597	1			T2	5		T3	4		T9	2
valid_sources[0x79]	10268	1			T2	1		T3	2		T10	6
valid_sources[0x7a]	9305	1			T2	1		T3	5		T10	6
valid_sources[0x7b]	10738	1			T9	2		T10	4		T11	2
valid_sources[0x7c]	9334	1			T2	1		T3	4		T10	2
valid_sources[0x7d]	9625	1			T2	3		T10	11		T12	4
valid_sources[0x7e]	9755	1			T2	2		T3	4		T11	3
valid_sources[0x7f]	9983	1			T2	5		T3	5		T9	1
valid_sources[0x80]	11054	1			T2	17		T3	1		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1490568

1

T1

757

T2

369

T3

143

values[0x0]

all_enables

biggest_size

141576

1

T1

304

T2

205

T3

150

values[0x1]

all_enables

biggest_size

140463

1

T1

285

T2

223

T3

165