Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	102076439	15897	0	0
claim_transition_if_regwen_rd_A	102076439	1340	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102076439	15897	0	0
T79	259797	3	0	0
T80	4314	0	0	0
T92	0	3	0	0
T93	0	3	0	0
T102	0	17	0	0
T106	0	4	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	29320	0	0	0
T150	76029	0	0	0
T151	31488	0	0	0
T152	30664	0	0	0
T153	21361	0	0	0
T154	21000	0	0	0
T155	49151	0	0	0
T156	32969	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102076439	1340	0	0
T108	0	39	0	0
T113	0	14	0	0
T115	0	80	0	0
T117	0	39	0	0
T124	0	35	0	0
T144	482477	1	0	0
T145	270764	0	0	0
T146	205765	0	0	0
T157	0	8	0	0
T158	0	9	0	0
T159	0	12	0	0
T160	0	3	0	0
T161	1452	0	0	0
T162	33267	0	0	0
T163	40752	0	0	0
T164	400124	0	0	0
T165	20215	0	0	0
T166	584362	0	0	0
T167	45591	0	0	0