Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1875903	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2110536

1

T1

970

T2

102

T3

16724

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3623668	1			T1	1096		T2	96		T3	31262
values[0x0]	180662	1			T1	231		T2	23		T3	674
values[0x1]	182109	1			T1	257		T2	41		T3	670

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1490775	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2495664

1

T1

1110

T2

114

T3

19909

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13456	1			T1	10		T4	2		T13	5
valid_sources[0x01]	13407	1			T1	5		T4	2		T13	5
valid_sources[0x02]	13707	1			T1	1		T4	2		T13	4
valid_sources[0x03]	13646	1			T1	8		T4	1		T13	6
valid_sources[0x04]	18468	1			T1	1		T13	4		T20	20
valid_sources[0x05]	13594	1			T1	4		T4	1		T13	5
valid_sources[0x06]	13330	1			T1	4		T4	2		T13	2
valid_sources[0x07]	13512	1			T1	6		T13	4		T20	26
valid_sources[0x08]	13581	1			T1	8		T13	5		T20	5
valid_sources[0x09]	46822	1			T1	14		T3	32487		T4	1
valid_sources[0x0a]	32681	1			T1	3		T13	2		T14	7
valid_sources[0x0b]	13762	1			T1	4		T4	1		T13	2
valid_sources[0x0c]	15140	1			T1	3		T13	4		T14	5
valid_sources[0x0d]	13798	1			T1	11		T4	2		T14	11
valid_sources[0x0e]	13788	1			T1	3		T4	1		T13	3
valid_sources[0x0f]	13601	1			T1	3		T3	17		T13	7
valid_sources[0x10]	13455	1			T1	6		T13	2		T20	7
valid_sources[0x11]	13998	1			T1	6		T12	26		T4	1
valid_sources[0x12]	13563	1			T1	5		T4	2		T13	2
valid_sources[0x13]	13834	1			T1	6		T4	2		T13	6
valid_sources[0x14]	14434	1			T1	2		T13	4		T20	8
valid_sources[0x15]	18098	1			T1	3		T4	1		T13	3
valid_sources[0x16]	13641	1			T1	5		T13	4		T20	10
valid_sources[0x17]	15333	1			T1	4		T3	17		T13	5
valid_sources[0x18]	16047	1			T1	6		T4	2		T13	6
valid_sources[0x19]	14302	1			T1	8		T4	2		T13	3
valid_sources[0x1a]	13161	1			T1	8		T4	1		T13	1
valid_sources[0x1b]	14624	1			T1	6		T4	2		T13	7
valid_sources[0x1c]	14411	1			T1	9		T13	2		T14	4
valid_sources[0x1d]	12985	1			T1	7		T4	3		T13	4
valid_sources[0x1e]	13314	1			T1	7		T13	4		T20	11
valid_sources[0x1f]	14402	1			T1	10		T4	1		T13	5
valid_sources[0x20]	24804	1			T1	4		T4	1		T13	6
valid_sources[0x21]	15050	1			T1	2		T13	7		T20	11
valid_sources[0x22]	13448	1			T1	6		T4	1		T13	6
valid_sources[0x23]	13821	1			T1	6		T4	2		T13	5
valid_sources[0x24]	13952	1			T1	3		T4	1		T13	1
valid_sources[0x25]	13861	1			T1	4		T13	6		T14	23
valid_sources[0x26]	13886	1			T1	8		T4	1		T13	8
valid_sources[0x27]	13674	1			T1	7		T4	2		T13	6
valid_sources[0x28]	15311	1			T1	4		T13	5		T20	4
valid_sources[0x29]	16405	1			T1	7		T13	10		T20	16
valid_sources[0x2a]	14502	1			T1	2		T13	4		T14	2
valid_sources[0x2b]	14139	1			T1	10		T13	3		T14	4
valid_sources[0x2c]	13167	1			T1	4		T4	1		T13	3
valid_sources[0x2d]	13119	1			T1	12		T13	9		T14	10
valid_sources[0x2e]	27509	1			T1	10		T13	3		T14	11
valid_sources[0x2f]	13558	1			T1	6		T13	1		T14	5
valid_sources[0x30]	15060	1			T1	6		T13	2		T14	1
valid_sources[0x31]	16644	1			T1	2		T4	2		T13	6
valid_sources[0x32]	13680	1			T1	8		T13	5		T20	28
valid_sources[0x33]	14236	1			T1	3		T13	2		T14	26
valid_sources[0x34]	13979	1			T1	5		T4	1		T13	7
valid_sources[0x35]	13786	1			T1	3		T13	3		T20	7
valid_sources[0x36]	25283	1			T1	10		T13	3		T20	6
valid_sources[0x37]	13667	1			T1	4		T13	8		T14	3
valid_sources[0x38]	15139	1			T1	3		T13	7		T14	2
valid_sources[0x39]	13925	1			T1	5		T4	1		T13	5
valid_sources[0x3a]	13949	1			T1	7		T13	5		T20	13
valid_sources[0x3b]	14741	1			T1	11		T4	2		T13	7
valid_sources[0x3c]	13415	1			T1	10		T4	1		T13	5
valid_sources[0x3d]	19871	1			T1	5		T4	1		T13	13
valid_sources[0x3e]	17353	1			T1	1		T13	2		T14	5
valid_sources[0x3f]	19078	1			T1	1		T13	4		T20	2
valid_sources[0x40]	17011	1			T1	13		T13	2		T14	25
valid_sources[0x41]	14949	1			T1	9		T13	4		T14	8
valid_sources[0x42]	13668	1			T1	7		T4	1		T13	4
valid_sources[0x43]	14267	1			T1	4		T13	3		T20	4
valid_sources[0x44]	20579	1			T1	8		T4	1		T13	7
valid_sources[0x45]	13636	1			T1	8		T4	2		T13	3
valid_sources[0x46]	14781	1			T1	5		T4	1		T13	4
valid_sources[0x47]	13448	1			T1	2		T3	17		T13	11
valid_sources[0x48]	15392	1			T1	9		T13	2		T14	1
valid_sources[0x49]	13749	1			T1	7		T13	4		T14	6
valid_sources[0x4a]	14462	1			T1	11		T13	4		T20	10
valid_sources[0x4b]	13475	1			T1	5		T4	1		T13	3
valid_sources[0x4c]	15387	1			T1	2		T13	4		T20	4
valid_sources[0x4d]	13752	1			T1	2		T4	1		T13	2
valid_sources[0x4e]	15432	1			T1	7		T4	1		T13	2
valid_sources[0x4f]	52704	1			T1	8		T13	8		T14	9
valid_sources[0x50]	17047	1			T1	4		T13	6		T14	3
valid_sources[0x51]	13733	1			T1	2		T13	10		T14	27
valid_sources[0x52]	12765	1			T1	6		T4	1		T13	4
valid_sources[0x53]	30412	1			T1	2		T4	3		T13	5
valid_sources[0x54]	15469	1			T1	4		T13	3		T14	2
valid_sources[0x55]	14996	1			T1	5		T4	1		T13	3
valid_sources[0x56]	13985	1			T1	6		T13	5		T20	9
valid_sources[0x57]	21218	1			T1	8		T13	10		T14	5
valid_sources[0x58]	13349	1			T1	14		T3	17		T4	1
valid_sources[0x59]	14038	1			T1	7		T13	6		T14	13
valid_sources[0x5a]	13840	1			T1	6		T4	1		T13	7
valid_sources[0x5b]	13083	1			T1	5		T4	2		T13	10
valid_sources[0x5c]	13780	1			T1	8		T4	1		T13	4
valid_sources[0x5d]	14157	1			T1	4		T4	1		T13	6
valid_sources[0x5e]	14268	1			T1	6		T13	5		T14	7
valid_sources[0x5f]	13790	1			T1	6		T4	2		T13	5
valid_sources[0x60]	14847	1			T1	3		T13	4		T20	9
valid_sources[0x61]	14347	1			T1	3		T13	5		T14	14
valid_sources[0x62]	13655	1			T1	9		T13	5		T14	7
valid_sources[0x63]	14667	1			T1	10		T13	3		T14	8
valid_sources[0x64]	15455	1			T1	13		T13	8		T14	1
valid_sources[0x65]	13330	1			T1	5		T4	1		T13	3
valid_sources[0x66]	13588	1			T1	7		T4	1		T13	3
valid_sources[0x67]	27008	1			T1	1		T13	8		T14	5
valid_sources[0x68]	16365	1			T1	6		T4	2		T13	1
valid_sources[0x69]	14202	1			T1	2		T4	1		T13	4
valid_sources[0x6a]	14203	1			T1	8		T13	4		T20	5
valid_sources[0x6b]	15487	1			T1	5		T13	4		T20	5
valid_sources[0x6c]	13710	1			T1	7		T4	2		T13	5
valid_sources[0x6d]	13406	1			T1	6		T4	1		T13	9
valid_sources[0x6e]	13336	1			T1	7		T13	3		T14	2
valid_sources[0x6f]	13602	1			T1	10		T4	1		T13	8
valid_sources[0x70]	13773	1			T1	9		T4	1		T13	3
valid_sources[0x71]	13809	1			T1	7		T13	7		T20	12
valid_sources[0x72]	15468	1			T1	1		T4	1		T13	5
valid_sources[0x73]	13473	1			T1	5		T4	1		T13	5
valid_sources[0x74]	20090	1			T1	4		T13	4		T14	5
valid_sources[0x75]	13952	1			T1	7		T4	1		T13	2
valid_sources[0x76]	13614	1			T1	11		T4	1		T13	5
valid_sources[0x77]	13769	1			T1	6		T4	1		T13	8
valid_sources[0x78]	15609	1			T1	11		T4	1		T13	9
valid_sources[0x79]	13482	1			T1	10		T13	4		T14	2
valid_sources[0x7a]	13263	1			T1	7		T4	1		T13	4
valid_sources[0x7b]	13539	1			T1	6		T4	1		T13	6
valid_sources[0x7c]	13420	1			T1	7		T4	1		T13	2
valid_sources[0x7d]	13872	1			T1	9		T4	1		T13	5
valid_sources[0x7e]	13949	1			T1	4		T4	1		T13	3
valid_sources[0x7f]	13870	1			T1	8		T13	4		T14	22
valid_sources[0x80]	13248	1			T1	11		T13	5		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1797602

1

T1

552

T2

46

T3

15548

values[0x0]

all_enables

biggest_size

156607

1

T1

195

T2

21

T3

595

values[0x1]

all_enables

biggest_size

156327

1

T1

223

T2

35

T3

581