Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	119372150	14128	0	0
claim_transition_if_regwen_rd_A	119372150	1383	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119372150	14128	0	0
T11	114052	5	0	0
T21	18862	0	0	0
T23	408813	3	0	0
T24	250592	0	0	0
T25	0	1	0	0
T45	0	3	0	0
T54	0	2	0	0
T56	5738	0	0	0
T57	3963	0	0	0
T74	28852	0	0	0
T76	2179	0	0	0
T90	0	1	0	0
T91	0	10	0	0
T131	0	6	0	0
T132	0	3	0	0
T133	0	9	0	0
T134	30485	0	0	0
T135	6008	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119372150	1383	0	0
T45	860612	7	0	0
T46	34006	0	0	0
T47	48572	0	0	0
T54	370786	0	0	0
T78	1649	0	0	0
T90	0	5	0	0
T102	0	18	0	0
T103	0	26	0	0
T136	0	2	0	0
T137	0	13	0	0
T138	0	2	0	0
T139	0	4	0	0
T140	0	7	0	0
T141	0	2	0	0
T142	4732	0	0	0
T143	34356	0	0	0
T144	1648	0	0	0
T145	5581	0	0	0
T146	17672	0	0	0