Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1926092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2167808

1

T1

645

T2

936

T3

166

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3712146	1			T1	580		T2	880		T3	151
values[0x0]	190555	1			T1	233		T2	277		T3	60
values[0x1]	191199	1			T1	183		T2	307		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1530285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2563615

1

T1

724

T2

1066

T3

182

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10862	1			T2	9		T4	12		T5	32
valid_sources[0x01]	11940	1			T2	8		T4	12		T5	21
valid_sources[0x02]	11076	1			T2	10		T4	9		T5	51
valid_sources[0x03]	11568	1			T2	1		T3	2		T4	8
valid_sources[0x04]	10766	1			T2	6		T3	4		T4	3
valid_sources[0x05]	10878	1			T2	11		T3	2		T4	10
valid_sources[0x06]	11157	1			T2	1		T3	1		T4	16
valid_sources[0x07]	11615	1			T2	2		T3	1		T4	10
valid_sources[0x08]	94640	1			T2	1		T3	1		T4	13
valid_sources[0x09]	13051	1			T2	11		T4	12		T5	27
valid_sources[0x0a]	10927	1			T2	6		T4	2		T5	33
valid_sources[0x0b]	10891	1			T2	4		T4	9		T5	33
valid_sources[0x0c]	10746	1			T2	4		T3	1		T4	12
valid_sources[0x0d]	15492	1			T2	9		T3	3		T4	15
valid_sources[0x0e]	11461	1			T1	213		T3	3		T4	11
valid_sources[0x0f]	11094	1			T2	4		T3	2		T4	9
valid_sources[0x10]	10852	1			T2	5		T4	6		T5	26
valid_sources[0x11]	11854	1			T2	2		T4	8		T5	17
valid_sources[0x12]	23672	1			T2	20		T3	2		T4	11
valid_sources[0x13]	11371	1			T4	10		T5	29		T9	9
valid_sources[0x14]	10852	1			T4	7		T5	24		T9	6
valid_sources[0x15]	18881	1			T2	9		T4	7		T5	31
valid_sources[0x16]	10989	1			T2	10		T3	1		T4	12
valid_sources[0x17]	11619	1			T2	3		T3	1		T4	9
valid_sources[0x18]	11038	1			T2	7		T3	2		T4	9
valid_sources[0x19]	11246	1			T3	3		T4	12		T5	33
valid_sources[0x1a]	11250	1			T3	1		T4	13		T5	18
valid_sources[0x1b]	11145	1			T2	5		T4	9		T5	22
valid_sources[0x1c]	12983	1			T1	159		T2	1		T3	1
valid_sources[0x1d]	63135	1			T2	7		T3	1		T4	9
valid_sources[0x1e]	11720	1			T2	8		T4	6		T5	28
valid_sources[0x1f]	23390	1			T2	10		T3	2		T4	10
valid_sources[0x20]	11940	1			T2	1		T4	5		T5	22
valid_sources[0x21]	11598	1			T2	2		T3	1		T4	13
valid_sources[0x22]	11454	1			T2	11		T4	10		T5	34
valid_sources[0x23]	10960	1			T4	7		T5	30		T9	4
valid_sources[0x24]	71105	1			T2	2		T3	1		T4	12
valid_sources[0x25]	11169	1			T2	14		T3	2		T4	16
valid_sources[0x26]	12505	1			T2	5		T3	1		T4	13
valid_sources[0x27]	11577	1			T2	2		T4	6		T5	18
valid_sources[0x28]	11059	1			T2	2		T4	12		T5	18
valid_sources[0x29]	11456	1			T2	17		T4	8		T5	12
valid_sources[0x2a]	11687	1			T1	11		T2	2		T3	3
valid_sources[0x2b]	19679	1			T2	4		T4	8		T5	22
valid_sources[0x2c]	10766	1			T2	15		T3	1		T4	8
valid_sources[0x2d]	13866	1			T2	2		T3	2		T4	9
valid_sources[0x2e]	11394	1			T3	1		T4	8		T5	28
valid_sources[0x2f]	11652	1			T2	9		T4	10		T5	28
valid_sources[0x30]	11546	1			T2	1		T4	13		T5	19
valid_sources[0x31]	12135	1			T2	1		T3	1		T4	7
valid_sources[0x32]	10782	1			T2	8		T3	3		T4	12
valid_sources[0x33]	10701	1			T2	13		T3	1		T4	8
valid_sources[0x34]	26108	1			T2	5		T4	19		T5	23
valid_sources[0x35]	10867	1			T2	6		T3	2		T4	12
valid_sources[0x36]	10931	1			T3	1		T4	11		T5	23
valid_sources[0x37]	10820	1			T4	7		T5	36		T9	1
valid_sources[0x38]	16133	1			T3	2		T4	14		T5	37
valid_sources[0x39]	10605	1			T2	4		T4	11		T5	22
valid_sources[0x3a]	12789	1			T2	2		T4	8		T5	23
valid_sources[0x3b]	11134	1			T1	55		T2	6		T3	2
valid_sources[0x3c]	10719	1			T2	9		T3	2		T4	9
valid_sources[0x3d]	11091	1			T2	1		T3	1		T4	7
valid_sources[0x3e]	12855	1			T3	1		T4	8		T5	32
valid_sources[0x3f]	11328	1			T2	11		T3	1		T4	12
valid_sources[0x40]	12445	1			T2	3		T4	6		T5	32
valid_sources[0x41]	11215	1			T2	6		T3	2		T4	14
valid_sources[0x42]	11066	1			T2	25		T3	2		T4	7
valid_sources[0x43]	10923	1			T2	2		T3	2		T4	8
valid_sources[0x44]	11277	1			T2	10		T4	9		T5	36
valid_sources[0x45]	11282	1			T2	13		T3	1		T4	8
valid_sources[0x46]	11270	1			T2	1		T3	1		T4	7
valid_sources[0x47]	12224	1			T2	9		T3	1		T4	10
valid_sources[0x48]	11800	1			T4	6		T5	36		T9	4
valid_sources[0x49]	10797	1			T2	1		T3	1		T4	6
valid_sources[0x4a]	12384	1			T1	27		T2	4		T3	1
valid_sources[0x4b]	11083	1			T2	10		T4	14		T5	27
valid_sources[0x4c]	11211	1			T2	6		T3	2		T4	8
valid_sources[0x4d]	10829	1			T2	4		T3	2		T4	10
valid_sources[0x4e]	11294	1			T2	13		T3	1		T4	11
valid_sources[0x4f]	12610	1			T2	14		T4	11		T5	24
valid_sources[0x50]	11282	1			T2	3		T4	12		T5	22
valid_sources[0x51]	10877	1			T2	5		T3	1		T4	7
valid_sources[0x52]	21063	1			T2	8		T4	6		T5	26
valid_sources[0x53]	10892	1			T2	11		T3	1		T4	16
valid_sources[0x54]	10435	1			T2	9		T4	8		T5	25
valid_sources[0x55]	20940	1			T2	12		T3	1		T4	6
valid_sources[0x56]	11672	1			T2	2		T3	1		T4	7
valid_sources[0x57]	11634	1			T2	2		T3	3		T4	5
valid_sources[0x58]	11786	1			T2	3		T3	2		T4	12
valid_sources[0x59]	11915	1			T2	5		T4	6		T5	18
valid_sources[0x5a]	10920	1			T2	1		T4	2		T5	17
valid_sources[0x5b]	11122	1			T2	5		T3	1		T4	9
valid_sources[0x5c]	20426	1			T2	6		T3	1		T4	6
valid_sources[0x5d]	12017	1			T1	20		T2	2		T4	9
valid_sources[0x5e]	11012	1			T2	3		T4	11		T5	25
valid_sources[0x5f]	11133	1			T2	3		T3	2		T4	11
valid_sources[0x60]	11451	1			T4	14		T5	24		T9	5
valid_sources[0x61]	11775	1			T2	26		T4	11		T5	28
valid_sources[0x62]	32642	1			T2	6		T3	2		T4	9
valid_sources[0x63]	11305	1			T2	10		T3	2		T4	9
valid_sources[0x64]	15692	1			T2	1		T4	4		T5	36
valid_sources[0x65]	10588	1			T2	10		T3	1		T4	15
valid_sources[0x66]	122165	1			T2	4		T3	1		T4	6
valid_sources[0x67]	11352	1			T2	7		T3	2		T4	13
valid_sources[0x68]	11525	1			T2	9		T3	2		T4	11
valid_sources[0x69]	10912	1			T4	9		T5	33		T9	12
valid_sources[0x6a]	10380	1			T2	7		T3	2		T4	7
valid_sources[0x6b]	10884	1			T2	1		T4	12		T5	24
valid_sources[0x6c]	10936	1			T2	12		T3	2		T4	12
valid_sources[0x6d]	10783	1			T1	18		T3	1		T4	9
valid_sources[0x6e]	14708	1			T2	2		T4	6		T5	22
valid_sources[0x6f]	11250	1			T2	9		T3	1		T4	8
valid_sources[0x70]	10683	1			T2	3		T4	4		T5	16
valid_sources[0x71]	11153	1			T2	7		T4	6		T5	14
valid_sources[0x72]	11967	1			T2	7		T3	3		T4	9
valid_sources[0x73]	15407	1			T2	8		T4	5		T5	25
valid_sources[0x74]	11277	1			T2	1		T4	12		T5	37
valid_sources[0x75]	12256	1			T2	10		T4	10		T5	16
valid_sources[0x76]	10866	1			T2	11		T3	3		T4	9
valid_sources[0x77]	12532	1			T3	2		T4	10		T5	20
valid_sources[0x78]	11129	1			T2	10		T3	2		T4	7
valid_sources[0x79]	10880	1			T2	1		T3	3		T4	8
valid_sources[0x7a]	10494	1			T2	8		T4	7		T5	28
valid_sources[0x7b]	11237	1			T2	3		T4	14		T5	43
valid_sources[0x7c]	10607	1			T2	6		T3	1		T4	11
valid_sources[0x7d]	11473	1			T3	1		T4	5		T5	18
valid_sources[0x7e]	10900	1			T2	15		T3	1		T4	6
valid_sources[0x7f]	10805	1			T2	21		T4	10		T5	33
valid_sources[0x80]	11029	1			T2	4		T3	1		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1838873

1

T1

276

T2

430

T3

76

values[0x0]

all_enables

biggest_size

165132

1

T1

208

T2

249

T3

44

values[0x1]

all_enables

biggest_size

163803

1

T1

161

T2

257

T3

46