Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	123351945	13933	0	0
claim_transition_if_regwen_rd_A	123351945	1344	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123351945	13933	0	0
T5	984284	1	0	0
T8	560168	3	0	0
T9	27052	0	0	0
T10	5745	0	0	0
T11	1058	0	0	0
T12	19500	0	0	0
T13	897	0	0	0
T14	0	1	0	0
T15	227415	1	0	0
T17	7414	0	0	0
T35	0	14	0	0
T36	0	8	0	0
T38	24222	0	0	0
T66	0	2	0	0
T130	0	8	0	0
T131	0	15	0	0
T132	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123351945	1344	0	0
T96	0	15	0	0
T100	0	45	0	0
T104	0	29	0	0
T133	453040	6	0	0
T134	0	6	0	0
T135	0	6	0	0
T136	0	1	0	0
T137	0	6	0	0
T138	0	22	0	0
T139	0	14	0	0
T140	176780	0	0	0
T141	25814	0	0	0
T142	32348	0	0	0
T143	35021	0	0	0
T144	1454	0	0	0
T145	4106	0	0	0
T146	559135	0	0	0
T147	14100	0	0	0
T148	3866	0	0	0