Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2061326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2297843

1

T1

836

T2

12

T3

776

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3990152	1			T1	835		T3	563		T4	544
values[0x0]	183347	1			T1	248		T2	25		T3	287
values[0x1]	185670	1			T1	240		T2	27		T3	297

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1639052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2720117

1

T1

950

T2

18

T3

848

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14251	1			T1	6		T3	4		T15	3
valid_sources[0x01]	12539	1			T1	3		T3	3		T32	3
valid_sources[0x02]	12304	1			T1	6		T3	8		T7	1
valid_sources[0x03]	11914	1			T1	3		T3	4		T6	1
valid_sources[0x04]	12207	1			T1	2		T3	7		T12	1
valid_sources[0x05]	11947	1			T1	5		T3	11		T12	1
valid_sources[0x06]	202446	1			T1	3		T3	6		T32	5
valid_sources[0x07]	12257	1			T1	6		T3	7		T6	2
valid_sources[0x08]	18142	1			T1	6		T3	10		T6	1
valid_sources[0x09]	18199	1			T1	5		T3	4		T23	1
valid_sources[0x0a]	12552	1			T1	7		T3	6		T15	8
valid_sources[0x0b]	12798	1			T1	3		T15	10		T7	5
valid_sources[0x0c]	13977	1			T1	11		T3	3		T15	37
valid_sources[0x0d]	12796	1			T1	4		T2	4		T3	5
valid_sources[0x0e]	16810	1			T1	2		T3	9		T15	9
valid_sources[0x0f]	12686	1			T1	7		T3	7		T6	4
valid_sources[0x10]	11922	1			T1	7		T7	3		T32	6
valid_sources[0x11]	12001	1			T1	12		T3	4		T15	14
valid_sources[0x12]	13789	1			T1	9		T3	4		T6	1
valid_sources[0x13]	12228	1			T1	12		T2	1		T3	5
valid_sources[0x14]	26148	1			T1	6		T2	1		T3	3
valid_sources[0x15]	11945	1			T1	3		T3	7		T15	4
valid_sources[0x16]	12518	1			T1	4		T3	4		T15	3
valid_sources[0x17]	13015	1			T1	6		T3	5		T15	40
valid_sources[0x18]	25831	1			T1	5		T3	8		T15	2
valid_sources[0x19]	13357	1			T1	1		T3	5		T15	10
valid_sources[0x1a]	34970	1			T1	6		T3	3		T15	7
valid_sources[0x1b]	11960	1			T1	6		T3	5		T12	1
valid_sources[0x1c]	12788	1			T1	8		T3	4		T12	1
valid_sources[0x1d]	11781	1			T1	5		T3	7		T15	5
valid_sources[0x1e]	28967	1			T1	9		T2	1		T3	5
valid_sources[0x1f]	12501	1			T1	3		T3	8		T15	4
valid_sources[0x20]	12907	1			T1	3		T3	4		T15	6
valid_sources[0x21]	15107	1			T1	4		T3	1		T15	5
valid_sources[0x22]	12447	1			T1	5		T3	5		T12	1
valid_sources[0x23]	15159	1			T1	5		T3	6		T6	1
valid_sources[0x24]	83335	1			T1	3		T2	1		T3	7
valid_sources[0x25]	11917	1			T1	5		T3	2		T15	3
valid_sources[0x26]	12329	1			T1	2		T3	10		T7	2
valid_sources[0x27]	14400	1			T1	2		T2	1		T3	8
valid_sources[0x28]	28177	1			T1	5		T3	3		T12	1
valid_sources[0x29]	11495	1			T1	7		T3	8		T15	5
valid_sources[0x2a]	31950	1			T1	6		T3	4		T15	51
valid_sources[0x2b]	11772	1			T1	4		T3	3		T7	1
valid_sources[0x2c]	13461	1			T1	7		T3	7		T15	14
valid_sources[0x2d]	16412	1			T1	7		T3	3		T15	16
valid_sources[0x2e]	12467	1			T1	10		T3	5		T15	18
valid_sources[0x2f]	12101	1			T1	7		T3	4		T15	12
valid_sources[0x30]	17254	1			T1	4		T3	4		T15	7
valid_sources[0x31]	12007	1			T1	7		T3	4		T7	4
valid_sources[0x32]	14570	1			T1	5		T3	7		T15	33
valid_sources[0x33]	12095	1			T1	3		T2	1		T3	4
valid_sources[0x34]	12257	1			T1	6		T3	4		T15	19
valid_sources[0x35]	12157	1			T1	3		T3	4		T6	1
valid_sources[0x36]	14460	1			T1	7		T3	6		T12	1
valid_sources[0x37]	12102	1			T1	4		T3	6		T6	1
valid_sources[0x38]	12331	1			T1	7		T3	3		T12	1
valid_sources[0x39]	12234	1			T1	6		T3	9		T15	12
valid_sources[0x3a]	11373	1			T1	3		T3	5		T7	4
valid_sources[0x3b]	15342	1			T1	5		T2	1		T3	3
valid_sources[0x3c]	12014	1			T1	3		T3	6		T12	2
valid_sources[0x3d]	11767	1			T1	9		T3	3		T7	1
valid_sources[0x3e]	12517	1			T1	6		T3	4		T15	1
valid_sources[0x3f]	11780	1			T1	9		T3	5		T15	26
valid_sources[0x40]	12150	1			T1	8		T3	4		T15	33
valid_sources[0x41]	12274	1			T1	5		T2	2		T3	6
valid_sources[0x42]	12091	1			T1	6		T3	3		T6	1
valid_sources[0x43]	12414	1			T1	8		T3	5		T15	18
valid_sources[0x44]	13268	1			T1	10		T3	3		T15	10
valid_sources[0x45]	12634	1			T1	3		T3	1		T15	1
valid_sources[0x46]	12848	1			T1	3		T3	6		T7	4
valid_sources[0x47]	12361	1			T1	2		T3	4		T15	22
valid_sources[0x48]	12656	1			T1	6		T3	3		T15	8
valid_sources[0x49]	17371	1			T1	4		T3	7		T15	10
valid_sources[0x4a]	11725	1			T1	5		T3	6		T15	1
valid_sources[0x4b]	12154	1			T1	7		T3	3		T15	24
valid_sources[0x4c]	15034	1			T1	4		T3	5		T15	4
valid_sources[0x4d]	60519	1			T1	9		T2	1		T3	2
valid_sources[0x4e]	12386	1			T1	4		T3	4		T15	12
valid_sources[0x4f]	13521	1			T1	4		T3	3		T15	1
valid_sources[0x50]	12614	1			T1	8		T15	5		T7	1
valid_sources[0x51]	12258	1			T1	3		T3	4		T15	35
valid_sources[0x52]	12133	1			T1	5		T3	5		T15	16
valid_sources[0x53]	13180	1			T1	5		T3	4		T15	5
valid_sources[0x54]	125466	1			T1	2		T3	4		T15	7
valid_sources[0x55]	12668	1			T1	8		T3	4		T15	14
valid_sources[0x56]	12139	1			T1	3		T3	4		T7	2
valid_sources[0x57]	12148	1			T1	8		T3	2		T6	3
valid_sources[0x58]	14009	1			T1	4		T2	6		T3	6
valid_sources[0x59]	12028	1			T1	3		T3	6		T15	13
valid_sources[0x5a]	12773	1			T1	3		T3	3		T6	2
valid_sources[0x5b]	11778	1			T1	7		T3	8		T15	9
valid_sources[0x5c]	12028	1			T1	6		T3	4		T15	14
valid_sources[0x5d]	12819	1			T1	5		T3	2		T15	21
valid_sources[0x5e]	12523	1			T1	5		T3	4		T15	15
valid_sources[0x5f]	12926	1			T1	8		T2	1		T3	2
valid_sources[0x60]	11944	1			T1	5		T3	3		T7	1
valid_sources[0x61]	15074	1			T1	7		T3	4		T15	11
valid_sources[0x62]	13658	1			T1	3		T3	8		T6	1
valid_sources[0x63]	11710	1			T1	7		T3	4		T15	21
valid_sources[0x64]	23182	1			T1	6		T3	8		T12	1
valid_sources[0x65]	13576	1			T1	5		T3	5		T7	1
valid_sources[0x66]	14033	1			T1	2		T2	1		T3	5
valid_sources[0x67]	12527	1			T1	5		T3	5		T15	22
valid_sources[0x68]	13064	1			T1	3		T2	1		T3	8
valid_sources[0x69]	12332	1			T1	3		T2	1		T3	8
valid_sources[0x6a]	12362	1			T1	7		T2	1		T3	8
valid_sources[0x6b]	12452	1			T1	4		T2	2		T3	7
valid_sources[0x6c]	12774	1			T1	3		T3	2		T6	1
valid_sources[0x6d]	12456	1			T1	5		T3	8		T15	9
valid_sources[0x6e]	12171	1			T1	5		T3	3		T15	3
valid_sources[0x6f]	15434	1			T1	6		T3	10		T15	19
valid_sources[0x70]	12548	1			T1	8		T3	1		T7	1
valid_sources[0x71]	12640	1			T1	7		T3	4		T6	1
valid_sources[0x72]	12877	1			T1	4		T3	2		T15	12
valid_sources[0x73]	12022	1			T1	1		T3	6		T15	28
valid_sources[0x74]	13417	1			T1	2		T2	1		T3	2
valid_sources[0x75]	12867	1			T1	5		T3	3		T7	3
valid_sources[0x76]	12258	1			T1	7		T3	4		T12	1
valid_sources[0x77]	15643	1			T1	6		T3	6		T15	16
valid_sources[0x78]	14239	1			T1	10		T3	2		T4	1008
valid_sources[0x79]	13491	1			T1	5		T3	1		T15	9
valid_sources[0x7a]	12722	1			T1	4		T3	6		T7	1
valid_sources[0x7b]	12396	1			T1	4		T3	6		T15	9
valid_sources[0x7c]	12421	1			T1	5		T3	1		T15	2
valid_sources[0x7d]	12841	1			T1	11		T3	7		T15	3
valid_sources[0x7e]	59574	1			T1	2		T3	9		T15	11
valid_sources[0x7f]	14507	1			T1	1		T2	1		T3	3
valid_sources[0x80]	13307	1			T1	5		T2	2		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1980393

1

T1

417

T3

268

T4

271

values[0x0]

all_enables

biggest_size

158551

1

T1

211

T2

8

T3

244

values[0x1]

all_enables

biggest_size

158899

1

T1

208

T2

4

T3

264