Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112513517	14200	0	0
claim_transition_if_regwen_rd_A	112513517	1726	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112513517	14200	0	0
T8	107480	0	0	0
T9	31081	0	0	0
T17	255996	3	0	0
T18	41731	0	0	0
T20	147215	0	0	0
T21	81201	0	0	0
T22	725267	0	0	0
T35	13678	0	0	0
T36	0	1	0	0
T38	0	4	0	0
T39	0	5	0	0
T40	28019	0	0	0
T49	0	18	0	0
T129	0	6	0	0
T130	0	4	0	0
T131	0	8	0	0
T132	0	4	0	0
T133	0	7	0	0
T134	3425	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112513517	1726	0	0
T92	7429	4	0	0
T93	6220	51	0	0
T94	13116	39	0	0
T95	4591	13	0	0
T112	1898	9	0	0
T121	10753	45	0	0
T135	2506	10	0	0
T136	9501	11	0	0
T137	1981	14	0	0
T138	2731	50	0	0