Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1643326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1865773

1

T1

12

T2

5

T3

824

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3158600	1			T2	33		T3	592		T4	9284
values[0x0]	175186	1			T1	16		T2	5		T3	288
values[0x1]	175313	1			T1	22		T2	3		T3	328

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1304424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2204675

1

T1

14

T2

18

T3

918

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8749	1			T2	2		T3	11		T5	8
valid_sources[0x01]	8506	1			T2	1		T3	4		T4	17
valid_sources[0x02]	10495	1			T3	4		T5	15		T14	39
valid_sources[0x03]	8445	1			T3	1		T4	34		T5	7
valid_sources[0x04]	9320	1			T2	1		T3	17		T5	5
valid_sources[0x05]	8369	1			T3	5		T5	3		T14	29
valid_sources[0x06]	9094	1			T3	3		T5	4		T14	15
valid_sources[0x07]	9690	1			T3	6		T5	2		T14	28
valid_sources[0x08]	9180	1			T3	3		T5	2		T14	24
valid_sources[0x09]	10817	1			T3	6		T5	6		T14	26
valid_sources[0x0a]	10532	1			T3	7		T5	1		T14	49
valid_sources[0x0b]	8411	1			T3	1		T5	13		T14	34
valid_sources[0x0c]	9159	1			T3	7		T5	3		T14	12
valid_sources[0x0d]	10489	1			T3	6		T5	11		T14	21
valid_sources[0x0e]	11969	1			T3	4		T5	5		T14	16
valid_sources[0x0f]	12832	1			T3	6		T5	10		T14	32
valid_sources[0x10]	12177	1			T3	6		T5	12		T14	28
valid_sources[0x11]	18569	1			T3	4		T5	10		T14	5
valid_sources[0x12]	9734	1			T3	2		T5	6		T14	17
valid_sources[0x13]	8910	1			T3	3		T5	1		T14	10
valid_sources[0x14]	8852	1			T3	4		T5	6		T14	17
valid_sources[0x15]	11498	1			T3	7		T5	8		T14	8
valid_sources[0x16]	10595	1			T3	8		T5	17		T14	17
valid_sources[0x17]	9282	1			T3	7		T5	5		T14	32
valid_sources[0x18]	10727	1			T3	3		T5	4		T14	9
valid_sources[0x19]	10299	1			T3	2		T5	6		T14	31
valid_sources[0x1a]	9743	1			T3	8		T14	31		T15	1
valid_sources[0x1b]	8855	1			T5	8		T14	47		T18	2
valid_sources[0x1c]	9643	1			T3	1		T5	8		T14	11
valid_sources[0x1d]	10179	1			T3	5		T5	4		T14	29
valid_sources[0x1e]	8697	1			T3	8		T5	3		T14	22
valid_sources[0x1f]	8970	1			T3	7		T5	14		T14	13
valid_sources[0x20]	9461	1			T3	5		T5	5		T14	9
valid_sources[0x21]	12924	1			T3	4		T5	7		T14	12
valid_sources[0x22]	8415	1			T3	7		T5	3		T14	28
valid_sources[0x23]	11048	1			T3	1		T5	11		T14	17
valid_sources[0x24]	8260	1			T3	10		T5	3		T14	55
valid_sources[0x25]	8880	1			T3	2		T5	7		T14	24
valid_sources[0x26]	11400	1			T3	7		T5	3		T14	18
valid_sources[0x27]	9002	1			T3	5		T5	9		T14	12
valid_sources[0x28]	8963	1			T3	7		T5	5		T14	29
valid_sources[0x29]	9511	1			T3	2		T5	2		T14	6
valid_sources[0x2a]	8659	1			T3	8		T5	5		T14	9
valid_sources[0x2b]	23742	1			T3	5		T5	6		T14	16
valid_sources[0x2c]	9821	1			T3	6		T5	7		T14	31
valid_sources[0x2d]	8521	1			T3	8		T5	10		T14	19
valid_sources[0x2e]	9325	1			T3	5		T5	16		T14	27
valid_sources[0x2f]	10073	1			T3	4		T5	7		T14	11
valid_sources[0x30]	8907	1			T3	7		T5	11		T14	9
valid_sources[0x31]	10606	1			T3	6		T5	2		T14	20
valid_sources[0x32]	8897	1			T3	8		T5	6		T14	16
valid_sources[0x33]	51253	1			T2	1		T3	11		T5	6
valid_sources[0x34]	9438	1			T3	7		T5	9		T14	39
valid_sources[0x35]	10965	1			T2	2		T3	6		T5	10
valid_sources[0x36]	10761	1			T3	3		T5	5		T14	12
valid_sources[0x37]	11197	1			T3	5		T5	13		T14	19
valid_sources[0x38]	9294	1			T3	7		T5	3		T14	15
valid_sources[0x39]	9085	1			T3	6		T5	2		T14	57
valid_sources[0x3a]	9800	1			T3	3		T5	10		T14	20
valid_sources[0x3b]	9012	1			T3	2		T5	8		T14	13
valid_sources[0x3c]	8675	1			T3	8		T5	7		T14	41
valid_sources[0x3d]	9101	1			T2	1		T3	1		T5	6
valid_sources[0x3e]	9236	1			T3	6		T5	5		T14	11
valid_sources[0x3f]	9071	1			T3	3		T14	23		T15	2
valid_sources[0x40]	8901	1			T3	4		T5	5		T14	32
valid_sources[0x41]	8532	1			T3	6		T5	5		T14	27
valid_sources[0x42]	8864	1			T3	4		T5	9		T14	34
valid_sources[0x43]	8992	1			T3	4		T5	9		T14	30
valid_sources[0x44]	10288	1			T2	1		T3	2		T5	8
valid_sources[0x45]	10078	1			T2	2		T3	5		T5	4
valid_sources[0x46]	9330	1			T3	4		T5	3		T14	14
valid_sources[0x47]	49177	1			T3	5		T5	10		T14	20
valid_sources[0x48]	9033	1			T3	6		T5	5		T14	22
valid_sources[0x49]	8806	1			T3	7		T5	3		T14	22
valid_sources[0x4a]	11443	1			T3	8		T5	15		T14	33
valid_sources[0x4b]	13444	1			T3	1		T5	8		T14	23
valid_sources[0x4c]	10464	1			T3	1		T5	3		T14	13
valid_sources[0x4d]	26931	1			T2	2		T3	4		T5	3
valid_sources[0x4e]	8615	1			T3	6		T14	29		T15	4
valid_sources[0x4f]	11415	1			T3	6		T5	6		T14	18
valid_sources[0x50]	10785	1			T2	1		T3	3		T5	9
valid_sources[0x51]	9582	1			T3	2		T5	3		T14	10
valid_sources[0x52]	9884	1			T3	3		T5	4		T14	29
valid_sources[0x53]	20915	1			T3	8		T5	5		T14	24
valid_sources[0x54]	12586	1			T3	5		T5	1		T14	10
valid_sources[0x55]	8960	1			T3	3		T5	1		T14	43
valid_sources[0x56]	9433	1			T2	2		T3	5		T5	4
valid_sources[0x57]	9452	1			T2	1		T3	4		T5	8
valid_sources[0x58]	18637	1			T3	1		T4	9283		T5	5
valid_sources[0x59]	110364	1			T3	4		T5	9		T14	26
valid_sources[0x5a]	8691	1			T3	4		T5	2		T14	13
valid_sources[0x5b]	30214	1			T3	3		T5	5		T14	30
valid_sources[0x5c]	8625	1			T3	4		T5	6		T14	10
valid_sources[0x5d]	17459	1			T3	10		T14	9		T15	5
valid_sources[0x5e]	9236	1			T2	1		T3	10		T5	9
valid_sources[0x5f]	81124	1			T3	7		T5	4		T14	36
valid_sources[0x60]	53070	1			T3	8		T5	9		T14	32
valid_sources[0x61]	9277	1			T3	6		T5	6		T14	32
valid_sources[0x62]	9151	1			T3	6		T5	5		T14	30
valid_sources[0x63]	9926	1			T3	9		T5	4		T14	25
valid_sources[0x64]	9917	1			T5	14		T14	8		T15	1
valid_sources[0x65]	9014	1			T3	4		T5	9		T14	14
valid_sources[0x66]	9105	1			T3	9		T5	5		T14	43
valid_sources[0x67]	8703	1			T3	6		T5	6		T14	17
valid_sources[0x68]	12032	1			T3	9		T5	4		T14	31
valid_sources[0x69]	10889	1			T3	9		T5	26		T14	8
valid_sources[0x6a]	8954	1			T3	6		T5	14		T14	21
valid_sources[0x6b]	10790	1			T3	1		T5	4		T14	9
valid_sources[0x6c]	9093	1			T3	1		T5	3		T14	41
valid_sources[0x6d]	8780	1			T3	8		T5	9		T14	10
valid_sources[0x6e]	9035	1			T3	4		T5	14		T14	53
valid_sources[0x6f]	10694	1			T2	2		T3	3		T5	7
valid_sources[0x70]	8686	1			T3	4		T5	5		T14	17
valid_sources[0x71]	13294	1			T2	1		T3	1		T5	14
valid_sources[0x72]	11975	1			T3	5		T5	4		T14	22
valid_sources[0x73]	32536	1			T3	5		T5	11		T14	18
valid_sources[0x74]	51661	1			T3	2		T5	2		T14	46
valid_sources[0x75]	8501	1			T2	1		T3	5		T5	8
valid_sources[0x76]	8758	1			T3	4		T5	5		T14	27
valid_sources[0x77]	9761	1			T3	1		T5	2		T14	26
valid_sources[0x78]	9854	1			T3	9		T5	5		T14	20
valid_sources[0x79]	12814	1			T3	5		T5	8		T14	14
valid_sources[0x7a]	9152	1			T3	6		T14	18		T15	2
valid_sources[0x7b]	11980	1			T3	2		T5	8		T14	18
valid_sources[0x7c]	9871	1			T3	2		T5	13		T14	32
valid_sources[0x7d]	9063	1			T3	10		T5	17		T14	28
valid_sources[0x7e]	24398	1			T3	8		T5	4		T14	30
valid_sources[0x7f]	9985	1			T3	5		T5	5		T14	14
valid_sources[0x80]	8791	1			T2	1		T3	4		T5	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1563648

1

T3

288

T4

4622

T5

388

values[0x0]

all_enables

biggest_size

151912

1

T1

5

T2

3

T3

246

values[0x1]

all_enables

biggest_size

150213

1

T1

7

T2

2

T3

290