Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106931856	12877	0	0
claim_transition_if_regwen_rd_A	106931856	1247	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106931856	12877	0	0
T10	54763	0	0	0
T22	137105	1	0	0
T26	4026	0	0	0
T60	42345	0	0	0
T67	30706	0	0	0
T69	0	2	0	0
T91	17723	0	0	0
T92	39045	0	0	0
T99	0	2	0	0
T111	0	2	0	0
T114	0	8	0	0
T115	0	7	0	0
T154	0	3	0	0
T155	0	12	0	0
T156	0	5	0	0
T157	0	15	0	0
T158	8128	0	0	0
T159	737	0	0	0
T160	31711	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106931856	1247	0	0
T114	506100	0	0	0
T116	0	40	0	0
T120	0	3	0	0
T121	0	8	0	0
T132	0	5	0	0
T156	0	4	0	0
T161	238472	1	0	0
T162	0	5	0	0
T163	0	73	0	0
T164	0	7	0	0
T165	0	25	0	0
T166	68967	0	0	0
T167	2020	0	0	0
T168	45050	0	0	0
T169	38532	0	0	0
T170	33447	0	0	0
T171	97249	0	0	0
T172	24614	0	0	0
T173	2122	0	0	0