Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56247 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2158 | 
1 | 
 | 
 | 
T16 | 
14 | 
 | 
T17 | 
7 | 
 | 
T18 | 
38 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57633 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
772 | 
1 | 
 | 
 | 
T41 | 
20 | 
 | 
T23 | 
15 | 
 | 
T61 | 
16 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56394 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2011 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T9 | 
9 | 
 | 
T16 | 
16 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56347 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2058 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T9 | 
11 | 
 | 
T16 | 
13 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56292 | 
1 | 
 | 
 | 
T1 | 
11 | 
 | 
T2 | 
13 | 
 | 
T3 | 
2 | 
| auto[1] | 
2113 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
1 | 
 | 
T9 | 
10 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
53136 | 
1 | 
 | 
 | 
T1 | 
7 | 
 | 
T2 | 
7 | 
 | 
T3 | 
2 | 
| no_err_inj | 
5269 | 
1 | 
 | 
 | 
T1 | 
6 | 
 | 
T2 | 
7 | 
 | 
T13 | 
16 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56196 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2209 | 
1 | 
 | 
 | 
T16 | 
14 | 
 | 
T17 | 
6 | 
 | 
T18 | 
25 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57672 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
733 | 
1 | 
 | 
 | 
T41 | 
25 | 
 | 
T23 | 
15 | 
 | 
T61 | 
10 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
39605 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[1] | 
18800 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56326 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
13 | 
 | 
T3 | 
2 | 
| auto[1] | 
2079 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T9 | 
6 | 
 | 
T16 | 
18 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56316 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
13 | 
 | 
T3 | 
2 | 
| auto[1] | 
2089 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T9 | 
7 | 
 | 
T24 | 
1 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56333 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2072 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T9 | 
12 | 
 | 
T16 | 
22 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56179 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2226 | 
1 | 
 | 
 | 
T16 | 
15 | 
 | 
T17 | 
13 | 
 | 
T18 | 
25 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56119 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[1] | 
2286 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T18 | 
20 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57684 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
721 | 
1 | 
 | 
 | 
T41 | 
21 | 
 | 
T23 | 
15 | 
 | 
T61 | 
27 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57700 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
705 | 
1 | 
 | 
 | 
T41 | 
13 | 
 | 
T23 | 
11 | 
 | 
T61 | 
16 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
57680 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
725 | 
1 | 
 | 
 | 
T41 | 
17 | 
 | 
T23 | 
10 | 
 | 
T61 | 
15 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
55514 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
| auto[1] | 
2891 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T24 | 
10 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54684 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
3721 | 
1 | 
 | 
 | 
T10 | 
78 | 
 | 
T21 | 
91 | 
 | 
T47 | 
69 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56310 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
13 | 
 | 
T3 | 
2 | 
| auto[1] | 
2095 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T9 | 
10 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56281 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
13 | 
 | 
T3 | 
2 | 
| auto[1] | 
2124 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T9 | 
9 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56256 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
12 | 
 | 
T3 | 
2 | 
| auto[1] | 
2149 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T9 | 
14 | 
 | 
T24 | 
1 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56218 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2187 | 
1 | 
 | 
 | 
T16 | 
16 | 
 | 
T17 | 
10 | 
 | 
T18 | 
31 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52558 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
5847 | 
1 | 
 | 
 | 
T14 | 
60 | 
 | 
T16 | 
10 | 
 | 
T17 | 
6 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54819 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
3586 | 
1 | 
 | 
 | 
T19 | 
87 | 
 | 
T59 | 
56 | 
 | 
T60 | 
85 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
58405 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56196 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2209 | 
1 | 
 | 
 | 
T16 | 
7 | 
 | 
T17 | 
5 | 
 | 
T18 | 
27 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56232 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2173 | 
1 | 
 | 
 | 
T16 | 
14 | 
 | 
T17 | 
13 | 
 | 
T18 | 
26 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
56317 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T3 | 
2 | 
| auto[1] | 
2088 | 
1 | 
 | 
 | 
T16 | 
9 | 
 | 
T17 | 
7 | 
 | 
T18 | 
22 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
51694 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T14 | 
60 | 
| auto[0] | 
no_err_inj | 
3820 | 
1 | 
 | 
 | 
T13 | 
16 | 
 | 
T16 | 
32 | 
 | 
T18 | 
15 | 
| auto[1] | 
err_inj | 
1442 | 
1 | 
 | 
 | 
T1 | 
7 | 
 | 
T2 | 
7 | 
 | 
T24 | 
4 | 
| auto[1] | 
no_err_inj | 
1449 | 
1 | 
 | 
 | 
T1 | 
6 | 
 | 
T2 | 
7 | 
 | 
T24 | 
6 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53519 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
| auto[0] | 
auto[1] | 
1995 | 
1 | 
 | 
 | 
T9 | 
9 | 
 | 
T16 | 
18 | 
 | 
T81 | 
6 | 
| auto[1] | 
auto[0] | 
2762 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
13 | 
 | 
T24 | 
10 | 
| auto[1] | 
auto[1] | 
129 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T18 | 
4 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53585 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
| auto[0] | 
auto[1] | 
1929 | 
1 | 
 | 
 | 
T9 | 
7 | 
 | 
T16 | 
14 | 
 | 
T81 | 
4 | 
| auto[1] | 
auto[0] | 
2731 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
13 | 
 | 
T24 | 
9 | 
| auto[1] | 
auto[1] | 
160 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T24 | 
1 | 
 | 
T16 | 
1 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53543 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
| auto[0] | 
auto[1] | 
1971 | 
1 | 
 | 
 | 
T9 | 
14 | 
 | 
T16 | 
21 | 
 | 
T81 | 
11 | 
| auto[1] | 
auto[0] | 
2713 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
12 | 
 | 
T24 | 
9 | 
| auto[1] | 
auto[1] | 
178 | 
1 | 
 | 
 | 
T2 | 
2 | 
 | 
T24 | 
1 | 
 | 
T16 | 
2 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53625 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
| auto[0] | 
auto[1] | 
1889 | 
1 | 
 | 
 | 
T9 | 
11 | 
 | 
T16 | 
13 | 
 | 
T81 | 
5 | 
| auto[1] | 
auto[0] | 
2722 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
14 | 
 | 
T24 | 
10 | 
| auto[1] | 
auto[1] | 
169 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T18 | 
1 | 
 | 
T137 | 
2 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53572 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
| auto[0] | 
auto[1] | 
1942 | 
1 | 
 | 
 | 
T9 | 
10 | 
 | 
T16 | 
16 | 
 | 
T81 | 
7 | 
| auto[1] | 
auto[0] | 
2720 | 
1 | 
 | 
 | 
T1 | 
11 | 
 | 
T2 | 
13 | 
 | 
T24 | 
9 | 
| auto[1] | 
auto[1] | 
171 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
1 | 
 | 
T24 | 
1 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
53653 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
| auto[0] | 
auto[1] | 
1861 | 
1 | 
 | 
 | 
T9 | 
9 | 
 | 
T16 | 
15 | 
 | 
T81 | 
9 | 
| auto[1] | 
auto[0] | 
2741 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
14 | 
 | 
T24 | 
10 | 
| auto[1] | 
auto[1] | 
150 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T16 | 
1 | 
 | 
T18 | 
4 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38349 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1256 | 
1 | 
 | 
 | 
T17 | 
7 | 
 | 
T194 | 
10 | 
 | 
T20 | 
23 | 
| auto[1] | 
auto[0] | 
17898 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
| auto[1] | 
auto[1] | 
902 | 
1 | 
 | 
 | 
T16 | 
14 | 
 | 
T18 | 
38 | 
 | 
T26 | 
8 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38325 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1280 | 
1 | 
 | 
 | 
T17 | 
6 | 
 | 
T194 | 
9 | 
 | 
T20 | 
20 | 
| auto[1] | 
auto[0] | 
17871 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
| auto[1] | 
auto[1] | 
929 | 
1 | 
 | 
 | 
T16 | 
14 | 
 | 
T18 | 
25 | 
 | 
T26 | 
12 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38344 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1261 | 
1 | 
 | 
 | 
T20 | 
12 | 
 | 
T38 | 
16 | 
 | 
T80 | 
36 | 
| auto[1] | 
auto[0] | 
17775 | 
1 | 
 | 
 | 
T9 | 
88 | 
 | 
T16 | 
203 | 
 | 
T18 | 
227 | 
| auto[1] | 
auto[1] | 
1025 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T18 | 
20 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38289 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1316 | 
1 | 
 | 
 | 
T17 | 
13 | 
 | 
T194 | 
3 | 
 | 
T20 | 
31 | 
| auto[1] | 
auto[0] | 
17890 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
| auto[1] | 
auto[1] | 
910 | 
1 | 
 | 
 | 
T16 | 
15 | 
 | 
T18 | 
25 | 
 | 
T26 | 
8 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34662 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
4943 | 
1 | 
 | 
 | 
T14 | 
60 | 
 | 
T17 | 
6 | 
 | 
T22 | 
65 | 
| auto[1] | 
auto[0] | 
17896 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
| auto[1] | 
auto[1] | 
904 | 
1 | 
 | 
 | 
T16 | 
10 | 
 | 
T18 | 
27 | 
 | 
T26 | 
9 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38409 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
13 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1196 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T16 | 
10 | 
| auto[1] | 
auto[0] | 
17872 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
79 | 
| auto[1] | 
auto[1] | 
928 | 
1 | 
 | 
 | 
T9 | 
9 | 
 | 
T16 | 
8 | 
 | 
T26 | 
18 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38448 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
13 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1157 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T24 | 
1 | 
| auto[1] | 
auto[0] | 
17862 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
78 | 
| auto[1] | 
auto[1] | 
938 | 
1 | 
 | 
 | 
T9 | 
10 | 
 | 
T16 | 
9 | 
 | 
T26 | 
10 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38402 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
13 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1203 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T24 | 
1 | 
 | 
T16 | 
7 | 
| auto[1] | 
auto[0] | 
17914 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
81 | 
| auto[1] | 
auto[1] | 
886 | 
1 | 
 | 
 | 
T9 | 
7 | 
 | 
T16 | 
8 | 
 | 
T26 | 
13 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38435 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
13 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1170 | 
1 | 
 | 
 | 
T2 | 
1 | 
 | 
T16 | 
12 | 
 | 
T81 | 
6 | 
| auto[1] | 
auto[0] | 
17891 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
82 | 
| auto[1] | 
auto[1] | 
909 | 
1 | 
 | 
 | 
T9 | 
6 | 
 | 
T16 | 
6 | 
 | 
T26 | 
17 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38458 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1147 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T16 | 
8 | 
 | 
T81 | 
5 | 
| auto[1] | 
auto[0] | 
17889 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
77 | 
| auto[1] | 
auto[1] | 
911 | 
1 | 
 | 
 | 
T9 | 
11 | 
 | 
T16 | 
5 | 
 | 
T26 | 
19 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38459 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1146 | 
1 | 
 | 
 | 
T1 | 
1 | 
 | 
T16 | 
5 | 
 | 
T81 | 
9 | 
| auto[1] | 
auto[0] | 
17935 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
79 | 
| auto[1] | 
auto[1] | 
865 | 
1 | 
 | 
 | 
T9 | 
9 | 
 | 
T16 | 
11 | 
 | 
T26 | 
14 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38440 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1165 | 
1 | 
 | 
 | 
T17 | 
7 | 
 | 
T194 | 
7 | 
 | 
T20 | 
21 | 
| auto[1] | 
auto[0] | 
17877 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
| auto[1] | 
auto[1] | 
923 | 
1 | 
 | 
 | 
T16 | 
9 | 
 | 
T18 | 
22 | 
 | 
T26 | 
16 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
38319 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T10 | 
78 | 
| auto[0] | 
auto[1] | 
1286 | 
1 | 
 | 
 | 
T17 | 
13 | 
 | 
T194 | 
5 | 
 | 
T20 | 
20 | 
| auto[1] | 
auto[0] | 
17913 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
| auto[1] | 
auto[1] | 
887 | 
1 | 
 | 
 | 
T16 | 
14 | 
 | 
T18 | 
26 | 
 | 
T26 | 
7 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37890 | 
1 | 
 | 
 | 
T10 | 
78 | 
 | 
T13 | 
16 | 
 | 
T14 | 
60 | 
| auto[0] | 
auto[1] | 
1715 | 
1 | 
 | 
 | 
T1 | 
13 | 
 | 
T2 | 
14 | 
 | 
T24 | 
10 | 
| auto[1] | 
auto[0] | 
17624 | 
1 | 
 | 
 | 
T3 | 
2 | 
 | 
T5 | 
12 | 
 | 
T9 | 
88 | 
| auto[1] | 
auto[1] | 
1176 | 
1 | 
 | 
 | 
T16 | 
14 | 
 | 
T195 | 
15 | 
 | 
T40 | 
27 |