Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117626692

1

T1

7079

T2

10243

T3

12324

auto[1]

1475951

1

T1

198

T2

198

T10

8820

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117635779

1

T1

6881

T2

10144

T3

12128

auto[1]

1466864

1

T1

396

T2

297

T3

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7885854	1			T1	1443		T2	1271		T3	253
auto[IdleSt]	23374089	1			T1	1402		T2	1377		T3	9050
auto[ClkMuxSt]	38541	1			T1	6		T2	7		T3	2
auto[CntIncrSt]	38316	1			T1	6		T2	7		T3	2
auto[CntProgSt]	1654314	1			T1	110		T2	1899		T3	34
auto[TransCheckSt]	29773	1			T1	6		T2	7		T10	65
auto[TokenHashSt]	52176612	1			T1	457		T2	704		T10	402
auto[FlashRmaSt]	36699	1			T1	6		T2	7		T10	71
auto[TokenCheck0St]	13755	1			T1	6		T2	7		T10	21
auto[TokenCheck1St]	10102	1			T1	6		T2	7		T10	21
auto[TransProgSt]	464808	1			T1	118		T2	1520		T10	37
auto[PostTransSt]	14017059	1			T1	1498		T2	1736		T3	1712
auto[ScrapSt]	140447	1			T13	33		T21	16		T16	389
auto[EscalateSt]	7082092	1			T1	1359		T2	1164		T3	1271
auto[InvalidSt]	12138015	1			T1	854		T2	727		T9	124605

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2167	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12138015	1			T1	854		T2	727		T9	124605
EscalateSt	7082092	1			T1	1359		T2	1164		T3	1271
ScrapSt	140447	1			T13	33		T21	16		T16	389
PostTransSt	14017059	1			T1	1498		T2	1736		T3	1712
TransProgSt	464808	1			T1	118		T2	1520		T10	37
TokenCheck1St	10102	1			T1	6		T2	7		T10	21
TokenCheck0St	13755	1			T1	6		T2	7		T10	21
FlashRmaSt	36699	1			T1	6		T2	7		T10	71
TokenHashSt	52176612	1			T1	457		T2	704		T10	402
TransCheckSt	29773	1			T1	6		T2	7		T10	65
CntProgSt	1654314	1			T1	110		T2	1899		T3	34
CntIncrSt	38316	1			T1	6		T2	7		T3	2
ClkMuxSt	38541	1			T1	6		T2	7		T3	2
IdleSt	23374089	1			T1	1402		T2	1377		T3	9050
ResetSt	7885854	1			T1	1443		T2	1271		T3	253
arcs[ResetSt=>IdleSt]	58581	1			T1	13		T2	15		T3	3
arcs[IdleSt=>ScrapSt]	312	1			T13	1		T21	4		T16	1
arcs[IdleSt=>ClkMuxSt]	38360	1			T1	6		T2	7		T3	2
arcs[ClkMuxSt=>CntIncrSt]	38316	1			T1	6		T2	7		T3	2
arcs[CntIncrSt=>PostTransSt]	2176	1			T16	14		T17	13		T18	26
arcs[CntIncrSt=>CntProgSt]	36083	1			T1	6		T2	7		T3	2
arcs[CntProgSt=>PostTransSt]	5182	1			T3	2		T5	12		T16	14
arcs[CntProgSt=>TransCheckSt]	29773	1			T1	6		T2	7		T10	65
arcs[TransCheckSt=>PostTransSt]	3890	1			T16	9		T17	7		T18	22
arcs[TransCheckSt=>TokenHashSt]	25770	1			T1	6		T2	7		T10	57
arcs[TokenHashSt=>PostTransSt]	11253	1			T14	60		T15	1		T36	1
arcs[TokenHashSt=>FlashRmaSt]	13786	1			T1	6		T2	7		T10	22
arcs[FlashRmaSt=>TokenCheck0St]	13755	1			T1	6		T2	7		T10	21
arcs[TokenCheck0St=>PostTransSt]	3605	1			T16	11		T17	6		T18	23
arcs[TokenCheck0St=>TokenCheck1St]	10102	1			T1	6		T2	7		T10	21
arcs[TokenCheck1St=>PostTransSt]	622	1			T16	3		T18	1		T26	2
arcs[TransProgSt=>PostTransSt]	8644	1			T1	6		T2	7		T10	16
arcs[IdleSt=>EscalateSt]	133	1			T21	6		T47	4		T48	4
arcs[ClkMuxSt=>EscalateSt]	44	1			T21	2		T47	2		T48	2
arcs[CntIncrSt=>EscalateSt]	57	1			T10	2		T21	1		T47	4
arcs[CntProgSt=>EscalateSt]	1128	1			T10	7		T21	24		T47	5
arcs[TransCheckSt=>EscalateSt]	113	1			T10	8		T21	2		T47	3
arcs[TokenHashSt=>EscalateSt]	731	1			T10	35		T21	18		T47	23
arcs[FlashRmaSt=>EscalateSt]	31	1			T10	1		T48	1		T49	3
arcs[TokenCheck0St=>EscalateSt]	48	1			T21	2		T48	1		T50	1
arcs[TokenCheck1St=>EscalateSt]	23	1			T10	1		T47	2		T53	1
arcs[TransProgSt=>EscalateSt]	813	1			T10	4		T21	25		T47	10
arcs[PostTransSt=>EscalateSt]	5486	1			T3	2		T10	16		T5	12
arcs[InvalidSt=>EscalateSt]	15299	1			T1	6		T2	5		T9	62

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7885665	1			T1	1443		T2	1271		T3	253
auto[0]	auto[IdleSt]	23373999	1			T1	1402		T2	1377		T3	9050
auto[0]	auto[ClkMuxSt]	38514	1			T1	6		T2	7		T3	2
auto[0]	auto[CntIncrSt]	38284	1			T1	6		T2	7		T3	2
auto[0]	auto[CntProgSt]	1653587	1			T1	110		T2	1899		T3	34
auto[0]	auto[TransCheckSt]	29694	1			T1	6		T2	7		T10	61
auto[0]	auto[TokenHashSt]	52176135	1			T1	457		T2	704		T10	377
auto[0]	auto[FlashRmaSt]	36678	1			T1	6		T2	7		T10	71
auto[0]	auto[TokenCheck0St]	13716	1			T1	6		T2	7		T10	21
auto[0]	auto[TokenCheck1St]	10087	1			T1	6		T2	7		T10	20
auto[0]	auto[TransProgSt]	464264	1			T1	118		T2	1520		T10	34
auto[0]	auto[PostTransSt]	14014269	1			T1	1498		T2	1736		T3	1712
auto[0]	auto[ScrapSt]	140398	1			T13	33		T21	15		T16	389
auto[0]	auto[EscalateSt]	5618968	1			T1	1163		T2	968		T3	1271
auto[0]	auto[InvalidSt]	12130267	1			T1	852		T2	725		T9	124575
auto[1]	auto[ResetSt]	189	1			T10	2		T21	4		T47	2
auto[1]	auto[IdleSt]	90	1			T21	3		T47	1		T48	3
auto[1]	auto[ClkMuxSt]	27	1			T21	1		T47	1		T48	1
auto[1]	auto[CntIncrSt]	32	1			T10	1		T47	2		T48	1
auto[1]	auto[CntProgSt]	727	1			T10	5		T21	18		T47	2
auto[1]	auto[TransCheckSt]	79	1			T10	4		T21	2		T47	2
auto[1]	auto[TokenHashSt]	477	1			T10	25		T21	13		T47	14
auto[1]	auto[FlashRmaSt]	21	1			T49	3		T152	2		T191	1
auto[1]	auto[TokenCheck0St]	39	1			T21	1		T48	1		T50	1
auto[1]	auto[TokenCheck1St]	15	1			T10	1		T53	1		T192	1
auto[1]	auto[TransProgSt]	544	1			T10	3		T21	14		T47	7
auto[1]	auto[PostTransSt]	2790	1			T10	13		T5	7		T21	2
auto[1]	auto[ScrapSt]	49	1			T21	1		T48	2		T50	2
auto[1]	auto[EscalateSt]	1463124	1			T1	196		T2	196		T10	8766
auto[1]	auto[InvalidSt]	7748	1			T1	2		T2	2		T9	30

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7885672	1			T1	1443		T2	1271		T3	253
auto[0]	auto[IdleSt]	23374000	1			T1	1402		T2	1377		T3	9050
auto[0]	auto[ClkMuxSt]	38510	1			T1	6		T2	7		T3	2
auto[0]	auto[CntIncrSt]	38273	1			T1	6		T2	7		T3	2
auto[0]	auto[CntProgSt]	1653548	1			T1	110		T2	1899		T3	34
auto[0]	auto[TransCheckSt]	29700	1			T1	6		T2	7		T10	59
auto[0]	auto[TokenHashSt]	52176114	1			T1	457		T2	704		T10	380
auto[0]	auto[FlashRmaSt]	36676	1			T1	6		T2	7		T10	70
auto[0]	auto[TokenCheck0St]	13723	1			T1	6		T2	7		T10	21
auto[0]	auto[TokenCheck1St]	10086	1			T1	6		T2	7		T10	21
auto[0]	auto[TransProgSt]	464265	1			T1	118		T2	1520		T10	34
auto[0]	auto[PostTransSt]	14014269	1			T1	1498		T2	1736		T3	1710
auto[0]	auto[ScrapSt]	140397	1			T13	33		T21	12		T16	389
auto[0]	auto[EscalateSt]	5627915	1			T1	967		T2	870		T3	1077
auto[0]	auto[InvalidSt]	12130464	1			T1	850		T2	724		T9	124573
auto[1]	auto[ResetSt]	182	1			T10	4		T21	1		T47	3
auto[1]	auto[IdleSt]	89	1			T21	5		T47	4		T48	1
auto[1]	auto[ClkMuxSt]	31	1			T21	1		T47	2		T48	2
auto[1]	auto[CntIncrSt]	43	1			T10	2		T21	1		T47	3
auto[1]	auto[CntProgSt]	766	1			T10	4		T21	13		T47	5
auto[1]	auto[TransCheckSt]	73	1			T10	6		T21	1		T47	2
auto[1]	auto[TokenHashSt]	498	1			T10	22		T21	16		T47	17
auto[1]	auto[FlashRmaSt]	23	1			T10	1		T48	1		T49	1
auto[1]	auto[TokenCheck0St]	32	1			T21	1		T48	1		T53	1
auto[1]	auto[TokenCheck1St]	16	1			T47	2		T53	1		T193	1
auto[1]	auto[TransProgSt]	543	1			T10	3		T21	22		T47	5
auto[1]	auto[PostTransSt]	2790	1			T3	2		T10	9		T5	5
auto[1]	auto[ScrapSt]	50	1			T21	4		T48	3		T50	1
auto[1]	auto[EscalateSt]	1454177	1			T1	392		T2	294		T3	194
auto[1]	auto[InvalidSt]	7551	1			T1	4		T2	3		T9	32