Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1988817	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2204517

1

T3

370

T9

233

T10

1578

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3856123	1			T3	330		T9	157		T10	3012
values[0x0]	167898	1			T3	117		T9	94		T10	54
values[0x1]	169313	1			T3	107		T9	82		T10	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1581732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2611602

1

T3

404

T9

263

T10

1884

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13853	1			T3	2		T9	6		T10	20
valid_sources[0x01]	13213	1			T10	8		T4	1		T18	11
valid_sources[0x02]	13311	1			T3	2		T10	7		T4	1
valid_sources[0x03]	13302	1			T21	1		T18	13		T16	7
valid_sources[0x04]	12446	1			T3	2		T9	1		T10	19
valid_sources[0x05]	13412	1			T9	1		T10	19		T21	9
valid_sources[0x06]	12864	1			T9	4		T10	13		T21	1
valid_sources[0x07]	13542	1			T3	4		T9	1		T10	10
valid_sources[0x08]	13565	1			T9	2		T10	7		T5	3
valid_sources[0x09]	13654	1			T10	11		T21	11		T18	14
valid_sources[0x0a]	13336	1			T3	3		T10	26		T21	4
valid_sources[0x0b]	13094	1			T9	3		T10	13		T21	10
valid_sources[0x0c]	91033	1			T3	3		T9	1		T10	16
valid_sources[0x0d]	13362	1			T3	5		T10	9		T21	2
valid_sources[0x0e]	19636	1			T3	7		T10	21		T4	1
valid_sources[0x0f]	13118	1			T10	4		T21	3		T18	12
valid_sources[0x10]	18960	1			T10	21		T21	16		T18	23
valid_sources[0x11]	13736	1			T9	2		T10	3		T21	2
valid_sources[0x12]	13175	1			T3	3		T9	1		T10	10
valid_sources[0x13]	16171	1			T9	1		T10	14		T21	4
valid_sources[0x14]	13083	1			T3	5		T9	2		T10	19
valid_sources[0x15]	13132	1			T10	16		T18	9		T16	10
valid_sources[0x16]	15223	1			T9	2		T10	13		T21	9
valid_sources[0x17]	14584	1			T10	9		T21	8		T18	9
valid_sources[0x18]	13009	1			T3	4		T9	1		T10	2
valid_sources[0x19]	13730	1			T3	14		T10	15		T21	5
valid_sources[0x1a]	13458	1			T9	1		T10	14		T21	4
valid_sources[0x1b]	15759	1			T3	6		T10	13		T21	2
valid_sources[0x1c]	13656	1			T9	1		T10	6		T21	10
valid_sources[0x1d]	16028	1			T9	2		T10	9		T21	2
valid_sources[0x1e]	15072	1			T3	4		T9	1		T10	6
valid_sources[0x1f]	13635	1			T9	4		T10	19		T21	8
valid_sources[0x20]	13051	1			T9	3		T10	19		T18	6
valid_sources[0x21]	12973	1			T9	3		T10	18		T4	1
valid_sources[0x22]	18728	1			T9	2		T10	6		T4	1
valid_sources[0x23]	13487	1			T9	3		T10	11		T18	10
valid_sources[0x24]	13631	1			T9	5		T10	10		T21	10
valid_sources[0x25]	12783	1			T9	2		T10	4		T21	2
valid_sources[0x26]	12539	1			T9	1		T10	6		T21	3
valid_sources[0x27]	13166	1			T10	10		T18	12		T16	4
valid_sources[0x28]	13256	1			T3	1		T9	6		T10	14
valid_sources[0x29]	13133	1			T3	1		T10	16		T21	4
valid_sources[0x2a]	13270	1			T9	2		T18	13		T16	11
valid_sources[0x2b]	12957	1			T3	1		T9	2		T10	21
valid_sources[0x2c]	14430	1			T3	16		T10	18		T21	2
valid_sources[0x2d]	15185	1			T3	5		T9	1		T10	2
valid_sources[0x2e]	12780	1			T3	2		T9	1		T10	6
valid_sources[0x2f]	13293	1			T3	1		T9	1		T10	11
valid_sources[0x30]	85830	1			T3	1		T10	13		T21	9
valid_sources[0x31]	13150	1			T3	2		T10	19		T4	1
valid_sources[0x32]	13403	1			T3	2		T10	3		T21	10
valid_sources[0x33]	14560	1			T10	17		T5	22		T21	15
valid_sources[0x34]	13164	1			T10	13		T21	12		T18	8
valid_sources[0x35]	14647	1			T3	3		T10	8		T21	3
valid_sources[0x36]	12847	1			T3	10		T10	25		T21	2
valid_sources[0x37]	13817	1			T3	6		T9	2		T10	13
valid_sources[0x38]	12981	1			T3	1		T10	13		T5	1
valid_sources[0x39]	43810	1			T9	1		T10	23		T21	7
valid_sources[0x3a]	13652	1			T9	2		T10	6		T21	2
valid_sources[0x3b]	16371	1			T9	1		T10	14		T21	10
valid_sources[0x3c]	14949	1			T3	1		T9	2		T10	12
valid_sources[0x3d]	13056	1			T3	2		T9	1		T10	37
valid_sources[0x3e]	13781	1			T9	1		T21	11		T18	9
valid_sources[0x3f]	13840	1			T3	2		T9	1		T10	10
valid_sources[0x40]	13428	1			T3	3		T10	14		T21	3
valid_sources[0x41]	22677	1			T9	1		T10	11		T21	1
valid_sources[0x42]	13259	1			T3	5		T10	35		T21	15
valid_sources[0x43]	41697	1			T9	1		T10	4		T21	6
valid_sources[0x44]	12855	1			T3	3		T9	1		T10	28
valid_sources[0x45]	13213	1			T3	6		T9	2		T10	3
valid_sources[0x46]	13352	1			T3	2		T9	2		T10	16
valid_sources[0x47]	12761	1			T3	16		T10	6		T21	1
valid_sources[0x48]	13575	1			T3	3		T9	1		T10	8
valid_sources[0x49]	12899	1			T10	5		T21	4		T18	11
valid_sources[0x4a]	14922	1			T3	1		T10	15		T21	1
valid_sources[0x4b]	13232	1			T10	10		T21	11		T18	12
valid_sources[0x4c]	15355	1			T9	3		T10	4		T21	7
valid_sources[0x4d]	12697	1			T3	5		T9	4		T10	15
valid_sources[0x4e]	13313	1			T3	2		T9	2		T10	11
valid_sources[0x4f]	13091	1			T3	7		T9	1		T10	22
valid_sources[0x50]	145622	1			T9	3		T10	15		T21	19
valid_sources[0x51]	13970	1			T9	2		T10	19		T21	6
valid_sources[0x52]	14998	1			T3	5		T9	3		T10	19
valid_sources[0x53]	12876	1			T9	1		T10	32		T21	1
valid_sources[0x54]	13488	1			T3	3		T9	3		T10	10
valid_sources[0x55]	13165	1			T3	4		T9	2		T10	14
valid_sources[0x56]	14526	1			T3	1		T9	3		T10	13
valid_sources[0x57]	13798	1			T3	2		T9	3		T10	12
valid_sources[0x58]	13146	1			T10	14		T21	14		T18	10
valid_sources[0x59]	13379	1			T9	1		T10	10		T21	5
valid_sources[0x5a]	19488	1			T3	4		T9	1		T10	4
valid_sources[0x5b]	13876	1			T3	6		T9	3		T10	3
valid_sources[0x5c]	13077	1			T3	1		T9	1		T10	6
valid_sources[0x5d]	61673	1			T3	1		T9	2		T10	15
valid_sources[0x5e]	13497	1			T10	4		T21	3		T18	8
valid_sources[0x5f]	14231	1			T3	1		T9	2		T10	15
valid_sources[0x60]	13448	1			T3	3		T10	2		T21	5
valid_sources[0x61]	15097	1			T9	2		T10	15		T21	4
valid_sources[0x62]	14245	1			T3	3		T9	7		T10	8
valid_sources[0x63]	35345	1			T3	2		T9	5		T10	17
valid_sources[0x64]	13112	1			T9	3		T10	13		T21	15
valid_sources[0x65]	13261	1			T3	8		T10	8		T4	1
valid_sources[0x66]	13372	1			T3	3		T9	7		T10	10
valid_sources[0x67]	13016	1			T3	2		T9	3		T10	11
valid_sources[0x68]	12851	1			T10	30		T21	1		T18	15
valid_sources[0x69]	12985	1			T9	1		T10	15		T21	6
valid_sources[0x6a]	14844	1			T9	2		T10	9		T21	4
valid_sources[0x6b]	13324	1			T3	6		T9	2		T10	7
valid_sources[0x6c]	12746	1			T3	2		T9	3		T10	10
valid_sources[0x6d]	13930	1			T3	1		T9	3		T10	4
valid_sources[0x6e]	14878	1			T9	2		T10	6		T21	7
valid_sources[0x6f]	13383	1			T9	2		T10	18		T12	2
valid_sources[0x70]	13654	1			T9	3		T10	17		T21	3
valid_sources[0x71]	14141	1			T3	2		T9	1		T10	2
valid_sources[0x72]	16605	1			T10	11		T21	3		T18	9
valid_sources[0x73]	13006	1			T3	1		T10	17		T21	9
valid_sources[0x74]	13400	1			T10	7		T21	1		T18	10
valid_sources[0x75]	13346	1			T3	7		T10	14		T21	5
valid_sources[0x76]	13376	1			T3	17		T9	2		T10	13
valid_sources[0x77]	13526	1			T3	2		T9	1		T10	24
valid_sources[0x78]	19648	1			T9	1		T10	14		T12	2
valid_sources[0x79]	15047	1			T3	1		T9	3		T10	6
valid_sources[0x7a]	13973	1			T3	9		T9	1		T10	12
valid_sources[0x7b]	19452	1			T9	1		T10	6		T21	6
valid_sources[0x7c]	15381	1			T3	9		T9	3		T10	17
valid_sources[0x7d]	16456	1			T3	6		T9	1		T10	15
valid_sources[0x7e]	14137	1			T10	30		T4	1		T21	5
valid_sources[0x7f]	13610	1			T3	2		T9	1		T10	6
valid_sources[0x80]	16346	1			T3	1		T10	7		T11	80

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1913455

1

T3

174

T9

72

T10

1495

values[0x0]

all_enables

biggest_size

145849

1

T3

106

T9

88

T10

46

values[0x1]

all_enables

biggest_size

145213

1

T3

90

T9

73

T10

37