Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	115581532	14578	0	0
claim_transition_if_regwen_rd_A	115581532	1232	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115581532	14578	0	0
T19	367824	19	0	0
T22	697640	0	0	0
T24	370380	0	0	0
T25	108147	0	0	0
T26	48721	0	0	0
T40	0	3	0	0
T53	31402	0	0	0
T55	5284	0	0	0
T72	10243	0	0	0
T75	33483	0	0	0
T76	34952	0	0	0
T84	0	7	0	0
T90	0	7	0	0
T121	0	16	0	0
T122	0	1	0	0
T123	0	4	0	0
T124	0	8	0	0
T125	0	5	0	0
T126	0	8	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115581532	1232	0	0
T39	128856	6	0	0
T74	111131	0	0	0
T80	1387	0	0	0
T87	0	5	0	0
T89	0	28	0	0
T93	0	9	0	0
T94	0	8	0	0
T108	0	61	0	0
T110	0	21	0	0
T127	0	17	0	0
T128	0	46	0	0
T129	0	3	0	0
T130	3254	0	0	0
T131	195779	0	0	0
T132	2473	0	0	0
T133	890	0	0	0
T134	172860	0	0	0
T135	1420	0	0	0
T136	30037	0	0	0