Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2284290	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2513157

1

T1

532

T3

5073

T5

88

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4439434	1			T1	374		T3	9174		T5	84
values[0x0]	178322	1			T1	207		T3	296		T5	31
values[0x1]	179691	1			T1	209		T3	248		T5	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1816531	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2980916

1

T1

584

T3

6039

T5

102

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15622	1			T1	3		T3	41		T6	5
valid_sources[0x01]	14830	1			T1	2		T3	28		T5	2
valid_sources[0x02]	15189	1			T1	2		T3	34		T19	4
valid_sources[0x03]	16498	1			T1	7		T3	27		T5	5
valid_sources[0x04]	16442	1			T1	3		T3	61		T19	1
valid_sources[0x05]	14814	1			T1	4		T3	35		T18	1
valid_sources[0x06]	14333	1			T1	2		T3	40		T18	1
valid_sources[0x07]	15031	1			T1	3		T3	41		T19	6
valid_sources[0x08]	14592	1			T1	2		T3	35		T5	1
valid_sources[0x09]	14813	1			T1	2		T3	52		T5	3
valid_sources[0x0a]	17413	1			T3	47		T6	1		T19	1
valid_sources[0x0b]	37361	1			T1	2		T3	42		T6	3
valid_sources[0x0c]	14747	1			T1	3		T3	23		T19	3
valid_sources[0x0d]	39228	1			T1	5		T3	37		T6	2
valid_sources[0x0e]	14833	1			T3	49		T5	1		T6	4
valid_sources[0x0f]	15953	1			T1	3		T3	25		T6	2
valid_sources[0x10]	15426	1			T1	1		T3	21		T19	7
valid_sources[0x11]	16468	1			T1	2		T3	45		T6	4
valid_sources[0x12]	16474	1			T1	10		T3	33		T19	2
valid_sources[0x13]	14583	1			T1	5		T3	66		T19	4
valid_sources[0x14]	14538	1			T1	3		T3	57		T6	1
valid_sources[0x15]	14888	1			T1	2		T3	33		T6	1
valid_sources[0x16]	14486	1			T1	9		T3	36		T6	2
valid_sources[0x17]	14954	1			T1	6		T3	38		T6	2
valid_sources[0x18]	22256	1			T1	4		T3	51		T5	2
valid_sources[0x19]	14700	1			T1	4		T3	23		T5	2
valid_sources[0x1a]	14561	1			T1	3		T3	58		T18	2
valid_sources[0x1b]	15863	1			T1	4		T3	42		T5	1
valid_sources[0x1c]	17766	1			T1	3		T3	38		T5	1
valid_sources[0x1d]	14686	1			T1	4		T3	20		T18	3
valid_sources[0x1e]	15120	1			T1	5		T3	36		T6	1
valid_sources[0x1f]	15252	1			T3	47		T19	6		T16	8
valid_sources[0x20]	14642	1			T1	5		T3	33		T19	6
valid_sources[0x21]	14250	1			T1	3		T3	33		T5	1
valid_sources[0x22]	14453	1			T1	3		T3	53		T6	4
valid_sources[0x23]	14619	1			T1	5		T3	20		T18	3
valid_sources[0x24]	15528	1			T1	6		T3	31		T5	2
valid_sources[0x25]	14766	1			T1	1		T3	39		T5	3
valid_sources[0x26]	22120	1			T1	3		T3	44		T6	4
valid_sources[0x27]	15542	1			T1	3		T3	21		T5	3
valid_sources[0x28]	21310	1			T1	2		T3	23		T18	3
valid_sources[0x29]	14970	1			T1	3		T3	20		T5	1
valid_sources[0x2a]	15382	1			T1	5		T3	60		T5	1
valid_sources[0x2b]	15450	1			T1	1		T3	46		T6	1
valid_sources[0x2c]	14604	1			T1	2		T3	31		T18	1
valid_sources[0x2d]	17757	1			T1	2		T3	49		T5	1
valid_sources[0x2e]	14257	1			T1	5		T3	51		T6	3
valid_sources[0x2f]	16893	1			T1	3		T3	50		T5	1
valid_sources[0x30]	15437	1			T1	4		T3	14		T18	1
valid_sources[0x31]	15606	1			T1	2		T3	52		T5	5
valid_sources[0x32]	14371	1			T3	49		T19	6		T16	6
valid_sources[0x33]	14719	1			T1	2		T3	48		T19	2
valid_sources[0x34]	16614	1			T3	44		T18	1		T19	1
valid_sources[0x35]	14847	1			T1	2		T3	36		T6	2
valid_sources[0x36]	19552	1			T1	2		T3	29		T5	1
valid_sources[0x37]	14804	1			T1	1		T3	30		T19	6
valid_sources[0x38]	16146	1			T1	3		T3	44		T19	3
valid_sources[0x39]	16336	1			T3	55		T18	1		T19	5
valid_sources[0x3a]	15551	1			T1	2		T3	34		T19	9
valid_sources[0x3b]	15963	1			T1	1		T3	43		T18	2
valid_sources[0x3c]	67964	1			T1	1		T3	21		T19	4
valid_sources[0x3d]	14795	1			T1	3		T3	52		T6	3
valid_sources[0x3e]	15013	1			T1	3		T3	32		T5	1
valid_sources[0x3f]	14549	1			T1	8		T3	23		T18	1
valid_sources[0x40]	18772	1			T1	2		T3	37		T5	2
valid_sources[0x41]	16961	1			T1	2		T3	40		T9	1727
valid_sources[0x42]	14308	1			T1	3		T3	24		T6	7
valid_sources[0x43]	46896	1			T1	4		T3	48		T6	1
valid_sources[0x44]	17477	1			T1	2		T3	24		T6	6
valid_sources[0x45]	15129	1			T3	46		T6	1		T19	10
valid_sources[0x46]	14348	1			T1	2		T3	70		T5	3
valid_sources[0x47]	15833	1			T1	6		T3	27		T6	7
valid_sources[0x48]	13920	1			T1	2		T3	40		T19	9
valid_sources[0x49]	15070	1			T1	2		T3	45		T5	1
valid_sources[0x4a]	14511	1			T1	1		T3	69		T5	3
valid_sources[0x4b]	23287	1			T1	6		T3	27		T19	8
valid_sources[0x4c]	14887	1			T1	2		T3	20		T5	1
valid_sources[0x4d]	57935	1			T1	2		T3	30		T6	3
valid_sources[0x4e]	15768	1			T1	3		T3	26		T19	6
valid_sources[0x4f]	16163	1			T1	5		T3	33		T19	3
valid_sources[0x50]	14902	1			T1	2		T3	35		T5	2
valid_sources[0x51]	54145	1			T3	34		T19	5		T56	4
valid_sources[0x52]	18664	1			T1	4		T3	41		T5	4
valid_sources[0x53]	14561	1			T1	3		T3	38		T5	2
valid_sources[0x54]	14688	1			T1	2		T3	29		T5	1
valid_sources[0x55]	14787	1			T1	2		T3	40		T6	1
valid_sources[0x56]	14942	1			T1	8		T3	35		T18	1
valid_sources[0x57]	14988	1			T1	4		T3	29		T5	1
valid_sources[0x58]	14659	1			T1	4		T3	29		T6	2
valid_sources[0x59]	16674	1			T1	3		T3	31		T5	1
valid_sources[0x5a]	14649	1			T1	1		T3	29		T5	1
valid_sources[0x5b]	14775	1			T1	2		T3	38		T19	4
valid_sources[0x5c]	16139	1			T1	2		T3	20		T19	2
valid_sources[0x5d]	14944	1			T1	2		T3	19		T6	6
valid_sources[0x5e]	14880	1			T1	5		T3	36		T6	6
valid_sources[0x5f]	14200	1			T1	2		T3	46		T19	4
valid_sources[0x60]	16549	1			T1	4		T3	43		T6	1
valid_sources[0x61]	14845	1			T1	2		T3	30		T5	2
valid_sources[0x62]	14794	1			T1	4		T3	39		T5	1
valid_sources[0x63]	14963	1			T1	4		T3	37		T5	2
valid_sources[0x64]	19016	1			T1	3		T3	77		T5	1
valid_sources[0x65]	16134	1			T1	1		T3	53		T19	3
valid_sources[0x66]	16370	1			T1	7		T3	56		T19	3
valid_sources[0x67]	20953	1			T1	3		T3	49		T18	2
valid_sources[0x68]	14494	1			T1	4		T3	36		T19	3
valid_sources[0x69]	14299	1			T1	1		T3	46		T19	4
valid_sources[0x6a]	17592	1			T1	6		T3	34		T6	3
valid_sources[0x6b]	25495	1			T1	4		T3	35		T6	1
valid_sources[0x6c]	14918	1			T1	5		T3	42		T6	3
valid_sources[0x6d]	16673	1			T1	7		T3	36		T18	1
valid_sources[0x6e]	14942	1			T1	4		T3	21		T19	7
valid_sources[0x6f]	16077	1			T1	3		T3	25		T18	1
valid_sources[0x70]	14509	1			T1	4		T3	45		T18	2
valid_sources[0x71]	15534	1			T1	3		T3	43		T5	4
valid_sources[0x72]	14477	1			T1	4		T3	23		T5	1
valid_sources[0x73]	16394	1			T3	51		T19	5		T16	7
valid_sources[0x74]	23365	1			T1	4		T3	27		T19	4
valid_sources[0x75]	14697	1			T1	2		T3	27		T19	1
valid_sources[0x76]	15099	1			T1	2		T3	39		T6	2
valid_sources[0x77]	14767	1			T1	8		T3	45		T5	1
valid_sources[0x78]	14571	1			T1	4		T3	32		T19	1
valid_sources[0x79]	14292	1			T1	4		T3	43		T6	2
valid_sources[0x7a]	17251	1			T1	3		T3	23		T19	3
valid_sources[0x7b]	14643	1			T1	6		T3	38		T19	1
valid_sources[0x7c]	15881	1			T1	2		T3	21		T6	1
valid_sources[0x7d]	21593	1			T1	2		T3	19		T5	1
valid_sources[0x7e]	215449	1			T1	10		T3	39		T18	1
valid_sources[0x7f]	14361	1			T1	3		T3	52		T5	4
valid_sources[0x80]	14358	1			T1	2		T3	34		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2204630

1

T1

165

T3

4589

T5

51

values[0x0]

all_enables

biggest_size

154594

1

T1

185

T3

259

T5

16

values[0x1]

all_enables

biggest_size

153933

1

T1

182

T3

225

T5

21