Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	131716930	15740	0	0
claim_transition_if_regwen_rd_A	131716930	896	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131716930	15740	0	0
T36	0	18	0	0
T50	245559	2	0	0
T73	245964	1	0	0
T74	508923	0	0	0
T99	0	13	0	0
T134	0	8	0	0
T135	0	3	0	0
T136	0	6	0	0
T137	0	4	0	0
T138	0	6	0	0
T139	0	1	0	0
T140	53233	0	0	0
T141	1351	0	0	0
T142	824	0	0	0
T143	38477	0	0	0
T144	29698	0	0	0
T145	9649	0	0	0
T146	33108	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131716930	896	0	0
T50	245559	7	0	0
T73	245964	0	0	0
T74	508923	0	0	0
T97	0	8	0	0
T101	0	11	0	0
T104	0	20	0	0
T112	0	34	0	0
T135	0	4	0	0
T140	53233	0	0	0
T141	1351	0	0	0
T142	824	0	0	0
T143	38477	0	0	0
T144	29698	0	0	0
T145	9649	0	0	0
T146	33108	0	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	0	110	0	0
T150	0	2	0	0