Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1435690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1654097

1

T1

12

T2

175

T3

874

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2744915	1			T2	129		T3	646		T5	423
values[0x0]	172452	1			T1	29		T2	83		T3	322
values[0x1]	172420	1			T1	27		T2	64		T3	310

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1139429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1950358

1

T1

17

T2

198

T3

968

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9203	1			T2	1		T3	7		T4	10
valid_sources[0x01]	10097	1			T2	1		T3	1		T4	7
valid_sources[0x02]	9315	1			T3	2		T4	7		T11	5
valid_sources[0x03]	9660	1			T3	2		T4	12		T11	6
valid_sources[0x04]	10810	1			T2	4		T3	9		T4	7
valid_sources[0x05]	9542	1			T1	3		T2	2		T3	5
valid_sources[0x06]	12209	1			T3	3		T4	12		T11	4
valid_sources[0x07]	20342	1			T3	4		T4	10		T11	12
valid_sources[0x08]	9229	1			T3	7		T4	3		T11	2
valid_sources[0x09]	9541	1			T3	5		T4	12		T11	12
valid_sources[0x0a]	9434	1			T2	2		T3	1		T4	10
valid_sources[0x0b]	9706	1			T3	3		T4	7		T11	1
valid_sources[0x0c]	9292	1			T3	5		T5	1		T4	10
valid_sources[0x0d]	9597	1			T3	5		T4	5		T11	10
valid_sources[0x0e]	10503	1			T2	1		T3	6		T4	7
valid_sources[0x0f]	9300	1			T3	3		T4	7		T11	25
valid_sources[0x10]	11122	1			T2	2		T3	8		T4	7
valid_sources[0x11]	32489	1			T3	6		T4	13		T11	7
valid_sources[0x12]	19955	1			T2	2		T3	2		T4	7
valid_sources[0x13]	9680	1			T3	2		T4	5		T11	7
valid_sources[0x14]	9438	1			T3	6		T4	8		T11	5
valid_sources[0x15]	9300	1			T1	3		T3	4		T4	9
valid_sources[0x16]	12134	1			T3	6		T4	11		T11	10
valid_sources[0x17]	9762	1			T3	11		T4	10		T11	11
valid_sources[0x18]	9241	1			T2	2		T3	6		T4	6
valid_sources[0x19]	9298	1			T2	2		T3	4		T4	12
valid_sources[0x1a]	9428	1			T2	1		T3	7		T4	5
valid_sources[0x1b]	18496	1			T2	1		T3	4		T4	6
valid_sources[0x1c]	9877	1			T2	1		T3	2		T4	10
valid_sources[0x1d]	9375	1			T3	4		T4	10		T11	8
valid_sources[0x1e]	9279	1			T2	4		T3	4		T4	4
valid_sources[0x1f]	11639	1			T3	9		T4	3		T11	17
valid_sources[0x20]	10242	1			T1	3		T3	2		T4	7
valid_sources[0x21]	10677	1			T3	5		T4	8		T11	1
valid_sources[0x22]	9595	1			T3	6		T4	5		T11	9
valid_sources[0x23]	9590	1			T2	2		T3	8		T4	12
valid_sources[0x24]	9635	1			T2	1		T3	4		T4	14
valid_sources[0x25]	42845	1			T2	3		T3	7		T4	8
valid_sources[0x26]	9391	1			T2	1		T3	4		T4	4
valid_sources[0x27]	9179	1			T3	4		T4	5		T11	12
valid_sources[0x28]	9346	1			T2	2		T3	6		T4	9
valid_sources[0x29]	9143	1			T3	4		T4	14		T11	11
valid_sources[0x2a]	10313	1			T2	1		T3	4		T4	12
valid_sources[0x2b]	25064	1			T1	4		T2	1		T3	3
valid_sources[0x2c]	9312	1			T2	5		T3	4		T4	9
valid_sources[0x2d]	10386	1			T2	5		T3	2		T4	11
valid_sources[0x2e]	9392	1			T2	1		T3	3		T4	11
valid_sources[0x2f]	9621	1			T2	1		T3	6		T4	13
valid_sources[0x30]	10818	1			T3	3		T4	9		T11	4
valid_sources[0x31]	9105	1			T2	1		T3	4		T4	6
valid_sources[0x32]	14163	1			T2	1		T3	5		T4	8
valid_sources[0x33]	9408	1			T1	1		T2	2		T3	1
valid_sources[0x34]	9434	1			T2	1		T3	6		T4	6
valid_sources[0x35]	9234	1			T2	7		T3	11		T4	9
valid_sources[0x36]	19962	1			T2	4		T3	3		T4	11
valid_sources[0x37]	9419	1			T1	3		T3	4		T4	7
valid_sources[0x38]	11296	1			T3	4		T4	5		T11	14
valid_sources[0x39]	9152	1			T3	6		T4	4		T11	3
valid_sources[0x3a]	14244	1			T3	6		T4	4		T11	9
valid_sources[0x3b]	10000	1			T3	8		T4	8		T11	2
valid_sources[0x3c]	9084	1			T3	3		T4	7		T11	2
valid_sources[0x3d]	9362	1			T3	4		T4	10		T11	6
valid_sources[0x3e]	9441	1			T3	4		T4	14		T11	17
valid_sources[0x3f]	9913	1			T2	1		T3	8		T4	11
valid_sources[0x40]	9937	1			T2	2		T3	4		T4	9
valid_sources[0x41]	21228	1			T3	2		T4	11		T11	2
valid_sources[0x42]	9216	1			T3	7		T4	3		T11	4
valid_sources[0x43]	9656	1			T3	4		T4	9		T11	11
valid_sources[0x44]	10023	1			T3	5		T4	11		T11	6
valid_sources[0x45]	65536	1			T3	7		T4	6		T11	2
valid_sources[0x46]	9578	1			T3	3		T4	14		T11	6
valid_sources[0x47]	10702	1			T2	2		T3	5		T4	6
valid_sources[0x48]	10737	1			T3	4		T4	11		T11	6
valid_sources[0x49]	9712	1			T3	4		T4	10		T11	1
valid_sources[0x4a]	9255	1			T2	6		T3	8		T4	7
valid_sources[0x4b]	11173	1			T3	5		T4	16		T11	13
valid_sources[0x4c]	9426	1			T2	1		T3	7		T4	9
valid_sources[0x4d]	9053	1			T2	2		T3	6		T4	6
valid_sources[0x4e]	10872	1			T3	5		T4	5		T11	16
valid_sources[0x4f]	10352	1			T2	2		T3	4		T5	838
valid_sources[0x50]	9353	1			T2	6		T3	8		T4	7
valid_sources[0x51]	19897	1			T3	5		T4	3		T11	5
valid_sources[0x52]	10042	1			T3	5		T4	14		T11	7
valid_sources[0x53]	9089	1			T3	2		T4	8		T11	4
valid_sources[0x54]	10110	1			T2	3		T3	5		T4	9
valid_sources[0x55]	9210	1			T3	4		T4	9		T11	9
valid_sources[0x56]	9210	1			T3	5		T4	10		T13	8
valid_sources[0x57]	9354	1			T3	9		T4	7		T11	4
valid_sources[0x58]	9505	1			T3	6		T4	8		T14	1
valid_sources[0x59]	9687	1			T3	5		T4	8		T11	1
valid_sources[0x5a]	9312	1			T2	1		T3	3		T4	8
valid_sources[0x5b]	17392	1			T3	6		T4	11		T11	3
valid_sources[0x5c]	144095	1			T3	3		T4	12		T11	5
valid_sources[0x5d]	9691	1			T3	4		T4	6		T11	12
valid_sources[0x5e]	9501	1			T3	6		T4	12		T11	3
valid_sources[0x5f]	13480	1			T2	14		T3	3		T4	12
valid_sources[0x60]	10490	1			T2	1		T3	7		T4	10
valid_sources[0x61]	9927	1			T2	1		T3	4		T4	5
valid_sources[0x62]	9320	1			T2	5		T3	5		T4	7
valid_sources[0x63]	9541	1			T3	6		T4	10		T11	8
valid_sources[0x64]	15369	1			T3	8		T4	10		T11	4
valid_sources[0x65]	9194	1			T3	7		T4	9		T11	5
valid_sources[0x66]	9661	1			T2	2		T3	4		T4	7
valid_sources[0x67]	10030	1			T3	5		T4	13		T11	6
valid_sources[0x68]	10544	1			T2	1		T3	2		T4	8
valid_sources[0x69]	9261	1			T2	2		T3	5		T4	11
valid_sources[0x6a]	15303	1			T1	2		T2	1		T3	7
valid_sources[0x6b]	9243	1			T3	7		T4	14		T11	3
valid_sources[0x6c]	9408	1			T3	3		T4	14		T11	1
valid_sources[0x6d]	9326	1			T1	1		T2	5		T3	4
valid_sources[0x6e]	9456	1			T1	1		T2	3		T4	13
valid_sources[0x6f]	9352	1			T3	5		T4	4		T11	7
valid_sources[0x70]	9372	1			T2	1		T3	13		T4	10
valid_sources[0x71]	11049	1			T3	5		T4	7		T11	7
valid_sources[0x72]	9171	1			T2	1		T3	4		T4	6
valid_sources[0x73]	9173	1			T1	1		T3	6		T4	9
valid_sources[0x74]	9312	1			T1	1		T2	4		T3	3
valid_sources[0x75]	9142	1			T2	1		T3	7		T4	10
valid_sources[0x76]	12292	1			T3	4		T4	6		T13	10
valid_sources[0x77]	9049	1			T3	9		T4	6		T11	10
valid_sources[0x78]	9840	1			T3	2		T5	4		T4	12
valid_sources[0x79]	9232	1			T2	2		T3	2		T4	6
valid_sources[0x7a]	9308	1			T2	4		T3	7		T4	8
valid_sources[0x7b]	9867	1			T2	1		T3	6		T4	9
valid_sources[0x7c]	12939	1			T2	3		T3	5		T4	6
valid_sources[0x7d]	10075	1			T3	4		T4	11		T11	5
valid_sources[0x7e]	9240	1			T3	8		T4	9		T11	3
valid_sources[0x7f]	9502	1			T3	6		T4	7		T11	5
valid_sources[0x80]	9539	1			T1	1		T2	7		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1357645

1

T2

54

T3

325

T5

215

values[0x0]

all_enables

biggest_size

149101

1

T1

8

T2

68

T3

279

values[0x1]

all_enables

biggest_size

147351

1

T1

4

T2

53

T3

270