Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	103252351	13702	0	0
claim_transition_if_regwen_rd_A	103252351	990	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103252351	13702	0	0
T19	0	1	0	0
T28	634239	5	0	0
T29	27621	0	0	0
T59	0	4	0	0
T64	6143	0	0	0
T76	0	2	0	0
T77	0	9	0	0
T87	0	2	0	0
T140	0	13	0	0
T141	0	3	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	25396	0	0	0
T145	1793	0	0	0
T146	6797	0	0	0
T147	31673	0	0	0
T148	28458	0	0	0
T149	10037	0	0	0
T150	5155	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103252351	990	0	0
T98	0	34	0	0
T100	0	3	0	0
T107	0	268	0	0
T128	0	7	0	0
T142	116986	1	0	0
T143	795614	0	0	0
T151	0	10	0	0
T152	0	28	0	0
T153	0	8	0	0
T154	0	23	0	0
T155	0	19	0	0
T156	1115	0	0	0
T157	7841	0	0	0
T158	4394	0	0	0
T159	31602	0	0	0
T160	18412	0	0	0
T161	164074	0	0	0
T162	29228	0	0	0
T163	8995	0	0	0