Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.25	97.92	96.12	93.40	100.00	98.52	98.51	96.29

Total test records in report: 1001

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4148606137

Jul 29 05:25:36 PM PDT 24

Jul 29 05:25:37 PM PDT 24

74203912 ps

Test location	/workspace/coverage/default/25.lc_ctrl_security_escalation.3957928174
Short name	T3
Test name
Test status
Simulation time	328409443 ps
CPU time	8.92 seconds
Started	Jul 29 05:36:42 PM PDT 24
Finished	Jul 29 05:36:52 PM PDT 24
Peak memory	225628 kb
Host	smart-19b82230-0c4c-41b3-a725-45c5808384de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957928174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3957928174
Directory	/workspace/25.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.61878326
Short name	T28
Test name
Test status
Simulation time	6606894640 ps
CPU time	181.67 seconds
Started	Jul 29 05:37:52 PM PDT 24
Finished	Jul 29 05:40:54 PM PDT 24
Peak memory	496948 kb
Host	smart-07e2b783-cd68-4c38-800e-f851b45d7052
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=61878326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.61878326
Directory	/workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_mubi.3023606218
Short name	T45
Test name
Test status
Simulation time	942484084 ps
CPU time	13.64 seconds
Started	Jul 29 05:37:09 PM PDT 24
Finished	Jul 29 05:37:22 PM PDT 24
Peak memory	226088 kb
Host	smart-834547d8-6bc8-4600-b9ca-a96bc20cd479
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023606218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3023606218
Directory	/workspace/32.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2044645717
Short name	T59
Test name
Test status
Simulation time	66056351712 ps
CPU time	1112.09 seconds
Started	Jul 29 05:35:45 PM PDT 24
Finished	Jul 29 05:54:17 PM PDT 24
Peak memory	283912 kb
Host	smart-0236f952-fcb1-46ee-a6cc-b69d80304a8b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2044645717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2044645717
Directory	/workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.lc_ctrl_errors.1646681367
Short name	T13
Test name
Test status
Simulation time	347875866 ps
CPU time	15.52 seconds
Started	Jul 29 05:35:08 PM PDT 24
Finished	Jul 29 05:35:23 PM PDT 24
Peak memory	226088 kb
Host	smart-b5d1686c-a33c-4077-89f7-e8c32b426d13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646681367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1646681367
Directory	/workspace/1.lc_ctrl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062142047
Short name	T138
Test name
Test status
Simulation time	62543944 ps
CPU time	2.44 seconds
Started	Jul 29 05:25:37 PM PDT 24
Finished	Jul 29 05:25:39 PM PDT 24
Peak memory	218772 kb
Host	smart-2ae0866f-dd5c-49c5-b18b-1413b743b5c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406214 2047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4062142047
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_cm.3380184345
Short name	T44
Test name
Test status
Simulation time	905242166 ps
CPU time	37.31 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:36:00 PM PDT 24
Peak memory	283132 kb
Host	smart-9f63e1c5-57d5-4b47-9586-b3f3a6f9defc
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380184345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3380184345
Directory	/workspace/4.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/35.lc_ctrl_security_escalation.3338113242
Short name	T20
Test name
Test status
Simulation time	1420275744 ps
CPU time	14.11 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	226076 kb
Host	smart-3349b0bc-7c27-4d78-bda5-665ac3c87fc0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338113242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3338113242
Directory	/workspace/35.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_jtag_access.3407256243
Short name	T8
Test name
Test status
Simulation time	2339029469 ps
CPU time	5.82 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:20 PM PDT 24
Peak memory	217232 kb
Host	smart-6a05bdef-de17-4bf9-8c5c-d2bec044abab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407256243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3407256243
Directory	/workspace/36.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.310166049
Short name	T98
Test name
Test status
Simulation time	232051680 ps
CPU time	2.51 seconds
Started	Jul 29 05:26:03 PM PDT 24
Finished	Jul 29 05:26:06 PM PDT 24
Peak memory	217656 kb
Host	smart-45d2ba70-9145-40de-babd-5af396388e39
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310166049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_ err.310166049
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all.4271096946
Short name	T51
Test name
Test status
Simulation time	21689751755 ps
CPU time	347.17 seconds
Started	Jul 29 05:37:13 PM PDT 24
Finished	Jul 29 05:43:01 PM PDT 24
Peak memory	251012 kb
Host	smart-77eefeb2-f5e4-4f93-a376-0b60fca7193c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271096946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.4271096946
Directory	/workspace/35.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_errors.2395479635
Short name	T164
Test name
Test status
Simulation time	572895784 ps
CPU time	16.18 seconds
Started	Jul 29 05:37:18 PM PDT 24
Finished	Jul 29 05:37:34 PM PDT 24
Peak memory	218384 kb
Host	smart-558b2040-cb95-46dc-9dbd-d1ab35c3b79e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2395479635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2395479635
Directory	/workspace/38.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_mux.578313710
Short name	T4
Test name
Test status
Simulation time	625343851 ps
CPU time	19.63 seconds
Started	Jul 29 05:36:02 PM PDT 24
Finished	Jul 29 05:36:22 PM PDT 24
Peak memory	218308 kb
Host	smart-d43c9526-b79f-4b94-8d66-c3c92959dad2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578313710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.578313710
Directory	/workspace/13.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_alert_test.3195392799
Short name	T1
Test name
Test status
Simulation time	81585521 ps
CPU time	0.99 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	209036 kb
Host	smart-03334691-e078-4eb6-9d68-7b2c392a6628
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195392799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3195392799
Directory	/workspace/10.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1514314584
Short name	T107
Test name
Test status
Simulation time	140174637 ps
CPU time	1.43 seconds
Started	Jul 29 05:25:01 PM PDT 24
Finished	Jul 29 05:25:03 PM PDT 24
Peak memory	209532 kb
Host	smart-6975cb04-c294-40ea-9b17-0482f39fc101
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514314584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin g.1514314584
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2913624515
Short name	T110
Test name
Test status
Simulation time	250779260 ps
CPU time	2.97 seconds
Started	Jul 29 05:25:42 PM PDT 24
Finished	Jul 29 05:25:45 PM PDT 24
Peak memory	222460 kb
Host	smart-88201462-8ea0-4d26-b153-01df5d3262d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913624515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.2913624515
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1069591059
Short name	T920
Test name
Test status
Simulation time	120311924 ps
CPU time	3.59 seconds
Started	Jul 29 05:25:32 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	218680 kb
Host	smart-19ad03bd-f185-409a-8e1b-e66b42858927
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069591059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1069591059
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3363452623
Short name	T123
Test name
Test status
Simulation time	237190092 ps
CPU time	3.4 seconds
Started	Jul 29 05:25:28 PM PDT 24
Finished	Jul 29 05:25:31 PM PDT 24
Peak memory	222252 kb
Host	smart-7fb8a131-2f35-4b62-b05c-66d001fb18f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363452623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_ err.3363452623
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1422193532
Short name	T118
Test name
Test status
Simulation time	42308156 ps
CPU time	1.83 seconds
Started	Jul 29 05:26:03 PM PDT 24
Finished	Jul 29 05:26:06 PM PDT 24
Peak memory	217660 kb
Host	smart-7874993f-2e2c-46b7-8a60-246552d3788b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422193532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1422193532
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3795580974
Short name	T117
Test name
Test status
Simulation time	113540793 ps
CPU time	3.16 seconds
Started	Jul 29 05:26:00 PM PDT 24
Finished	Jul 29 05:26:03 PM PDT 24
Peak memory	217608 kb
Host	smart-53dfd2ee-9782-4b44-9e4a-ddb93fce572c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795580974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg _err.3795580974
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.lc_ctrl_security_escalation.2488140301
Short name	T467
Test name
Test status
Simulation time	316885113 ps
CPU time	11.83 seconds
Started	Jul 29 05:35:11 PM PDT 24
Finished	Jul 29 05:35:23 PM PDT 24
Peak memory	226180 kb
Host	smart-340623a0-8d87-4af1-a25b-9a1ec579908a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488140301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2488140301
Directory	/workspace/1.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2292574555
Short name	T722
Test name
Test status
Simulation time	896370549 ps
CPU time	46.9 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:37:13 PM PDT 24
Peak memory	251020 kb
Host	smart-00d19147-7c2c-497b-aab6-1ed7a5c30014
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292574555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt ag_state_failure.2292574555
Directory	/workspace/19.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_mubi.3198276133
Short name	T18
Test name
Test status
Simulation time	578179927 ps
CPU time	22.38 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:37:08 PM PDT 24
Peak memory	226188 kb
Host	smart-ba60f0f4-cd5a-44cd-9642-ec8943810e20
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198276133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3198276133
Directory	/workspace/26.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1773710196
Short name	T129
Test name
Test status
Simulation time	174646695 ps
CPU time	3.65 seconds
Started	Jul 29 05:26:00 PM PDT 24
Finished	Jul 29 05:26:03 PM PDT 24
Peak memory	217664 kb
Host	smart-fb78458e-6863-4921-ad38-69bae10245fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773710196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg _err.1773710196
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2434816103
Short name	T133
Test name
Test status
Simulation time	189168795 ps
CPU time	2.91 seconds
Started	Jul 29 05:25:16 PM PDT 24
Finished	Jul 29 05:25:19 PM PDT 24
Peak memory	222632 kb
Host	smart-dce83840-4b94-4b69-87a6-21f55a00d7bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434816103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_ err.2434816103
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.561316789
Short name	T183
Test name
Test status
Simulation time	12583457 ps
CPU time	1.02 seconds
Started	Jul 29 05:24:48 PM PDT 24
Finished	Jul 29 05:24:49 PM PDT 24
Peak memory	209204 kb
Host	smart-81a99a49-33e0-405a-a42a-3c34d8c71281
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561316789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.561316789
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3390632933
Short name	T188
Test name
Test status
Simulation time	12314028 ps
CPU time	0.86 seconds
Started	Jul 29 05:25:04 PM PDT 24
Finished	Jul 29 05:25:04 PM PDT 24
Peak memory	209224 kb
Host	smart-8c4ba68a-5172-4cab-834b-03c20fa0733b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390632933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3390632933
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3891535947
Short name	T12
Test name
Test status
Simulation time	34283787 ps
CPU time	0.83 seconds
Started	Jul 29 05:37:49 PM PDT 24
Finished	Jul 29 05:37:50 PM PDT 24
Peak memory	211964 kb
Host	smart-38e53907-e840-4320-921c-c0e98b66b7ea
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891535947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c trl_volatile_unlock_smoke.3891535947
Directory	/workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_claim_transition_if.216907451
Short name	T199
Test name
Test status
Simulation time	11115346 ps
CPU time	0.97 seconds
Started	Jul 29 05:35:09 PM PDT 24
Finished	Jul 29 05:35:11 PM PDT 24
Peak memory	208888 kb
Host	smart-e17212f1-be57-4e32-891f-029b83cdb84b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216907451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.216907451
Directory	/workspace/1.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/2.lc_ctrl_claim_transition_if.816101703
Short name	T197
Test name
Test status
Simulation time	86503904 ps
CPU time	0.89 seconds
Started	Jul 29 05:35:13 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	208796 kb
Host	smart-32cf37a2-bb53-4b48-b698-26aa6c1e354c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=816101703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.816101703
Directory	/workspace/2.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/4.lc_ctrl_claim_transition_if.2562994124
Short name	T200
Test name
Test status
Simulation time	11253906 ps
CPU time	0.81 seconds
Started	Jul 29 05:35:28 PM PDT 24
Finished	Jul 29 05:35:29 PM PDT 24
Peak memory	208780 kb
Host	smart-3bc5c2db-ea4b-49f7-be41-1e60c9f6bc11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562994124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2562994124
Directory	/workspace/4.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/5.lc_ctrl_claim_transition_if.790711760
Short name	T202
Test name
Test status
Simulation time	12551033 ps
CPU time	0.98 seconds
Started	Jul 29 05:35:33 PM PDT 24
Finished	Jul 29 05:35:34 PM PDT 24
Peak memory	208888 kb
Host	smart-a8804952-b28d-4696-8889-05959c690217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790711760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.790711760
Directory	/workspace/5.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_mux.3896308525
Short name	T21
Test name
Test status
Simulation time	1514591469 ps
CPU time	10.33 seconds
Started	Jul 29 05:37:38 PM PDT 24
Finished	Jul 29 05:37:49 PM PDT 24
Peak memory	226136 kb
Host	smart-a1e49b34-2a3c-4e07-9f15-14429a59d566
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896308525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 3896308525
Directory	/workspace/45.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2107147317
Short name	T914
Test name
Test status
Simulation time	3356484049 ps
CPU time	4.24 seconds
Started	Jul 29 05:24:51 PM PDT 24
Finished	Jul 29 05:24:55 PM PDT 24
Peak memory	208732 kb
Host	smart-ffc04819-bf0e-4d8f-8c04-bf16574d7edd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107147317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2107147317
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3029920486
Short name	T126
Test name
Test status
Simulation time	304601062 ps
CPU time	3.57 seconds
Started	Jul 29 05:24:52 PM PDT 24
Finished	Jul 29 05:24:56 PM PDT 24
Peak memory	213568 kb
Host	smart-4ca8fb5f-dd32-42be-92eb-08fd35a5a897
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029920486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_ err.3029920486
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.744308772
Short name	T121
Test name
Test status
Simulation time	66133351 ps
CPU time	1.82 seconds
Started	Jul 29 05:24:59 PM PDT 24
Finished	Jul 29 05:25:01 PM PDT 24
Peak memory	221880 kb
Host	smart-32624d41-8df0-4162-a88b-8a47869a2521
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744308772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e rr.744308772
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.882200980
Short name	T127
Test name
Test status
Simulation time	68983906 ps
CPU time	2.79 seconds
Started	Jul 29 05:25:45 PM PDT 24
Finished	Jul 29 05:25:48 PM PDT 24
Peak memory	217524 kb
Host	smart-016ec018-31ea-4ccf-ab89-11c443447896
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882200980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_ err.882200980
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4162903645
Short name	T102
Test name
Test status
Simulation time	259921371 ps
CPU time	2.6 seconds
Started	Jul 29 05:25:57 PM PDT 24
Finished	Jul 29 05:25:59 PM PDT 24
Peak memory	217656 kb
Host	smart-3f201a2d-168f-4fb9-b542-312d260083d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162903645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg _err.4162903645
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2601447836
Short name	T103
Test name
Test status
Simulation time	80628422 ps
CPU time	2.86 seconds
Started	Jul 29 05:26:00 PM PDT 24
Finished	Jul 29 05:26:03 PM PDT 24
Peak memory	222216 kb
Host	smart-b77044f3-2dd6-40e3-8d88-728091a2ec80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601447836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg _err.2601447836
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1183499550
Short name	T122
Test name
Test status
Simulation time	84969997 ps
CPU time	2.71 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	222564 kb
Host	smart-f4529aac-a9a2-4dfa-91eb-bef0d3963893
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183499550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_ err.1183499550
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all.1178883568
Short name	T53
Test name
Test status
Simulation time	48369178512 ps
CPU time	210.37 seconds
Started	Jul 29 05:35:07 PM PDT 24
Finished	Jul 29 05:38:37 PM PDT 24
Peak memory	283836 kb
Host	smart-a7aaa7d8-eadb-49ee-af2e-00d5ce456be7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178883568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.1178883568
Directory	/workspace/0.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_errors.300069148
Short name	T50
Test name
Test status
Simulation time	1138101347 ps
CPU time	14.05 seconds
Started	Jul 29 05:36:47 PM PDT 24
Finished	Jul 29 05:37:01 PM PDT 24
Peak memory	218232 kb
Host	smart-ff5224ea-e603-4247-825d-7fdae485b65c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300069148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.300069148
Directory	/workspace/24.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_access.3858911910
Short name	T7
Test name
Test status
Simulation time	542017300 ps
CPU time	3.82 seconds
Started	Jul 29 05:35:09 PM PDT 24
Finished	Jul 29 05:35:13 PM PDT 24
Peak memory	217364 kb
Host	smart-7ce1b859-19aa-4e5b-90ef-3a40a3aee225
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858911910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3858911910
Directory	/workspace/1.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.796036560
Short name	T6
Test name
Test status
Simulation time	2485079544 ps
CPU time	8.31 seconds
Started	Jul 29 05:36:22 PM PDT 24
Finished	Jul 29 05:36:30 PM PDT 24
Peak memory	218256 kb
Host	smart-40fb747e-1f5d-4470-b2e4-84cbe2d31bfd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796036560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag _prog_failure.796036560
Directory	/workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3663328307
Short name	T966
Test name
Test status
Simulation time	30252114 ps
CPU time	1.23 seconds
Started	Jul 29 05:24:56 PM PDT 24
Finished	Jul 29 05:24:57 PM PDT 24
Peak memory	209508 kb
Host	smart-69316396-7083-40df-90b9-d34899ab77a6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663328307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.3663328307
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.154889174
Short name	T877
Test name
Test status
Simulation time	25459221 ps
CPU time	1.46 seconds
Started	Jul 29 05:24:51 PM PDT 24
Finished	Jul 29 05:24:53 PM PDT 24
Peak memory	209312 kb
Host	smart-28cec23b-fe9a-491e-984f-aa964ddf7623
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154889174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash .154889174
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2432343993
Short name	T990
Test name
Test status
Simulation time	55901419 ps
CPU time	0.99 seconds
Started	Jul 29 05:24:51 PM PDT 24
Finished	Jul 29 05:24:53 PM PDT 24
Peak memory	210112 kb
Host	smart-428bd1a2-7ab9-4d0c-abe2-1a926e4170a6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432343993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese t.2432343993
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.570648866
Short name	T924
Test name
Test status
Simulation time	48600233 ps
CPU time	1.53 seconds
Started	Jul 29 05:24:58 PM PDT 24
Finished	Jul 29 05:25:00 PM PDT 24
Peak memory	217744 kb
Host	smart-4ba03739-ab5b-4bc7-a724-17161c78d0f0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570648866 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.570648866
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.922041194
Short name	T963
Test name
Test status
Simulation time	81423286 ps
CPU time	1.63 seconds
Started	Jul 29 05:24:51 PM PDT 24
Finished	Jul 29 05:24:53 PM PDT 24
Peak memory	208112 kb
Host	smart-7032d961-287e-4ef1-a97f-086b8b775d88
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922041194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.lc_ctrl_jtag_alert_test.922041194
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1693887570
Short name	T139
Test name
Test status
Simulation time	833556767 ps
CPU time	9.95 seconds
Started	Jul 29 05:24:50 PM PDT 24
Finished	Jul 29 05:25:00 PM PDT 24
Peak memory	209572 kb
Host	smart-f2d9e81b-00a3-4057-8229-1ba2c352946b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693887570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1693887570
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3618416378
Short name	T975
Test name
Test status
Simulation time	695219611 ps
CPU time	1.85 seconds
Started	Jul 29 05:24:52 PM PDT 24
Finished	Jul 29 05:24:54 PM PDT 24
Peak memory	211020 kb
Host	smart-c1b16122-81c5-47ba-ba88-79ee890f5b02
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618416378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3618416378
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1699001231
Short name	T919
Test name
Test status
Simulation time	157541526 ps
CPU time	2.04 seconds
Started	Jul 29 05:24:51 PM PDT 24
Finished	Jul 29 05:24:54 PM PDT 24
Peak memory	218680 kb
Host	smart-6877f0e0-0a56-4f3a-877e-730d5745e924
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169900 1231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1699001231
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3349554164
Short name	T953
Test name
Test status
Simulation time	38660357 ps
CPU time	1.13 seconds
Started	Jul 29 05:24:49 PM PDT 24
Finished	Jul 29 05:24:50 PM PDT 24
Peak memory	209400 kb
Host	smart-58af9be3-8f31-4cc9-8367-f5f5f48bc34b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349554164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.3349554164
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3055987579
Short name	T969
Test name
Test status
Simulation time	50528385 ps
CPU time	1.34 seconds
Started	Jul 29 05:24:48 PM PDT 24
Finished	Jul 29 05:24:49 PM PDT 24
Peak memory	208880 kb
Host	smart-ff80b370-401b-494c-bab2-ace27dd6c9aa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055987579 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3055987579
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.785799564
Short name	T928
Test name
Test status
Simulation time	30762378 ps
CPU time	1.1 seconds
Started	Jul 29 05:24:59 PM PDT 24
Finished	Jul 29 05:25:00 PM PDT 24
Peak memory	209496 kb
Host	smart-707267ce-d761-4865-8b85-fc9a92754098
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785799564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ same_csr_outstanding.785799564
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3427194961
Short name	T999
Test name
Test status
Simulation time	143066399 ps
CPU time	1.83 seconds
Started	Jul 29 05:24:52 PM PDT 24
Finished	Jul 29 05:24:54 PM PDT 24
Peak memory	217580 kb
Host	smart-53fc5fdc-6ebf-4f56-a9da-463bd29179dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427194961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3427194961
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2706825865
Short name	T905
Test name
Test status
Simulation time	52365369 ps
CPU time	1.69 seconds
Started	Jul 29 05:25:02 PM PDT 24
Finished	Jul 29 05:25:04 PM PDT 24
Peak memory	209488 kb
Host	smart-3c60f442-6fb1-448b-899f-159efa475244
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706825865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.2706825865
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.630529884
Short name	T933
Test name
Test status
Simulation time	64665858 ps
CPU time	1 seconds
Started	Jul 29 05:25:00 PM PDT 24
Finished	Jul 29 05:25:01 PM PDT 24
Peak memory	218000 kb
Host	smart-f4d92fdd-fc9c-4fc7-9786-ab153b36dc90
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630529884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset .630529884
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.790958732
Short name	T941
Test name
Test status
Simulation time	31050063 ps
CPU time	2.07 seconds
Started	Jul 29 05:25:01 PM PDT 24
Finished	Jul 29 05:25:03 PM PDT 24
Peak memory	219352 kb
Host	smart-d8e027c4-d880-4bed-9ead-5dd648894d31
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790958732 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.790958732
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1480615346
Short name	T881
Test name
Test status
Simulation time	59386674 ps
CPU time	1.34 seconds
Started	Jul 29 05:24:59 PM PDT 24
Finished	Jul 29 05:25:00 PM PDT 24
Peak memory	209364 kb
Host	smart-5db5d826-aa7f-4b4f-8b5a-518d87b40126
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480615346 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1480615346
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3269339641
Short name	T889
Test name
Test status
Simulation time	444776783 ps
CPU time	11.28 seconds
Started	Jul 29 05:24:54 PM PDT 24
Finished	Jul 29 05:25:06 PM PDT 24
Peak memory	209292 kb
Host	smart-7ebe48ae-835e-448b-94fe-49dc5bf9b1ca
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269339641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3269339641
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2553655601
Short name	T113
Test name
Test status
Simulation time	353560372 ps
CPU time	9.63 seconds
Started	Jul 29 05:25:00 PM PDT 24
Finished	Jul 29 05:25:09 PM PDT 24
Peak memory	208248 kb
Host	smart-a9ff1c76-7b80-4064-be8d-cbaab252e8f1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553655601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2553655601
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.954993819
Short name	T891
Test name
Test status
Simulation time	46294546 ps
CPU time	1.9 seconds
Started	Jul 29 05:24:57 PM PDT 24
Finished	Jul 29 05:24:59 PM PDT 24
Peak memory	211028 kb
Host	smart-c4d1b64d-33b7-4fec-9063-9c6fa3b52f60
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954993819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.954993819
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.204694018
Short name	T942
Test name
Test status
Simulation time	116777656 ps
CPU time	2.23 seconds
Started	Jul 29 05:24:56 PM PDT 24
Finished	Jul 29 05:24:59 PM PDT 24
Peak memory	218048 kb
Host	smart-938c75fc-8dc7-4fd1-91b1-0b8b8de0bc46
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204694 018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.204694018
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.493243508
Short name	T961
Test name
Test status
Simulation time	249018848 ps
CPU time	3.45 seconds
Started	Jul 29 05:24:55 PM PDT 24
Finished	Jul 29 05:24:58 PM PDT 24
Peak memory	209408 kb
Host	smart-746c303a-0b1c-416a-804e-9584f9f11eb1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493243508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.493243508
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1878621644
Short name	T997
Test name
Test status
Simulation time	33049703 ps
CPU time	1.1 seconds
Started	Jul 29 05:24:58 PM PDT 24
Finished	Jul 29 05:24:59 PM PDT 24
Peak memory	209448 kb
Host	smart-6a87d6f0-fef1-49d0-b196-0a110d22ad84
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878621644 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1878621644
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1386180641
Short name	T105
Test name
Test status
Simulation time	105713324 ps
CPU time	1.23 seconds
Started	Jul 29 05:25:02 PM PDT 24
Finished	Jul 29 05:25:03 PM PDT 24
Peak memory	209488 kb
Host	smart-7aa05988-b692-4754-80d1-f75dcbee0883
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386180641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _same_csr_outstanding.1386180641
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1330753622
Short name	T992
Test name
Test status
Simulation time	36364688 ps
CPU time	2.19 seconds
Started	Jul 29 05:24:58 PM PDT 24
Finished	Jul 29 05:25:00 PM PDT 24
Peak memory	217720 kb
Host	smart-7d9f08aa-61b7-48b4-a53a-cf4dbe01f6af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330753622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1330753622
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.547642944
Short name	T959
Test name
Test status
Simulation time	30930752 ps
CPU time	1.33 seconds
Started	Jul 29 05:25:45 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	217912 kb
Host	smart-e6afe282-a9e8-4473-b3bc-c9f94f038bff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547642944 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.547642944
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3416778320
Short name	T876
Test name
Test status
Simulation time	20054497 ps
CPU time	0.89 seconds
Started	Jul 29 05:25:45 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	209312 kb
Host	smart-c045f943-fa08-4794-9893-af25e4d7745a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416778320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3416778320
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1382421464
Short name	T908
Test name
Test status
Simulation time	135097526 ps
CPU time	1.29 seconds
Started	Jul 29 05:25:43 PM PDT 24
Finished	Jul 29 05:25:45 PM PDT 24
Peak memory	211400 kb
Host	smart-93028590-45ca-4a2d-b458-3361e60696af
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382421464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.1382421464
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1836643036
Short name	T987
Test name
Test status
Simulation time	45674022 ps
CPU time	3.38 seconds
Started	Jul 29 05:25:43 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	218472 kb
Host	smart-4d2f8c77-6d59-405e-aea1-7985bd9da8f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836643036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1836643036
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4220373813
Short name	T993
Test name
Test status
Simulation time	20181510 ps
CPU time	1.45 seconds
Started	Jul 29 05:25:44 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	219776 kb
Host	smart-d58865d8-1592-4e30-a502-e82f8b1bad07
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220373813 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4220373813
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.287593650
Short name	T1000
Test name
Test status
Simulation time	16594407 ps
CPU time	0.96 seconds
Started	Jul 29 05:25:43 PM PDT 24
Finished	Jul 29 05:25:45 PM PDT 24
Peak memory	209384 kb
Host	smart-864678aa-96a3-425c-9c14-bb9892e7e163
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287593650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.287593650
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3727720196
Short name	T964
Test name
Test status
Simulation time	15869734 ps
CPU time	1.16 seconds
Started	Jul 29 05:25:46 PM PDT 24
Finished	Jul 29 05:25:47 PM PDT 24
Peak memory	209552 kb
Host	smart-423edb40-572f-447a-a9ac-fc10d8d85e6a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727720196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_same_csr_outstanding.3727720196
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1008407978
Short name	T926
Test name
Test status
Simulation time	44124977 ps
CPU time	2.84 seconds
Started	Jul 29 05:25:44 PM PDT 24
Finished	Jul 29 05:25:47 PM PDT 24
Peak memory	217684 kb
Host	smart-5037484d-a6cc-4580-8e2f-db647afb3e75
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008407978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1008407978
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1688567393
Short name	T988
Test name
Test status
Simulation time	21752349 ps
CPU time	1.11 seconds
Started	Jul 29 05:25:51 PM PDT 24
Finished	Jul 29 05:25:52 PM PDT 24
Peak memory	218800 kb
Host	smart-f399fc47-5eb2-4117-b70b-a748ebe06cdd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688567393 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1688567393
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2716903076
Short name	T902
Test name
Test status
Simulation time	124452588 ps
CPU time	0.8 seconds
Started	Jul 29 05:25:49 PM PDT 24
Finished	Jul 29 05:25:50 PM PDT 24
Peak memory	209312 kb
Host	smart-17c6ec96-92de-453c-a73a-f7f6c7973752
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716903076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2716903076
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3333464925
Short name	T948
Test name
Test status
Simulation time	67723903 ps
CPU time	1.43 seconds
Started	Jul 29 05:25:58 PM PDT 24
Finished	Jul 29 05:25:59 PM PDT 24
Peak memory	209456 kb
Host	smart-d43a0453-fe2a-4eec-a3f1-fece08e9b91c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333464925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.3333464925
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.313181755
Short name	T99
Test name
Test status
Simulation time	98676714 ps
CPU time	3.15 seconds
Started	Jul 29 05:25:43 PM PDT 24
Finished	Jul 29 05:25:47 PM PDT 24
Peak memory	217636 kb
Host	smart-5d95b9ba-5a63-47e8-bcca-16385162684d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313181755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.313181755
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.975152752
Short name	T128
Test name
Test status
Simulation time	52183116 ps
CPU time	1.28 seconds
Started	Jul 29 05:25:48 PM PDT 24
Finished	Jul 29 05:25:49 PM PDT 24
Peak memory	217852 kb
Host	smart-8c01fb26-e8b5-4749-a4ff-4f4e3e28672e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975152752 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.975152752
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.146191782
Short name	T912
Test name
Test status
Simulation time	77915479 ps
CPU time	0.94 seconds
Started	Jul 29 05:26:00 PM PDT 24
Finished	Jul 29 05:26:01 PM PDT 24
Peak memory	209500 kb
Host	smart-e8051537-eab0-4d63-89d2-9d36197c8cdb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146191782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.146191782
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2253706197
Short name	T906
Test name
Test status
Simulation time	117085199 ps
CPU time	1.38 seconds
Started	Jul 29 05:25:54 PM PDT 24
Finished	Jul 29 05:25:55 PM PDT 24
Peak memory	209576 kb
Host	smart-57eec607-3932-4365-9575-9107e75fe3d3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253706197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.2253706197
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1396128425
Short name	T116
Test name
Test status
Simulation time	214442995 ps
CPU time	3.02 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:03 PM PDT 24
Peak memory	218012 kb
Host	smart-42594cd0-5e7e-4262-bb3d-c491bedff4f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396128425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1396128425
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2717271445
Short name	T124
Test name
Test status
Simulation time	123534500 ps
CPU time	1.96 seconds
Started	Jul 29 05:26:00 PM PDT 24
Finished	Jul 29 05:26:02 PM PDT 24
Peak memory	222384 kb
Host	smart-9d7963d7-de3f-4848-bd3f-fec7c524fb9d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717271445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.2717271445
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.365338090
Short name	T104
Test name
Test status
Simulation time	62384783 ps
CPU time	1.22 seconds
Started	Jul 29 05:25:57 PM PDT 24
Finished	Jul 29 05:25:58 PM PDT 24
Peak memory	217860 kb
Host	smart-d30ab22a-fbcf-44b5-b73d-a9106b4cc4dc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365338090 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.365338090
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1876750015
Short name	T134
Test name
Test status
Simulation time	114347933 ps
CPU time	1.03 seconds
Started	Jul 29 05:25:57 PM PDT 24
Finished	Jul 29 05:25:58 PM PDT 24
Peak memory	209496 kb
Host	smart-e6c05070-4021-4b8f-98b8-1fbd3d03ea93
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876750015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1876750015
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.40870633
Short name	T922
Test name
Test status
Simulation time	189966238 ps
CPU time	1.66 seconds
Started	Jul 29 05:26:02 PM PDT 24
Finished	Jul 29 05:26:04 PM PDT 24
Peak memory	209544 kb
Host	smart-a3c34358-e617-4452-9236-28c07c13c7be
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40870633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_ same_csr_outstanding.40870633
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.130843179
Short name	T998
Test name
Test status
Simulation time	126043058 ps
CPU time	3.31 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:02 PM PDT 24
Peak memory	217672 kb
Host	smart-c9b26fb9-cd94-45ba-b226-2e8dab4f29f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130843179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.130843179
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.149720008
Short name	T120
Test name
Test status
Simulation time	121008993 ps
CPU time	3.24 seconds
Started	Jul 29 05:26:01 PM PDT 24
Finished	Jul 29 05:26:04 PM PDT 24
Peak memory	222536 kb
Host	smart-95a5b42d-4a4f-4932-b9f9-d7333b7356fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149720008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_ err.149720008
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.397987149
Short name	T994
Test name
Test status
Simulation time	139314958 ps
CPU time	1.32 seconds
Started	Jul 29 05:26:01 PM PDT 24
Finished	Jul 29 05:26:02 PM PDT 24
Peak memory	217720 kb
Host	smart-9f80e291-ba49-4669-9a3f-22c1b360272d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397987149 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.397987149
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2248190969
Short name	T153
Test name
Test status
Simulation time	64339558 ps
CPU time	0.89 seconds
Started	Jul 29 05:25:58 PM PDT 24
Finished	Jul 29 05:25:59 PM PDT 24
Peak memory	209476 kb
Host	smart-115915c0-08ac-48e8-aec8-c66aa76ef5c7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248190969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2248190969
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.863408472
Short name	T193
Test name
Test status
Simulation time	24834443 ps
CPU time	1.06 seconds
Started	Jul 29 05:26:00 PM PDT 24
Finished	Jul 29 05:26:01 PM PDT 24
Peak memory	209632 kb
Host	smart-d08b8ab7-5778-4752-b4bf-5781d1fc4589
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863408472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _same_csr_outstanding.863408472
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1508767419
Short name	T940
Test name
Test status
Simulation time	226978674 ps
CPU time	3.57 seconds
Started	Jul 29 05:26:00 PM PDT 24
Finished	Jul 29 05:26:04 PM PDT 24
Peak memory	217616 kb
Host	smart-c7d5e9a6-a451-4244-a6c6-89fa0ac904b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508767419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1508767419
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2858029369
Short name	T152
Test name
Test status
Simulation time	25944733 ps
CPU time	1.21 seconds
Started	Jul 29 05:25:57 PM PDT 24
Finished	Jul 29 05:25:58 PM PDT 24
Peak memory	217780 kb
Host	smart-7540d8b8-96e4-4a34-a37e-595af3ee875b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858029369 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2858029369
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1065625217
Short name	T106
Test name
Test status
Simulation time	17472001 ps
CPU time	1.11 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:01 PM PDT 24
Peak memory	209324 kb
Host	smart-b2f64e01-c090-41b1-9404-310e9ecb4e7e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065625217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1065625217
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2711460280
Short name	T923
Test name
Test status
Simulation time	49608450 ps
CPU time	1.22 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:01 PM PDT 24
Peak memory	209484 kb
Host	smart-5d7d8b0f-0aaa-4bc2-b9b3-7ccced551c98
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711460280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.2711460280
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2888157529
Short name	T957
Test name
Test status
Simulation time	42009645 ps
CPU time	2.65 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:02 PM PDT 24
Peak memory	217788 kb
Host	smart-03202e19-ec3a-4548-b387-3173ad307590
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888157529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2888157529
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3314433207
Short name	T204
Test name
Test status
Simulation time	48195359 ps
CPU time	1.97 seconds
Started	Jul 29 05:26:01 PM PDT 24
Finished	Jul 29 05:26:03 PM PDT 24
Peak memory	222236 kb
Host	smart-3c68b952-5114-471e-ac39-57da03b56889
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314433207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg _err.3314433207
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2126500182
Short name	T894
Test name
Test status
Simulation time	71383028 ps
CPU time	1.48 seconds
Started	Jul 29 05:26:01 PM PDT 24
Finished	Jul 29 05:26:02 PM PDT 24
Peak memory	217924 kb
Host	smart-7efa22db-1faf-4a94-89f1-7b06e598577c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126500182 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2126500182
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1532339896
Short name	T880
Test name
Test status
Simulation time	55425984 ps
CPU time	0.98 seconds
Started	Jul 29 05:25:56 PM PDT 24
Finished	Jul 29 05:25:57 PM PDT 24
Peak memory	209468 kb
Host	smart-fbd2e728-e6ab-44fc-90f1-8f47eab79c77
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532339896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1532339896
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2345454254
Short name	T910
Test name
Test status
Simulation time	21027900 ps
CPU time	1.44 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:00 PM PDT 24
Peak memory	209448 kb
Host	smart-68c2995e-3c2a-4178-a4b6-aedc7214b275
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345454254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_same_csr_outstanding.2345454254
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3706878089
Short name	T976
Test name
Test status
Simulation time	51442135 ps
CPU time	2.56 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:02 PM PDT 24
Peak memory	218732 kb
Host	smart-ddd3d6b4-3b39-489e-bd12-ff137c2e03a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706878089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3706878089
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.563008083
Short name	T115
Test name
Test status
Simulation time	21828523 ps
CPU time	1.78 seconds
Started	Jul 29 05:26:03 PM PDT 24
Finished	Jul 29 05:26:05 PM PDT 24
Peak memory	219632 kb
Host	smart-3903e43c-fa62-4b37-8782-734cc30192fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563008083 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.563008083
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3026152052
Short name	T916
Test name
Test status
Simulation time	27855536 ps
CPU time	0.88 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:00 PM PDT 24
Peak memory	209452 kb
Host	smart-544f3d9d-8800-4342-979f-27b5a74248e2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026152052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3026152052
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3826911447
Short name	T194
Test name
Test status
Simulation time	77454480 ps
CPU time	1.44 seconds
Started	Jul 29 05:26:02 PM PDT 24
Finished	Jul 29 05:26:04 PM PDT 24
Peak memory	211688 kb
Host	smart-6f0ccb12-91f6-4327-8e3b-68e1d642c333
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826911447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.3826911447
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2802486863
Short name	T101
Test name
Test status
Simulation time	50870253 ps
CPU time	1.16 seconds
Started	Jul 29 05:26:02 PM PDT 24
Finished	Jul 29 05:26:04 PM PDT 24
Peak memory	217696 kb
Host	smart-7f2dbba0-5da7-42b1-a928-f92a0e127118
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802486863 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2802486863
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3461340580
Short name	T977
Test name
Test status
Simulation time	36813885 ps
CPU time	0.86 seconds
Started	Jul 29 05:26:01 PM PDT 24
Finished	Jul 29 05:26:02 PM PDT 24
Peak memory	209008 kb
Host	smart-6e7e248f-8fb6-4d5c-ad87-783f48cb7b7c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461340580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3461340580
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3688019764
Short name	T938
Test name
Test status
Simulation time	26601366 ps
CPU time	1.08 seconds
Started	Jul 29 05:26:03 PM PDT 24
Finished	Jul 29 05:26:04 PM PDT 24
Peak memory	209380 kb
Host	smart-7761d617-9685-4534-a34f-2f8fd433458f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688019764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_same_csr_outstanding.3688019764
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.384322007
Short name	T974
Test name
Test status
Simulation time	512194987 ps
CPU time	3.84 seconds
Started	Jul 29 05:25:59 PM PDT 24
Finished	Jul 29 05:26:03 PM PDT 24
Peak memory	218668 kb
Host	smart-ae9994e3-1ecd-4fb1-8c3b-d301fda5d358
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384322007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.384322007
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3297996624
Short name	T884
Test name
Test status
Simulation time	326349466 ps
CPU time	1.61 seconds
Started	Jul 29 05:25:14 PM PDT 24
Finished	Jul 29 05:25:15 PM PDT 24
Peak memory	209460 kb
Host	smart-46849ffb-3f2a-44b5-8583-6dc6a931f3ae
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297996624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.3297996624
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3620450235
Short name	T189
Test name
Test status
Simulation time	73452233 ps
CPU time	1.17 seconds
Started	Jul 29 05:25:16 PM PDT 24
Finished	Jul 29 05:25:17 PM PDT 24
Peak memory	208412 kb
Host	smart-965a27f4-2ade-4bd4-a08b-cf4bbc804775
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620450235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.3620450235
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1091457084
Short name	T114
Test name
Test status
Simulation time	32885015 ps
CPU time	0.96 seconds
Started	Jul 29 05:25:16 PM PDT 24
Finished	Jul 29 05:25:17 PM PDT 24
Peak memory	209956 kb
Host	smart-a0fe800f-e106-4696-ae1b-5d0b705ef80a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091457084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.1091457084
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1207084539
Short name	T903
Test name
Test status
Simulation time	156826457 ps
CPU time	1.31 seconds
Started	Jul 29 05:25:17 PM PDT 24
Finished	Jul 29 05:25:18 PM PDT 24
Peak memory	217720 kb
Host	smart-5f77d617-18da-4c75-ad41-fe04cf9c0830
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207084539 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1207084539
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1134470704
Short name	T915
Test name
Test status
Simulation time	18238623 ps
CPU time	0.96 seconds
Started	Jul 29 05:25:17 PM PDT 24
Finished	Jul 29 05:25:18 PM PDT 24
Peak memory	209380 kb
Host	smart-f10f7d9b-edff-4a3e-8350-55d290fe82f4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134470704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1134470704
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1110903589
Short name	T883
Test name
Test status
Simulation time	75678514 ps
CPU time	2.5 seconds
Started	Jul 29 05:25:16 PM PDT 24
Finished	Jul 29 05:25:19 PM PDT 24
Peak memory	209180 kb
Host	smart-0a2b4a22-2c6d-4122-910d-c8b1885e9bd4
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110903589 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1110903589
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3259327407
Short name	T137
Test name
Test status
Simulation time	372964599 ps
CPU time	4.63 seconds
Started	Jul 29 05:25:17 PM PDT 24
Finished	Jul 29 05:25:22 PM PDT 24
Peak memory	208656 kb
Host	smart-7c87b7c2-1e33-47a3-aa44-d608f909b4e8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259327407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3259327407
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.510957067
Short name	T886
Test name
Test status
Simulation time	6810292211 ps
CPU time	9.24 seconds
Started	Jul 29 05:25:01 PM PDT 24
Finished	Jul 29 05:25:11 PM PDT 24
Peak memory	209440 kb
Host	smart-aa81df62-9106-465d-a3e6-808f12ceeee1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510957067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.510957067
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4152734270
Short name	T898
Test name
Test status
Simulation time	227736891 ps
CPU time	2.11 seconds
Started	Jul 29 05:25:02 PM PDT 24
Finished	Jul 29 05:25:04 PM PDT 24
Peak memory	210928 kb
Host	smart-15d6ea2a-72b3-4c8b-9829-df47b0691a80
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152734270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4152734270
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3695211764
Short name	T937
Test name
Test status
Simulation time	325418329 ps
CPU time	2.93 seconds
Started	Jul 29 05:25:14 PM PDT 24
Finished	Jul 29 05:25:17 PM PDT 24
Peak memory	218764 kb
Host	smart-0bd3a61f-5544-4655-b5d0-5cd309fcd3d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369521 1764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3695211764
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4089603387
Short name	T944
Test name
Test status
Simulation time	164525673 ps
CPU time	1.07 seconds
Started	Jul 29 05:25:04 PM PDT 24
Finished	Jul 29 05:25:05 PM PDT 24
Peak memory	209376 kb
Host	smart-e5a07596-2efe-479a-bf4c-a1b1697a0937
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089603387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.4089603387
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1049665996
Short name	T917
Test name
Test status
Simulation time	107843561 ps
CPU time	0.94 seconds
Started	Jul 29 05:25:14 PM PDT 24
Finished	Jul 29 05:25:15 PM PDT 24
Peak memory	209448 kb
Host	smart-91266f96-178e-438d-85b7-b16731dd6320
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049665996 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1049665996
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.983304519
Short name	T192
Test name
Test status
Simulation time	185567111 ps
CPU time	1.38 seconds
Started	Jul 29 05:25:15 PM PDT 24
Finished	Jul 29 05:25:17 PM PDT 24
Peak memory	209552 kb
Host	smart-ea970fcd-4147-43f6-8390-871ea7333164
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983304519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ same_csr_outstanding.983304519
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1134632815
Short name	T119
Test name
Test status
Simulation time	88718960 ps
CPU time	2.84 seconds
Started	Jul 29 05:25:13 PM PDT 24
Finished	Jul 29 05:25:16 PM PDT 24
Peak memory	218116 kb
Host	smart-91bd6be6-0197-42e1-b871-9737478c9119
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134632815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1134632815
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2590482169
Short name	T187
Test name
Test status
Simulation time	48834839 ps
CPU time	1.39 seconds
Started	Jul 29 05:25:29 PM PDT 24
Finished	Jul 29 05:25:30 PM PDT 24
Peak memory	209460 kb
Host	smart-f39f8f79-c4ca-49e9-9ce0-2198011abbcb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590482169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.2590482169
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3515289105
Short name	T946
Test name
Test status
Simulation time	129965624 ps
CPU time	1.31 seconds
Started	Jul 29 05:25:27 PM PDT 24
Finished	Jul 29 05:25:28 PM PDT 24
Peak memory	208164 kb
Host	smart-1a56e2af-d4cf-4cce-88a2-273abfb7bbf3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515289105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.3515289105
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1084042256
Short name	T186
Test name
Test status
Simulation time	15387063 ps
CPU time	0.95 seconds
Started	Jul 29 05:25:27 PM PDT 24
Finished	Jul 29 05:25:28 PM PDT 24
Peak memory	210016 kb
Host	smart-14a7a758-4271-4529-967f-7b09386610d3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084042256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.1084042256
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3983240833
Short name	T125
Test name
Test status
Simulation time	86634224 ps
CPU time	1.5 seconds
Started	Jul 29 05:25:26 PM PDT 24
Finished	Jul 29 05:25:28 PM PDT 24
Peak memory	217860 kb
Host	smart-3bc2097d-739f-4eed-a17e-cec4b58be032
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983240833 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3983240833
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1572319111
Short name	T184
Test name
Test status
Simulation time	15971311 ps
CPU time	1.13 seconds
Started	Jul 29 05:25:26 PM PDT 24
Finished	Jul 29 05:25:27 PM PDT 24
Peak memory	209472 kb
Host	smart-5375c24d-ab64-4a67-a901-09ea465c5b03
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572319111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1572319111
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2252383686
Short name	T882
Test name
Test status
Simulation time	136967284 ps
CPU time	1.07 seconds
Started	Jul 29 05:25:29 PM PDT 24
Finished	Jul 29 05:25:31 PM PDT 24
Peak memory	209284 kb
Host	smart-0cbcfa28-ca0f-44c9-96bf-cc61e3011f90
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252383686 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2252383686
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1394952701
Short name	T995
Test name
Test status
Simulation time	926489222 ps
CPU time	4.39 seconds
Started	Jul 29 05:25:28 PM PDT 24
Finished	Jul 29 05:25:33 PM PDT 24
Peak memory	209292 kb
Host	smart-2d16d608-eb2d-46d5-8ad2-b56eec126eaa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394952701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1394952701
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3383959409
Short name	T901
Test name
Test status
Simulation time	1812655260 ps
CPU time	22.26 seconds
Started	Jul 29 05:25:29 PM PDT 24
Finished	Jul 29 05:25:52 PM PDT 24
Peak memory	209412 kb
Host	smart-0ba305bc-e9c8-4350-a2a8-284bb1c4939b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383959409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3383959409
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.850305753
Short name	T892
Test name
Test status
Simulation time	193223842 ps
CPU time	1.83 seconds
Started	Jul 29 05:25:28 PM PDT 24
Finished	Jul 29 05:25:30 PM PDT 24
Peak memory	210888 kb
Host	smart-d8a5ea92-92bb-40cd-99b3-f1899e173097
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850305753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.850305753
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1292256341
Short name	T911
Test name
Test status
Simulation time	356407399 ps
CPU time	1.74 seconds
Started	Jul 29 05:25:27 PM PDT 24
Finished	Jul 29 05:25:29 PM PDT 24
Peak memory	218600 kb
Host	smart-a6c59dcb-42cd-4144-8376-f829a7d8a5f8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129225 6341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1292256341
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.966952742
Short name	T945
Test name
Test status
Simulation time	95044636 ps
CPU time	1.24 seconds
Started	Jul 29 05:25:27 PM PDT 24
Finished	Jul 29 05:25:29 PM PDT 24
Peak memory	208488 kb
Host	smart-f6bd93e2-c7d8-4006-9dbf-f7993d1014d0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966952742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.966952742
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1412241608
Short name	T962
Test name
Test status
Simulation time	14746601 ps
CPU time	1.04 seconds
Started	Jul 29 05:25:27 PM PDT 24
Finished	Jul 29 05:25:28 PM PDT 24
Peak memory	209460 kb
Host	smart-4a88c019-7cb3-42e5-bdc4-f44ee84696b7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412241608 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1412241608
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3181581288
Short name	T155
Test name
Test status
Simulation time	212369038 ps
CPU time	1.33 seconds
Started	Jul 29 05:25:28 PM PDT 24
Finished	Jul 29 05:25:30 PM PDT 24
Peak memory	209408 kb
Host	smart-969111f3-7dda-411a-8b55-110aacb8aef4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181581288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _same_csr_outstanding.3181581288
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1559093947
Short name	T980
Test name
Test status
Simulation time	185569302 ps
CPU time	1.75 seconds
Started	Jul 29 05:25:26 PM PDT 24
Finished	Jul 29 05:25:28 PM PDT 24
Peak memory	217692 kb
Host	smart-cddf01e0-eeba-4010-af5e-8843feba43d4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559093947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1559093947
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3587027027
Short name	T970
Test name
Test status
Simulation time	32328685 ps
CPU time	1.18 seconds
Started	Jul 29 05:25:33 PM PDT 24
Finished	Jul 29 05:25:34 PM PDT 24
Peak memory	209468 kb
Host	smart-d14d9c5d-0ec9-4429-87cc-7181d97fbff3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587027027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin g.3587027027
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1973013182
Short name	T893
Test name
Test status
Simulation time	85776177 ps
CPU time	1.96 seconds
Started	Jul 29 05:25:37 PM PDT 24
Finished	Jul 29 05:25:39 PM PDT 24
Peak memory	209520 kb
Host	smart-9e4956e9-13f3-4a2a-b1a6-ac82e626a408
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973013182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.1973013182
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3808690910
Short name	T954
Test name
Test status
Simulation time	50140440 ps
CPU time	0.97 seconds
Started	Jul 29 05:25:34 PM PDT 24
Finished	Jul 29 05:25:35 PM PDT 24
Peak memory	208844 kb
Host	smart-5a29e6ae-b4b7-4342-891f-63d77faacaf6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808690910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese t.3808690910
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.120310660
Short name	T913
Test name
Test status
Simulation time	32814949 ps
CPU time	1.25 seconds
Started	Jul 29 05:25:33 PM PDT 24
Finished	Jul 29 05:25:35 PM PDT 24
Peak memory	217756 kb
Host	smart-ead48b6e-f674-4c36-8e44-859868d1926c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120310660 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.120310660
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2656582944
Short name	T982
Test name
Test status
Simulation time	60140069 ps
CPU time	1.05 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	209220 kb
Host	smart-3dd0be79-1199-4eca-a1ab-9a6cc56de7b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656582944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2656582944
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1818547001
Short name	T985
Test name
Test status
Simulation time	190723272 ps
CPU time	1.86 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	208012 kb
Host	smart-6a465c9a-6911-49ad-b899-1ab895d81855
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818547001 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1818547001
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3372036084
Short name	T956
Test name
Test status
Simulation time	3303582966 ps
CPU time	14.19 seconds
Started	Jul 29 05:25:28 PM PDT 24
Finished	Jul 29 05:25:42 PM PDT 24
Peak memory	209480 kb
Host	smart-43c70e1a-ac90-41df-9c1b-c5bb1ee8cea0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372036084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3372036084
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.305687075
Short name	T927
Test name
Test status
Simulation time	1381269231 ps
CPU time	13.08 seconds
Started	Jul 29 05:25:29 PM PDT 24
Finished	Jul 29 05:25:42 PM PDT 24
Peak memory	209120 kb
Host	smart-2de55da9-dcb5-4fc2-9636-0b9522126c6d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305687075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.305687075
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4073587459
Short name	T960
Test name
Test status
Simulation time	100518698 ps
CPU time	1.96 seconds
Started	Jul 29 05:25:27 PM PDT 24
Finished	Jul 29 05:25:29 PM PDT 24
Peak memory	211024 kb
Host	smart-93c0d8f6-2c03-4d0b-9e5e-5dcc4a2de575
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073587459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4073587459
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.4170092602
Short name	T907
Test name
Test status
Simulation time	126953028 ps
CPU time	1.31 seconds
Started	Jul 29 05:25:28 PM PDT 24
Finished	Jul 29 05:25:29 PM PDT 24
Peak memory	209384 kb
Host	smart-ba90f9f9-8c72-4d61-abdb-1acca386c5cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170092602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.4170092602
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1116372136
Short name	T190
Test name
Test status
Simulation time	35718854 ps
CPU time	1.39 seconds
Started	Jul 29 05:25:33 PM PDT 24
Finished	Jul 29 05:25:34 PM PDT 24
Peak memory	211592 kb
Host	smart-8125e49b-dbb6-4174-8637-9808cd7b2b6d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116372136 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1116372136
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2506651000
Short name	T979
Test name
Test status
Simulation time	54435378 ps
CPU time	1.1 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	209592 kb
Host	smart-294216e8-7a80-4da9-b508-29c3ebecd558
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506651000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _same_csr_outstanding.2506651000
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3965371729
Short name	T111
Test name
Test status
Simulation time	98539943 ps
CPU time	2.92 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	222708 kb
Host	smart-77aceed6-078d-445c-9e53-03246abff7a8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965371729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_ err.3965371729
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1842918792
Short name	T996
Test name
Test status
Simulation time	18930143 ps
CPU time	1.1 seconds
Started	Jul 29 05:25:38 PM PDT 24
Finished	Jul 29 05:25:39 PM PDT 24
Peak memory	217664 kb
Host	smart-89129bc6-fd5b-406a-81d5-0b25de6038ec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842918792 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1842918792
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2818693344
Short name	T185
Test name
Test status
Simulation time	38271788 ps
CPU time	0.83 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:40 PM PDT 24
Peak memory	209312 kb
Host	smart-8bd84f7b-4e85-4564-a976-72c0e83cea16
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818693344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2818693344
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1434268121
Short name	T930
Test name
Test status
Simulation time	44450423 ps
CPU time	1.74 seconds
Started	Jul 29 05:25:34 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	209312 kb
Host	smart-0685ade2-d5a2-4784-aea3-7a7a3b514cdd
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434268121 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1434268121
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2500873596
Short name	T878
Test name
Test status
Simulation time	515564722 ps
CPU time	12.58 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:52 PM PDT 24
Peak memory	209244 kb
Host	smart-22fdaa6a-9144-4b62-9cf1-1c18c3348156
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500873596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2500873596
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1918743112
Short name	T943
Test name
Test status
Simulation time	6870744208 ps
CPU time	14.57 seconds
Started	Jul 29 05:25:33 PM PDT 24
Finished	Jul 29 05:25:48 PM PDT 24
Peak memory	209484 kb
Host	smart-84e5869a-bf80-4927-a2e0-a4f5101e32e1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918743112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1918743112
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3610900408
Short name	T925
Test name
Test status
Simulation time	184346329 ps
CPU time	1.27 seconds
Started	Jul 29 05:25:33 PM PDT 24
Finished	Jul 29 05:25:34 PM PDT 24
Peak memory	210796 kb
Host	smart-78ca9019-b154-4498-982a-007b4b49ae9e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610900408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3610900408
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3433090160
Short name	T112
Test name
Test status
Simulation time	698374763 ps
CPU time	2.91 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	217796 kb
Host	smart-23d7ae7f-db98-405b-b94e-51675aafa084
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343309 0160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3433090160
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3652756064
Short name	T950
Test name
Test status
Simulation time	114030587 ps
CPU time	1.47 seconds
Started	Jul 29 05:25:33 PM PDT 24
Finished	Jul 29 05:25:35 PM PDT 24
Peak memory	209328 kb
Host	smart-1c826755-b4e0-4910-ae19-cb470930575b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652756064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.3652756064
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3749762766
Short name	T929
Test name
Test status
Simulation time	97423599 ps
CPU time	1.15 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:40 PM PDT 24
Peak memory	209604 kb
Host	smart-5606763b-764e-4044-a959-90335b40e01e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749762766 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3749762766
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.536353660
Short name	T931
Test name
Test status
Simulation time	30520062 ps
CPU time	1.1 seconds
Started	Jul 29 05:25:34 PM PDT 24
Finished	Jul 29 05:25:35 PM PDT 24
Peak memory	209424 kb
Host	smart-307a1575-e6bb-452a-8980-ee4140bc506b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536353660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ same_csr_outstanding.536353660
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3561552703
Short name	T108
Test name
Test status
Simulation time	212080880 ps
CPU time	1.81 seconds
Started	Jul 29 05:25:37 PM PDT 24
Finished	Jul 29 05:25:39 PM PDT 24
Peak memory	218668 kb
Host	smart-3027dd3a-551d-44cb-907f-61760154b411
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561552703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3561552703
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2141543470
Short name	T989
Test name
Test status
Simulation time	305954493 ps
CPU time	2.01 seconds
Started	Jul 29 05:25:34 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	222332 kb
Host	smart-b38376e1-95da-48e7-be97-dabb80b1ba83
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141543470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_ err.2141543470
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3755907765
Short name	T972
Test name
Test status
Simulation time	84120786 ps
CPU time	1.12 seconds
Started	Jul 29 05:25:36 PM PDT 24
Finished	Jul 29 05:25:37 PM PDT 24
Peak memory	218704 kb
Host	smart-b347d56a-3b18-429d-a34b-6ccaeacc8af1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755907765 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3755907765
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3927037880
Short name	T967
Test name
Test status
Simulation time	16409895 ps
CPU time	1.09 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	209456 kb
Host	smart-5a8a970a-9fe0-49ec-a3d1-d0535eea480d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927037880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3927037880
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2308755589
Short name	T934
Test name
Test status
Simulation time	31287914 ps
CPU time	0.97 seconds
Started	Jul 29 05:25:32 PM PDT 24
Finished	Jul 29 05:25:33 PM PDT 24
Peak memory	209276 kb
Host	smart-cd388fee-9936-4ea5-828f-609638a91bbd
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308755589 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2308755589
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.201907091
Short name	T983
Test name
Test status
Simulation time	869474378 ps
CPU time	8.66 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:44 PM PDT 24
Peak memory	209212 kb
Host	smart-5360a27f-cbdd-439c-8789-9a7f4c4d9bd6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201907091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.lc_ctrl_jtag_csr_aliasing.201907091
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3382826645
Short name	T918
Test name
Test status
Simulation time	492545479 ps
CPU time	5.59 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:44 PM PDT 24
Peak memory	209200 kb
Host	smart-6584c553-7d7e-427e-b296-bfcfe79f26ff
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382826645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3382826645
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.110071794
Short name	T973
Test name
Test status
Simulation time	109711882 ps
CPU time	3.42 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	211112 kb
Host	smart-82e139a5-a0bd-4d75-94c8-e7aa225b5726
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110071794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.110071794
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2024995734
Short name	T951
Test name
Test status
Simulation time	147504190 ps
CPU time	4.67 seconds
Started	Jul 29 05:25:36 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	217640 kb
Host	smart-e01a7339-006d-4c52-9942-2829a44a55bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202499 5734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2024995734
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.392438185
Short name	T896
Test name
Test status
Simulation time	746235207 ps
CPU time	4.65 seconds
Started	Jul 29 05:25:32 PM PDT 24
Finished	Jul 29 05:25:37 PM PDT 24
Peak memory	209376 kb
Host	smart-ff767432-60ed-49e8-b5be-c98cd53e4791
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392438185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.392438185
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1770347063
Short name	T981
Test name
Test status
Simulation time	41882122 ps
CPU time	1.98 seconds
Started	Jul 29 05:25:36 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	211460 kb
Host	smart-e3aca4b5-6cc5-4c0c-aab6-41ee2c0e943f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770347063 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1770347063
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3721752944
Short name	T971
Test name
Test status
Simulation time	56255827 ps
CPU time	1.21 seconds
Started	Jul 29 05:25:34 PM PDT 24
Finished	Jul 29 05:25:35 PM PDT 24
Peak memory	209536 kb
Host	smart-5500e844-92cc-4b39-82dd-814644f9470f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721752944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _same_csr_outstanding.3721752944
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2393769174
Short name	T109
Test name
Test status
Simulation time	325499954 ps
CPU time	2.44 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:42 PM PDT 24
Peak memory	217716 kb
Host	smart-07260716-cfc9-4dfc-952a-5f6b134f0b3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393769174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2393769174
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2437899241
Short name	T130
Test name
Test status
Simulation time	252953842 ps
CPU time	2.73 seconds
Started	Jul 29 05:25:38 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	217664 kb
Host	smart-9fede774-8f74-4181-b531-ee65dc973269
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437899241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_ err.2437899241
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1394720877
Short name	T965
Test name
Test status
Simulation time	35199786 ps
CPU time	1.04 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	217976 kb
Host	smart-d353be01-9f67-41a5-bde2-7dea9eb7b65b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394720877 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1394720877
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4148606137
Short name	T1001
Test name
Test status
Simulation time	74203912 ps
CPU time	0.84 seconds
Started	Jul 29 05:25:36 PM PDT 24
Finished	Jul 29 05:25:37 PM PDT 24
Peak memory	208660 kb
Host	smart-2cba7fe9-0110-4954-9653-134bc937a9f5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148606137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4148606137
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3094419787
Short name	T879
Test name
Test status
Simulation time	94257234 ps
CPU time	1.69 seconds
Started	Jul 29 05:25:33 PM PDT 24
Finished	Jul 29 05:25:35 PM PDT 24
Peak memory	209360 kb
Host	smart-6d202e53-aabc-4b60-ada1-dd5e0dc92c3d
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094419787 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3094419787
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1523035969
Short name	T888
Test name
Test status
Simulation time	1161097842 ps
CPU time	6.98 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	208676 kb
Host	smart-7b64652f-3870-4ed5-9a92-80a229a3f0c6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523035969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1523035969
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1994925015
Short name	T991
Test name
Test status
Simulation time	1668876882 ps
CPU time	5.86 seconds
Started	Jul 29 05:25:40 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	209396 kb
Host	smart-736e8a72-4b96-41f4-b646-4b8b59850216
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994925015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1994925015
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2302265714
Short name	T952
Test name
Test status
Simulation time	150320520 ps
CPU time	3.76 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:43 PM PDT 24
Peak memory	211116 kb
Host	smart-8e82c7c0-3d3a-4f14-8e8c-e3c161263e70
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302265714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2302265714
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1356647692
Short name	T949
Test name
Test status
Simulation time	60354957 ps
CPU time	1.68 seconds
Started	Jul 29 05:25:40 PM PDT 24
Finished	Jul 29 05:25:42 PM PDT 24
Peak memory	218968 kb
Host	smart-fc72aa75-fb61-4949-95c6-3beea54323fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135664 7692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1356647692
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3263002058
Short name	T136
Test name
Test status
Simulation time	55493319 ps
CPU time	1.44 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	209412 kb
Host	smart-a054cf57-f7a8-4094-b2f5-bce4de27278a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263002058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.3263002058
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4054830514
Short name	T154
Test name
Test status
Simulation time	32012853 ps
CPU time	1.15 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	209500 kb
Host	smart-40f5f6fa-17d7-4448-bc04-4499c6ca7b38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054830514 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4054830514
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1762079206
Short name	T939
Test name
Test status
Simulation time	30103359 ps
CPU time	1.5 seconds
Started	Jul 29 05:25:35 PM PDT 24
Finished	Jul 29 05:25:36 PM PDT 24
Peak memory	209464 kb
Host	smart-1c543a54-bdf2-47e9-a3b8-64434218f008
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762079206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _same_csr_outstanding.1762079206
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3093521348
Short name	T909
Test name
Test status
Simulation time	129330669 ps
CPU time	2.17 seconds
Started	Jul 29 05:25:38 PM PDT 24
Finished	Jul 29 05:25:40 PM PDT 24
Peak memory	218720 kb
Host	smart-de5018e0-4fa5-4a16-b60e-ec3cc287682d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093521348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3093521348
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.479937454
Short name	T921
Test name
Test status
Simulation time	20264746 ps
CPU time	1.06 seconds
Started	Jul 29 05:25:37 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	219388 kb
Host	smart-091a8b24-f93d-4893-82af-29a0455ff95f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479937454 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.479937454
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2859399949
Short name	T890
Test name
Test status
Simulation time	17471888 ps
CPU time	0.92 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	209112 kb
Host	smart-5ad5b6c9-d0b2-4f78-990b-7a211c024533
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859399949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2859399949
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3536519014
Short name	T955
Test name
Test status
Simulation time	64035550 ps
CPU time	2.15 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:42 PM PDT 24
Peak memory	208004 kb
Host	smart-1612407c-bcc3-4897-9d0a-221063bc86f2
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536519014 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3536519014
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.339889070
Short name	T885
Test name
Test status
Simulation time	377629681 ps
CPU time	2.97 seconds
Started	Jul 29 05:25:40 PM PDT 24
Finished	Jul 29 05:25:43 PM PDT 24
Peak memory	208624 kb
Host	smart-6d149006-9dbd-407d-b661-51ce29948a46
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339889070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_aliasing.339889070
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.812753712
Short name	T897
Test name
Test status
Simulation time	1806882803 ps
CPU time	9.81 seconds
Started	Jul 29 05:25:38 PM PDT 24
Finished	Jul 29 05:25:48 PM PDT 24
Peak memory	209220 kb
Host	smart-4c12c11f-3f8a-4fab-b47a-31a46aa6b102
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812753712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.812753712
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4087010070
Short name	T895
Test name
Test status
Simulation time	94698780 ps
CPU time	1.88 seconds
Started	Jul 29 05:25:37 PM PDT 24
Finished	Jul 29 05:25:39 PM PDT 24
Peak memory	211068 kb
Host	smart-9b672941-fd27-4919-86ef-6a08cb9a4fbe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087010070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4087010070
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3071385435
Short name	T935
Test name
Test status
Simulation time	423761641 ps
CPU time	5.14 seconds
Started	Jul 29 05:25:36 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	218260 kb
Host	smart-73bb3eda-6ded-4d2e-9c93-e650fa66ecbd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307138 5435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3071385435
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4274727700
Short name	T899
Test name
Test status
Simulation time	166980653 ps
CPU time	2.37 seconds
Started	Jul 29 05:25:38 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	209344 kb
Host	smart-88c1a278-b10a-48ea-9cd5-1abb5b4e7576
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274727700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.4274727700
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2424887645
Short name	T191
Test name
Test status
Simulation time	51418023 ps
CPU time	1.07 seconds
Started	Jul 29 05:25:44 PM PDT 24
Finished	Jul 29 05:25:45 PM PDT 24
Peak memory	209520 kb
Host	smart-b3b0876b-9897-4189-9030-e799d1070e25
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424887645 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2424887645
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3161986548
Short name	T947
Test name
Test status
Simulation time	50129514 ps
CPU time	1.46 seconds
Started	Jul 29 05:25:36 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	209356 kb
Host	smart-5248f9fe-b6eb-48aa-becd-1ad2a6fe937a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161986548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _same_csr_outstanding.3161986548
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1623518743
Short name	T100
Test name
Test status
Simulation time	84352875 ps
CPU time	2.34 seconds
Started	Jul 29 05:25:44 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	217772 kb
Host	smart-ee0f9455-7443-4786-ba4b-ac8cac5d965a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623518743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1623518743
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3463778041
Short name	T131
Test name
Test status
Simulation time	974643881 ps
CPU time	2.42 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	217628 kb
Host	smart-f511814d-2069-4721-a61f-827739571373
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463778041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.3463778041
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1165777136
Short name	T986
Test name
Test status
Simulation time	254008789 ps
CPU time	1.58 seconds
Started	Jul 29 05:25:45 PM PDT 24
Finished	Jul 29 05:25:47 PM PDT 24
Peak memory	219568 kb
Host	smart-58efecdc-f2b5-4d22-bf47-a152484c00f4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165777136 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1165777136
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.952071492
Short name	T984
Test name
Test status
Simulation time	29526486 ps
CPU time	0.87 seconds
Started	Jul 29 05:25:44 PM PDT 24
Finished	Jul 29 05:25:45 PM PDT 24
Peak memory	209000 kb
Host	smart-57072364-7bdf-4216-9519-2516cbbb104f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952071492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.952071492
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1459662600
Short name	T958
Test name
Test status
Simulation time	91686326 ps
CPU time	1.55 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	209476 kb
Host	smart-90c69c42-4393-4547-9069-09dae689526c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459662600 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1459662600
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4194437160
Short name	T135
Test name
Test status
Simulation time	3458400984 ps
CPU time	10.31 seconds
Started	Jul 29 05:25:39 PM PDT 24
Finished	Jul 29 05:25:50 PM PDT 24
Peak memory	209476 kb
Host	smart-7ab2becd-2a1c-4811-802a-7570575972a6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194437160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.4194437160
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4272953271
Short name	T968
Test name
Test status
Simulation time	2351541769 ps
CPU time	50.81 seconds
Started	Jul 29 05:25:36 PM PDT 24
Finished	Jul 29 05:26:27 PM PDT 24
Peak memory	208924 kb
Host	smart-78fb884b-8182-4ada-8013-8c143a93c800
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272953271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4272953271
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2965097647
Short name	T900
Test name
Test status
Simulation time	526305235 ps
CPU time	2.74 seconds
Started	Jul 29 05:25:38 PM PDT 24
Finished	Jul 29 05:25:41 PM PDT 24
Peak memory	211048 kb
Host	smart-98556d13-204a-43a0-9a49-b317fd8b422a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965097647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2965097647
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3830110982
Short name	T978
Test name
Test status
Simulation time	504904303 ps
CPU time	2.32 seconds
Started	Jul 29 05:25:38 PM PDT 24
Finished	Jul 29 05:25:40 PM PDT 24
Peak memory	217804 kb
Host	smart-c8867751-8c15-4ee1-80b3-8080bc51b537
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383011 0982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3830110982
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2788791619
Short name	T887
Test name
Test status
Simulation time	450175186 ps
CPU time	1.15 seconds
Started	Jul 29 05:25:37 PM PDT 24
Finished	Jul 29 05:25:38 PM PDT 24
Peak memory	209416 kb
Host	smart-15f6124c-6e27-4113-a6c1-bb20fd0321c8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788791619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.2788791619
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.414668122
Short name	T932
Test name
Test status
Simulation time	52413836 ps
CPU time	1.01 seconds
Started	Jul 29 05:25:41 PM PDT 24
Finished	Jul 29 05:25:42 PM PDT 24
Peak memory	209444 kb
Host	smart-e8be2be5-3bd4-4435-8a33-7676753f36d3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414668122 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.414668122
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2773768669
Short name	T904
Test name
Test status
Simulation time	15357695 ps
CPU time	1.18 seconds
Started	Jul 29 05:25:45 PM PDT 24
Finished	Jul 29 05:25:46 PM PDT 24
Peak memory	209448 kb
Host	smart-a5700710-c1ff-42e6-90b7-0007d8ed60f6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773768669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _same_csr_outstanding.2773768669
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4290807981
Short name	T936
Test name
Test status
Simulation time	39056507 ps
CPU time	1.57 seconds
Started	Jul 29 05:25:37 PM PDT 24
Finished	Jul 29 05:25:39 PM PDT 24
Peak memory	217712 kb
Host	smart-74f92070-594b-432c-80b7-4be30d7c4aaf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290807981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4290807981
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1774181265
Short name	T132
Test name
Test status
Simulation time	163781663 ps
CPU time	2.94 seconds
Started	Jul 29 05:25:44 PM PDT 24
Finished	Jul 29 05:25:47 PM PDT 24
Peak memory	217720 kb
Host	smart-af797a39-c01b-4add-a198-91993c34dd38
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774181265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_ err.1774181265
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_alert_test.1496806372
Short name	T791
Test name
Test status
Simulation time	12693520 ps
CPU time	0.98 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	208932 kb
Host	smart-b25edb7f-bfa6-43b2-baf2-ae990f8db764
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496806372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1496806372
Directory	/workspace/0.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.lc_ctrl_claim_transition_if.2484202102
Short name	T178
Test name
Test status
Simulation time	10547522 ps
CPU time	0.99 seconds
Started	Jul 29 05:35:04 PM PDT 24
Finished	Jul 29 05:35:05 PM PDT 24
Peak memory	208856 kb
Host	smart-e50f2c74-3dc7-4ab7-87f8-1210679d102e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484202102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2484202102
Directory	/workspace/0.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/0.lc_ctrl_errors.1244547334
Short name	T521
Test name
Test status
Simulation time	1347012905 ps
CPU time	10.89 seconds
Started	Jul 29 05:35:02 PM PDT 24
Finished	Jul 29 05:35:13 PM PDT 24
Peak memory	218376 kb
Host	smart-48b38df1-05c4-494f-bdf0-f8e513f8ee97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244547334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1244547334
Directory	/workspace/0.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_access.1825152483
Short name	T730
Test name
Test status
Simulation time	1193326728 ps
CPU time	11.84 seconds
Started	Jul 29 05:35:03 PM PDT 24
Finished	Jul 29 05:35:15 PM PDT 24
Peak memory	217460 kb
Host	smart-98d7d5b9-289d-4c79-9caf-5ee3dca1d848
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825152483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1825152483
Directory	/workspace/0.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_errors.1464095815
Short name	T429
Test name
Test status
Simulation time	1237492785 ps
CPU time	40.09 seconds
Started	Jul 29 05:35:02 PM PDT 24
Finished	Jul 29 05:35:42 PM PDT 24
Peak memory	226116 kb
Host	smart-65ac3db8-438f-4a71-9d10-559196e1e61b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464095815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er rors.1464095815
Directory	/workspace/0.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_priority.528705788
Short name	T330
Test name
Test status
Simulation time	141322818 ps
CPU time	2.67 seconds
Started	Jul 29 05:35:03 PM PDT 24
Finished	Jul 29 05:35:05 PM PDT 24
Peak memory	217560 kb
Host	smart-b427ddd8-3dd2-4467-b52a-89253605b608
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528705788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.528705788
Directory	/workspace/0.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1076347485
Short name	T775
Test name
Test status
Simulation time	1742223676 ps
CPU time	13.41 seconds
Started	Jul 29 05:35:03 PM PDT 24
Finished	Jul 29 05:35:16 PM PDT 24
Peak memory	218296 kb
Host	smart-c1b947b3-1ee1-4361-b472-23035889db76
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076347485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _prog_failure.1076347485
Directory	/workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1250521558
Short name	T292
Test name
Test status
Simulation time	1952411991 ps
CPU time	15.34 seconds
Started	Jul 29 05:35:06 PM PDT 24
Finished	Jul 29 05:35:22 PM PDT 24
Peak memory	217744 kb
Host	smart-05fc6ef1-538f-4828-bd97-3a86c52cb3c4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250521558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_regwen_during_op.1250521558
Directory	/workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_smoke.3880950321
Short name	T710
Test name
Test status
Simulation time	429346957 ps
CPU time	3.45 seconds
Started	Jul 29 05:35:04 PM PDT 24
Finished	Jul 29 05:35:07 PM PDT 24
Peak memory	217748 kb
Host	smart-22e0d886-0902-4120-92a5-aa9d1be89daa
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880950321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke. 3880950321
Directory	/workspace/0.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_failure.522743314
Short name	T838
Test name
Test status
Simulation time	1404552747 ps
CPU time	47.57 seconds
Started	Jul 29 05:35:07 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	252856 kb
Host	smart-f8d3d146-270f-4b31-a1ec-809740c61ea9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522743314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _state_failure.522743314
Directory	/workspace/0.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1367357207
Short name	T244
Test name
Test status
Simulation time	8172772058 ps
CPU time	20.28 seconds
Started	Jul 29 05:35:03 PM PDT 24
Finished	Jul 29 05:35:24 PM PDT 24
Peak memory	250996 kb
Host	smart-3b39f2b8-ce5e-4051-ae88-08e905a1570e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367357207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.1367357207
Directory	/workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_prog_failure.1301586977
Short name	T387
Test name
Test status
Simulation time	125846198 ps
CPU time	1.93 seconds
Started	Jul 29 05:35:06 PM PDT 24
Finished	Jul 29 05:35:08 PM PDT 24
Peak memory	218364 kb
Host	smart-9f1778ef-de3c-4c1e-ae9e-4909a093c416
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1301586977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1301586977
Directory	/workspace/0.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_regwen_during_op.3650412150
Short name	T691
Test name
Test status
Simulation time	675896250 ps
CPU time	22.58 seconds
Started	Jul 29 05:35:06 PM PDT 24
Finished	Jul 29 05:35:28 PM PDT 24
Peak memory	214404 kb
Host	smart-82f1bb7a-ab32-4c71-bf45-4c3ffb4f08e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650412150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3650412150
Directory	/workspace/0.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_cm.2431753749
Short name	T93
Test name
Test status
Simulation time	891496292 ps
CPU time	32.99 seconds
Started	Jul 29 05:35:11 PM PDT 24
Finished	Jul 29 05:35:44 PM PDT 24
Peak memory	268088 kb
Host	smart-5f16fcac-0fcb-4b2d-bd9d-0501aea98a5e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431753749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2431753749
Directory	/workspace/0.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_mubi.1853612724
Short name	T532
Test name
Test status
Simulation time	1364514758 ps
CPU time	18.35 seconds
Started	Jul 29 05:35:02 PM PDT 24
Finished	Jul 29 05:35:21 PM PDT 24
Peak memory	226152 kb
Host	smart-223f7cd1-0293-4847-95a5-96acc06e77f9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853612724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1853612724
Directory	/workspace/0.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_digest.3152520925
Short name	T478
Test name
Test status
Simulation time	605816506 ps
CPU time	13.37 seconds
Started	Jul 29 05:35:03 PM PDT 24
Finished	Jul 29 05:35:17 PM PDT 24
Peak memory	218280 kb
Host	smart-62601b46-3947-4dc0-abbd-df8881fbe3a7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152520925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di gest.3152520925
Directory	/workspace/0.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_mux.2859269292
Short name	T372
Test name
Test status
Simulation time	293891644 ps
CPU time	8.54 seconds
Started	Jul 29 05:35:04 PM PDT 24
Finished	Jul 29 05:35:13 PM PDT 24
Peak memory	226040 kb
Host	smart-700d27f9-a84e-4198-a43d-4038aeec3ddb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859269292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2 859269292
Directory	/workspace/0.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/0.lc_ctrl_security_escalation.4137027399
Short name	T637
Test name
Test status
Simulation time	657940210 ps
CPU time	11.98 seconds
Started	Jul 29 05:35:03 PM PDT 24
Finished	Jul 29 05:35:15 PM PDT 24
Peak memory	226220 kb
Host	smart-a5a9d2ba-9fac-47ad-b06f-4b134d049477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137027399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4137027399
Directory	/workspace/0.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_smoke.80854017
Short name	T82
Test name
Test status
Simulation time	65230133 ps
CPU time	2.88 seconds
Started	Jul 29 05:35:05 PM PDT 24
Finished	Jul 29 05:35:08 PM PDT 24
Peak memory	214656 kb
Host	smart-7f6fe35e-6068-416e-9425-8184759bce2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80854017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.80854017
Directory	/workspace/0.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_failure.2259726142
Short name	T701
Test name
Test status
Simulation time	785220388 ps
CPU time	31.58 seconds
Started	Jul 29 05:35:06 PM PDT 24
Finished	Jul 29 05:35:38 PM PDT 24
Peak memory	245556 kb
Host	smart-4377c9f1-41ac-4fc0-a930-5adacc83d9ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259726142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2259726142
Directory	/workspace/0.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_post_trans.3143458751
Short name	T774
Test name
Test status
Simulation time	187120895 ps
CPU time	8.48 seconds
Started	Jul 29 05:35:04 PM PDT 24
Finished	Jul 29 05:35:12 PM PDT 24
Peak memory	250992 kb
Host	smart-b745f629-7952-4495-bb2a-4b8d8d7ee55d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143458751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3143458751
Directory	/workspace/0.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2760926796
Short name	T76
Test name
Test status
Simulation time	23970218619 ps
CPU time	486.46 seconds
Started	Jul 29 05:35:08 PM PDT 24
Finished	Jul 29 05:43:15 PM PDT 24
Peak memory	540740 kb
Host	smart-f1b22387-08f6-4719-807f-16ff77c5eb8a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2760926796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2760926796
Directory	/workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1805247231
Short name	T737
Test name
Test status
Simulation time	23836373 ps
CPU time	0.94 seconds
Started	Jul 29 05:35:04 PM PDT 24
Finished	Jul 29 05:35:05 PM PDT 24
Peak memory	212004 kb
Host	smart-d593e6e2-3217-4c51-9573-93aa781fa71b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805247231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct rl_volatile_unlock_smoke.1805247231
Directory	/workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_alert_test.1236097426
Short name	T419
Test name
Test status
Simulation time	67774895 ps
CPU time	1.21 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	209016 kb
Host	smart-64df1d81-e016-4e60-ad27-2b1b8906072c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236097426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1236097426
Directory	/workspace/1.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_errors.4137879395
Short name	T686
Test name
Test status
Simulation time	2475662792 ps
CPU time	28.08 seconds
Started	Jul 29 05:35:11 PM PDT 24
Finished	Jul 29 05:35:39 PM PDT 24
Peak memory	219064 kb
Host	smart-d628d0e6-d1bb-4fb0-80a2-384d3773334b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137879395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.4137879395
Directory	/workspace/1.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_priority.55524649
Short name	T630
Test name
Test status
Simulation time	532591354 ps
CPU time	2.95 seconds
Started	Jul 29 05:35:08 PM PDT 24
Finished	Jul 29 05:35:11 PM PDT 24
Peak memory	217704 kb
Host	smart-f69329f0-07ad-4886-8dac-15902472608d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55524649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.55524649
Directory	/workspace/1.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2498817511
Short name	T273
Test name
Test status
Simulation time	902666363 ps
CPU time	6.17 seconds
Started	Jul 29 05:35:07 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	218288 kb
Host	smart-1acdad78-e808-434e-8774-f3f5a3a8b0a4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498817511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag _prog_failure.2498817511
Directory	/workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3703342353
Short name	T554
Test name
Test status
Simulation time	1570961974 ps
CPU time	22.06 seconds
Started	Jul 29 05:35:10 PM PDT 24
Finished	Jul 29 05:35:32 PM PDT 24
Peak memory	217648 kb
Host	smart-f9cece65-d453-4b46-9416-c58b176e99ab
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703342353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.3703342353
Directory	/workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_smoke.447755927
Short name	T665
Test name
Test status
Simulation time	233780318 ps
CPU time	4.56 seconds
Started	Jul 29 05:35:09 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	217712 kb
Host	smart-3e76cdeb-c10f-45c7-b9c2-7980e221a633
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447755927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.447755927
Directory	/workspace/1.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1993156929
Short name	T411
Test name
Test status
Simulation time	1753186431 ps
CPU time	73.1 seconds
Started	Jul 29 05:35:08 PM PDT 24
Finished	Jul 29 05:36:21 PM PDT 24
Peak memory	267364 kb
Host	smart-0fc004ae-e6bd-4fca-845d-95d2fbf9f386
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993156929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.1993156929
Directory	/workspace/1.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1934644828
Short name	T430
Test name
Test status
Simulation time	854470780 ps
CPU time	18.83 seconds
Started	Jul 29 05:35:09 PM PDT 24
Finished	Jul 29 05:35:28 PM PDT 24
Peak memory	250944 kb
Host	smart-900ca1cd-4215-4a56-8790-5dc795976261
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934644828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_state_post_trans.1934644828
Directory	/workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_prog_failure.1597211115
Short name	T850
Test name
Test status
Simulation time	201800103 ps
CPU time	4.8 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:17 PM PDT 24
Peak memory	218288 kb
Host	smart-fb4da2f0-f14b-444a-a759-54c59ecbb7ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597211115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1597211115
Directory	/workspace/1.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_regwen_during_op.3032807136
Short name	T300
Test name
Test status
Simulation time	791236474 ps
CPU time	11.95 seconds
Started	Jul 29 05:35:10 PM PDT 24
Finished	Jul 29 05:35:22 PM PDT 24
Peak memory	214548 kb
Host	smart-643e4e8f-7ea5-45e7-87ba-b1148d3624c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032807136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3032807136
Directory	/workspace/1.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_cm.3212136899
Short name	T58
Test name
Test status
Simulation time	214816037 ps
CPU time	22.19 seconds
Started	Jul 29 05:35:10 PM PDT 24
Finished	Jul 29 05:35:32 PM PDT 24
Peak memory	281412 kb
Host	smart-da90ba4c-3be4-4f93-a803-83873b814356
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212136899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3212136899
Directory	/workspace/1.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_mubi.379332321
Short name	T695
Test name
Test status
Simulation time	2729517247 ps
CPU time	16.92 seconds
Started	Jul 29 05:35:07 PM PDT 24
Finished	Jul 29 05:35:24 PM PDT 24
Peak memory	226256 kb
Host	smart-e940574c-daf9-483b-bbee-ae259021f207
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379332321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.379332321
Directory	/workspace/1.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_digest.1276087799
Short name	T808
Test name
Test status
Simulation time	2712618923 ps
CPU time	15.86 seconds
Started	Jul 29 05:35:10 PM PDT 24
Finished	Jul 29 05:35:26 PM PDT 24
Peak memory	218376 kb
Host	smart-1cfea571-0155-45f1-9692-8f37d2891083
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276087799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di gest.1276087799
Directory	/workspace/1.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_mux.3070229635
Short name	T799
Test name
Test status
Simulation time	270598724 ps
CPU time	11.01 seconds
Started	Jul 29 05:35:14 PM PDT 24
Finished	Jul 29 05:35:25 PM PDT 24
Peak memory	226116 kb
Host	smart-4cf7021e-4637-4e9a-9ede-65c971161077
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070229635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3 070229635
Directory	/workspace/1.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/1.lc_ctrl_smoke.1180631111
Short name	T339
Test name
Test status
Simulation time	268823469 ps
CPU time	2.56 seconds
Started	Jul 29 05:35:08 PM PDT 24
Finished	Jul 29 05:35:10 PM PDT 24
Peak memory	217748 kb
Host	smart-5aec6092-9a14-4ae2-90aa-b0ec3f56bc4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180631111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1180631111
Directory	/workspace/1.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_failure.2131239579
Short name	T496
Test name
Test status
Simulation time	284656638 ps
CPU time	24.27 seconds
Started	Jul 29 05:35:10 PM PDT 24
Finished	Jul 29 05:35:34 PM PDT 24
Peak memory	250900 kb
Host	smart-f5b7d461-5614-4c43-8be1-471e16e5fe7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131239579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2131239579
Directory	/workspace/1.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_post_trans.2763542988
Short name	T485
Test name
Test status
Simulation time	64875512 ps
CPU time	6.46 seconds
Started	Jul 29 05:35:08 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	248676 kb
Host	smart-464d1f6c-6a46-4562-b8fd-9543865279bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763542988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2763542988
Directory	/workspace/1.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all.1056393174
Short name	T785
Test name
Test status
Simulation time	102622243575 ps
CPU time	765.31 seconds
Started	Jul 29 05:35:10 PM PDT 24
Finished	Jul 29 05:47:56 PM PDT 24
Peak memory	226236 kb
Host	smart-2bd503c3-ab8f-48e1-a876-b4780bb9daa1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056393174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.1056393174
Directory	/workspace/1.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.73315215
Short name	T427
Test name
Test status
Simulation time	78304851716 ps
CPU time	746.81 seconds
Started	Jul 29 05:35:07 PM PDT 24
Finished	Jul 29 05:47:34 PM PDT 24
Peak memory	300052 kb
Host	smart-6b724cf1-f62f-43b0-a2a1-264b472e70c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=73315215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.73315215
Directory	/workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4229185850
Short name	T312
Test name
Test status
Simulation time	15731425 ps
CPU time	1.03 seconds
Started	Jul 29 05:35:09 PM PDT 24
Finished	Jul 29 05:35:10 PM PDT 24
Peak memory	211964 kb
Host	smart-3ba2c1a1-9440-4ccb-9f3d-7b0299cdb603
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229185850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_volatile_unlock_smoke.4229185850
Directory	/workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_errors.2077010269
Short name	T331
Test name
Test status
Simulation time	1201050825 ps
CPU time	11.46 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:36:03 PM PDT 24
Peak memory	218380 kb
Host	smart-fdf0f7de-bd8c-45db-a01d-6fc3b63750e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077010269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2077010269
Directory	/workspace/10.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_access.1476746769
Short name	T34
Test name
Test status
Simulation time	1010821058 ps
CPU time	3.28 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:35:55 PM PDT 24
Peak memory	217204 kb
Host	smart-e5ee7c4c-7c22-4b62-9c19-fd155fffd316
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476746769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1476746769
Directory	/workspace/10.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_errors.256683579
Short name	T849
Test name
Test status
Simulation time	2432410490 ps
CPU time	42.6 seconds
Started	Jul 29 05:35:53 PM PDT 24
Finished	Jul 29 05:36:35 PM PDT 24
Peak memory	218380 kb
Host	smart-dffa60b4-ee74-44d4-a808-d02f8761560c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256683579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er rors.256683579
Directory	/workspace/10.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2018337098
Short name	T846
Test name
Test status
Simulation time	410037295 ps
CPU time	3.04 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:35:55 PM PDT 24
Peak memory	218348 kb
Host	smart-448f53d5-ed13-424c-87bf-986a7a73269e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018337098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.2018337098
Directory	/workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_smoke.614416379
Short name	T741
Test name
Test status
Simulation time	448058680 ps
CPU time	1.94 seconds
Started	Jul 29 05:36:02 PM PDT 24
Finished	Jul 29 05:36:04 PM PDT 24
Peak memory	217700 kb
Host	smart-20cb0cd0-0e01-4c50-9b1a-852bf3d3f0bc
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614416379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke. 614416379
Directory	/workspace/10.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.4153604660
Short name	T457
Test name
Test status
Simulation time	1198812696 ps
CPU time	38.9 seconds
Started	Jul 29 05:35:48 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	250836 kb
Host	smart-23375368-92a0-4b7b-b8e5-014cd0262cce
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153604660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_state_failure.4153604660
Directory	/workspace/10.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.51753447
Short name	T511
Test name
Test status
Simulation time	7278624971 ps
CPU time	12.26 seconds
Started	Jul 29 05:35:50 PM PDT 24
Finished	Jul 29 05:36:02 PM PDT 24
Peak memory	250480 kb
Host	smart-eafd24a4-9674-4bb0-94f6-4e47414037c2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51753447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_j tag_state_post_trans.51753447
Directory	/workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_prog_failure.4047322472
Short name	T42
Test name
Test status
Simulation time	172240428 ps
CPU time	2.47 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	218360 kb
Host	smart-ac43d4bd-8e3b-4019-a07f-5cc664b4babf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047322472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4047322472
Directory	/workspace/10.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_mubi.2291979292
Short name	T549
Test name
Test status
Simulation time	924611293 ps
CPU time	10.46 seconds
Started	Jul 29 05:35:50 PM PDT 24
Finished	Jul 29 05:36:00 PM PDT 24
Peak memory	218432 kb
Host	smart-c4782af0-6b8c-42d3-89bd-b53a46b388b6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291979292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2291979292
Directory	/workspace/10.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_digest.2893392457
Short name	T516
Test name
Test status
Simulation time	359028632 ps
CPU time	11.65 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:36:03 PM PDT 24
Peak memory	226120 kb
Host	smart-efc0efac-12e5-4462-85de-6e58e92d6940
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893392457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d igest.2893392457
Directory	/workspace/10.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_mux.373876529
Short name	T359
Test name
Test status
Simulation time	892549647 ps
CPU time	9.75 seconds
Started	Jul 29 05:35:51 PM PDT 24
Finished	Jul 29 05:36:01 PM PDT 24
Peak memory	218332 kb
Host	smart-c8321a7c-61af-4cf1-9f05-8d1c8be20909
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373876529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.373876529
Directory	/workspace/10.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_security_escalation.409540390
Short name	T55
Test name
Test status
Simulation time	314756845 ps
CPU time	7.92 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:36:00 PM PDT 24
Peak memory	218368 kb
Host	smart-fe2cfb9e-67de-4d4e-b75b-b2d7b4b1fa87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409540390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.409540390
Directory	/workspace/10.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/10.lc_ctrl_smoke.3035004401
Short name	T75
Test name
Test status
Simulation time	119806385 ps
CPU time	1.92 seconds
Started	Jul 29 05:36:06 PM PDT 24
Finished	Jul 29 05:36:08 PM PDT 24
Peak memory	214020 kb
Host	smart-e02ef3a5-e760-4ce0-8acd-c71dfaf0c07d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035004401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3035004401
Directory	/workspace/10.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_failure.4154954978
Short name	T621
Test name
Test status
Simulation time	1257397985 ps
CPU time	33.31 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:36:26 PM PDT 24
Peak memory	250920 kb
Host	smart-82be6f13-c6db-4ab7-9493-49df7e63b9ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154954978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4154954978
Directory	/workspace/10.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_post_trans.3994411262
Short name	T371
Test name
Test status
Simulation time	93389061 ps
CPU time	5.77 seconds
Started	Jul 29 05:35:49 PM PDT 24
Finished	Jul 29 05:35:55 PM PDT 24
Peak memory	250384 kb
Host	smart-5a76d20e-d636-4f55-ab0f-9bd977b1db68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994411262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3994411262
Directory	/workspace/10.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all.3277731082
Short name	T316
Test name
Test status
Simulation time	6911529206 ps
CPU time	62.23 seconds
Started	Jul 29 05:35:48 PM PDT 24
Finished	Jul 29 05:36:50 PM PDT 24
Peak memory	250544 kb
Host	smart-cd121fc4-e95d-460c-9d1d-cd9306eddae6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277731082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.3277731082
Directory	/workspace/10.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4233314481
Short name	T765
Test name
Test status
Simulation time	79415912 ps
CPU time	0.81 seconds
Started	Jul 29 05:35:51 PM PDT 24
Finished	Jul 29 05:35:52 PM PDT 24
Peak memory	212016 kb
Host	smart-f55758a0-6c10-4fce-8d93-efc9979c8438
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233314481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_volatile_unlock_smoke.4233314481
Directory	/workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_alert_test.2035943622
Short name	T176
Test name
Test status
Simulation time	78462082 ps
CPU time	0.94 seconds
Started	Jul 29 05:35:57 PM PDT 24
Finished	Jul 29 05:35:58 PM PDT 24
Peak memory	209036 kb
Host	smart-02b13d0d-41ab-4aa3-bd71-1b6d06b90fb1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035943622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2035943622
Directory	/workspace/11.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.lc_ctrl_errors.933856519
Short name	T334
Test name
Test status
Simulation time	272152008 ps
CPU time	12.37 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:36:04 PM PDT 24
Peak memory	226168 kb
Host	smart-176b1fd8-b475-4d99-8938-9df1390e12ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933856519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.933856519
Directory	/workspace/11.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_access.548103469
Short name	T346
Test name
Test status
Simulation time	3478809388 ps
CPU time	11.39 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:36:08 PM PDT 24
Peak memory	217836 kb
Host	smart-d6b81007-bf0a-49aa-9863-5b9e1680f38d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548103469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.548103469
Directory	/workspace/11.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_errors.1112243439
Short name	T443
Test name
Test status
Simulation time	1680162389 ps
CPU time	51.36 seconds
Started	Jul 29 05:35:55 PM PDT 24
Finished	Jul 29 05:36:47 PM PDT 24
Peak memory	226280 kb
Host	smart-472bd765-8921-4f14-a3bf-248c43478c42
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112243439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e rrors.1112243439
Directory	/workspace/11.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.350980802
Short name	T828
Test name
Test status
Simulation time	7158123487 ps
CPU time	7.5 seconds
Started	Jul 29 05:35:59 PM PDT 24
Finished	Jul 29 05:36:06 PM PDT 24
Peak memory	218268 kb
Host	smart-98fa93b9-9b46-4685-b9de-c0b56126a74a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350980802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag _prog_failure.350980802
Directory	/workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_smoke.2594334364
Short name	T813
Test name
Test status
Simulation time	272251640 ps
CPU time	5.1 seconds
Started	Jul 29 05:35:51 PM PDT 24
Finished	Jul 29 05:35:56 PM PDT 24
Peak memory	217644 kb
Host	smart-fc0320e6-91c1-4d99-aba5-3344f38bcfa3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594334364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke .2594334364
Directory	/workspace/11.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_failure.4228186330
Short name	T350
Test name
Test status
Simulation time	4427472302 ps
CPU time	58.2 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:36:54 PM PDT 24
Peak memory	283744 kb
Host	smart-11295e99-097d-4d1a-9682-b0bb163c1aca
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228186330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt ag_state_failure.4228186330
Directory	/workspace/11.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1667280891
Short name	T852
Test name
Test status
Simulation time	800026595 ps
CPU time	28.71 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	250844 kb
Host	smart-b4f22130-2a2a-4edb-b9ae-bbfbbf1c8613
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667280891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_state_post_trans.1667280891
Directory	/workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_prog_failure.1909793325
Short name	T329
Test name
Test status
Simulation time	22157464 ps
CPU time	1.84 seconds
Started	Jul 29 05:35:51 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	218308 kb
Host	smart-c9149a20-d13b-4826-a06f-8a3bec6bcd35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909793325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1909793325
Directory	/workspace/11.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_mubi.2759946181
Short name	T505
Test name
Test status
Simulation time	831062613 ps
CPU time	12.24 seconds
Started	Jul 29 05:35:53 PM PDT 24
Finished	Jul 29 05:36:06 PM PDT 24
Peak memory	218368 kb
Host	smart-6f10a3fd-9c2d-438a-895f-47af8ed71810
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759946181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2759946181
Directory	/workspace/11.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_digest.1996868945
Short name	T435
Test name
Test status
Simulation time	793747549 ps
CPU time	11.09 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:36:07 PM PDT 24
Peak memory	218272 kb
Host	smart-2677f469-46ba-45f7-912f-033e05312838
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996868945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d igest.1996868945
Directory	/workspace/11.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_mux.3620997691
Short name	T535
Test name
Test status
Simulation time	890497606 ps
CPU time	16.04 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:36:12 PM PDT 24
Peak memory	218312 kb
Host	smart-21832d90-e67f-4cd7-a870-535d2b73a5a8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620997691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux. 3620997691
Directory	/workspace/11.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/11.lc_ctrl_security_escalation.343544126
Short name	T663
Test name
Test status
Simulation time	5568938710 ps
CPU time	16.62 seconds
Started	Jul 29 05:35:53 PM PDT 24
Finished	Jul 29 05:36:10 PM PDT 24
Peak memory	218480 kb
Host	smart-643526e9-4674-4eea-81e5-87133c9f129f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343544126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.343544126
Directory	/workspace/11.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_smoke.1526823441
Short name	T264
Test name
Test status
Simulation time	120369639 ps
CPU time	1.45 seconds
Started	Jul 29 05:35:53 PM PDT 24
Finished	Jul 29 05:35:55 PM PDT 24
Peak memory	217800 kb
Host	smart-76a5d1ee-c881-4908-83ee-942f8d332af1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526823441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1526823441
Directory	/workspace/11.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_failure.2240327342
Short name	T748
Test name
Test status
Simulation time	284792155 ps
CPU time	33.09 seconds
Started	Jul 29 05:35:53 PM PDT 24
Finished	Jul 29 05:36:26 PM PDT 24
Peak memory	250992 kb
Host	smart-9d986ef7-d3e4-4df9-bd26-7c1ff5b84d64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2240327342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2240327342
Directory	/workspace/11.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_post_trans.1322720932
Short name	T487
Test name
Test status
Simulation time	576498272 ps
CPU time	8.84 seconds
Started	Jul 29 05:35:50 PM PDT 24
Finished	Jul 29 05:35:59 PM PDT 24
Peak memory	250980 kb
Host	smart-f9cdfe08-d837-4e95-9d64-0c25ac886e26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322720932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1322720932
Directory	/workspace/11.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all.2852940882
Short name	T161
Test name
Test status
Simulation time	4001793962 ps
CPU time	49.92 seconds
Started	Jul 29 05:35:57 PM PDT 24
Finished	Jul 29 05:36:47 PM PDT 24
Peak memory	277708 kb
Host	smart-d260c90a-424e-4f4e-a8cc-c1cc7ff8bf5d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852940882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.2852940882
Directory	/workspace/11.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2573936158
Short name	T142
Test name
Test status
Simulation time	24371909451 ps
CPU time	272.7 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:40:29 PM PDT 24
Peak memory	286640 kb
Host	smart-a5c28148-4d97-4884-929a-9bd233ac4a93
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2573936158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2573936158
Directory	/workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.197594120
Short name	T446
Test name
Test status
Simulation time	21472841 ps
CPU time	0.95 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	211944 kb
Host	smart-66887d74-5dea-4e9e-ad8d-b0cfd60f1242
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197594120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_volatile_unlock_smoke.197594120
Directory	/workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_alert_test.1939175177
Short name	T585
Test name
Test status
Simulation time	41169871 ps
CPU time	0.85 seconds
Started	Jul 29 05:35:59 PM PDT 24
Finished	Jul 29 05:36:00 PM PDT 24
Peak memory	208884 kb
Host	smart-9617a63a-f0b0-48a6-ab49-29aeb6efdf0a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939175177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1939175177
Directory	/workspace/12.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_errors.575066985
Short name	T262
Test name
Test status
Simulation time	2759726630 ps
CPU time	15.51 seconds
Started	Jul 29 05:35:55 PM PDT 24
Finished	Jul 29 05:36:10 PM PDT 24
Peak memory	218456 kb
Host	smart-cfe439f9-d6cd-48fd-b66a-511693c8df97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575066985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.575066985
Directory	/workspace/12.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_access.3180414081
Short name	T724
Test name
Test status
Simulation time	3500944141 ps
CPU time	21.27 seconds
Started	Jul 29 05:36:00 PM PDT 24
Finished	Jul 29 05:36:22 PM PDT 24
Peak memory	217692 kb
Host	smart-14f08217-66a8-4a19-bb34-4654f5651ae7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180414081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3180414081
Directory	/workspace/12.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_errors.4160977649
Short name	T497
Test name
Test status
Simulation time	1743900241 ps
CPU time	56.15 seconds
Started	Jul 29 05:35:59 PM PDT 24
Finished	Jul 29 05:36:55 PM PDT 24
Peak memory	226108 kb
Host	smart-e5191ba9-8d79-4a88-ae69-e063293ba20c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160977649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e rrors.4160977649
Directory	/workspace/12.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2019449191
Short name	T742
Test name
Test status
Simulation time	675186647 ps
CPU time	19.09 seconds
Started	Jul 29 05:36:03 PM PDT 24
Finished	Jul 29 05:36:22 PM PDT 24
Peak memory	218316 kb
Host	smart-9cc2a34a-b3a7-4fd6-b467-a7eb1ce183f4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019449191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_prog_failure.2019449191
Directory	/workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_smoke.461988684
Short name	T606
Test name
Test status
Simulation time	739507573 ps
CPU time	6.11 seconds
Started	Jul 29 05:36:03 PM PDT 24
Finished	Jul 29 05:36:09 PM PDT 24
Peak memory	217816 kb
Host	smart-532f36a3-ad04-4374-9835-36635e5fb7ac
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461988684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke. 461988684
Directory	/workspace/12.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2326040641
Short name	T779
Test name
Test status
Simulation time	1296889843 ps
CPU time	57.54 seconds
Started	Jul 29 05:36:00 PM PDT 24
Finished	Jul 29 05:36:58 PM PDT 24
Peak memory	267336 kb
Host	smart-d972f6ad-c2ef-4154-87b1-d6f7b7a38e90
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326040641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt ag_state_failure.2326040641
Directory	/workspace/12.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2071640248
Short name	T615
Test name
Test status
Simulation time	359519335 ps
CPU time	16.07 seconds
Started	Jul 29 05:36:01 PM PDT 24
Finished	Jul 29 05:36:17 PM PDT 24
Peak memory	250024 kb
Host	smart-dbbc4a3f-0853-45a6-88a3-c2e72d798af9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071640248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.2071640248
Directory	/workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_prog_failure.1551694749
Short name	T618
Test name
Test status
Simulation time	333458307 ps
CPU time	7.01 seconds
Started	Jul 29 05:35:55 PM PDT 24
Finished	Jul 29 05:36:02 PM PDT 24
Peak memory	223100 kb
Host	smart-7e079bf3-9deb-4665-bc03-a3eebc71fc05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551694749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1551694749
Directory	/workspace/12.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_mubi.2866958609
Short name	T49
Test name
Test status
Simulation time	351021027 ps
CPU time	10.56 seconds
Started	Jul 29 05:36:01 PM PDT 24
Finished	Jul 29 05:36:12 PM PDT 24
Peak memory	226148 kb
Host	smart-51ebe8a8-ab1f-4003-9d91-35cec5cd79c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866958609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2866958609
Directory	/workspace/12.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_digest.925927671
Short name	T299
Test name
Test status
Simulation time	429457295 ps
CPU time	10.19 seconds
Started	Jul 29 05:36:00 PM PDT 24
Finished	Jul 29 05:36:10 PM PDT 24
Peak memory	218224 kb
Host	smart-1aaf78d1-8fe7-40fc-9962-4acb9f26a96c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925927671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di gest.925927671
Directory	/workspace/12.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_mux.4189140692
Short name	T364
Test name
Test status
Simulation time	271092240 ps
CPU time	11.21 seconds
Started	Jul 29 05:36:01 PM PDT 24
Finished	Jul 29 05:36:13 PM PDT 24
Peak memory	218332 kb
Host	smart-b9bf768c-ec8c-4f96-b92a-1ddb6c5f43b8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189140692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux. 4189140692
Directory	/workspace/12.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/12.lc_ctrl_security_escalation.1622030906
Short name	T586
Test name
Test status
Simulation time	785423763 ps
CPU time	12.54 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:36:08 PM PDT 24
Peak memory	226120 kb
Host	smart-732e0377-4d94-422e-a168-302c5b77de5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622030906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1622030906
Directory	/workspace/12.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/12.lc_ctrl_smoke.700351510
Short name	T469
Test name
Test status
Simulation time	66544734 ps
CPU time	2.42 seconds
Started	Jul 29 05:35:55 PM PDT 24
Finished	Jul 29 05:35:57 PM PDT 24
Peak memory	217848 kb
Host	smart-7d9d2ea8-c72f-4857-a480-786eb4b1a094
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=700351510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.700351510
Directory	/workspace/12.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_failure.2991205347
Short name	T480
Test name
Test status
Simulation time	1059917479 ps
CPU time	22.41 seconds
Started	Jul 29 05:35:56 PM PDT 24
Finished	Jul 29 05:36:18 PM PDT 24
Peak memory	251016 kb
Host	smart-9d070b57-7fc5-4595-8f12-e6897ab18c34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2991205347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2991205347
Directory	/workspace/12.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_post_trans.1140129916
Short name	T693
Test name
Test status
Simulation time	88987540 ps
CPU time	7.52 seconds
Started	Jul 29 05:35:54 PM PDT 24
Finished	Jul 29 05:36:02 PM PDT 24
Peak memory	251012 kb
Host	smart-9b37af95-6279-4a4a-841f-0fc96bfac9cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140129916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1140129916
Directory	/workspace/12.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all.1415139139
Short name	T682
Test name
Test status
Simulation time	5814622765 ps
CPU time	91.07 seconds
Started	Jul 29 05:36:00 PM PDT 24
Finished	Jul 29 05:37:31 PM PDT 24
Peak memory	271784 kb
Host	smart-d35aa26f-7531-4247-890b-1104c875ee94
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415139139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.1415139139
Directory	/workspace/12.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2064385881
Short name	T156
Test name
Test status
Simulation time	11753517 ps
CPU time	0.97 seconds
Started	Jul 29 05:35:53 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	211928 kb
Host	smart-1ed0522b-a76d-4132-bf9a-e68e86c9eedc
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064385881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_volatile_unlock_smoke.2064385881
Directory	/workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_alert_test.4051127025
Short name	T588
Test name
Test status
Simulation time	17402717 ps
CPU time	0.91 seconds
Started	Jul 29 05:36:06 PM PDT 24
Finished	Jul 29 05:36:07 PM PDT 24
Peak memory	208976 kb
Host	smart-dd20b394-c4f0-4b31-a5e3-d7cd83f24026
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051127025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4051127025
Directory	/workspace/13.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.lc_ctrl_errors.1575785795
Short name	T211
Test name
Test status
Simulation time	620706666 ps
CPU time	16.07 seconds
Started	Jul 29 05:36:02 PM PDT 24
Finished	Jul 29 05:36:18 PM PDT 24
Peak memory	226176 kb
Host	smart-cc12ce80-86f8-425b-8836-ced97f693134
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575785795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1575785795
Directory	/workspace/13.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_access.3032467594
Short name	T545
Test name
Test status
Simulation time	165360420 ps
CPU time	3.26 seconds
Started	Jul 29 05:36:03 PM PDT 24
Finished	Jul 29 05:36:06 PM PDT 24
Peak memory	217312 kb
Host	smart-80d6638a-4619-470c-a2e7-acb88b5806d6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032467594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3032467594
Directory	/workspace/13.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_errors.3498025490
Short name	T17
Test name
Test status
Simulation time	5947516368 ps
CPU time	28.13 seconds
Started	Jul 29 05:36:00 PM PDT 24
Finished	Jul 29 05:36:28 PM PDT 24
Peak memory	218940 kb
Host	smart-431c2b00-c03f-4a60-8584-d9a38505c813
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498025490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e rrors.3498025490
Directory	/workspace/13.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2599969949
Short name	T317
Test name
Test status
Simulation time	833689042 ps
CPU time	7.66 seconds
Started	Jul 29 05:36:03 PM PDT 24
Finished	Jul 29 05:36:11 PM PDT 24
Peak memory	218288 kb
Host	smart-b9dfd53e-a12b-4c9d-bf22-b2b42b5b78f8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599969949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta g_prog_failure.2599969949
Directory	/workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_smoke.718061917
Short name	T548
Test name
Test status
Simulation time	190218646 ps
CPU time	2.06 seconds
Started	Jul 29 05:36:03 PM PDT 24
Finished	Jul 29 05:36:05 PM PDT 24
Peak memory	217832 kb
Host	smart-9ec81a0e-4e7e-4aa6-b34a-f0fb26c46028
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718061917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke. 718061917
Directory	/workspace/13.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2450323608
Short name	T601
Test name
Test status
Simulation time	6593361249 ps
CPU time	58.09 seconds
Started	Jul 29 05:36:01 PM PDT 24
Finished	Jul 29 05:36:59 PM PDT 24
Peak memory	267528 kb
Host	smart-76a4eec6-a51b-43e2-8c25-50013ce72626
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450323608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt ag_state_failure.2450323608
Directory	/workspace/13.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1946680329
Short name	T786
Test name
Test status
Simulation time	719115751 ps
CPU time	16.41 seconds
Started	Jul 29 05:36:01 PM PDT 24
Finished	Jul 29 05:36:18 PM PDT 24
Peak memory	249580 kb
Host	smart-f6631cba-f6b5-4b0d-a078-e8b0a29b2886
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946680329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_state_post_trans.1946680329
Directory	/workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_prog_failure.99028258
Short name	T278
Test name
Test status
Simulation time	1033342218 ps
CPU time	4.4 seconds
Started	Jul 29 05:36:01 PM PDT 24
Finished	Jul 29 05:36:05 PM PDT 24
Peak memory	218360 kb
Host	smart-650d260c-1df7-4c2a-b2d3-093f93ecca85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99028258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.99028258
Directory	/workspace/13.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_mubi.3198636647
Short name	T404
Test name
Test status
Simulation time	691463430 ps
CPU time	10.59 seconds
Started	Jul 29 05:36:03 PM PDT 24
Finished	Jul 29 05:36:14 PM PDT 24
Peak memory	218464 kb
Host	smart-930ee103-2e1f-46cd-aacb-1033ba65e2d2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198636647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3198636647
Directory	/workspace/13.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_digest.279456873
Short name	T388
Test name
Test status
Simulation time	4524346988 ps
CPU time	19.47 seconds
Started	Jul 29 05:36:05 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	226184 kb
Host	smart-c857f385-6c16-4a33-9918-00359076b04e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279456873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di gest.279456873
Directory	/workspace/13.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/13.lc_ctrl_security_escalation.165837483
Short name	T321
Test name
Test status
Simulation time	286865106 ps
CPU time	7.24 seconds
Started	Jul 29 05:36:01 PM PDT 24
Finished	Jul 29 05:36:09 PM PDT 24
Peak memory	218436 kb
Host	smart-c08cc0a4-8925-473f-a304-f17fa8dde120
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165837483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.165837483
Directory	/workspace/13.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/13.lc_ctrl_smoke.1658781757
Short name	T414
Test name
Test status
Simulation time	307729880 ps
CPU time	4.84 seconds
Started	Jul 29 05:35:59 PM PDT 24
Finished	Jul 29 05:36:03 PM PDT 24
Peak memory	217808 kb
Host	smart-a1a9b2bc-45f5-4da6-9aba-6206af5b0937
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658781757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1658781757
Directory	/workspace/13.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_failure.2940077375
Short name	T407
Test name
Test status
Simulation time	526203234 ps
CPU time	24.33 seconds
Started	Jul 29 05:36:00 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	250944 kb
Host	smart-dee60618-d48b-4af3-a516-43388f2cfde6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940077375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2940077375
Directory	/workspace/13.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_post_trans.2605999406
Short name	T399
Test name
Test status
Simulation time	58696952 ps
CPU time	10.41 seconds
Started	Jul 29 05:36:02 PM PDT 24
Finished	Jul 29 05:36:12 PM PDT 24
Peak memory	251120 kb
Host	smart-401f73c0-85ce-4f09-8d46-2619bb7da46f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605999406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2605999406
Directory	/workspace/13.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all.642086128
Short name	T417
Test name
Test status
Simulation time	42022516787 ps
CPU time	129.14 seconds
Started	Jul 29 05:36:07 PM PDT 24
Finished	Jul 29 05:38:16 PM PDT 24
Peak memory	220552 kb
Host	smart-1fd63010-dab9-41e0-9439-46a10825d055
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642086128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.642086128
Directory	/workspace/13.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3957212507
Short name	T656
Test name
Test status
Simulation time	10651979470 ps
CPU time	384.33 seconds
Started	Jul 29 05:36:04 PM PDT 24
Finished	Jul 29 05:42:29 PM PDT 24
Peak memory	289564 kb
Host	smart-e0f9bcaf-448f-4282-bb1e-81893c14d768
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3957212507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3957212507
Directory	/workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.987641928
Short name	T502
Test name
Test status
Simulation time	22938975 ps
CPU time	0.88 seconds
Started	Jul 29 05:35:59 PM PDT 24
Finished	Jul 29 05:36:00 PM PDT 24
Peak memory	212116 kb
Host	smart-b46b8e2f-dba7-4e77-98ac-6d28952139b8
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987641928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct rl_volatile_unlock_smoke.987641928
Directory	/workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_alert_test.3516992296
Short name	T389
Test name
Test status
Simulation time	16491872 ps
CPU time	1.1 seconds
Started	Jul 29 05:36:13 PM PDT 24
Finished	Jul 29 05:36:14 PM PDT 24
Peak memory	209076 kb
Host	smart-00a0d837-4301-41db-8419-e8ee941ad79a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516992296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3516992296
Directory	/workspace/14.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.lc_ctrl_errors.3770851293
Short name	T246
Test name
Test status
Simulation time	907373126 ps
CPU time	23.27 seconds
Started	Jul 29 05:36:08 PM PDT 24
Finished	Jul 29 05:36:31 PM PDT 24
Peak memory	218364 kb
Host	smart-504ae698-386b-473a-81fc-08d70c84677c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770851293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3770851293
Directory	/workspace/14.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_access.3696291034
Short name	T286
Test name
Test status
Simulation time	140948310 ps
CPU time	4.19 seconds
Started	Jul 29 05:36:05 PM PDT 24
Finished	Jul 29 05:36:09 PM PDT 24
Peak memory	217132 kb
Host	smart-97e8bd94-58c5-4f36-a4a2-f31959cc1a3d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696291034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3696291034
Directory	/workspace/14.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_errors.333523012
Short name	T788
Test name
Test status
Simulation time	5693472351 ps
CPU time	37.57 seconds
Started	Jul 29 05:36:09 PM PDT 24
Finished	Jul 29 05:36:46 PM PDT 24
Peak memory	226196 kb
Host	smart-de455d7f-48a5-4be2-bb48-7d9c5788ace7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333523012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er rors.333523012
Directory	/workspace/14.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2662285975
Short name	T29
Test name
Test status
Simulation time	1381133434 ps
CPU time	5.07 seconds
Started	Jul 29 05:36:07 PM PDT 24
Finished	Jul 29 05:36:12 PM PDT 24
Peak memory	223016 kb
Host	smart-ea7d7d6d-a85d-482b-a285-eb7be8738d7f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662285975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_prog_failure.2662285975
Directory	/workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_smoke.3485642406
Short name	T385
Test name
Test status
Simulation time	435524311 ps
CPU time	4.34 seconds
Started	Jul 29 05:36:06 PM PDT 24
Finished	Jul 29 05:36:10 PM PDT 24
Peak memory	217904 kb
Host	smart-793c7de1-59a2-4af4-ae35-241cfdf26d05
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485642406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke .3485642406
Directory	/workspace/14.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3325178335
Short name	T91
Test name
Test status
Simulation time	2365162394 ps
CPU time	38.7 seconds
Started	Jul 29 05:36:07 PM PDT 24
Finished	Jul 29 05:36:46 PM PDT 24
Peak memory	249076 kb
Host	smart-dbf93aef-41eb-4651-be1a-b70ca94cee1d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325178335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt ag_state_failure.3325178335
Directory	/workspace/14.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.239868734
Short name	T680
Test name
Test status
Simulation time	389155230 ps
CPU time	12.5 seconds
Started	Jul 29 05:36:05 PM PDT 24
Finished	Jul 29 05:36:18 PM PDT 24
Peak memory	249456 kb
Host	smart-0e2d5d29-6ff8-4328-b7c4-76e6c41582e2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239868734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_ jtag_state_post_trans.239868734
Directory	/workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_prog_failure.1716695784
Short name	T668
Test name
Test status
Simulation time	654930142 ps
CPU time	2.75 seconds
Started	Jul 29 05:36:04 PM PDT 24
Finished	Jul 29 05:36:07 PM PDT 24
Peak memory	218336 kb
Host	smart-8bad5c14-21a7-46c3-ae01-850e65da6556
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716695784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1716695784
Directory	/workspace/14.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_mubi.1051158688
Short name	T144
Test name
Test status
Simulation time	540393973 ps
CPU time	13.83 seconds
Started	Jul 29 05:36:05 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	226200 kb
Host	smart-949cadff-ee16-4484-a79e-ec3e838be04e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051158688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1051158688
Directory	/workspace/14.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_digest.696166630
Short name	T728
Test name
Test status
Simulation time	3281874828 ps
CPU time	19.88 seconds
Started	Jul 29 05:36:05 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	218380 kb
Host	smart-21e0cfd0-3e09-4d60-b63f-fa77f7b8bcfe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696166630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di gest.696166630
Directory	/workspace/14.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_mux.2620990177
Short name	T420
Test name
Test status
Simulation time	438821743 ps
CPU time	13.51 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:28 PM PDT 24
Peak memory	225136 kb
Host	smart-45c11830-449d-4683-b0a6-ee2d903f875e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620990177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux. 2620990177
Directory	/workspace/14.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/14.lc_ctrl_security_escalation.3742317615
Short name	T410
Test name
Test status
Simulation time	1763275398 ps
CPU time	12.12 seconds
Started	Jul 29 05:36:06 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	226192 kb
Host	smart-f01b949a-4372-4a40-a9f0-be3e323c5b20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742317615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3742317615
Directory	/workspace/14.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/14.lc_ctrl_smoke.4190714767
Short name	T709
Test name
Test status
Simulation time	54571783 ps
CPU time	3.03 seconds
Started	Jul 29 05:36:04 PM PDT 24
Finished	Jul 29 05:36:07 PM PDT 24
Peak memory	217816 kb
Host	smart-75c437df-5fd5-4c40-bd99-3b8732163ece
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190714767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4190714767
Directory	/workspace/14.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_failure.1510870303
Short name	T570
Test name
Test status
Simulation time	181993744 ps
CPU time	19.72 seconds
Started	Jul 29 05:36:06 PM PDT 24
Finished	Jul 29 05:36:26 PM PDT 24
Peak memory	251092 kb
Host	smart-a5f2762d-ac0b-443c-9511-0b994869ae68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510870303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1510870303
Directory	/workspace/14.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_post_trans.3010020154
Short name	T247
Test name
Test status
Simulation time	87258265 ps
CPU time	7.52 seconds
Started	Jul 29 05:36:04 PM PDT 24
Finished	Jul 29 05:36:12 PM PDT 24
Peak memory	251008 kb
Host	smart-94e03fba-c98c-4bf1-afaa-f489985be057
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010020154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3010020154
Directory	/workspace/14.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all.2243206070
Short name	T84
Test name
Test status
Simulation time	3221958142 ps
CPU time	116.96 seconds
Started	Jul 29 05:36:05 PM PDT 24
Finished	Jul 29 05:38:02 PM PDT 24
Peak memory	275776 kb
Host	smart-4de300be-47a8-45d2-8002-0bc9e19a4726
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243206070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.2243206070
Directory	/workspace/14.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1510835897
Short name	T81
Test name
Test status
Simulation time	23777788583 ps
CPU time	403.3 seconds
Started	Jul 29 05:36:07 PM PDT 24
Finished	Jul 29 05:42:51 PM PDT 24
Peak memory	421640 kb
Host	smart-637d92c5-1e4f-43e0-89e1-1a4ee2edef85
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1510835897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1510835897
Directory	/workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1912809374
Short name	T573
Test name
Test status
Simulation time	72037273 ps
CPU time	1.05 seconds
Started	Jul 29 05:36:09 PM PDT 24
Finished	Jul 29 05:36:10 PM PDT 24
Peak memory	212980 kb
Host	smart-7d80fcf2-444c-45cf-8f6c-90c81d736aaa
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912809374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.1912809374
Directory	/workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_alert_test.1270219060
Short name	T145
Test name
Test status
Simulation time	61896516 ps
CPU time	1.2 seconds
Started	Jul 29 05:36:18 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	209048 kb
Host	smart-88664f3f-ff9c-4070-bb27-621a475ad5f0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270219060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1270219060
Directory	/workspace/15.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.lc_ctrl_errors.1756217881
Short name	T384
Test name
Test status
Simulation time	388605443 ps
CPU time	13.82 seconds
Started	Jul 29 05:36:13 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	218280 kb
Host	smart-30a5f732-1db4-4087-a6a8-8016bf57665d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756217881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1756217881
Directory	/workspace/15.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_access.1367817337
Short name	T635
Test name
Test status
Simulation time	639532664 ps
CPU time	15.95 seconds
Started	Jul 29 05:36:11 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	217600 kb
Host	smart-e53bfbd5-14fc-4444-89db-255cb7cd3fa4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367817337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1367817337
Directory	/workspace/15.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_errors.220233708
Short name	T47
Test name
Test status
Simulation time	6671063121 ps
CPU time	53.71 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:37:09 PM PDT 24
Peak memory	219092 kb
Host	smart-50e25777-2f5a-48d2-bb59-bf8a6577066c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220233708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er rors.220233708
Directory	/workspace/15.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2060929189
Short name	T222
Test name
Test status
Simulation time	182447203 ps
CPU time	6.81 seconds
Started	Jul 29 05:36:12 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	218304 kb
Host	smart-0114e3dd-063d-4604-9fa1-7397cc58bca2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060929189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_prog_failure.2060929189
Directory	/workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_smoke.4184188263
Short name	T344
Test name
Test status
Simulation time	750466771 ps
CPU time	8.46 seconds
Started	Jul 29 05:36:11 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	217724 kb
Host	smart-fc5c3b04-fd60-4e23-8b5d-3bf1f81d993e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184188263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke .4184188263
Directory	/workspace/15.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2351736026
Short name	T746
Test name
Test status
Simulation time	6316238387 ps
CPU time	51.9 seconds
Started	Jul 29 05:36:09 PM PDT 24
Finished	Jul 29 05:37:01 PM PDT 24
Peak memory	275904 kb
Host	smart-ae1666d5-dd1c-488a-9f16-0dacbb6fa4c0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351736026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.2351736026
Directory	/workspace/15.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.677585570
Short name	T750
Test name
Test status
Simulation time	842370140 ps
CPU time	14.35 seconds
Started	Jul 29 05:36:10 PM PDT 24
Finished	Jul 29 05:36:24 PM PDT 24
Peak memory	250952 kb
Host	smart-ac3a59ba-eb11-4994-8f9e-905cae1a97f0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677585570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_ jtag_state_post_trans.677585570
Directory	/workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_prog_failure.1570352280
Short name	T403
Test name
Test status
Simulation time	109759046 ps
CPU time	1.97 seconds
Started	Jul 29 05:36:10 PM PDT 24
Finished	Jul 29 05:36:12 PM PDT 24
Peak memory	222148 kb
Host	smart-b81a0f2c-57aa-41e3-8796-ab8159a9b335
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1570352280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1570352280
Directory	/workspace/15.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_mubi.2493266502
Short name	T711
Test name
Test status
Simulation time	1650016420 ps
CPU time	18.1 seconds
Started	Jul 29 05:36:10 PM PDT 24
Finished	Jul 29 05:36:28 PM PDT 24
Peak memory	226116 kb
Host	smart-c15cf06d-06f7-4009-b6f4-a7cbb363e72f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493266502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2493266502
Directory	/workspace/15.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_digest.3473345428
Short name	T752
Test name
Test status
Simulation time	427913655 ps
CPU time	16.28 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:31 PM PDT 24
Peak memory	226120 kb
Host	smart-7f4d82f3-c545-4591-a722-c17f3b0c1f4d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473345428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d igest.3473345428
Directory	/workspace/15.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_mux.3537430724
Short name	T793
Test name
Test status
Simulation time	297381097 ps
CPU time	12.18 seconds
Started	Jul 29 05:36:11 PM PDT 24
Finished	Jul 29 05:36:24 PM PDT 24
Peak memory	218220 kb
Host	smart-e9eb3859-fea4-4354-9744-3a43aa5b59d4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537430724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux. 3537430724
Directory	/workspace/15.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_security_escalation.3553979551
Short name	T787
Test name
Test status
Simulation time	243357007 ps
CPU time	7.92 seconds
Started	Jul 29 05:36:09 PM PDT 24
Finished	Jul 29 05:36:17 PM PDT 24
Peak memory	226188 kb
Host	smart-a00f42c2-7b81-4cdc-bdee-ba44875f4031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553979551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3553979551
Directory	/workspace/15.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/15.lc_ctrl_smoke.542394338
Short name	T544
Test name
Test status
Simulation time	364733039 ps
CPU time	3.6 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	217800 kb
Host	smart-f7c01793-754a-43ed-8230-4f8df33c5ad8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542394338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.542394338
Directory	/workspace/15.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_failure.3693313057
Short name	T629
Test name
Test status
Simulation time	5083030902 ps
CPU time	27.3 seconds
Started	Jul 29 05:36:10 PM PDT 24
Finished	Jul 29 05:36:37 PM PDT 24
Peak memory	246504 kb
Host	smart-3689cdbb-f4ea-4edd-8598-0fb9b4f36b0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693313057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3693313057
Directory	/workspace/15.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_post_trans.208564549
Short name	T572
Test name
Test status
Simulation time	131533498 ps
CPU time	4.02 seconds
Started	Jul 29 05:36:12 PM PDT 24
Finished	Jul 29 05:36:16 PM PDT 24
Peak memory	222640 kb
Host	smart-7ac3033f-6c60-4ba8-b702-427a892414e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208564549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.208564549
Directory	/workspace/15.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all.3643430486
Short name	T379
Test name
Test status
Simulation time	4103170317 ps
CPU time	87.74 seconds
Started	Jul 29 05:36:10 PM PDT 24
Finished	Jul 29 05:37:38 PM PDT 24
Peak memory	269896 kb
Host	smart-12acc283-2be0-427c-b5c7-5ddeef7658c7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643430486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.3643430486
Directory	/workspace/15.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3581168471
Short name	T647
Test name
Test status
Simulation time	17291308 ps
CPU time	0.92 seconds
Started	Jul 29 05:36:08 PM PDT 24
Finished	Jul 29 05:36:09 PM PDT 24
Peak memory	212020 kb
Host	smart-06f80cef-4290-4760-9bb7-58fd85c67717
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581168471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_volatile_unlock_smoke.3581168471
Directory	/workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_alert_test.3870734154
Short name	T853
Test name
Test status
Simulation time	23836741 ps
CPU time	0.96 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:16 PM PDT 24
Peak memory	208972 kb
Host	smart-0b567461-97d5-4b83-aa87-504f0eea9ffc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870734154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3870734154
Directory	/workspace/16.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.lc_ctrl_errors.1953118928
Short name	T640
Test name
Test status
Simulation time	1242077473 ps
CPU time	16.39 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	226092 kb
Host	smart-422966fe-861d-43b2-9f27-9597b45ceeec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1953118928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1953118928
Directory	/workspace/16.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_access.3162522140
Short name	T31
Test name
Test status
Simulation time	393727332 ps
CPU time	5.16 seconds
Started	Jul 29 05:36:14 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	217636 kb
Host	smart-3e36f240-b318-4743-8b5c-69aec1ca8219
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162522140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3162522140
Directory	/workspace/16.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_errors.3002987799
Short name	T798
Test name
Test status
Simulation time	1060457881 ps
CPU time	34.47 seconds
Started	Jul 29 05:36:16 PM PDT 24
Finished	Jul 29 05:36:51 PM PDT 24
Peak memory	218940 kb
Host	smart-f91ef26f-3f68-4d40-af2f-acff9dc404b6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002987799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e rrors.3002987799
Directory	/workspace/16.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1277208134
Short name	T867
Test name
Test status
Simulation time	1112111183 ps
CPU time	6.39 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:21 PM PDT 24
Peak memory	223196 kb
Host	smart-4998b670-5214-4e32-9d54-c81ccee6c223
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277208134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_prog_failure.1277208134
Directory	/workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_smoke.510102552
Short name	T475
Test name
Test status
Simulation time	378331545 ps
CPU time	6.53 seconds
Started	Jul 29 05:36:13 PM PDT 24
Finished	Jul 29 05:36:20 PM PDT 24
Peak memory	217620 kb
Host	smart-f8df3899-a106-4087-9625-7af7daae33c8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510102552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke. 510102552
Directory	/workspace/16.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1039070317
Short name	T840
Test name
Test status
Simulation time	2055823039 ps
CPU time	53.68 seconds
Started	Jul 29 05:36:16 PM PDT 24
Finished	Jul 29 05:37:10 PM PDT 24
Peak memory	268640 kb
Host	smart-28d63f95-d64e-4f90-b3ff-67af9aaeda64
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039070317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_state_failure.1039070317
Directory	/workspace/16.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1997187003
Short name	T27
Test name
Test status
Simulation time	1600925621 ps
CPU time	16.97 seconds
Started	Jul 29 05:36:17 PM PDT 24
Finished	Jul 29 05:36:34 PM PDT 24
Peak memory	250444 kb
Host	smart-aa83a7e1-f0b8-48f5-aecc-b75138b873f5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997187003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_state_post_trans.1997187003
Directory	/workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_prog_failure.2422484694
Short name	T458
Test name
Test status
Simulation time	23183617 ps
CPU time	2.01 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:17 PM PDT 24
Peak memory	218376 kb
Host	smart-8c3a4f0b-8fc5-4539-b3b8-47ed4e5d9692
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422484694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2422484694
Directory	/workspace/16.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_mubi.891461033
Short name	T559
Test name
Test status
Simulation time	1860990079 ps
CPU time	10.75 seconds
Started	Jul 29 05:36:19 PM PDT 24
Finished	Jul 29 05:36:30 PM PDT 24
Peak memory	226076 kb
Host	smart-dca210be-f147-4110-9c73-baced740cff1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891461033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.891461033
Directory	/workspace/16.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_digest.1932482986
Short name	T533
Test name
Test status
Simulation time	178108742 ps
CPU time	8.64 seconds
Started	Jul 29 05:36:16 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	226132 kb
Host	smart-4a7a6510-19ed-45f0-9d18-abac089009c0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932482986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d igest.1932482986
Directory	/workspace/16.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_mux.3330832736
Short name	T381
Test name
Test status
Simulation time	1199916873 ps
CPU time	8.68 seconds
Started	Jul 29 05:36:18 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	218336 kb
Host	smart-c866188e-fc72-47a3-9bb5-def33f81b562
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330832736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux. 3330832736
Directory	/workspace/16.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/16.lc_ctrl_security_escalation.3941452399
Short name	T625
Test name
Test status
Simulation time	1677920244 ps
CPU time	10 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	226184 kb
Host	smart-5ebdb68c-8c8f-41b0-8ddb-62bd61ee67be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941452399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3941452399
Directory	/workspace/16.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/16.lc_ctrl_smoke.3111086687
Short name	T561
Test name
Test status
Simulation time	249153977 ps
CPU time	3.08 seconds
Started	Jul 29 05:36:17 PM PDT 24
Finished	Jul 29 05:36:20 PM PDT 24
Peak memory	224592 kb
Host	smart-22daa8ab-182d-41f0-9c96-80a86d78ddc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111086687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3111086687
Directory	/workspace/16.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_failure.470889980
Short name	T733
Test name
Test status
Simulation time	752025732 ps
CPU time	27.35 seconds
Started	Jul 29 05:36:14 PM PDT 24
Finished	Jul 29 05:36:41 PM PDT 24
Peak memory	251012 kb
Host	smart-0458e127-cc66-4e66-86c4-4476deff508b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470889980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.470889980
Directory	/workspace/16.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_post_trans.3334338810
Short name	T347
Test name
Test status
Simulation time	78383576 ps
CPU time	6.2 seconds
Started	Jul 29 05:36:14 PM PDT 24
Finished	Jul 29 05:36:20 PM PDT 24
Peak memory	246708 kb
Host	smart-69490c66-6952-4687-9e38-b33d175a2419
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334338810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3334338810
Directory	/workspace/16.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all.213898046
Short name	T756
Test name
Test status
Simulation time	14179080618 ps
CPU time	116.29 seconds
Started	Jul 29 05:36:16 PM PDT 24
Finished	Jul 29 05:38:13 PM PDT 24
Peak memory	272760 kb
Host	smart-a18c3c87-2257-4568-b75f-3c3a8bc381db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213898046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.213898046
Directory	/workspace/16.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2816585862
Short name	T196
Test name
Test status
Simulation time	43041627710 ps
CPU time	2822 seconds
Started	Jul 29 05:36:17 PM PDT 24
Finished	Jul 29 06:23:20 PM PDT 24
Peak memory	644392 kb
Host	smart-4df69a58-d5e4-45ba-bdeb-1aaa12006e62
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2816585862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2816585862
Directory	/workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4237561320
Short name	T349
Test name
Test status
Simulation time	21854592 ps
CPU time	0.98 seconds
Started	Jul 29 05:36:17 PM PDT 24
Finished	Jul 29 05:36:18 PM PDT 24
Peak memory	212024 kb
Host	smart-fbe4a41e-78a1-41b9-8248-a4b101bde235
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237561320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c trl_volatile_unlock_smoke.4237561320
Directory	/workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_alert_test.3752378237
Short name	T325
Test name
Test status
Simulation time	22264106 ps
CPU time	1.07 seconds
Started	Jul 29 05:36:25 PM PDT 24
Finished	Jul 29 05:36:26 PM PDT 24
Peak memory	208996 kb
Host	smart-57c6e790-348b-4775-85d5-bcb263437f86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752378237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3752378237
Directory	/workspace/17.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.lc_ctrl_errors.231248537
Short name	T592
Test name
Test status
Simulation time	2355569566 ps
CPU time	13.94 seconds
Started	Jul 29 05:36:15 PM PDT 24
Finished	Jul 29 05:36:29 PM PDT 24
Peak memory	218340 kb
Host	smart-ef4e512a-bd6b-4c75-9708-f36def099aed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231248537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.231248537
Directory	/workspace/17.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_access.3671280664
Short name	T604
Test name
Test status
Simulation time	4229012075 ps
CPU time	10.31 seconds
Started	Jul 29 05:36:21 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	217880 kb
Host	smart-834b773e-a4ba-432a-9f86-bea5d85878c8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671280664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3671280664
Directory	/workspace/17.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_errors.3490317873
Short name	T675
Test name
Test status
Simulation time	2150311158 ps
CPU time	45.57 seconds
Started	Jul 29 05:36:22 PM PDT 24
Finished	Jul 29 05:37:08 PM PDT 24
Peak memory	218436 kb
Host	smart-49cfe2e8-bbac-4713-80df-d5b79cf5f172
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490317873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e rrors.3490317873
Directory	/workspace/17.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_smoke.761933292
Short name	T517
Test name
Test status
Simulation time	358255388 ps
CPU time	10.9 seconds
Started	Jul 29 05:36:21 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	217620 kb
Host	smart-23e56e78-23bb-4d92-ae83-bf3fecf4c61c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761933292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke. 761933292
Directory	/workspace/17.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.218453617
Short name	T661
Test name
Test status
Simulation time	2015549407 ps
CPU time	48.51 seconds
Started	Jul 29 05:36:20 PM PDT 24
Finished	Jul 29 05:37:09 PM PDT 24
Peak memory	267988 kb
Host	smart-d5c862b2-e94f-4c4f-9c25-4b93c1167d43
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218453617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_state_failure.218453617
Directory	/workspace/17.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1933137716
Short name	T590
Test name
Test status
Simulation time	427666306 ps
CPU time	14.81 seconds
Started	Jul 29 05:36:20 PM PDT 24
Finished	Jul 29 05:36:35 PM PDT 24
Peak memory	251040 kb
Host	smart-c9cbf5a3-f881-4252-a61b-0c9a915ee615
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933137716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_state_post_trans.1933137716
Directory	/workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_prog_failure.3364793370
Short name	T230
Test name
Test status
Simulation time	231248129 ps
CPU time	1.47 seconds
Started	Jul 29 05:36:18 PM PDT 24
Finished	Jul 29 05:36:20 PM PDT 24
Peak memory	218356 kb
Host	smart-1751057b-326e-4f77-a5b2-365955ab543a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3364793370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3364793370
Directory	/workspace/17.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_mubi.1296130540
Short name	T633
Test name
Test status
Simulation time	335136658 ps
CPU time	10.92 seconds
Started	Jul 29 05:36:24 PM PDT 24
Finished	Jul 29 05:36:35 PM PDT 24
Peak memory	226188 kb
Host	smart-1c516677-cb9a-4989-8556-c499a030c945
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296130540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1296130540
Directory	/workspace/17.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_digest.876772994
Short name	T707
Test name
Test status
Simulation time	1568980362 ps
CPU time	10.53 seconds
Started	Jul 29 05:36:21 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	218316 kb
Host	smart-7ef549c7-dd70-4f35-99c3-102085de16fd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876772994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di gest.876772994
Directory	/workspace/17.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_mux.725777126
Short name	T365
Test name
Test status
Simulation time	646529169 ps
CPU time	18.14 seconds
Started	Jul 29 05:36:19 PM PDT 24
Finished	Jul 29 05:36:38 PM PDT 24
Peak memory	218324 kb
Host	smart-9366dac5-b7e3-4876-b6ac-09416abfab2b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725777126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.725777126
Directory	/workspace/17.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/17.lc_ctrl_security_escalation.3201659659
Short name	T311
Test name
Test status
Simulation time	1418471745 ps
CPU time	8.29 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:35 PM PDT 24
Peak memory	225048 kb
Host	smart-be251453-aca2-441d-9732-d8e09c673d48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201659659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3201659659
Directory	/workspace/17.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_smoke.4258542742
Short name	T757
Test name
Test status
Simulation time	43934430 ps
CPU time	2.63 seconds
Started	Jul 29 05:36:16 PM PDT 24
Finished	Jul 29 05:36:19 PM PDT 24
Peak memory	217784 kb
Host	smart-f53ad37e-cbc0-4d0b-b841-bb1e42f52137
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258542742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4258542742
Directory	/workspace/17.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_failure.561269944
Short name	T540
Test name
Test status
Simulation time	207312959 ps
CPU time	25.71 seconds
Started	Jul 29 05:36:16 PM PDT 24
Finished	Jul 29 05:36:42 PM PDT 24
Peak memory	246132 kb
Host	smart-577d1db2-3e69-474a-ba20-41da2e6c6381
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561269944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.561269944
Directory	/workspace/17.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_post_trans.4224715831
Short name	T547
Test name
Test status
Simulation time	314848814 ps
CPU time	6.1 seconds
Started	Jul 29 05:36:18 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	251012 kb
Host	smart-08ae7ac2-18ac-4a0b-8a56-fd46faab24e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224715831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4224715831
Directory	/workspace/17.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all.4110628886
Short name	T855
Test name
Test status
Simulation time	14710174800 ps
CPU time	59.97 seconds
Started	Jul 29 05:36:19 PM PDT 24
Finished	Jul 29 05:37:20 PM PDT 24
Peak memory	248316 kb
Host	smart-df148325-8dc6-4eb1-bef0-fef326d78fbf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110628886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.4110628886
Directory	/workspace/17.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1626512282
Short name	T179
Test name
Test status
Simulation time	43771286 ps
CPU time	0.82 seconds
Started	Jul 29 05:36:17 PM PDT 24
Finished	Jul 29 05:36:18 PM PDT 24
Peak memory	211984 kb
Host	smart-c14cb76b-52b7-4f25-9fda-b96e00a4c703
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626512282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_volatile_unlock_smoke.1626512282
Directory	/workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_alert_test.1028160810
Short name	T468
Test name
Test status
Simulation time	31757896 ps
CPU time	1.39 seconds
Started	Jul 29 05:36:27 PM PDT 24
Finished	Jul 29 05:36:29 PM PDT 24
Peak memory	209064 kb
Host	smart-f017afd9-27fb-4d0c-b1b8-dc84c34ebb6d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028160810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1028160810
Directory	/workspace/18.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.lc_ctrl_errors.3046058643
Short name	T343
Test name
Test status
Simulation time	1518322940 ps
CPU time	12.23 seconds
Started	Jul 29 05:36:20 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	218276 kb
Host	smart-86f2e61b-e56c-467e-8ca3-53210776ce57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046058643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3046058643
Directory	/workspace/18.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_access.741178594
Short name	T664
Test name
Test status
Simulation time	1144283963 ps
CPU time	7.21 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:34 PM PDT 24
Peak memory	217512 kb
Host	smart-99cbcc38-c323-4d19-a611-da9457d1ef38
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741178594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.741178594
Directory	/workspace/18.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2261477636
Short name	T530
Test name
Test status
Simulation time	1196251152 ps
CPU time	6.34 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	218296 kb
Host	smart-6a32d750-1d0d-4fdf-b659-d8e232c5b1cc
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261477636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_prog_failure.2261477636
Directory	/workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_smoke.2975583393
Short name	T872
Test name
Test status
Simulation time	131041897 ps
CPU time	1.68 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	217720 kb
Host	smart-f3edbba1-e63c-45f4-9df6-c7719f5f1e57
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975583393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke .2975583393
Directory	/workspace/18.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.739158614
Short name	T619
Test name
Test status
Simulation time	1998503327 ps
CPU time	51.15 seconds
Started	Jul 29 05:36:20 PM PDT 24
Finished	Jul 29 05:37:11 PM PDT 24
Peak memory	277212 kb
Host	smart-b3b88c06-3349-4ac8-9cb7-33725ce98e65
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739158614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_state_failure.739158614
Directory	/workspace/18.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1077177433
Short name	T269
Test name
Test status
Simulation time	517071338 ps
CPU time	11.95 seconds
Started	Jul 29 05:36:27 PM PDT 24
Finished	Jul 29 05:36:40 PM PDT 24
Peak memory	250372 kb
Host	smart-75d71abb-437b-4cd2-8eee-a5b9a823372e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077177433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.1077177433
Directory	/workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_prog_failure.1142654918
Short name	T174
Test name
Test status
Simulation time	127677177 ps
CPU time	3.47 seconds
Started	Jul 29 05:36:21 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	222728 kb
Host	smart-1b48afe8-e870-4248-91ae-111a380305d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142654918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1142654918
Directory	/workspace/18.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_mubi.4286266785
Short name	T537
Test name
Test status
Simulation time	576379523 ps
CPU time	23.8 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:50 PM PDT 24
Peak memory	218428 kb
Host	smart-99a04130-4e9d-42eb-be05-9cacdcc63c3b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286266785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.4286266785
Directory	/workspace/18.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_digest.2382907905
Short name	T294
Test name
Test status
Simulation time	1010495035 ps
CPU time	11.5 seconds
Started	Jul 29 05:36:24 PM PDT 24
Finished	Jul 29 05:36:36 PM PDT 24
Peak memory	226040 kb
Host	smart-124d6dd1-aaa4-4276-a126-e6015535530d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382907905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d igest.2382907905
Directory	/workspace/18.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_mux.1099787413
Short name	T460
Test name
Test status
Simulation time	344852467 ps
CPU time	13.61 seconds
Started	Jul 29 05:36:24 PM PDT 24
Finished	Jul 29 05:36:37 PM PDT 24
Peak memory	226068 kb
Host	smart-f48458aa-98ba-4e1b-91c4-4d084c2648bb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099787413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux. 1099787413
Directory	/workspace/18.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/18.lc_ctrl_security_escalation.2108662430
Short name	T208
Test name
Test status
Simulation time	486264000 ps
CPU time	17 seconds
Started	Jul 29 05:36:21 PM PDT 24
Finished	Jul 29 05:36:38 PM PDT 24
Peak memory	226156 kb
Host	smart-e2c238bc-308f-4a3f-a895-394b56b1600d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2108662430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2108662430
Directory	/workspace/18.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/18.lc_ctrl_smoke.795668939
Short name	T297
Test name
Test status
Simulation time	172766969 ps
CPU time	6.18 seconds
Started	Jul 29 05:36:19 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	217808 kb
Host	smart-44d7b72d-8f83-4e72-b0f7-5b71a0601ed0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795668939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.795668939
Directory	/workspace/18.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_failure.242846003
Short name	T266
Test name
Test status
Simulation time	714415128 ps
CPU time	19.18 seconds
Started	Jul 29 05:36:25 PM PDT 24
Finished	Jul 29 05:36:44 PM PDT 24
Peak memory	251012 kb
Host	smart-145962d5-9c73-4b7f-b274-3b23f1375aa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242846003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.242846003
Directory	/workspace/18.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_post_trans.2969018424
Short name	T43
Test name
Test status
Simulation time	50190623 ps
CPU time	5.87 seconds
Started	Jul 29 05:36:20 PM PDT 24
Finished	Jul 29 05:36:26 PM PDT 24
Peak memory	246876 kb
Host	smart-6bc54f24-d68f-4341-a935-8201f4d2f6f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969018424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2969018424
Directory	/workspace/18.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all.1467444241
Short name	T659
Test name
Test status
Simulation time	39056912824 ps
CPU time	280.89 seconds
Started	Jul 29 05:36:27 PM PDT 24
Finished	Jul 29 05:41:08 PM PDT 24
Peak memory	286580 kb
Host	smart-df644725-cf02-4673-826e-24eb0536e8a2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467444241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.1467444241
Directory	/workspace/18.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2539904728
Short name	T171
Test name
Test status
Simulation time	13978698 ps
CPU time	0.92 seconds
Started	Jul 29 05:36:24 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	212048 kb
Host	smart-ff29bc7c-ceaa-4875-a263-ccd59c8c748b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539904728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_volatile_unlock_smoke.2539904728
Directory	/workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_alert_test.86335266
Short name	T70
Test name
Test status
Simulation time	57165309 ps
CPU time	0.88 seconds
Started	Jul 29 05:36:29 PM PDT 24
Finished	Jul 29 05:36:30 PM PDT 24
Peak memory	208944 kb
Host	smart-ab4dd8fe-03ae-42ce-a5cf-fbb6c37b82cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86335266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.86335266
Directory	/workspace/19.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_errors.2760152732
Short name	T603
Test name
Test status
Simulation time	200721991 ps
CPU time	8.03 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:36:36 PM PDT 24
Peak memory	218364 kb
Host	smart-598a4b4d-ce23-4409-84c1-74a7ce6ad1f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760152732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2760152732
Directory	/workspace/19.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_access.2730260867
Short name	T464
Test name
Test status
Simulation time	107305275 ps
CPU time	2.07 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:36:30 PM PDT 24
Peak memory	217140 kb
Host	smart-706f3b99-c142-4aad-8aa4-6599bb6178df
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730260867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2730260867
Directory	/workspace/19.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_errors.2646169250
Short name	T593
Test name
Test status
Simulation time	1026566983 ps
CPU time	19.44 seconds
Started	Jul 29 05:36:27 PM PDT 24
Finished	Jul 29 05:36:47 PM PDT 24
Peak memory	218316 kb
Host	smart-0b822a7a-b62e-4fb4-a5aa-81d558921090
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646169250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.2646169250
Directory	/workspace/19.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.789089368
Short name	T506
Test name
Test status
Simulation time	4082339140 ps
CPU time	8.75 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:36 PM PDT 24
Peak memory	218412 kb
Host	smart-691d59bc-1d7e-4222-b642-dc37c9a4f2b7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789089368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag _prog_failure.789089368
Directory	/workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_smoke.2581227539
Short name	T860
Test name
Test status
Simulation time	2464856445 ps
CPU time	12.6 seconds
Started	Jul 29 05:36:29 PM PDT 24
Finished	Jul 29 05:36:42 PM PDT 24
Peak memory	217712 kb
Host	smart-7d8acc27-0096-4096-a685-8b8f256b4267
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581227539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke .2581227539
Directory	/workspace/19.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3121706932
Short name	T513
Test name
Test status
Simulation time	378073883 ps
CPU time	13.4 seconds
Started	Jul 29 05:36:27 PM PDT 24
Finished	Jul 29 05:36:41 PM PDT 24
Peak memory	226368 kb
Host	smart-2b9ad9dc-3249-4dca-b488-98c851e1dcdb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121706932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_state_post_trans.3121706932
Directory	/workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_prog_failure.1668261258
Short name	T643
Test name
Test status
Simulation time	267090958 ps
CPU time	2.63 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:36:31 PM PDT 24
Peak memory	218356 kb
Host	smart-8327914e-cc79-473d-a983-3343780b339f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668261258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1668261258
Directory	/workspace/19.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_mubi.2354641916
Short name	T291
Test name
Test status
Simulation time	297452131 ps
CPU time	13.42 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:40 PM PDT 24
Peak memory	219176 kb
Host	smart-61770939-06cd-4d3c-818a-96eb0374b17f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354641916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2354641916
Directory	/workspace/19.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_digest.2315045326
Short name	T617
Test name
Test status
Simulation time	528638605 ps
CPU time	7.93 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:36:36 PM PDT 24
Peak memory	218312 kb
Host	smart-f7048774-5d15-4e98-a450-5493686ed4d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315045326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d igest.2315045326
Directory	/workspace/19.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_mux.790746470
Short name	T296
Test name
Test status
Simulation time	255904000 ps
CPU time	10.35 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:37 PM PDT 24
Peak memory	226024 kb
Host	smart-e81fbe25-4040-4704-8c75-2ce86a646e28
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790746470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.790746470
Directory	/workspace/19.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/19.lc_ctrl_security_escalation.4041674457
Short name	T538
Test name
Test status
Simulation time	4803705616 ps
CPU time	19.51 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:36:48 PM PDT 24
Peak memory	226236 kb
Host	smart-ffb9c3bb-4a3b-4b61-8fb9-26d194a0d275
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4041674457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.4041674457
Directory	/workspace/19.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_smoke.1083703683
Short name	T158
Test name
Test status
Simulation time	183172036 ps
CPU time	3.1 seconds
Started	Jul 29 05:36:24 PM PDT 24
Finished	Jul 29 05:36:28 PM PDT 24
Peak memory	214912 kb
Host	smart-ec43c34f-8796-4a43-8f26-f6e9c95bf625
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083703683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1083703683
Directory	/workspace/19.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_failure.3041354490
Short name	T531
Test name
Test status
Simulation time	1114098078 ps
CPU time	28.98 seconds
Started	Jul 29 05:36:22 PM PDT 24
Finished	Jul 29 05:36:52 PM PDT 24
Peak memory	250940 kb
Host	smart-eeb60b9d-332f-4ad6-997e-736d9f03e86b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041354490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3041354490
Directory	/workspace/19.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_post_trans.3113495853
Short name	T163
Test name
Test status
Simulation time	97805802 ps
CPU time	8.74 seconds
Started	Jul 29 05:36:27 PM PDT 24
Finished	Jul 29 05:36:36 PM PDT 24
Peak memory	250996 kb
Host	smart-367595d9-e93c-40ba-a88a-2453316c7423
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113495853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3113495853
Directory	/workspace/19.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all.2910793359
Short name	T85
Test name
Test status
Simulation time	9045702983 ps
CPU time	60.94 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:37:29 PM PDT 24
Peak memory	276020 kb
Host	smart-35a7698c-2ae7-447c-b897-45c8951fd8b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910793359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.2910793359
Directory	/workspace/19.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3756850723
Short name	T19
Test name
Test status
Simulation time	222987398896 ps
CPU time	850.98 seconds
Started	Jul 29 05:36:30 PM PDT 24
Finished	Jul 29 05:50:41 PM PDT 24
Peak memory	300412 kb
Host	smart-124f9db7-15b7-4f5b-b196-3d9388282b94
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3756850723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3756850723
Directory	/workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.830409578
Short name	T560
Test name
Test status
Simulation time	31510008 ps
CPU time	0.95 seconds
Started	Jul 29 05:36:26 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	212904 kb
Host	smart-a9827246-0da6-4494-9d20-31919d86ac25
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830409578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct rl_volatile_unlock_smoke.830409578
Directory	/workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_alert_test.2418694054
Short name	T442
Test name
Test status
Simulation time	21244129 ps
CPU time	1.01 seconds
Started	Jul 29 05:35:13 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	209012 kb
Host	smart-c586e2a7-ee14-478d-bd6a-35a50ce74915
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418694054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2418694054
Directory	/workspace/2.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.lc_ctrl_errors.1150878307
Short name	T790
Test name
Test status
Simulation time	363763699 ps
CPU time	13.5 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:26 PM PDT 24
Peak memory	218376 kb
Host	smart-77e00465-31c0-4458-855b-ebf2be1699a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150878307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1150878307
Directory	/workspace/2.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_access.2612017694
Short name	T749
Test name
Test status
Simulation time	1245966609 ps
CPU time	4.05 seconds
Started	Jul 29 05:35:11 PM PDT 24
Finished	Jul 29 05:35:15 PM PDT 24
Peak memory	217364 kb
Host	smart-46ab02d8-f90a-43d4-a3b4-e123c45e3d5d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612017694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2612017694
Directory	/workspace/2.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_errors.2330366023
Short name	T608
Test name
Test status
Simulation time	8999501547 ps
CPU time	37.95 seconds
Started	Jul 29 05:35:15 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	219016 kb
Host	smart-1ea18a70-3663-419d-ba76-931206d97a2d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330366023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er rors.2330366023
Directory	/workspace/2.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_priority.244302860
Short name	T827
Test name
Test status
Simulation time	8500847648 ps
CPU time	16.59 seconds
Started	Jul 29 05:35:15 PM PDT 24
Finished	Jul 29 05:35:32 PM PDT 24
Peak memory	217964 kb
Host	smart-0174e60b-ae08-44bc-88e1-41af69fd3d21
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244302860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.244302860
Directory	/workspace/2.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3872560387
Short name	T650
Test name
Test status
Simulation time	2847592943 ps
CPU time	10.59 seconds
Started	Jul 29 05:35:13 PM PDT 24
Finished	Jul 29 05:35:23 PM PDT 24
Peak memory	218364 kb
Host	smart-db784024-ad88-4c28-be34-3af2a18dab0a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872560387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _prog_failure.3872560387
Directory	/workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1320061585
Short name	T727
Test name
Test status
Simulation time	1500098224 ps
CPU time	41.6 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	217616 kb
Host	smart-af256a1c-4f81-481d-b7c3-53525858f0e2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320061585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_regwen_during_op.1320061585
Directory	/workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_smoke.1134629595
Short name	T483
Test name
Test status
Simulation time	800618424 ps
CPU time	20.47 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:43 PM PDT 24
Peak memory	217732 kb
Host	smart-dd4368bd-73c5-4669-9ebf-f39bdfb24dee
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134629595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke. 1134629595
Directory	/workspace/2.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1353307130
Short name	T568
Test name
Test status
Simulation time	4549515496 ps
CPU time	39.76 seconds
Started	Jul 29 05:35:15 PM PDT 24
Finished	Jul 29 05:35:55 PM PDT 24
Peak memory	275596 kb
Host	smart-4ed07c23-8706-4f91-964b-09eb9131cb82
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353307130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_state_failure.1353307130
Directory	/workspace/2.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.833363265
Short name	T555
Test name
Test status
Simulation time	611547415 ps
CPU time	12.4 seconds
Started	Jul 29 05:35:15 PM PDT 24
Finished	Jul 29 05:35:28 PM PDT 24
Peak memory	250916 kb
Host	smart-8876945d-1457-4a54-8e01-76273f12b59b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833363265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j tag_state_post_trans.833363265
Directory	/workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_prog_failure.517664244
Short name	T556
Test name
Test status
Simulation time	1464228081 ps
CPU time	3.21 seconds
Started	Jul 29 05:35:23 PM PDT 24
Finished	Jul 29 05:35:26 PM PDT 24
Peak memory	218364 kb
Host	smart-9c655dd4-3a21-4ca6-866e-1e4e91f5abba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517664244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.517664244
Directory	/workspace/2.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_regwen_during_op.90612730
Short name	T68
Test name
Test status
Simulation time	458107940 ps
CPU time	8.56 seconds
Started	Jul 29 05:35:18 PM PDT 24
Finished	Jul 29 05:35:26 PM PDT 24
Peak memory	217788 kb
Host	smart-59eeb3a8-0194-4901-9d39-f10c3f13e02f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90612730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.90612730
Directory	/workspace/2.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_cm.1549302279
Short name	T54
Test name
Test status
Simulation time	414088635 ps
CPU time	22.28 seconds
Started	Jul 29 05:35:14 PM PDT 24
Finished	Jul 29 05:35:36 PM PDT 24
Peak memory	268664 kb
Host	smart-2673aaf4-4b0b-43fe-ac39-13887e07da54
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549302279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1549302279
Directory	/workspace/2.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_mubi.1337017491
Short name	T479
Test name
Test status
Simulation time	1625617535 ps
CPU time	17.67 seconds
Started	Jul 29 05:35:15 PM PDT 24
Finished	Jul 29 05:35:33 PM PDT 24
Peak memory	226152 kb
Host	smart-d52a7878-4dc3-4b56-869d-c1e3d3594483
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337017491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1337017491
Directory	/workspace/2.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_digest.482928180
Short name	T704
Test name
Test status
Simulation time	1406182444 ps
CPU time	13.94 seconds
Started	Jul 29 05:35:13 PM PDT 24
Finished	Jul 29 05:35:27 PM PDT 24
Peak memory	226112 kb
Host	smart-d242f4cd-b03b-4f5d-a73b-db208cef0c76
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482928180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig est.482928180
Directory	/workspace/2.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_mux.1072568716
Short name	T218
Test name
Test status
Simulation time	440022418 ps
CPU time	9.2 seconds
Started	Jul 29 05:35:15 PM PDT 24
Finished	Jul 29 05:35:24 PM PDT 24
Peak memory	226116 kb
Host	smart-34fdcfad-b50f-43ba-9221-63f772cb2910
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072568716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1 072568716
Directory	/workspace/2.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/2.lc_ctrl_security_escalation.4282101470
Short name	T22
Test name
Test status
Simulation time	1240546114 ps
CPU time	14.71 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:27 PM PDT 24
Peak memory	226100 kb
Host	smart-2db03ac1-c40f-431f-be0b-4ef036c23db6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282101470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.4282101470
Directory	/workspace/2.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/2.lc_ctrl_smoke.1837586058
Short name	T611
Test name
Test status
Simulation time	174553219 ps
CPU time	1.65 seconds
Started	Jul 29 05:35:11 PM PDT 24
Finished	Jul 29 05:35:13 PM PDT 24
Peak memory	213776 kb
Host	smart-b6dd3552-4480-414c-bd2a-d21b2f39b717
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837586058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1837586058
Directory	/workspace/2.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_failure.4117470272
Short name	T839
Test name
Test status
Simulation time	482457204 ps
CPU time	25.83 seconds
Started	Jul 29 05:35:14 PM PDT 24
Finished	Jul 29 05:35:40 PM PDT 24
Peak memory	251044 kb
Host	smart-d27d0fa8-7096-4e56-8b39-58a09af07051
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4117470272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4117470272
Directory	/workspace/2.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_post_trans.1712727741
Short name	T699
Test name
Test status
Simulation time	152947294 ps
CPU time	7.04 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:19 PM PDT 24
Peak memory	250912 kb
Host	smart-282593bd-84da-4f39-a709-17f92fca490a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712727741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1712727741
Directory	/workspace/2.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_stress_all.4147564788
Short name	T383
Test name
Test status
Simulation time	3924717818 ps
CPU time	106.66 seconds
Started	Jul 29 05:35:14 PM PDT 24
Finished	Jul 29 05:37:00 PM PDT 24
Peak memory	274228 kb
Host	smart-548ec5bd-75cd-4a05-9479-07f616e65705
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147564788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.4147564788
Directory	/workspace/2.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.41978914
Short name	T738
Test name
Test status
Simulation time	34589058 ps
CPU time	0.84 seconds
Started	Jul 29 05:35:12 PM PDT 24
Finished	Jul 29 05:35:12 PM PDT 24
Peak memory	212028 kb
Host	smart-e9aae2b7-6271-41e1-b710-a031346f93d0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41978914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _volatile_unlock_smoke.41978914
Directory	/workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_alert_test.2495107483
Short name	T272
Test name
Test status
Simulation time	23019978 ps
CPU time	0.98 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:36:37 PM PDT 24
Peak memory	209204 kb
Host	smart-233c9981-90b4-4116-9e35-866f29589ee1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495107483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2495107483
Directory	/workspace/20.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.lc_ctrl_errors.1112313327
Short name	T415
Test name
Test status
Simulation time	7852659439 ps
CPU time	20.8 seconds
Started	Jul 29 05:36:29 PM PDT 24
Finished	Jul 29 05:36:50 PM PDT 24
Peak memory	218776 kb
Host	smart-f451bd8a-bb6a-4de2-be70-181f7075fb31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112313327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1112313327
Directory	/workspace/20.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/20.lc_ctrl_jtag_access.936810809
Short name	T157
Test name
Test status
Simulation time	79222419 ps
CPU time	1.6 seconds
Started	Jul 29 05:36:30 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	217248 kb
Host	smart-9ee29c6c-be06-4be7-bacc-6da1cc16b526
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936810809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.936810809
Directory	/workspace/20.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/20.lc_ctrl_prog_failure.3574656094
Short name	T229
Test name
Test status
Simulation time	47714667 ps
CPU time	2.19 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:36:31 PM PDT 24
Peak memory	222316 kb
Host	smart-aa6952ef-26a5-4506-86f4-ec47b4eed8ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574656094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3574656094
Directory	/workspace/20.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_mubi.2789201244
Short name	T214
Test name
Test status
Simulation time	1985710765 ps
CPU time	16.89 seconds
Started	Jul 29 05:36:31 PM PDT 24
Finished	Jul 29 05:36:48 PM PDT 24
Peak memory	226184 kb
Host	smart-2eb44833-27dd-457a-918b-1e78e1e7bb82
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789201244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2789201244
Directory	/workspace/20.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_digest.3636890337
Short name	T681
Test name
Test status
Simulation time	1214413106 ps
CPU time	7.71 seconds
Started	Jul 29 05:36:28 PM PDT 24
Finished	Jul 29 05:36:36 PM PDT 24
Peak memory	218328 kb
Host	smart-5acb9e2d-a2bd-4c3a-a3c8-07a5c2151a11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636890337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d igest.3636890337
Directory	/workspace/20.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_mux.1235722081
Short name	T61
Test name
Test status
Simulation time	6322764338 ps
CPU time	10.37 seconds
Started	Jul 29 05:36:30 PM PDT 24
Finished	Jul 29 05:36:41 PM PDT 24
Peak memory	218372 kb
Host	smart-a4b6a6f3-93f8-4e23-b560-89a8142357b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235722081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 1235722081
Directory	/workspace/20.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/20.lc_ctrl_security_escalation.3474540045
Short name	T802
Test name
Test status
Simulation time	244779650 ps
CPU time	9.18 seconds
Started	Jul 29 05:36:31 PM PDT 24
Finished	Jul 29 05:36:40 PM PDT 24
Peak memory	226168 kb
Host	smart-f8a72b43-1787-46b9-afac-9f366085a318
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474540045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3474540045
Directory	/workspace/20.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/20.lc_ctrl_smoke.2275108667
Short name	T449
Test name
Test status
Simulation time	349383309 ps
CPU time	1.94 seconds
Started	Jul 29 05:36:29 PM PDT 24
Finished	Jul 29 05:36:31 PM PDT 24
Peak memory	214092 kb
Host	smart-2caafd1a-b9b2-4a9d-a911-3a137d7e2bc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275108667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2275108667
Directory	/workspace/20.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_failure.774065378
Short name	T753
Test name
Test status
Simulation time	219977927 ps
CPU time	18.21 seconds
Started	Jul 29 05:36:35 PM PDT 24
Finished	Jul 29 05:36:54 PM PDT 24
Peak memory	250920 kb
Host	smart-92a84754-3401-40f0-9c36-8e65684fc1f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=774065378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.774065378
Directory	/workspace/20.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_post_trans.3432055431
Short name	T638
Test name
Test status
Simulation time	66244769 ps
CPU time	6.89 seconds
Started	Jul 29 05:36:31 PM PDT 24
Finished	Jul 29 05:36:38 PM PDT 24
Peak memory	246964 kb
Host	smart-c5aab967-a720-43ab-bf2f-a0b7166ee1d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3432055431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3432055431
Directory	/workspace/20.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all.1543650669
Short name	T182
Test name
Test status
Simulation time	6443359710 ps
CPU time	118.66 seconds
Started	Jul 29 05:36:33 PM PDT 24
Finished	Jul 29 05:38:31 PM PDT 24
Peak memory	267896 kb
Host	smart-93c938b8-aed5-4a76-b220-8f91741224c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543650669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.1543650669
Directory	/workspace/20.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1792810977
Short name	T261
Test name
Test status
Simulation time	33172127 ps
CPU time	0.8 seconds
Started	Jul 29 05:36:32 PM PDT 24
Finished	Jul 29 05:36:33 PM PDT 24
Peak memory	212120 kb
Host	smart-806ca9da-29e1-4efb-b71b-e2ab4156243d
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792810977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c trl_volatile_unlock_smoke.1792810977
Directory	/workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_alert_test.1634540329
Short name	T557
Test name
Test status
Simulation time	19250669 ps
CPU time	0.81 seconds
Started	Jul 29 05:36:33 PM PDT 24
Finished	Jul 29 05:36:34 PM PDT 24
Peak memory	209412 kb
Host	smart-b4caff75-0112-4195-82ed-7523dc3e3f85
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634540329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1634540329
Directory	/workspace/21.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.lc_ctrl_errors.1010598354
Short name	T162
Test name
Test status
Simulation time	1623920904 ps
CPU time	12.82 seconds
Started	Jul 29 05:36:32 PM PDT 24
Finished	Jul 29 05:36:45 PM PDT 24
Peak memory	218356 kb
Host	smart-d4372b4a-2f9a-4820-83af-2aa2c9d111ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1010598354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1010598354
Directory	/workspace/21.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/21.lc_ctrl_jtag_access.1155070695
Short name	T36
Test name
Test status
Simulation time	488057175 ps
CPU time	12.55 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:36:49 PM PDT 24
Peak memory	217552 kb
Host	smart-de20e20c-f3e7-4a67-9e1f-ba3b2a7e5ec0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155070695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1155070695
Directory	/workspace/21.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/21.lc_ctrl_prog_failure.4202810893
Short name	T357
Test name
Test status
Simulation time	121456632 ps
CPU time	1.74 seconds
Started	Jul 29 05:36:32 PM PDT 24
Finished	Jul 29 05:36:34 PM PDT 24
Peak memory	218336 kb
Host	smart-1f77e04d-ec4f-4a6c-b0bc-6b375ee2ddf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202810893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4202810893
Directory	/workspace/21.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_mubi.3102528944
Short name	T332
Test name
Test status
Simulation time	1485722519 ps
CPU time	13.47 seconds
Started	Jul 29 05:36:35 PM PDT 24
Finished	Jul 29 05:36:49 PM PDT 24
Peak memory	219984 kb
Host	smart-bdcb96f2-9d26-4d09-9d1a-6b890bb15d0e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102528944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3102528944
Directory	/workspace/21.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_digest.2766441357
Short name	T253
Test name
Test status
Simulation time	2337412243 ps
CPU time	12.16 seconds
Started	Jul 29 05:36:34 PM PDT 24
Finished	Jul 29 05:36:47 PM PDT 24
Peak memory	218356 kb
Host	smart-4859f08c-0c37-4c28-808a-8a2c6e0c786d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766441357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d igest.2766441357
Directory	/workspace/21.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_mux.2409565845
Short name	T669
Test name
Test status
Simulation time	268161383 ps
CPU time	8.52 seconds
Started	Jul 29 05:36:29 PM PDT 24
Finished	Jul 29 05:36:38 PM PDT 24
Peak memory	218324 kb
Host	smart-aa477191-37d9-490b-aa0d-5af41314ed21
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409565845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 2409565845
Directory	/workspace/21.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/21.lc_ctrl_security_escalation.63338265
Short name	T447
Test name
Test status
Simulation time	601064223 ps
CPU time	12.94 seconds
Started	Jul 29 05:36:31 PM PDT 24
Finished	Jul 29 05:36:44 PM PDT 24
Peak memory	218432 kb
Host	smart-429a97f2-f49b-4cec-bf15-c296305b3d61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=63338265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.63338265
Directory	/workspace/21.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_smoke.2997999099
Short name	T451
Test name
Test status
Simulation time	125174321 ps
CPU time	2.24 seconds
Started	Jul 29 05:36:32 PM PDT 24
Finished	Jul 29 05:36:34 PM PDT 24
Peak memory	214792 kb
Host	smart-3e00f99a-4788-4ce6-9964-950e675639d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997999099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2997999099
Directory	/workspace/21.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_failure.1719981238
Short name	T416
Test name
Test status
Simulation time	419293981 ps
CPU time	23.94 seconds
Started	Jul 29 05:36:35 PM PDT 24
Finished	Jul 29 05:36:59 PM PDT 24
Peak memory	250932 kb
Host	smart-f9bcd98e-3ca2-4ac4-a64c-33db370b0ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719981238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1719981238
Directory	/workspace/21.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_post_trans.2322840574
Short name	T734
Test name
Test status
Simulation time	81427383 ps
CPU time	3.39 seconds
Started	Jul 29 05:36:31 PM PDT 24
Finished	Jul 29 05:36:35 PM PDT 24
Peak memory	226464 kb
Host	smart-fd4e8c3a-94ac-43e2-b39c-e93072ecefb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322840574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2322840574
Directory	/workspace/21.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all.4012920787
Short name	T578
Test name
Test status
Simulation time	51054052634 ps
CPU time	79.46 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:37:55 PM PDT 24
Peak memory	267388 kb
Host	smart-6fd9c0ed-2bed-426a-b31f-d86aeba77c5b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012920787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.4012920787
Directory	/workspace/21.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3184216393
Short name	T143
Test name
Test status
Simulation time	46801250961 ps
CPU time	182.28 seconds
Started	Jul 29 05:36:32 PM PDT 24
Finished	Jul 29 05:39:34 PM PDT 24
Peak memory	275952 kb
Host	smart-f99a52bf-4a52-4c05-9a4c-f968dc641123
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3184216393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3184216393
Directory	/workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.5121975
Short name	T729
Test name
Test status
Simulation time	14628968 ps
CPU time	0.96 seconds
Started	Jul 29 05:36:31 PM PDT 24
Finished	Jul 29 05:36:32 PM PDT 24
Peak memory	212040 kb
Host	smart-35d5b4a0-a123-4781-8b58-7204a4d5f1c5
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5121975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl _volatile_unlock_smoke.5121975
Directory	/workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_alert_test.63028905
Short name	T258
Test name
Test status
Simulation time	49993152 ps
CPU time	0.91 seconds
Started	Jul 29 05:36:37 PM PDT 24
Finished	Jul 29 05:36:39 PM PDT 24
Peak memory	208968 kb
Host	smart-599d7c22-aedd-40f7-bd73-7e8410f94692
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63028905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.63028905
Directory	/workspace/22.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.lc_ctrl_errors.3716670722
Short name	T498
Test name
Test status
Simulation time	609586453 ps
CPU time	16.41 seconds
Started	Jul 29 05:36:39 PM PDT 24
Finished	Jul 29 05:36:55 PM PDT 24
Peak memory	218364 kb
Host	smart-66562a95-7628-4ab7-a571-0f9643ab8f72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716670722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3716670722
Directory	/workspace/22.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/22.lc_ctrl_jtag_access.3354700807
Short name	T180
Test name
Test status
Simulation time	348092190 ps
CPU time	9.9 seconds
Started	Jul 29 05:36:35 PM PDT 24
Finished	Jul 29 05:36:45 PM PDT 24
Peak memory	217632 kb
Host	smart-9a1c5731-b08f-48e4-b848-da6261401a19
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354700807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3354700807
Directory	/workspace/22.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/22.lc_ctrl_prog_failure.4128890892
Short name	T712
Test name
Test status
Simulation time	672346331 ps
CPU time	2.42 seconds
Started	Jul 29 05:36:35 PM PDT 24
Finished	Jul 29 05:36:37 PM PDT 24
Peak memory	218356 kb
Host	smart-50561019-dc16-4e6a-badb-8dcdaea60c0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128890892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.4128890892
Directory	/workspace/22.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_mubi.3743808972
Short name	T624
Test name
Test status
Simulation time	996192336 ps
CPU time	14.74 seconds
Started	Jul 29 05:36:37 PM PDT 24
Finished	Jul 29 05:36:52 PM PDT 24
Peak memory	226188 kb
Host	smart-98ddf657-1880-480b-ac5b-885d67f13335
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743808972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3743808972
Directory	/workspace/22.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_digest.3945231820
Short name	T314
Test name
Test status
Simulation time	2736237138 ps
CPU time	10.76 seconds
Started	Jul 29 05:36:39 PM PDT 24
Finished	Jul 29 05:36:49 PM PDT 24
Peak memory	226184 kb
Host	smart-0fe89041-eec8-4a6c-be31-dcd1d7e96c8d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945231820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d igest.3945231820
Directory	/workspace/22.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_mux.1835708808
Short name	T280
Test name
Test status
Simulation time	356866711 ps
CPU time	11.36 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:36:47 PM PDT 24
Peak memory	218328 kb
Host	smart-295ac606-3146-4bb0-ab14-f15305436641
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835708808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux. 1835708808
Directory	/workspace/22.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/22.lc_ctrl_security_escalation.1628317183
Short name	T206
Test name
Test status
Simulation time	814523867 ps
CPU time	10.49 seconds
Started	Jul 29 05:36:35 PM PDT 24
Finished	Jul 29 05:36:46 PM PDT 24
Peak memory	218372 kb
Host	smart-b30e3ce9-3d73-460d-9ab9-c168c16cc41b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628317183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1628317183
Directory	/workspace/22.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/22.lc_ctrl_smoke.1290953861
Short name	T2
Test name
Test status
Simulation time	97470375 ps
CPU time	2.75 seconds
Started	Jul 29 05:36:30 PM PDT 24
Finished	Jul 29 05:36:33 PM PDT 24
Peak memory	214664 kb
Host	smart-d7f477f0-a495-423c-9fcb-838d458714ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290953861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1290953861
Directory	/workspace/22.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_failure.1073001133
Short name	T370
Test name
Test status
Simulation time	247852257 ps
CPU time	19.24 seconds
Started	Jul 29 05:36:31 PM PDT 24
Finished	Jul 29 05:36:51 PM PDT 24
Peak memory	250976 kb
Host	smart-a27cfcc9-71d1-426e-9a68-604a9754f7e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073001133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1073001133
Directory	/workspace/22.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_post_trans.961119971
Short name	T401
Test name
Test status
Simulation time	241651316 ps
CPU time	3.64 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:36:40 PM PDT 24
Peak memory	226584 kb
Host	smart-832cb4e6-c9b7-441f-aedd-3732f7c0b984
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=961119971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.961119971
Directory	/workspace/22.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all.1023942218
Short name	T374
Test name
Test status
Simulation time	90308138391 ps
CPU time	83.01 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:38:00 PM PDT 24
Peak memory	259428 kb
Host	smart-e949c33a-567d-451b-987d-40451e551fd8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023942218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.1023942218
Directory	/workspace/22.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.919221785
Short name	T219
Test name
Test status
Simulation time	12823143 ps
CPU time	1.05 seconds
Started	Jul 29 05:36:30 PM PDT 24
Finished	Jul 29 05:36:31 PM PDT 24
Peak memory	212000 kb
Host	smart-06c948a4-bb01-47a3-be95-f9129bfdfe4f
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919221785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct rl_volatile_unlock_smoke.919221785
Directory	/workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_alert_test.2894319297
Short name	T736
Test name
Test status
Simulation time	35590980 ps
CPU time	1.12 seconds
Started	Jul 29 05:36:39 PM PDT 24
Finished	Jul 29 05:36:40 PM PDT 24
Peak memory	208944 kb
Host	smart-7793efd5-17e0-4785-a79b-57177c2c4950
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894319297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2894319297
Directory	/workspace/23.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.lc_ctrl_errors.2200286067
Short name	T803
Test name
Test status
Simulation time	2075733602 ps
CPU time	13.82 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:36:51 PM PDT 24
Peak memory	226152 kb
Host	smart-2d24bef7-74a6-4f3b-b5f4-ad52797093fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2200286067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2200286067
Directory	/workspace/23.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/23.lc_ctrl_jtag_access.1694052821
Short name	T303
Test name
Test status
Simulation time	1486709225 ps
CPU time	18.49 seconds
Started	Jul 29 05:36:37 PM PDT 24
Finished	Jul 29 05:36:55 PM PDT 24
Peak memory	217304 kb
Host	smart-38d04360-331b-4706-9390-8397bf692c66
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694052821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1694052821
Directory	/workspace/23.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/23.lc_ctrl_prog_failure.146014414
Short name	T40
Test name
Test status
Simulation time	35068478 ps
CPU time	2.43 seconds
Started	Jul 29 05:36:35 PM PDT 24
Finished	Jul 29 05:36:38 PM PDT 24
Peak memory	218324 kb
Host	smart-0358ce7e-951d-439e-abf8-6ba6c082c64e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146014414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.146014414
Directory	/workspace/23.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_mubi.1646144621
Short name	T271
Test name
Test status
Simulation time	732743937 ps
CPU time	11.44 seconds
Started	Jul 29 05:36:39 PM PDT 24
Finished	Jul 29 05:36:50 PM PDT 24
Peak memory	226188 kb
Host	smart-b3fde041-b52e-44cb-a48a-93809e56f6c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646144621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1646144621
Directory	/workspace/23.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_digest.358902369
Short name	T213
Test name
Test status
Simulation time	459401819 ps
CPU time	9.49 seconds
Started	Jul 29 05:36:40 PM PDT 24
Finished	Jul 29 05:36:50 PM PDT 24
Peak memory	226064 kb
Host	smart-7473830c-678b-406a-8e27-6c1cde3f4f3a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358902369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di gest.358902369
Directory	/workspace/23.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_mux.3707068117
Short name	T519
Test name
Test status
Simulation time	408846983 ps
CPU time	9.23 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:36:45 PM PDT 24
Peak memory	218320 kb
Host	smart-106e501e-c998-48b4-8c71-ce82ab5485bb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707068117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux. 3707068117
Directory	/workspace/23.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/23.lc_ctrl_security_escalation.2201714362
Short name	T455
Test name
Test status
Simulation time	2240155832 ps
CPU time	10.4 seconds
Started	Jul 29 05:36:34 PM PDT 24
Finished	Jul 29 05:36:44 PM PDT 24
Peak memory	225832 kb
Host	smart-a1bcd4f4-a268-4224-9150-14ecf8534477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201714362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2201714362
Directory	/workspace/23.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/23.lc_ctrl_smoke.3034290840
Short name	T811
Test name
Test status
Simulation time	165454857 ps
CPU time	5 seconds
Started	Jul 29 05:36:37 PM PDT 24
Finished	Jul 29 05:36:43 PM PDT 24
Peak memory	217716 kb
Host	smart-d6f4bd43-48f5-45c9-b7f8-a9a76612daa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034290840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3034290840
Directory	/workspace/23.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_failure.1804826381
Short name	T240
Test name
Test status
Simulation time	762090063 ps
CPU time	16.94 seconds
Started	Jul 29 05:36:34 PM PDT 24
Finished	Jul 29 05:36:51 PM PDT 24
Peak memory	250952 kb
Host	smart-7badaeee-2184-4cd0-9e18-c7ec37b44be1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804826381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1804826381
Directory	/workspace/23.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_post_trans.1129362365
Short name	T845
Test name
Test status
Simulation time	109498393 ps
CPU time	4.38 seconds
Started	Jul 29 05:36:34 PM PDT 24
Finished	Jul 29 05:36:38 PM PDT 24
Peak memory	226444 kb
Host	smart-b26b6e62-8594-45d6-888f-76ee9cbf512e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129362365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1129362365
Directory	/workspace/23.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all.218476695
Short name	T242
Test name
Test status
Simulation time	7913128666 ps
CPU time	68.4 seconds
Started	Jul 29 05:36:41 PM PDT 24
Finished	Jul 29 05:37:49 PM PDT 24
Peak memory	251076 kb
Host	smart-8789645d-8389-433d-bc9f-2998553c3e99
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218476695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.218476695
Directory	/workspace/23.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1618424447
Short name	T216
Test name
Test status
Simulation time	13966085 ps
CPU time	0.9 seconds
Started	Jul 29 05:36:36 PM PDT 24
Finished	Jul 29 05:36:37 PM PDT 24
Peak memory	212016 kb
Host	smart-41afbfea-ca32-4a48-bcf0-104bbb7c61db
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618424447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.1618424447
Directory	/workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_alert_test.2413576195
Short name	T224
Test name
Test status
Simulation time	29674234 ps
CPU time	1.13 seconds
Started	Jul 29 05:36:42 PM PDT 24
Finished	Jul 29 05:36:43 PM PDT 24
Peak memory	209068 kb
Host	smart-55c979e2-3337-4f53-8939-7fc50592790a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413576195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2413576195
Directory	/workspace/24.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.lc_ctrl_jtag_access.2915315126
Short name	T642
Test name
Test status
Simulation time	218551538 ps
CPU time	2.07 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:36:49 PM PDT 24
Peak memory	217100 kb
Host	smart-28fa517d-3494-4cb4-95f2-1baf5f503255
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915315126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2915315126
Directory	/workspace/24.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_prog_failure.1667032374
Short name	T721
Test name
Test status
Simulation time	19464741 ps
CPU time	1.53 seconds
Started	Jul 29 05:36:41 PM PDT 24
Finished	Jul 29 05:36:43 PM PDT 24
Peak memory	218372 kb
Host	smart-d8c9c205-d5b7-4c7d-8087-2039d8598183
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667032374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1667032374
Directory	/workspace/24.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_mubi.125161481
Short name	T620
Test name
Test status
Simulation time	418890347 ps
CPU time	17.16 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	218932 kb
Host	smart-8c4a10e2-8e84-43b6-bf3c-41814e2be313
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125161481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.125161481
Directory	/workspace/24.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_digest.1858281580
Short name	T697
Test name
Test status
Simulation time	309661697 ps
CPU time	13.97 seconds
Started	Jul 29 05:36:38 PM PDT 24
Finished	Jul 29 05:36:52 PM PDT 24
Peak memory	218244 kb
Host	smart-a5838cf9-deb5-4c75-a665-20b13735a5a3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858281580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d igest.1858281580
Directory	/workspace/24.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_mux.3374782392
Short name	T492
Test name
Test status
Simulation time	2077928821 ps
CPU time	9.83 seconds
Started	Jul 29 05:36:40 PM PDT 24
Finished	Jul 29 05:36:50 PM PDT 24
Peak memory	218308 kb
Host	smart-939479ba-aa81-43e0-b1cd-876df0086a9c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374782392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux. 3374782392
Directory	/workspace/24.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/24.lc_ctrl_security_escalation.3210994192
Short name	T529
Test name
Test status
Simulation time	476514314 ps
CPU time	10.79 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:36:57 PM PDT 24
Peak memory	226112 kb
Host	smart-db132531-d3bd-4c49-b394-2ba38bbea396
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210994192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3210994192
Directory	/workspace/24.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/24.lc_ctrl_smoke.685381825
Short name	T444
Test name
Test status
Simulation time	50296598 ps
CPU time	2.97 seconds
Started	Jul 29 05:36:39 PM PDT 24
Finished	Jul 29 05:36:42 PM PDT 24
Peak memory	217712 kb
Host	smart-6ce5867f-3725-4b42-927b-eefe2c8f2d77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685381825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.685381825
Directory	/workspace/24.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_failure.2513280705
Short name	T231
Test name
Test status
Simulation time	398175155 ps
CPU time	28.14 seconds
Started	Jul 29 05:36:41 PM PDT 24
Finished	Jul 29 05:37:09 PM PDT 24
Peak memory	250984 kb
Host	smart-74978f95-4702-4db9-869c-2b92caf2327b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513280705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2513280705
Directory	/workspace/24.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_post_trans.4179200086
Short name	T322
Test name
Test status
Simulation time	186313050 ps
CPU time	6.51 seconds
Started	Jul 29 05:36:40 PM PDT 24
Finished	Jul 29 05:36:47 PM PDT 24
Peak memory	250532 kb
Host	smart-aafe3f47-803c-43d8-ba75-f9614d0fac02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179200086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4179200086
Directory	/workspace/24.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all.1829580664
Short name	T313
Test name
Test status
Simulation time	7759312306 ps
CPU time	141.11 seconds
Started	Jul 29 05:36:40 PM PDT 24
Finished	Jul 29 05:39:01 PM PDT 24
Peak memory	221084 kb
Host	smart-558f6d62-a33b-4c4d-9f92-4db3b23f1e73
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829580664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all.1829580664
Directory	/workspace/24.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1135839054
Short name	T783
Test name
Test status
Simulation time	17540949247 ps
CPU time	272.23 seconds
Started	Jul 29 05:36:41 PM PDT 24
Finished	Jul 29 05:41:14 PM PDT 24
Peak memory	317012 kb
Host	smart-846b424e-4b01-4a78-8042-f6d0c6ed90e7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1135839054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1135839054
Directory	/workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1304530143
Short name	T376
Test name
Test status
Simulation time	30074148 ps
CPU time	1.52 seconds
Started	Jul 29 05:36:41 PM PDT 24
Finished	Jul 29 05:36:43 PM PDT 24
Peak memory	217876 kb
Host	smart-38832250-3265-451b-ac51-c91eb8663325
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304530143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c trl_volatile_unlock_smoke.1304530143
Directory	/workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_alert_test.3260277434
Short name	T817
Test name
Test status
Simulation time	42403240 ps
CPU time	0.99 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:36:46 PM PDT 24
Peak memory	209008 kb
Host	smart-dc617148-d3cc-4ed2-bcf9-dd339829a4f9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260277434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3260277434
Directory	/workspace/25.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.lc_ctrl_errors.165804694
Short name	T298
Test name
Test status
Simulation time	3891488928 ps
CPU time	14.06 seconds
Started	Jul 29 05:36:42 PM PDT 24
Finished	Jul 29 05:36:56 PM PDT 24
Peak memory	226248 kb
Host	smart-1bd92960-3ad7-49cb-a538-e28e0f9c9721
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165804694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.165804694
Directory	/workspace/25.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/25.lc_ctrl_jtag_access.1451176589
Short name	T452
Test name
Test status
Simulation time	504693041 ps
CPU time	7.75 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:36:53 PM PDT 24
Peak memory	217228 kb
Host	smart-96259c1f-bdc2-41b1-86fe-d75d3fbd7480
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451176589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1451176589
Directory	/workspace/25.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/25.lc_ctrl_prog_failure.6438843
Short name	T702
Test name
Test status
Simulation time	17749370 ps
CPU time	1.54 seconds
Started	Jul 29 05:36:43 PM PDT 24
Finished	Jul 29 05:36:44 PM PDT 24
Peak memory	218336 kb
Host	smart-409f905c-68a9-4e16-9825-4194dbeef4b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6438843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.6438843
Directory	/workspace/25.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_mubi.1131878001
Short name	T579
Test name
Test status
Simulation time	1140423965 ps
CPU time	10.95 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:36:56 PM PDT 24
Peak memory	226132 kb
Host	smart-3f6164b8-0904-4563-9bd5-4dcc7610dd15
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131878001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1131878001
Directory	/workspace/25.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_digest.2432603832
Short name	T599
Test name
Test status
Simulation time	324886042 ps
CPU time	8.18 seconds
Started	Jul 29 05:36:47 PM PDT 24
Finished	Jul 29 05:36:55 PM PDT 24
Peak memory	218216 kb
Host	smart-f2034375-8d34-427a-9251-c0f577d9da32
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432603832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d igest.2432603832
Directory	/workspace/25.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_mux.3091521351
Short name	T433
Test name
Test status
Simulation time	289657599 ps
CPU time	8.25 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:36:53 PM PDT 24
Peak memory	226084 kb
Host	smart-1d959b1d-e819-4e43-b8ea-dc1c9fa38e0f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091521351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux. 3091521351
Directory	/workspace/25.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/25.lc_ctrl_smoke.3383113321
Short name	T14
Test name
Test status
Simulation time	93973137 ps
CPU time	3.65 seconds
Started	Jul 29 05:36:42 PM PDT 24
Finished	Jul 29 05:36:46 PM PDT 24
Peak memory	215124 kb
Host	smart-c6b890cd-e4fd-4490-b36c-b17e6994da69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383113321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3383113321
Directory	/workspace/25.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_failure.1990662225
Short name	T363
Test name
Test status
Simulation time	238019478 ps
CPU time	21.92 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:37:08 PM PDT 24
Peak memory	250908 kb
Host	smart-14d4df80-76eb-4b43-8cd5-9dd7407b4dac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990662225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1990662225
Directory	/workspace/25.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_post_trans.4068846840
Short name	T474
Test name
Test status
Simulation time	292714213 ps
CPU time	6.4 seconds
Started	Jul 29 05:36:40 PM PDT 24
Finished	Jul 29 05:36:47 PM PDT 24
Peak memory	246932 kb
Host	smart-f01f334d-444f-466a-a726-5f3ae902bb82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068846840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.4068846840
Directory	/workspace/25.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all.545950362
Short name	T764
Test name
Test status
Simulation time	2800323534 ps
CPU time	76.62 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:38:03 PM PDT 24
Peak memory	278740 kb
Host	smart-c0fafef3-0648-46b8-b7a9-b03501781fad
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545950362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.545950362
Directory	/workspace/25.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.1271916860
Short name	T539
Test name
Test status
Simulation time	77884088221 ps
CPU time	330.54 seconds
Started	Jul 29 05:36:44 PM PDT 24
Finished	Jul 29 05:42:15 PM PDT 24
Peak memory	309476 kb
Host	smart-2f2b846d-64ab-4c81-a78e-d7981b162a64
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1271916860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.1271916860
Directory	/workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1446140999
Short name	T789
Test name
Test status
Simulation time	20497083 ps
CPU time	0.89 seconds
Started	Jul 29 05:36:43 PM PDT 24
Finished	Jul 29 05:36:44 PM PDT 24
Peak memory	212044 kb
Host	smart-2d12d4d9-436b-4361-bf3e-20a1cd76969e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446140999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.1446140999
Directory	/workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_alert_test.3951570438
Short name	T546
Test name
Test status
Simulation time	22300198 ps
CPU time	0.95 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:36:48 PM PDT 24
Peak memory	208892 kb
Host	smart-56d756ae-e369-4c0f-82cd-7512acc84174
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951570438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3951570438
Directory	/workspace/26.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.lc_ctrl_errors.1884787360
Short name	T232
Test name
Test status
Simulation time	188635810 ps
CPU time	9.62 seconds
Started	Jul 29 05:36:44 PM PDT 24
Finished	Jul 29 05:36:54 PM PDT 24
Peak memory	218356 kb
Host	smart-7d91514a-80e3-419d-bbc1-013ee5eed0a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884787360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1884787360
Directory	/workspace/26.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_jtag_access.1894650903
Short name	T37
Test name
Test status
Simulation time	337262757 ps
CPU time	9.47 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:36:55 PM PDT 24
Peak memory	217488 kb
Host	smart-5257e6cb-2f39-4580-af4e-264e31bf50ea
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894650903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1894650903
Directory	/workspace/26.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/26.lc_ctrl_prog_failure.150342977
Short name	T595
Test name
Test status
Simulation time	69197181 ps
CPU time	1.61 seconds
Started	Jul 29 05:36:44 PM PDT 24
Finished	Jul 29 05:36:46 PM PDT 24
Peak memory	218360 kb
Host	smart-81642ec2-6ed5-4938-bd4b-91c8c3f279ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150342977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.150342977
Directory	/workspace/26.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_digest.2070585951
Short name	T395
Test name
Test status
Simulation time	2355174374 ps
CPU time	19.19 seconds
Started	Jul 29 05:36:47 PM PDT 24
Finished	Jul 29 05:37:06 PM PDT 24
Peak memory	219036 kb
Host	smart-eeed7c8e-bf8c-409e-9ca6-004c06fd70ef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070585951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d igest.2070585951
Directory	/workspace/26.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_mux.541955909
Short name	T228
Test name
Test status
Simulation time	744726357 ps
CPU time	12.01 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:36:58 PM PDT 24
Peak memory	226100 kb
Host	smart-21e3bef9-d77b-49a2-a585-160c116d537f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541955909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.541955909
Directory	/workspace/26.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/26.lc_ctrl_security_escalation.1531150587
Short name	T57
Test name
Test status
Simulation time	276789507 ps
CPU time	7.95 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:36:54 PM PDT 24
Peak memory	225156 kb
Host	smart-f57f4535-8a49-4940-92e6-4dfa47810252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531150587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1531150587
Directory	/workspace/26.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/26.lc_ctrl_smoke.525564499
Short name	T65
Test name
Test status
Simulation time	43927320 ps
CPU time	3.13 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:36:48 PM PDT 24
Peak memory	214676 kb
Host	smart-3d39c27e-3230-4d99-8618-0a570a9b0531
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525564499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.525564499
Directory	/workspace/26.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_failure.2473054044
Short name	T571
Test name
Test status
Simulation time	194121837 ps
CPU time	15.86 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:37:01 PM PDT 24
Peak memory	250968 kb
Host	smart-beceb49e-8582-49b6-9ef7-6ce91757b9fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473054044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2473054044
Directory	/workspace/26.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_post_trans.2986922241
Short name	T353
Test name
Test status
Simulation time	105622738 ps
CPU time	7.54 seconds
Started	Jul 29 05:36:45 PM PDT 24
Finished	Jul 29 05:36:53 PM PDT 24
Peak memory	250464 kb
Host	smart-5f6ae583-4308-47b6-91a5-f243858368fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986922241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2986922241
Directory	/workspace/26.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all.2875294613
Short name	T744
Test name
Test status
Simulation time	5489609866 ps
CPU time	43.44 seconds
Started	Jul 29 05:36:48 PM PDT 24
Finished	Jul 29 05:37:32 PM PDT 24
Peak memory	250788 kb
Host	smart-4e6a2860-3444-449d-a5d9-497e2bc85017
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875294613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.2875294613
Directory	/workspace/26.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.603337777
Short name	T858
Test name
Test status
Simulation time	18771353 ps
CPU time	0.85 seconds
Started	Jul 29 05:36:47 PM PDT 24
Finished	Jul 29 05:36:48 PM PDT 24
Peak memory	212028 kb
Host	smart-fd97edb9-fb21-433c-94c4-056ee84272e4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603337777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct rl_volatile_unlock_smoke.603337777
Directory	/workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_alert_test.1308821356
Short name	T504
Test name
Test status
Simulation time	35221174 ps
CPU time	1.19 seconds
Started	Jul 29 05:36:49 PM PDT 24
Finished	Jul 29 05:36:51 PM PDT 24
Peak memory	209140 kb
Host	smart-ae34ffc3-1ca7-4c8d-803b-7514f459b43f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308821356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1308821356
Directory	/workspace/27.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.lc_ctrl_errors.4023235760
Short name	T584
Test name
Test status
Simulation time	642208812 ps
CPU time	15.48 seconds
Started	Jul 29 05:36:49 PM PDT 24
Finished	Jul 29 05:37:05 PM PDT 24
Peak memory	226180 kb
Host	smart-8d0eab76-4580-43ff-b6a1-60b52b37c3ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023235760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.4023235760
Directory	/workspace/27.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/27.lc_ctrl_jtag_access.940373285
Short name	T392
Test name
Test status
Simulation time	712941596 ps
CPU time	7.41 seconds
Started	Jul 29 05:36:49 PM PDT 24
Finished	Jul 29 05:36:57 PM PDT 24
Peak memory	217824 kb
Host	smart-c69be413-5999-4f0c-9fb1-d913992512e5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940373285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.940373285
Directory	/workspace/27.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/27.lc_ctrl_prog_failure.1157767932
Short name	T375
Test name
Test status
Simulation time	124025291 ps
CPU time	2.07 seconds
Started	Jul 29 05:36:50 PM PDT 24
Finished	Jul 29 05:36:52 PM PDT 24
Peak memory	222120 kb
Host	smart-797eb391-9427-40e3-afcc-4efca90386d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1157767932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1157767932
Directory	/workspace/27.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_mubi.922738105
Short name	T758
Test name
Test status
Simulation time	898884407 ps
CPU time	15.38 seconds
Started	Jul 29 05:36:50 PM PDT 24
Finished	Jul 29 05:37:05 PM PDT 24
Peak memory	218436 kb
Host	smart-6b54de33-268b-4942-9652-f172632e5f09
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922738105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.922738105
Directory	/workspace/27.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_digest.1145046148
Short name	T564
Test name
Test status
Simulation time	5551161619 ps
CPU time	23.38 seconds
Started	Jul 29 05:36:50 PM PDT 24
Finished	Jul 29 05:37:13 PM PDT 24
Peak memory	218380 kb
Host	smart-c9e163bf-af18-429c-8cf6-504352bf3d12
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145046148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d igest.1145046148
Directory	/workspace/27.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_mux.312699328
Short name	T324
Test name
Test status
Simulation time	536107620 ps
CPU time	7.16 seconds
Started	Jul 29 05:36:50 PM PDT 24
Finished	Jul 29 05:36:57 PM PDT 24
Peak memory	218328 kb
Host	smart-3e9f7cd9-d4dc-461a-9a73-f5f893e23c44
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312699328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.312699328
Directory	/workspace/27.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_security_escalation.327943472
Short name	T735
Test name
Test status
Simulation time	843351023 ps
CPU time	9.08 seconds
Started	Jul 29 05:36:49 PM PDT 24
Finished	Jul 29 05:36:58 PM PDT 24
Peak memory	226184 kb
Host	smart-dbd7e95e-d87d-4029-a789-a8ccbb20dc7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327943472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.327943472
Directory	/workspace/27.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/27.lc_ctrl_smoke.4068875463
Short name	T78
Test name
Test status
Simulation time	156844212 ps
CPU time	2.58 seconds
Started	Jul 29 05:36:48 PM PDT 24
Finished	Jul 29 05:36:51 PM PDT 24
Peak memory	214440 kb
Host	smart-911e38a5-633d-42e5-a5b4-0dee521ca1be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068875463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4068875463
Directory	/workspace/27.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_failure.3205197742
Short name	T609
Test name
Test status
Simulation time	419325264 ps
CPU time	13.11 seconds
Started	Jul 29 05:36:46 PM PDT 24
Finished	Jul 29 05:36:59 PM PDT 24
Peak memory	250872 kb
Host	smart-1946d851-1141-48dd-ab03-25ab4b7b887e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205197742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3205197742
Directory	/workspace/27.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_post_trans.2048661228
Short name	T563
Test name
Test status
Simulation time	54155557 ps
CPU time	7.31 seconds
Started	Jul 29 05:36:48 PM PDT 24
Finished	Jul 29 05:36:56 PM PDT 24
Peak memory	250852 kb
Host	smart-d2c34917-eb1c-4ad4-8d46-20b5f602a73c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048661228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2048661228
Directory	/workspace/27.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all.2556918205
Short name	T777
Test name
Test status
Simulation time	10647839175 ps
CPU time	139.32 seconds
Started	Jul 29 05:36:52 PM PDT 24
Finished	Jul 29 05:39:11 PM PDT 24
Peak memory	281904 kb
Host	smart-678c0b7d-5857-471c-beda-8873b5380f2b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556918205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.2556918205
Directory	/workspace/27.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2475515465
Short name	T151
Test name
Test status
Simulation time	302079809639 ps
CPU time	1231.94 seconds
Started	Jul 29 05:36:51 PM PDT 24
Finished	Jul 29 05:57:23 PM PDT 24
Peak memory	513324 kb
Host	smart-bb371695-bdc6-4561-b9de-e611fcbb6b2f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2475515465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2475515465
Directory	/workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3896037153
Short name	T367
Test name
Test status
Simulation time	30682922 ps
CPU time	0.81 seconds
Started	Jul 29 05:36:48 PM PDT 24
Finished	Jul 29 05:36:49 PM PDT 24
Peak memory	208108 kb
Host	smart-94bcfd60-9267-42ea-a060-fa953ad53998
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896037153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c trl_volatile_unlock_smoke.3896037153
Directory	/workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_alert_test.2453295322
Short name	T690
Test name
Test status
Simulation time	77902590 ps
CPU time	1.01 seconds
Started	Jul 29 05:36:57 PM PDT 24
Finished	Jul 29 05:36:58 PM PDT 24
Peak memory	209008 kb
Host	smart-8732f87c-4f8c-496e-90b4-65fc9769f80e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453295322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2453295322
Directory	/workspace/28.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.lc_ctrl_errors.3523756398
Short name	T463
Test name
Test status
Simulation time	297657688 ps
CPU time	13.59 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:37:09 PM PDT 24
Peak memory	218388 kb
Host	smart-56829348-a95f-4777-b09a-067335be11f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523756398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3523756398
Directory	/workspace/28.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_jtag_access.3467639383
Short name	T477
Test name
Test status
Simulation time	842382733 ps
CPU time	5.33 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:37:01 PM PDT 24
Peak memory	217768 kb
Host	smart-aca8e2da-72b1-4a26-9549-48067ed2c401
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467639383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3467639383
Directory	/workspace/28.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/28.lc_ctrl_prog_failure.1959025447
Short name	T653
Test name
Test status
Simulation time	432420928 ps
CPU time	3.3 seconds
Started	Jul 29 05:36:57 PM PDT 24
Finished	Jul 29 05:37:00 PM PDT 24
Peak memory	218364 kb
Host	smart-d8ede1df-8ae7-473c-b775-ad0464732da6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959025447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1959025447
Directory	/workspace/28.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_mubi.1196862580
Short name	T676
Test name
Test status
Simulation time	790646975 ps
CPU time	11.78 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:37:07 PM PDT 24
Peak memory	226156 kb
Host	smart-79d920a2-993e-4698-a7a5-8ebc824b8c8e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196862580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1196862580
Directory	/workspace/28.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_digest.1798027426
Short name	T672
Test name
Test status
Simulation time	389586674 ps
CPU time	8.82 seconds
Started	Jul 29 05:36:54 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	218312 kb
Host	smart-e1735178-ddc9-4fb6-bdb9-3c9106b084a3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798027426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.1798027426
Directory	/workspace/28.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_mux.3232015743
Short name	T245
Test name
Test status
Simulation time	780242806 ps
CPU time	7.59 seconds
Started	Jul 29 05:36:54 PM PDT 24
Finished	Jul 29 05:37:02 PM PDT 24
Peak memory	218332 kb
Host	smart-362ac644-7f16-4f73-840f-c1227df037ae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232015743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux. 3232015743
Directory	/workspace/28.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/28.lc_ctrl_security_escalation.346537607
Short name	T706
Test name
Test status
Simulation time	195791848 ps
CPU time	7.66 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	226180 kb
Host	smart-efde233f-73fa-4da9-b316-ddace3f2cc11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346537607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.346537607
Directory	/workspace/28.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/28.lc_ctrl_smoke.72750023
Short name	T64
Test name
Test status
Simulation time	125376488 ps
CPU time	3.94 seconds
Started	Jul 29 05:36:57 PM PDT 24
Finished	Jul 29 05:37:01 PM PDT 24
Peak memory	217692 kb
Host	smart-404cda3a-e0e6-4d38-949c-0f296f19a8dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72750023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.72750023
Directory	/workspace/28.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_failure.3450563784
Short name	T759
Test name
Test status
Simulation time	274987643 ps
CPU time	28.1 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	247620 kb
Host	smart-75a2f61e-9e11-426d-9446-0f8813ef88cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450563784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3450563784
Directory	/workspace/28.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_post_trans.977614490
Short name	T612
Test name
Test status
Simulation time	229405226 ps
CPU time	3.46 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:36:58 PM PDT 24
Peak memory	222304 kb
Host	smart-a053a64b-235a-40cf-a222-ae6d88db1e37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977614490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.977614490
Directory	/workspace/28.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all.793931882
Short name	T360
Test name
Test status
Simulation time	5487239598 ps
CPU time	51.08 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:37:46 PM PDT 24
Peak memory	247916 kb
Host	smart-2da74a10-8f51-454a-aaf1-a9b0e9bcc929
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793931882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.793931882
Directory	/workspace/28.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3671910150
Short name	T597
Test name
Test status
Simulation time	24402909 ps
CPU time	0.95 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:36:57 PM PDT 24
Peak memory	212068 kb
Host	smart-4eb6995c-805b-49f2-813f-33207135cbb2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671910150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c trl_volatile_unlock_smoke.3671910150
Directory	/workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_alert_test.1132491136
Short name	T425
Test name
Test status
Simulation time	98017009 ps
CPU time	1.07 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:36:56 PM PDT 24
Peak memory	208956 kb
Host	smart-977cd374-cfad-4009-b420-8eeaff118741
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132491136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1132491136
Directory	/workspace/29.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.lc_ctrl_errors.854998874
Short name	T641
Test name
Test status
Simulation time	1061186177 ps
CPU time	9.28 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:37:06 PM PDT 24
Peak memory	218300 kb
Host	smart-1eb39f12-3e16-4201-9aff-dfcde63020dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854998874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.854998874
Directory	/workspace/29.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/29.lc_ctrl_jtag_access.3752406691
Short name	T566
Test name
Test status
Simulation time	127564761 ps
CPU time	2.17 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:36:57 PM PDT 24
Peak memory	217188 kb
Host	smart-1f90cf2a-7242-4820-ba80-0885d3736bb7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752406691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3752406691
Directory	/workspace/29.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/29.lc_ctrl_prog_failure.3828005781
Short name	T565
Test name
Test status
Simulation time	59264169 ps
CPU time	2.27 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:36:57 PM PDT 24
Peak memory	218364 kb
Host	smart-23b2fa9e-c84f-4ea8-9fec-3df5645b00a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828005781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3828005781
Directory	/workspace/29.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_mubi.751516913
Short name	T48
Test name
Test status
Simulation time	4558556677 ps
CPU time	8.07 seconds
Started	Jul 29 05:36:58 PM PDT 24
Finished	Jul 29 05:37:06 PM PDT 24
Peak memory	220136 kb
Host	smart-3f045bfb-0aca-46dc-ad87-d082e68c8e55
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751516913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.751516913
Directory	/workspace/29.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_digest.3963379687
Short name	T340
Test name
Test status
Simulation time	600946168 ps
CPU time	12.69 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:37:09 PM PDT 24
Peak memory	226132 kb
Host	smart-ec0234c9-c7b3-41d9-9b41-1967e884a2de
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963379687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d igest.3963379687
Directory	/workspace/29.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_mux.3452334691
Short name	T396
Test name
Test status
Simulation time	228725057 ps
CPU time	8.59 seconds
Started	Jul 29 05:36:54 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	218320 kb
Host	smart-7217bb64-9de0-4746-8705-e7d52038d7da
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452334691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 3452334691
Directory	/workspace/29.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/29.lc_ctrl_security_escalation.612504099
Short name	T207
Test name
Test status
Simulation time	386542095 ps
CPU time	13.74 seconds
Started	Jul 29 05:36:54 PM PDT 24
Finished	Jul 29 05:37:08 PM PDT 24
Peak memory	226168 kb
Host	smart-86f0efd1-8382-4c53-972a-4bf1d89b17de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612504099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.612504099
Directory	/workspace/29.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/29.lc_ctrl_smoke.3090382790
Short name	T293
Test name
Test status
Simulation time	52131651 ps
CPU time	2.48 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:36:58 PM PDT 24
Peak memory	217812 kb
Host	smart-4e290207-49ec-4613-9e08-12e0a8638490
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090382790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3090382790
Directory	/workspace/29.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_failure.2245270270
Short name	T868
Test name
Test status
Simulation time	1187840132 ps
CPU time	18.48 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:37:13 PM PDT 24
Peak memory	251024 kb
Host	smart-2f70d1ec-3cfb-45ba-8ccb-7ed0492df5c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2245270270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2245270270
Directory	/workspace/29.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_post_trans.3670363472
Short name	T282
Test name
Test status
Simulation time	77208000 ps
CPU time	7.49 seconds
Started	Jul 29 05:36:56 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	248568 kb
Host	smart-997626ed-9edd-4e1d-b5c9-0b69ead9e7c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670363472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3670363472
Directory	/workspace/29.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all.3586354990
Short name	T795
Test name
Test status
Simulation time	4945570867 ps
CPU time	43.41 seconds
Started	Jul 29 05:36:54 PM PDT 24
Finished	Jul 29 05:37:38 PM PDT 24
Peak memory	247620 kb
Host	smart-9da16319-1dfd-4a49-8ed2-03a2647e9d52
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586354990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.3586354990
Directory	/workspace/29.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2160579432
Short name	T177
Test name
Test status
Simulation time	72769364 ps
CPU time	1.26 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:36:57 PM PDT 24
Peak memory	218232 kb
Host	smart-fa35bbee-b0f5-400c-8c8a-6138c3a75ab3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160579432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c trl_volatile_unlock_smoke.2160579432
Directory	/workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_alert_test.220565756
Short name	T527
Test name
Test status
Simulation time	33221871 ps
CPU time	1.03 seconds
Started	Jul 29 05:35:27 PM PDT 24
Finished	Jul 29 05:35:28 PM PDT 24
Peak memory	209064 kb
Host	smart-31d5814f-8e78-4c2d-b73d-34c5ad713d30
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220565756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.220565756
Directory	/workspace/3.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.lc_ctrl_claim_transition_if.1491925534
Short name	T448
Test name
Test status
Simulation time	11934865 ps
CPU time	0.94 seconds
Started	Jul 29 05:35:18 PM PDT 24
Finished	Jul 29 05:35:19 PM PDT 24
Peak memory	208860 kb
Host	smart-c1c00fe2-9c0d-463a-a2b5-179f26c8e009
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491925534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1491925534
Directory	/workspace/3.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/3.lc_ctrl_errors.1901903663
Short name	T507
Test name
Test status
Simulation time	627012640 ps
CPU time	26.76 seconds
Started	Jul 29 05:35:18 PM PDT 24
Finished	Jul 29 05:35:45 PM PDT 24
Peak memory	226072 kb
Host	smart-306f4fa1-b7f9-4aa1-8f87-1a6b3b38aadc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901903663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1901903663
Directory	/workspace/3.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_access.1640852550
Short name	T380
Test name
Test status
Simulation time	137795104 ps
CPU time	1.72 seconds
Started	Jul 29 05:35:18 PM PDT 24
Finished	Jul 29 05:35:20 PM PDT 24
Peak memory	217080 kb
Host	smart-a851f7ac-80a8-4ae0-a8c3-15a51661f315
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640852550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1640852550
Directory	/workspace/3.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_errors.464366754
Short name	T440
Test name
Test status
Simulation time	8739415108 ps
CPU time	58.04 seconds
Started	Jul 29 05:35:19 PM PDT 24
Finished	Jul 29 05:36:17 PM PDT 24
Peak memory	219032 kb
Host	smart-84b7b6b5-d1e7-4617-b69f-0d15acb24fb9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464366754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err ors.464366754
Directory	/workspace/3.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_priority.4125765290
Short name	T428
Test name
Test status
Simulation time	386007712 ps
CPU time	2.72 seconds
Started	Jul 29 05:35:21 PM PDT 24
Finished	Jul 29 05:35:24 PM PDT 24
Peak memory	217436 kb
Host	smart-2f0681dd-16f7-4de8-ba51-69152712fd20
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125765290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4 125765290
Directory	/workspace/3.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4147364831
Short name	T689
Test name
Test status
Simulation time	499528912 ps
CPU time	14.39 seconds
Started	Jul 29 05:35:18 PM PDT 24
Finished	Jul 29 05:35:33 PM PDT 24
Peak memory	218372 kb
Host	smart-db070f63-7198-4eb5-accf-13242caa723a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147364831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _prog_failure.4147364831
Directory	/workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.987532842
Short name	T660
Test name
Test status
Simulation time	11126441311 ps
CPU time	21.29 seconds
Started	Jul 29 05:35:18 PM PDT 24
Finished	Jul 29 05:35:40 PM PDT 24
Peak memory	217800 kb
Host	smart-cf3dd25c-f500-4102-b7f7-121d458910b5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987532842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j tag_regwen_during_op.987532842
Directory	/workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_smoke.343246439
Short name	T534
Test name
Test status
Simulation time	448307899 ps
CPU time	12.07 seconds
Started	Jul 29 05:35:19 PM PDT 24
Finished	Jul 29 05:35:31 PM PDT 24
Peak memory	217728 kb
Host	smart-d060317c-59a3-4a2e-a682-ed5f3139dc8d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343246439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.343246439
Directory	/workspace/3.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3847965157
Short name	T306
Test name
Test status
Simulation time	2200190967 ps
CPU time	59.5 seconds
Started	Jul 29 05:35:28 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	283432 kb
Host	smart-939b33d5-c2b7-47ec-9f69-2eeac47a77b8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847965157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.3847965157
Directory	/workspace/3.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1975489976
Short name	T173
Test name
Test status
Simulation time	4734855029 ps
CPU time	17.5 seconds
Started	Jul 29 05:35:20 PM PDT 24
Finished	Jul 29 05:35:37 PM PDT 24
Peak memory	251000 kb
Host	smart-db3a6eaf-f222-44a4-ae43-08405f85712a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975489976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_state_post_trans.1975489976
Directory	/workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_prog_failure.3002355746
Short name	T769
Test name
Test status
Simulation time	56689586 ps
CPU time	2.4 seconds
Started	Jul 29 05:35:11 PM PDT 24
Finished	Jul 29 05:35:14 PM PDT 24
Peak memory	222488 kb
Host	smart-3239a0ff-0050-46c8-a5cd-5601859b19d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002355746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3002355746
Directory	/workspace/3.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_regwen_during_op.3257749142
Short name	T830
Test name
Test status
Simulation time	405422816 ps
CPU time	7.98 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:30 PM PDT 24
Peak memory	217796 kb
Host	smart-5575f22e-8c0e-4080-bfb9-4777db7d0177
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257749142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3257749142
Directory	/workspace/3.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_cm.1499477658
Short name	T88
Test name
Test status
Simulation time	498142955 ps
CPU time	36.53 seconds
Started	Jul 29 05:35:16 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	284200 kb
Host	smart-6aca91b7-a732-4f81-91f8-d68c50e48b48
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499477658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1499477658
Directory	/workspace/3.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_mubi.2339734841
Short name	T713
Test name
Test status
Simulation time	375431269 ps
CPU time	12.1 seconds
Started	Jul 29 05:35:17 PM PDT 24
Finished	Jul 29 05:35:30 PM PDT 24
Peak memory	226184 kb
Host	smart-c8670b28-03cb-43c8-8e15-9c8a7444804b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339734841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2339734841
Directory	/workspace/3.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_digest.2625692174
Short name	T553
Test name
Test status
Simulation time	352691036 ps
CPU time	10.86 seconds
Started	Jul 29 05:35:18 PM PDT 24
Finished	Jul 29 05:35:29 PM PDT 24
Peak memory	218308 kb
Host	smart-4e108ea1-bb58-4c49-9529-3c7641afe947
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625692174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di gest.2625692174
Directory	/workspace/3.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_mux.46597501
Short name	T438
Test name
Test status
Simulation time	345248811 ps
CPU time	13.36 seconds
Started	Jul 29 05:35:20 PM PDT 24
Finished	Jul 29 05:35:33 PM PDT 24
Peak memory	218316 kb
Host	smart-fa405bce-837b-4607-ba39-ffba787a0fb8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46597501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.46597501
Directory	/workspace/3.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/3.lc_ctrl_security_escalation.1888378856
Short name	T648
Test name
Test status
Simulation time	289750915 ps
CPU time	11.5 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:34 PM PDT 24
Peak memory	225760 kb
Host	smart-f94a5994-2e7f-49fe-b810-3547a3acea03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888378856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1888378856
Directory	/workspace/3.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/3.lc_ctrl_smoke.3672085354
Short name	T841
Test name
Test status
Simulation time	105988422 ps
CPU time	1.82 seconds
Started	Jul 29 05:35:14 PM PDT 24
Finished	Jul 29 05:35:16 PM PDT 24
Peak memory	217928 kb
Host	smart-09b45581-9adb-4666-a19c-322ae9f9ddcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672085354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3672085354
Directory	/workspace/3.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_failure.1888419272
Short name	T409
Test name
Test status
Simulation time	989104006 ps
CPU time	30.51 seconds
Started	Jul 29 05:35:13 PM PDT 24
Finished	Jul 29 05:35:44 PM PDT 24
Peak memory	250984 kb
Host	smart-5df5224d-e1ea-4bfb-92e7-dded4f172ae8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888419272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1888419272
Directory	/workspace/3.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_post_trans.4043852519
Short name	T854
Test name
Test status
Simulation time	100097729 ps
CPU time	4.97 seconds
Started	Jul 29 05:35:23 PM PDT 24
Finished	Jul 29 05:35:28 PM PDT 24
Peak memory	222544 kb
Host	smart-0498ed65-9055-4f95-a78b-d88fa26d3617
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043852519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4043852519
Directory	/workspace/3.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all.2228205445
Short name	T424
Test name
Test status
Simulation time	123212165273 ps
CPU time	186.08 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:38:28 PM PDT 24
Peak memory	279676 kb
Host	smart-947cb2ad-9736-4dad-890e-cc1aa995c59b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228205445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.2228205445
Directory	/workspace/3.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2538559217
Short name	T684
Test name
Test status
Simulation time	36676805 ps
CPU time	0.81 seconds
Started	Jul 29 05:35:14 PM PDT 24
Finished	Jul 29 05:35:15 PM PDT 24
Peak memory	211948 kb
Host	smart-053e1a02-da3a-4060-b70d-6680228f2353
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538559217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct rl_volatile_unlock_smoke.2538559217
Directory	/workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_alert_test.3953105630
Short name	T260
Test name
Test status
Simulation time	36287268 ps
CPU time	0.93 seconds
Started	Jul 29 05:37:01 PM PDT 24
Finished	Jul 29 05:37:02 PM PDT 24
Peak memory	208992 kb
Host	smart-e4d724f1-a205-44df-8d68-594938a21dfd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953105630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3953105630
Directory	/workspace/30.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.lc_ctrl_errors.1624012996
Short name	T378
Test name
Test status
Simulation time	361948903 ps
CPU time	17.25 seconds
Started	Jul 29 05:37:01 PM PDT 24
Finished	Jul 29 05:37:18 PM PDT 24
Peak memory	218348 kb
Host	smart-793b1de1-1e6f-4422-a26a-5347ce0c4a62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624012996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1624012996
Directory	/workspace/30.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_jtag_access.241465574
Short name	T289
Test name
Test status
Simulation time	408772180 ps
CPU time	3.19 seconds
Started	Jul 29 05:37:00 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	217152 kb
Host	smart-4b64bdb4-ff8a-48d0-a28d-af4f8b2ede85
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241465574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.241465574
Directory	/workspace/30.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/30.lc_ctrl_prog_failure.4235945313
Short name	T581
Test name
Test status
Simulation time	30372508 ps
CPU time	2.12 seconds
Started	Jul 29 05:37:03 PM PDT 24
Finished	Jul 29 05:37:05 PM PDT 24
Peak memory	222276 kb
Host	smart-d3aeccf5-7467-4470-aebf-de82b3eabcab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235945313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.4235945313
Directory	/workspace/30.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_mubi.454097820
Short name	T238
Test name
Test status
Simulation time	396331046 ps
CPU time	12.43 seconds
Started	Jul 29 05:36:59 PM PDT 24
Finished	Jul 29 05:37:11 PM PDT 24
Peak memory	218360 kb
Host	smart-1a4ee1ff-610a-40f4-93f1-fe3c1af4515d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454097820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.454097820
Directory	/workspace/30.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_digest.1278006744
Short name	T86
Test name
Test status
Simulation time	448760429 ps
CPU time	9.89 seconds
Started	Jul 29 05:37:02 PM PDT 24
Finished	Jul 29 05:37:12 PM PDT 24
Peak memory	226092 kb
Host	smart-e5b993bd-572e-4126-a56a-cae42ba76c23
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278006744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d igest.1278006744
Directory	/workspace/30.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_mux.3952061722
Short name	T837
Test name
Test status
Simulation time	335655462 ps
CPU time	12.25 seconds
Started	Jul 29 05:37:00 PM PDT 24
Finished	Jul 29 05:37:13 PM PDT 24
Peak memory	226116 kb
Host	smart-6e5447bd-7c2a-4e8b-8714-c36f9ccf6e57
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952061722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux. 3952061722
Directory	/workspace/30.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/30.lc_ctrl_security_escalation.2376399090
Short name	T56
Test name
Test status
Simulation time	249155396 ps
CPU time	10.54 seconds
Started	Jul 29 05:37:01 PM PDT 24
Finished	Jul 29 05:37:11 PM PDT 24
Peak memory	218368 kb
Host	smart-e8a23f8c-213a-4c6d-bde7-feb52ee1b30d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376399090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2376399090
Directory	/workspace/30.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/30.lc_ctrl_smoke.3417719476
Short name	T408
Test name
Test status
Simulation time	40402076 ps
CPU time	2.98 seconds
Started	Jul 29 05:36:55 PM PDT 24
Finished	Jul 29 05:36:58 PM PDT 24
Peak memory	214640 kb
Host	smart-226d466f-b8af-4308-a7d8-8512858b4de3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417719476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3417719476
Directory	/workspace/30.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_failure.2280935804
Short name	T210
Test name
Test status
Simulation time	770098947 ps
CPU time	23.99 seconds
Started	Jul 29 05:37:02 PM PDT 24
Finished	Jul 29 05:37:26 PM PDT 24
Peak memory	251032 kb
Host	smart-23d7a8d2-497d-4c24-8402-5afc53e51430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280935804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2280935804
Directory	/workspace/30.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_post_trans.3739844401
Short name	T482
Test name
Test status
Simulation time	146043670 ps
CPU time	2.88 seconds
Started	Jul 29 05:36:59 PM PDT 24
Finished	Jul 29 05:37:02 PM PDT 24
Peak memory	222220 kb
Host	smart-7471dd9e-bc89-418d-bc2b-c09899e59eaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739844401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3739844401
Directory	/workspace/30.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all.985500707
Short name	T552
Test name
Test status
Simulation time	49334979094 ps
CPU time	382.59 seconds
Started	Jul 29 05:37:02 PM PDT 24
Finished	Jul 29 05:43:25 PM PDT 24
Peak memory	253816 kb
Host	smart-a37afd54-e768-47a8-a691-871f6ef8d5b1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985500707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.985500707
Directory	/workspace/30.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3670802496
Short name	T809
Test name
Test status
Simulation time	24168954 ps
CPU time	0.93 seconds
Started	Jul 29 05:36:54 PM PDT 24
Finished	Jul 29 05:36:55 PM PDT 24
Peak memory	212076 kb
Host	smart-db37af47-4f20-4ef8-b906-f801bfd79bb1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670802496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c trl_volatile_unlock_smoke.3670802496
Directory	/workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_alert_test.2947582674
Short name	T439
Test name
Test status
Simulation time	87470345 ps
CPU time	0.95 seconds
Started	Jul 29 05:37:02 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	208908 kb
Host	smart-a635836f-2369-4ac6-a2c7-0332a574c3d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947582674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2947582674
Directory	/workspace/31.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.lc_ctrl_errors.2485155336
Short name	T580
Test name
Test status
Simulation time	615293640 ps
CPU time	14.72 seconds
Started	Jul 29 05:36:59 PM PDT 24
Finished	Jul 29 05:37:14 PM PDT 24
Peak memory	226164 kb
Host	smart-77a3ff0a-7709-4c7e-91d7-2d53d3e05cd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485155336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2485155336
Directory	/workspace/31.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/31.lc_ctrl_jtag_access.2089567368
Short name	T33
Test name
Test status
Simulation time	1464052567 ps
CPU time	10.67 seconds
Started	Jul 29 05:37:04 PM PDT 24
Finished	Jul 29 05:37:14 PM PDT 24
Peak memory	217396 kb
Host	smart-19b8574e-3006-4052-8307-0b42f8c3453b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089567368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2089567368
Directory	/workspace/31.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/31.lc_ctrl_prog_failure.825075878
Short name	T290
Test name
Test status
Simulation time	64048060 ps
CPU time	2.75 seconds
Started	Jul 29 05:37:01 PM PDT 24
Finished	Jul 29 05:37:04 PM PDT 24
Peak memory	218292 kb
Host	smart-c2ed7f4a-218f-44f6-982b-dbf594004a04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825075878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.825075878
Directory	/workspace/31.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_mubi.2145118798
Short name	T842
Test name
Test status
Simulation time	1274411399 ps
CPU time	19.51 seconds
Started	Jul 29 05:37:00 PM PDT 24
Finished	Jul 29 05:37:20 PM PDT 24
Peak memory	226188 kb
Host	smart-c3ee93f8-d608-4b87-ac10-980ee1ee8025
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145118798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2145118798
Directory	/workspace/31.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_digest.3345977292
Short name	T829
Test name
Test status
Simulation time	255113924 ps
CPU time	10.34 seconds
Started	Jul 29 05:36:59 PM PDT 24
Finished	Jul 29 05:37:10 PM PDT 24
Peak memory	226004 kb
Host	smart-9851a9da-093e-40ce-ad3e-8b76684783ed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345977292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d igest.3345977292
Directory	/workspace/31.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_mux.1379742536
Short name	T874
Test name
Test status
Simulation time	262295785 ps
CPU time	9.73 seconds
Started	Jul 29 05:36:59 PM PDT 24
Finished	Jul 29 05:37:09 PM PDT 24
Peak memory	226128 kb
Host	smart-8ba89c1f-8deb-45d2-a482-fbd2ba517fc1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379742536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux. 1379742536
Directory	/workspace/31.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/31.lc_ctrl_security_escalation.3368522552
Short name	T515
Test name
Test status
Simulation time	657081124 ps
CPU time	15.41 seconds
Started	Jul 29 05:36:59 PM PDT 24
Finished	Jul 29 05:37:15 PM PDT 24
Peak memory	226088 kb
Host	smart-28288b41-50cd-4180-b990-d35c8d44b39d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368522552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3368522552
Directory	/workspace/31.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/31.lc_ctrl_smoke.216691250
Short name	T66
Test name
Test status
Simulation time	178917703 ps
CPU time	2.68 seconds
Started	Jul 29 05:36:59 PM PDT 24
Finished	Jul 29 05:37:02 PM PDT 24
Peak memory	214708 kb
Host	smart-65e4a77f-cddc-47d1-8505-f6b5051ed9a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216691250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.216691250
Directory	/workspace/31.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_failure.1600976043
Short name	T96
Test name
Test status
Simulation time	273193764 ps
CPU time	35.12 seconds
Started	Jul 29 05:37:00 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	251008 kb
Host	smart-36f98259-4fb5-4088-99ab-db9a80b2ed55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600976043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1600976043
Directory	/workspace/31.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_post_trans.3422846950
Short name	T598
Test name
Test status
Simulation time	43963725 ps
CPU time	3.14 seconds
Started	Jul 29 05:37:00 PM PDT 24
Finished	Jul 29 05:37:03 PM PDT 24
Peak memory	226448 kb
Host	smart-82b4ae33-5233-472d-8e3e-9cd247d26e40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422846950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3422846950
Directory	/workspace/31.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all.3152650022
Short name	T662
Test name
Test status
Simulation time	8693618167 ps
CPU time	106.99 seconds
Started	Jul 29 05:37:02 PM PDT 24
Finished	Jul 29 05:38:49 PM PDT 24
Peak memory	282876 kb
Host	smart-37de9c38-94c3-4652-a062-64b7c1120d00
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152650022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.3152650022
Directory	/workspace/31.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3536882840
Short name	T338
Test name
Test status
Simulation time	15035808 ps
CPU time	0.91 seconds
Started	Jul 29 05:37:01 PM PDT 24
Finished	Jul 29 05:37:02 PM PDT 24
Peak memory	213072 kb
Host	smart-7f58a1af-eab1-4451-8c5b-7940e307a892
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536882840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.3536882840
Directory	/workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_alert_test.1289205184
Short name	T421
Test name
Test status
Simulation time	50708714 ps
CPU time	1.01 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:11 PM PDT 24
Peak memory	209008 kb
Host	smart-32cd310c-48b1-42d5-9e09-79181e67b3e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289205184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1289205184
Directory	/workspace/32.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_errors.2963841771
Short name	T335
Test name
Test status
Simulation time	4218890479 ps
CPU time	14.06 seconds
Started	Jul 29 05:37:07 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	218488 kb
Host	smart-d1675785-cf16-4a07-a705-5ed478205b31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963841771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2963841771
Directory	/workspace/32.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/32.lc_ctrl_jtag_access.1089911644
Short name	T596
Test name
Test status
Simulation time	518682796 ps
CPU time	6.81 seconds
Started	Jul 29 05:37:04 PM PDT 24
Finished	Jul 29 05:37:11 PM PDT 24
Peak memory	217492 kb
Host	smart-f722ce99-16b3-4b88-b86a-0a5d31ae2452
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089911644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1089911644
Directory	/workspace/32.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/32.lc_ctrl_prog_failure.1146998194
Short name	T336
Test name
Test status
Simulation time	477057659 ps
CPU time	3.19 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:14 PM PDT 24
Peak memory	218356 kb
Host	smart-142e4648-35c2-413c-8970-3f2c0f1dc21d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146998194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1146998194
Directory	/workspace/32.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_digest.1548008086
Short name	T172
Test name
Test status
Simulation time	238129691 ps
CPU time	9.06 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:20 PM PDT 24
Peak memory	218312 kb
Host	smart-13fbeded-3deb-4733-afcd-c568185ba283
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548008086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d igest.1548008086
Directory	/workspace/32.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_mux.3766603898
Short name	T508
Test name
Test status
Simulation time	309539401 ps
CPU time	10.89 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	226036 kb
Host	smart-3b5edf61-a4c1-489f-bdcb-51567a1ace4b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766603898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 3766603898
Directory	/workspace/32.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/32.lc_ctrl_security_escalation.3013801406
Short name	T875
Test name
Test status
Simulation time	259275228 ps
CPU time	9.69 seconds
Started	Jul 29 05:37:08 PM PDT 24
Finished	Jul 29 05:37:18 PM PDT 24
Peak memory	218440 kb
Host	smart-2ebe50a8-7bae-4890-b716-103928f564e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013801406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3013801406
Directory	/workspace/32.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/32.lc_ctrl_smoke.2150032881
Short name	T83
Test name
Test status
Simulation time	67752213 ps
CPU time	1.39 seconds
Started	Jul 29 05:37:00 PM PDT 24
Finished	Jul 29 05:37:01 PM PDT 24
Peak memory	213868 kb
Host	smart-64836240-0b95-462c-ad86-dcbcbd0c88fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2150032881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2150032881
Directory	/workspace/32.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_failure.552448545
Short name	T248
Test name
Test status
Simulation time	206696937 ps
CPU time	18.93 seconds
Started	Jul 29 05:37:07 PM PDT 24
Finished	Jul 29 05:37:26 PM PDT 24
Peak memory	250948 kb
Host	smart-cc08aef3-249f-48d9-b3af-f72b8ea6952b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552448545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.552448545
Directory	/workspace/32.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_post_trans.1054644816
Short name	T309
Test name
Test status
Simulation time	111307267 ps
CPU time	3.87 seconds
Started	Jul 29 05:37:07 PM PDT 24
Finished	Jul 29 05:37:11 PM PDT 24
Peak memory	222580 kb
Host	smart-07d4d530-5f6a-4c93-a2af-a5d00b103ff8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054644816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1054644816
Directory	/workspace/32.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all.2673948524
Short name	T658
Test name
Test status
Simulation time	41364118267 ps
CPU time	199.06 seconds
Started	Jul 29 05:37:05 PM PDT 24
Finished	Jul 29 05:40:24 PM PDT 24
Peak memory	281944 kb
Host	smart-43413dd5-f6dc-4156-855e-0bb71ea3897d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673948524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.2673948524
Directory	/workspace/32.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1339692799
Short name	T87
Test name
Test status
Simulation time	133303801420 ps
CPU time	967.62 seconds
Started	Jul 29 05:37:05 PM PDT 24
Finished	Jul 29 05:53:13 PM PDT 24
Peak memory	529724 kb
Host	smart-24ea6ae4-213f-4b6f-bdb8-38ded27f7836
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1339692799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1339692799
Directory	/workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3418980051
Short name	T252
Test name
Test status
Simulation time	66715219 ps
CPU time	0.83 seconds
Started	Jul 29 05:36:58 PM PDT 24
Finished	Jul 29 05:36:59 PM PDT 24
Peak memory	211996 kb
Host	smart-6a351810-470c-42c2-9927-5114db8816d7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418980051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c trl_volatile_unlock_smoke.3418980051
Directory	/workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_alert_test.3018932245
Short name	T74
Test name
Test status
Simulation time	39058600 ps
CPU time	1.19 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:11 PM PDT 24
Peak memory	209032 kb
Host	smart-5e167a96-3114-48fa-8625-df7c59a7e451
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018932245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3018932245
Directory	/workspace/33.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.lc_ctrl_errors.3968210915
Short name	T52
Test name
Test status
Simulation time	317658642 ps
CPU time	16.78 seconds
Started	Jul 29 05:37:07 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	226160 kb
Host	smart-3ab8dbde-fc4c-498b-a533-372a3ce4c599
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968210915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3968210915
Directory	/workspace/33.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/33.lc_ctrl_jtag_access.1269461797
Short name	T861
Test name
Test status
Simulation time	1719747754 ps
CPU time	20.24 seconds
Started	Jul 29 05:37:08 PM PDT 24
Finished	Jul 29 05:37:29 PM PDT 24
Peak memory	217500 kb
Host	smart-0e907d79-02ee-403a-b063-4dc61a2c33b7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269461797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1269461797
Directory	/workspace/33.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/33.lc_ctrl_prog_failure.271116869
Short name	T715
Test name
Test status
Simulation time	180449480 ps
CPU time	2.8 seconds
Started	Jul 29 05:37:05 PM PDT 24
Finished	Jul 29 05:37:07 PM PDT 24
Peak memory	218272 kb
Host	smart-c8fc95bf-152d-4724-b0a0-2c61bc75aafb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271116869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.271116869
Directory	/workspace/33.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_mubi.2622177601
Short name	T148
Test name
Test status
Simulation time	1138380364 ps
CPU time	14.23 seconds
Started	Jul 29 05:37:09 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	226180 kb
Host	smart-1fff9522-0c87-4791-aeb8-63bf3e726300
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622177601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2622177601
Directory	/workspace/33.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_digest.3399749935
Short name	T667
Test name
Test status
Simulation time	1629626279 ps
CPU time	19.56 seconds
Started	Jul 29 05:37:07 PM PDT 24
Finished	Jul 29 05:37:27 PM PDT 24
Peak memory	218204 kb
Host	smart-6506cb17-a073-4d79-b96b-4ebc8898ac40
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399749935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.3399749935
Directory	/workspace/33.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_mux.3109124603
Short name	T687
Test name
Test status
Simulation time	1486361699 ps
CPU time	8.87 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:19 PM PDT 24
Peak memory	225264 kb
Host	smart-6451aa87-686e-4a39-8e9d-818bc6a68e1a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109124603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux. 3109124603
Directory	/workspace/33.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/33.lc_ctrl_security_escalation.1675301955
Short name	T688
Test name
Test status
Simulation time	213770640 ps
CPU time	9.67 seconds
Started	Jul 29 05:37:08 PM PDT 24
Finished	Jul 29 05:37:18 PM PDT 24
Peak memory	226080 kb
Host	smart-13aa91c6-0885-4bbb-9a06-bfc478174584
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675301955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1675301955
Directory	/workspace/33.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_smoke.3030727811
Short name	T518
Test name
Test status
Simulation time	147194661 ps
CPU time	2.13 seconds
Started	Jul 29 05:37:06 PM PDT 24
Finished	Jul 29 05:37:08 PM PDT 24
Peak memory	214316 kb
Host	smart-5471485c-bb75-44ee-aaf8-f448d05e3f02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030727811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3030727811
Directory	/workspace/33.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_failure.1854829731
Short name	T782
Test name
Test status
Simulation time	264556775 ps
CPU time	30.48 seconds
Started	Jul 29 05:37:06 PM PDT 24
Finished	Jul 29 05:37:37 PM PDT 24
Peak memory	251012 kb
Host	smart-1c4b2e1e-cfe7-4a9a-b090-ffbccd27632d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854829731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1854829731
Directory	/workspace/33.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_post_trans.945888739
Short name	T489
Test name
Test status
Simulation time	45606607 ps
CPU time	7.34 seconds
Started	Jul 29 05:37:06 PM PDT 24
Finished	Jul 29 05:37:14 PM PDT 24
Peak memory	250864 kb
Host	smart-36105cda-d923-44b6-8f7e-c3e7ee7fe548
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945888739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.945888739
Directory	/workspace/33.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all.3568171704
Short name	T10
Test name
Test status
Simulation time	883475840 ps
CPU time	23.41 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:34 PM PDT 24
Peak memory	251000 kb
Host	smart-7c2f6fd1-907b-4d90-82ce-9cdd04ab267b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568171704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.3568171704
Directory	/workspace/33.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4019395975
Short name	T797
Test name
Test status
Simulation time	62011870 ps
CPU time	0.87 seconds
Started	Jul 29 05:37:05 PM PDT 24
Finished	Jul 29 05:37:06 PM PDT 24
Peak memory	212076 kb
Host	smart-bd8b78bf-8096-439f-87ab-28dd10f002d2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019395975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c trl_volatile_unlock_smoke.4019395975
Directory	/workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_alert_test.4119713499
Short name	T281
Test name
Test status
Simulation time	60793226 ps
CPU time	0.89 seconds
Started	Jul 29 05:37:11 PM PDT 24
Finished	Jul 29 05:37:12 PM PDT 24
Peak memory	208936 kb
Host	smart-7abad61d-6bab-4256-8349-1b11b65115b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119713499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.4119713499
Directory	/workspace/34.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.lc_ctrl_errors.3005029482
Short name	T356
Test name
Test status
Simulation time	463615366 ps
CPU time	12.92 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:25 PM PDT 24
Peak memory	226180 kb
Host	smart-e66a0514-5e9b-4aef-aa5c-75075fbd062c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005029482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3005029482
Directory	/workspace/34.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/34.lc_ctrl_jtag_access.2874358424
Short name	T843
Test name
Test status
Simulation time	345579074 ps
CPU time	4.79 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:15 PM PDT 24
Peak memory	217452 kb
Host	smart-39c0781a-e947-44f4-a053-e40cdec2a015
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874358424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2874358424
Directory	/workspace/34.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/34.lc_ctrl_prog_failure.2388772602
Short name	T587
Test name
Test status
Simulation time	264686577 ps
CPU time	3.57 seconds
Started	Jul 29 05:37:11 PM PDT 24
Finished	Jul 29 05:37:15 PM PDT 24
Peak memory	218340 kb
Host	smart-677490ce-6871-4176-94c0-2a200c053004
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388772602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2388772602
Directory	/workspace/34.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_mubi.4200068923
Short name	T159
Test name
Test status
Simulation time	6320788337 ps
CPU time	9.79 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:20 PM PDT 24
Peak memory	226248 kb
Host	smart-5f8cb327-cdf8-49ec-945b-d3d821c00d99
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200068923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4200068923
Directory	/workspace/34.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_digest.2540366474
Short name	T236
Test name
Test status
Simulation time	375351908 ps
CPU time	10.5 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:23 PM PDT 24
Peak memory	218308 kb
Host	smart-ed153168-315f-4d03-89f6-c7e548e9c0d6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540366474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d igest.2540366474
Directory	/workspace/34.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_mux.714738377
Short name	T719
Test name
Test status
Simulation time	3863179517 ps
CPU time	11.52 seconds
Started	Jul 29 05:37:10 PM PDT 24
Finished	Jul 29 05:37:22 PM PDT 24
Peak memory	226180 kb
Host	smart-09bd303e-5c34-4c8c-b80b-e5b04c166313
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714738377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.714738377
Directory	/workspace/34.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/34.lc_ctrl_security_escalation.884113122
Short name	T835
Test name
Test status
Simulation time	739094670 ps
CPU time	7.07 seconds
Started	Jul 29 05:37:11 PM PDT 24
Finished	Jul 29 05:37:18 PM PDT 24
Peak memory	224688 kb
Host	smart-4b6b21f8-a2c1-4cf9-ab1b-c66f03be7865
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884113122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.884113122
Directory	/workspace/34.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/34.lc_ctrl_smoke.3521574802
Short name	T847
Test name
Test status
Simulation time	27936379 ps
CPU time	1.89 seconds
Started	Jul 29 05:37:11 PM PDT 24
Finished	Jul 29 05:37:13 PM PDT 24
Peak memory	222364 kb
Host	smart-edce9757-309c-4cdc-95a4-371a1ebcb289
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521574802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3521574802
Directory	/workspace/34.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_failure.128467989
Short name	T295
Test name
Test status
Simulation time	399240650 ps
CPU time	23.32 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:38 PM PDT 24
Peak memory	250960 kb
Host	smart-54693782-40a2-44dd-a0f0-5f1fe72403b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=128467989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.128467989
Directory	/workspace/34.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_post_trans.2112940334
Short name	T220
Test name
Test status
Simulation time	574640204 ps
CPU time	10.52 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:22 PM PDT 24
Peak memory	250928 kb
Host	smart-80bdbe68-664b-42d5-8104-4fdd274e1da2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112940334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2112940334
Directory	/workspace/34.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all.1689996303
Short name	T60
Test name
Test status
Simulation time	19569660578 ps
CPU time	172.34 seconds
Started	Jul 29 05:37:13 PM PDT 24
Finished	Jul 29 05:40:05 PM PDT 24
Peak memory	251060 kb
Host	smart-a8a8bd5d-4c16-4aa2-9da3-a29afe8d4741
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689996303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.1689996303
Directory	/workspace/34.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.229329371
Short name	T670
Test name
Test status
Simulation time	81941073410 ps
CPU time	749.18 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:49:43 PM PDT 24
Peak memory	299740 kb
Host	smart-b6ea2b99-2672-4cbb-869c-8242bc58d3f1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=229329371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.229329371
Directory	/workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.615058521
Short name	T778
Test name
Test status
Simulation time	38802547 ps
CPU time	0.89 seconds
Started	Jul 29 05:37:13 PM PDT 24
Finished	Jul 29 05:37:14 PM PDT 24
Peak memory	212108 kb
Host	smart-bfcd6417-19a7-44e7-a5bb-c3b37963fd4b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615058521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct rl_volatile_unlock_smoke.615058521
Directory	/workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_alert_test.1474185131
Short name	T268
Test name
Test status
Simulation time	157183384 ps
CPU time	0.86 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:13 PM PDT 24
Peak memory	208820 kb
Host	smart-7f1fea79-57fd-44bf-be1f-be967c021d1b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474185131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1474185131
Directory	/workspace/35.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.lc_ctrl_errors.2359737226
Short name	T318
Test name
Test status
Simulation time	1184482149 ps
CPU time	9.99 seconds
Started	Jul 29 05:37:09 PM PDT 24
Finished	Jul 29 05:37:19 PM PDT 24
Peak memory	218364 kb
Host	smart-7a80e7e7-eae9-4ae6-91cf-919af8c85dc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359737226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2359737226
Directory	/workspace/35.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/35.lc_ctrl_jtag_access.289962405
Short name	T9
Test name
Test status
Simulation time	1041708246 ps
CPU time	2.17 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:14 PM PDT 24
Peak memory	217232 kb
Host	smart-722db819-bb5c-4b3e-95c3-789272ba6d0d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289962405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.289962405
Directory	/workspace/35.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/35.lc_ctrl_prog_failure.83609102
Short name	T510
Test name
Test status
Simulation time	71815962 ps
CPU time	3.77 seconds
Started	Jul 29 05:37:13 PM PDT 24
Finished	Jul 29 05:37:17 PM PDT 24
Peak memory	222424 kb
Host	smart-dbf102bf-e4c5-4e13-aa68-dc28b092dffd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83609102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.83609102
Directory	/workspace/35.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_mubi.35044862
Short name	T639
Test name
Test status
Simulation time	442354247 ps
CPU time	8.76 seconds
Started	Jul 29 05:37:13 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	218396 kb
Host	smart-57f04fa9-167f-4c9f-9378-0a9169ca0d70
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.35044862
Directory	/workspace/35.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_digest.2720742713
Short name	T820
Test name
Test status
Simulation time	182086048 ps
CPU time	8.61 seconds
Started	Jul 29 05:37:15 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	218460 kb
Host	smart-48d8b376-093b-45bc-9d32-b40c7eb071f4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720742713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d igest.2720742713
Directory	/workspace/35.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_mux.3282642823
Short name	T832
Test name
Test status
Simulation time	1226686611 ps
CPU time	9.07 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	226100 kb
Host	smart-5165070c-34c2-4dc2-95e0-6ba0a227d066
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282642823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux. 3282642823
Directory	/workspace/35.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/35.lc_ctrl_smoke.151108920
Short name	T673
Test name
Test status
Simulation time	51726540 ps
CPU time	1.78 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:14 PM PDT 24
Peak memory	217780 kb
Host	smart-9b571c35-4432-47c3-91c0-78c3d6e4c9a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151108920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.151108920
Directory	/workspace/35.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_failure.3149839182
Short name	T796
Test name
Test status
Simulation time	2788091496 ps
CPU time	23.55 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	247380 kb
Host	smart-cd6bc853-2df9-4032-b497-d587ddc02451
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149839182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3149839182
Directory	/workspace/35.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_post_trans.1346761015
Short name	T422
Test name
Test status
Simulation time	315176834 ps
CPU time	7.25 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:19 PM PDT 24
Peak memory	251004 kb
Host	smart-7c69a9b0-2f7f-4555-adb6-22be1e10f0cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346761015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1346761015
Directory	/workspace/35.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.2057753300
Short name	T466
Test name
Test status
Simulation time	53750060320 ps
CPU time	480.66 seconds
Started	Jul 29 05:37:11 PM PDT 24
Finished	Jul 29 05:45:12 PM PDT 24
Peak memory	333100 kb
Host	smart-3d5496bc-19f2-429c-80cc-85c16518ba12
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2057753300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.2057753300
Directory	/workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.387792371
Short name	T267
Test name
Test status
Simulation time	32468694 ps
CPU time	0.97 seconds
Started	Jul 29 05:37:11 PM PDT 24
Finished	Jul 29 05:37:12 PM PDT 24
Peak memory	211964 kb
Host	smart-34220674-fb4f-47c4-a274-e0ac02e2bfda
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387792371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct rl_volatile_unlock_smoke.387792371
Directory	/workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_alert_test.1610740141
Short name	T307
Test name
Test status
Simulation time	26887370 ps
CPU time	1.03 seconds
Started	Jul 29 05:37:17 PM PDT 24
Finished	Jul 29 05:37:18 PM PDT 24
Peak memory	209016 kb
Host	smart-f80d50ff-62fc-4c37-bd53-43d4d121467c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610740141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1610740141
Directory	/workspace/36.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_errors.843166589
Short name	T46
Test name
Test status
Simulation time	1023598547 ps
CPU time	12.18 seconds
Started	Jul 29 05:37:16 PM PDT 24
Finished	Jul 29 05:37:28 PM PDT 24
Peak memory	226176 kb
Host	smart-80bf2513-37cb-428f-b381-fcefd35bb76f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843166589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.843166589
Directory	/workspace/36.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/36.lc_ctrl_prog_failure.1897890672
Short name	T551
Test name
Test status
Simulation time	57929797 ps
CPU time	2.19 seconds
Started	Jul 29 05:37:16 PM PDT 24
Finished	Jul 29 05:37:18 PM PDT 24
Peak memory	218352 kb
Host	smart-f048edff-8c15-407a-ad31-24d79ffe5c1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897890672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1897890672
Directory	/workspace/36.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_mubi.595973876
Short name	T434
Test name
Test status
Simulation time	1328928995 ps
CPU time	15.53 seconds
Started	Jul 29 05:37:15 PM PDT 24
Finished	Jul 29 05:37:30 PM PDT 24
Peak memory	226180 kb
Host	smart-217f8f54-a36f-4bac-8fb2-8aee3c7fac70
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595973876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.595973876
Directory	/workspace/36.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_digest.171629771
Short name	T836
Test name
Test status
Simulation time	1032115174 ps
CPU time	10.39 seconds
Started	Jul 29 05:37:17 PM PDT 24
Finished	Jul 29 05:37:28 PM PDT 24
Peak memory	218320 kb
Host	smart-1fe6ddaf-3403-4ea7-883e-e74006cc015a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171629771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di gest.171629771
Directory	/workspace/36.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_mux.4181487961
Short name	T870
Test name
Test status
Simulation time	486999230 ps
CPU time	8.69 seconds
Started	Jul 29 05:37:15 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	218332 kb
Host	smart-6b6f6b58-ee6d-430c-93ff-0be04e8c318d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181487961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux. 4181487961
Directory	/workspace/36.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/36.lc_ctrl_security_escalation.585087887
Short name	T806
Test name
Test status
Simulation time	1194915404 ps
CPU time	14.93 seconds
Started	Jul 29 05:37:15 PM PDT 24
Finished	Jul 29 05:37:30 PM PDT 24
Peak memory	218504 kb
Host	smart-38e63e58-5b05-4656-b5a7-83fc81e8aad2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585087887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.585087887
Directory	/workspace/36.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_smoke.1022679101
Short name	T67
Test name
Test status
Simulation time	96882197 ps
CPU time	1.02 seconds
Started	Jul 29 05:37:12 PM PDT 24
Finished	Jul 29 05:37:13 PM PDT 24
Peak memory	217796 kb
Host	smart-877e4a03-f633-4f25-8fbb-25c1a40c14b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1022679101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1022679101
Directory	/workspace/36.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_failure.3838877593
Short name	T270
Test name
Test status
Simulation time	737369977 ps
CPU time	16.76 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:31 PM PDT 24
Peak memory	250940 kb
Host	smart-59c6e7e5-4027-4c93-b978-99f0ebbe7053
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838877593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3838877593
Directory	/workspace/36.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_post_trans.3725414059
Short name	T869
Test name
Test status
Simulation time	99445603 ps
CPU time	6.91 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	246728 kb
Host	smart-24631340-0e18-405c-9a0b-e3c1c2b0f898
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725414059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3725414059
Directory	/workspace/36.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all.4081362570
Short name	T781
Test name
Test status
Simulation time	1367929867 ps
CPU time	30.37 seconds
Started	Jul 29 05:37:17 PM PDT 24
Finished	Jul 29 05:37:47 PM PDT 24
Peak memory	250996 kb
Host	smart-800492d8-33cc-43ab-bf55-32c2b443f486
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081362570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.4081362570
Directory	/workspace/36.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.4026758761
Short name	T543
Test name
Test status
Simulation time	38563392 ps
CPU time	0.89 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:15 PM PDT 24
Peak memory	212180 kb
Host	smart-4db55015-1a09-4114-b668-9ed427a4e447
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026758761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.4026758761
Directory	/workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_alert_test.4251654006
Short name	T358
Test name
Test status
Simulation time	39071594 ps
CPU time	0.9 seconds
Started	Jul 29 05:37:20 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	208924 kb
Host	smart-ae9c8263-9215-43a7-870d-32cc9936a6eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251654006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4251654006
Directory	/workspace/37.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.lc_ctrl_errors.1881916736
Short name	T490
Test name
Test status
Simulation time	405651455 ps
CPU time	10.6 seconds
Started	Jul 29 05:37:16 PM PDT 24
Finished	Jul 29 05:37:26 PM PDT 24
Peak memory	226164 kb
Host	smart-559f6a41-4445-4728-a88e-074eaceabe2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881916736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1881916736
Directory	/workspace/37.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/37.lc_ctrl_jtag_access.673914078
Short name	T32
Test name
Test status
Simulation time	532672870 ps
CPU time	2.33 seconds
Started	Jul 29 05:37:15 PM PDT 24
Finished	Jul 29 05:37:17 PM PDT 24
Peak memory	217124 kb
Host	smart-076b3979-e1cd-4b64-9b09-ae2760ca42f4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673914078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.673914078
Directory	/workspace/37.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/37.lc_ctrl_prog_failure.4027126054
Short name	T859
Test name
Test status
Simulation time	86846869 ps
CPU time	2.69 seconds
Started	Jul 29 05:37:17 PM PDT 24
Finished	Jul 29 05:37:20 PM PDT 24
Peak memory	218396 kb
Host	smart-3ef25076-de93-4263-b4a9-70524a66b2c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027126054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4027126054
Directory	/workspace/37.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_mubi.4008356348
Short name	T304
Test name
Test status
Simulation time	921442468 ps
CPU time	12.98 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:27 PM PDT 24
Peak memory	226156 kb
Host	smart-78d17b1c-18b0-411b-9e6d-14c4cc36146d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008356348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.4008356348
Directory	/workspace/37.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_digest.2654118488
Short name	T351
Test name
Test status
Simulation time	1564548540 ps
CPU time	10.44 seconds
Started	Jul 29 05:37:23 PM PDT 24
Finished	Jul 29 05:37:34 PM PDT 24
Peak memory	218288 kb
Host	smart-9c9e6b8e-c7f0-4c9a-a372-446c6a4d71c6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654118488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.2654118488
Directory	/workspace/37.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_mux.2164482046
Short name	T41
Test name
Test status
Simulation time	268632513 ps
CPU time	8.11 seconds
Started	Jul 29 05:37:19 PM PDT 24
Finished	Jul 29 05:37:28 PM PDT 24
Peak memory	218480 kb
Host	smart-22eabe8b-54bd-4353-b69c-48a2a61f371e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164482046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux. 2164482046
Directory	/workspace/37.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/37.lc_ctrl_security_escalation.1108680502
Short name	T873
Test name
Test status
Simulation time	353321910 ps
CPU time	7.97 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:22 PM PDT 24
Peak memory	226164 kb
Host	smart-0327325e-b7aa-4904-ba46-ba7d7c8dd2b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108680502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1108680502
Directory	/workspace/37.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/37.lc_ctrl_smoke.1953333825
Short name	T400
Test name
Test status
Simulation time	20868251 ps
CPU time	1.56 seconds
Started	Jul 29 05:37:16 PM PDT 24
Finished	Jul 29 05:37:17 PM PDT 24
Peak memory	217808 kb
Host	smart-3a04024f-cb96-440e-87e0-4166e38893b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1953333825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1953333825
Directory	/workspace/37.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_failure.3426413353
Short name	T582
Test name
Test status
Simulation time	365019572 ps
CPU time	17.37 seconds
Started	Jul 29 05:37:14 PM PDT 24
Finished	Jul 29 05:37:32 PM PDT 24
Peak memory	251020 kb
Host	smart-5f3dc2b6-5827-4d53-a9ff-866153c24dab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426413353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3426413353
Directory	/workspace/37.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_post_trans.2769837936
Short name	T632
Test name
Test status
Simulation time	257856001 ps
CPU time	3.02 seconds
Started	Jul 29 05:37:16 PM PDT 24
Finished	Jul 29 05:37:19 PM PDT 24
Peak memory	218340 kb
Host	smart-41f0eca3-b446-4077-878b-427c1f605b7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769837936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2769837936
Directory	/workspace/37.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all.1769326443
Short name	T97
Test name
Test status
Simulation time	9584108430 ps
CPU time	311.46 seconds
Started	Jul 29 05:37:21 PM PDT 24
Finished	Jul 29 05:42:33 PM PDT 24
Peak memory	283268 kb
Host	smart-ea1d9fa3-ba56-41d5-aa63-f7d65c3ac75a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769326443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.1769326443
Directory	/workspace/37.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1155657622
Short name	T816
Test name
Test status
Simulation time	58855526817 ps
CPU time	1038.96 seconds
Started	Jul 29 05:37:21 PM PDT 24
Finished	Jul 29 05:54:40 PM PDT 24
Peak memory	438672 kb
Host	smart-59ae4cfa-5ba4-45d2-a9e5-f2292f9d9178
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1155657622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1155657622
Directory	/workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3193933249
Short name	T223
Test name
Test status
Simulation time	13890480 ps
CPU time	0.85 seconds
Started	Jul 29 05:37:16 PM PDT 24
Finished	Jul 29 05:37:17 PM PDT 24
Peak memory	212044 kb
Host	smart-62dd2bbf-b846-44ac-9cc7-8c55d488d271
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193933249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.3193933249
Directory	/workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_alert_test.3976764134
Short name	T221
Test name
Test status
Simulation time	18405575 ps
CPU time	0.98 seconds
Started	Jul 29 05:37:20 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	209004 kb
Host	smart-95c3b435-0126-4d4f-9914-0e19b42cb69b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976764134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3976764134
Directory	/workspace/38.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.lc_ctrl_jtag_access.709741883
Short name	T302
Test name
Test status
Simulation time	987246500 ps
CPU time	9.75 seconds
Started	Jul 29 05:37:21 PM PDT 24
Finished	Jul 29 05:37:31 PM PDT 24
Peak memory	217372 kb
Host	smart-27ca9986-d880-4cb5-849b-411a3452bbae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709741883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.709741883
Directory	/workspace/38.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/38.lc_ctrl_prog_failure.2612684293
Short name	T627
Test name
Test status
Simulation time	766115969 ps
CPU time	2.83 seconds
Started	Jul 29 05:37:21 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	222604 kb
Host	smart-bd6f1d3b-a43c-439f-b77e-d7745bb60d89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612684293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2612684293
Directory	/workspace/38.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_mubi.3796032205
Short name	T465
Test name
Test status
Simulation time	271860653 ps
CPU time	10.05 seconds
Started	Jul 29 05:37:23 PM PDT 24
Finished	Jul 29 05:37:33 PM PDT 24
Peak memory	218388 kb
Host	smart-f983a97e-d547-4399-82dd-188c6071d301
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796032205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3796032205
Directory	/workspace/38.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_digest.481602418
Short name	T766
Test name
Test status
Simulation time	402697824 ps
CPU time	11.51 seconds
Started	Jul 29 05:37:21 PM PDT 24
Finished	Jul 29 05:37:33 PM PDT 24
Peak memory	218292 kb
Host	smart-c09ac460-47e5-4758-bec1-9387fc35311a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481602418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di gest.481602418
Directory	/workspace/38.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_mux.2852744364
Short name	T23
Test name
Test status
Simulation time	1948895701 ps
CPU time	9.81 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:37:34 PM PDT 24
Peak memory	218264 kb
Host	smart-11e44ab5-e280-4391-89c8-77e813e3fc3d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852744364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux. 2852744364
Directory	/workspace/38.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/38.lc_ctrl_security_escalation.2136057743
Short name	T674
Test name
Test status
Simulation time	7920640565 ps
CPU time	9.64 seconds
Started	Jul 29 05:37:18 PM PDT 24
Finished	Jul 29 05:37:28 PM PDT 24
Peak memory	226076 kb
Host	smart-8817a732-fee3-4de7-8273-0af43db54044
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136057743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2136057743
Directory	/workspace/38.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/38.lc_ctrl_smoke.3228001877
Short name	T284
Test name
Test status
Simulation time	498618015 ps
CPU time	3.05 seconds
Started	Jul 29 05:37:19 PM PDT 24
Finished	Jul 29 05:37:22 PM PDT 24
Peak memory	217692 kb
Host	smart-1a1cca52-4ee1-42b0-8e13-123d6ca0db1b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228001877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3228001877
Directory	/workspace/38.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_failure.2280446701
Short name	T773
Test name
Test status
Simulation time	491306406 ps
CPU time	27.26 seconds
Started	Jul 29 05:37:19 PM PDT 24
Finished	Jul 29 05:37:46 PM PDT 24
Peak memory	250932 kb
Host	smart-84c37c49-6630-4b9a-9037-0f4777f658b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280446701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2280446701
Directory	/workspace/38.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_post_trans.2273365793
Short name	T149
Test name
Test status
Simulation time	102436698 ps
CPU time	8.22 seconds
Started	Jul 29 05:37:21 PM PDT 24
Finished	Jul 29 05:37:29 PM PDT 24
Peak memory	250932 kb
Host	smart-35e480ad-944c-46c6-abee-ea5f1bc33463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2273365793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2273365793
Directory	/workspace/38.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all.228594865
Short name	T257
Test name
Test status
Simulation time	3878697323 ps
CPU time	129.12 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:39:34 PM PDT 24
Peak memory	251052 kb
Host	smart-2428db9b-96c6-4689-b7df-d940d8a6e5fd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228594865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.228594865
Directory	/workspace/38.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2770343095
Short name	T77
Test name
Test status
Simulation time	62320276615 ps
CPU time	463.07 seconds
Started	Jul 29 05:37:18 PM PDT 24
Finished	Jul 29 05:45:02 PM PDT 24
Peak memory	334276 kb
Host	smart-97b9fcc9-1ae0-49ca-af3a-341b177dc052
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2770343095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2770343095
Directory	/workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4233177646
Short name	T525
Test name
Test status
Simulation time	41039601 ps
CPU time	1.03 seconds
Started	Jul 29 05:37:20 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	212040 kb
Host	smart-1a7cbdca-f260-4622-bb4e-e62a4282017f
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233177646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c trl_volatile_unlock_smoke.4233177646
Directory	/workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_alert_test.3948103806
Short name	T73
Test name
Test status
Simulation time	16155529 ps
CPU time	0.86 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:26 PM PDT 24
Peak memory	208868 kb
Host	smart-bda140f4-6c01-42a0-a0e7-5f0d859fc766
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948103806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3948103806
Directory	/workspace/39.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.lc_ctrl_errors.2042811623
Short name	T287
Test name
Test status
Simulation time	453217142 ps
CPU time	21.45 seconds
Started	Jul 29 05:37:27 PM PDT 24
Finished	Jul 29 05:37:48 PM PDT 24
Peak memory	218288 kb
Host	smart-777b03d8-0419-42f2-9aeb-3a8af9de39fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042811623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2042811623
Directory	/workspace/39.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/39.lc_ctrl_jtag_access.1048687011
Short name	T450
Test name
Test status
Simulation time	3728023071 ps
CPU time	10.12 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	218028 kb
Host	smart-9eb1b8d2-01c1-4314-9b31-040ae09addd4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048687011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1048687011
Directory	/workspace/39.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/39.lc_ctrl_prog_failure.2047887364
Short name	T743
Test name
Test status
Simulation time	273911968 ps
CPU time	2.63 seconds
Started	Jul 29 05:37:22 PM PDT 24
Finished	Jul 29 05:37:25 PM PDT 24
Peak memory	218372 kb
Host	smart-f9c95b29-ab14-4859-a75c-b092cd113f85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047887364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2047887364
Directory	/workspace/39.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_mubi.1356907613
Short name	T274
Test name
Test status
Simulation time	2029125505 ps
CPU time	14.54 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	226172 kb
Host	smart-d5f4d292-d140-43d0-9ead-b2ef1a4d7cbd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356907613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1356907613
Directory	/workspace/39.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_digest.933615709
Short name	T716
Test name
Test status
Simulation time	1839548218 ps
CPU time	14.56 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	226112 kb
Host	smart-3a16be72-c663-4edb-bfa9-6c7e5b8da37c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933615709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di gest.933615709
Directory	/workspace/39.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_mux.2230954816
Short name	T94
Test name
Test status
Simulation time	538496085 ps
CPU time	7.02 seconds
Started	Jul 29 05:37:22 PM PDT 24
Finished	Jul 29 05:37:29 PM PDT 24
Peak memory	218324 kb
Host	smart-d397ba1b-6f9e-4189-8205-ffef3d7ea783
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230954816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux. 2230954816
Directory	/workspace/39.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/39.lc_ctrl_security_escalation.959339370
Short name	T654
Test name
Test status
Simulation time	483634488 ps
CPU time	11.05 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	226096 kb
Host	smart-a3ca59f6-4b46-4450-a2f4-bd1db19fc140
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959339370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.959339370
Directory	/workspace/39.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/39.lc_ctrl_smoke.3373193405
Short name	T747
Test name
Test status
Simulation time	146890057 ps
CPU time	3.77 seconds
Started	Jul 29 05:37:19 PM PDT 24
Finished	Jul 29 05:37:23 PM PDT 24
Peak memory	217804 kb
Host	smart-22d92c43-8318-47ac-b9df-5733cc8fd8f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373193405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3373193405
Directory	/workspace/39.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_failure.3988642405
Short name	T649
Test name
Test status
Simulation time	1089148021 ps
CPU time	33.76 seconds
Started	Jul 29 05:37:21 PM PDT 24
Finished	Jul 29 05:37:55 PM PDT 24
Peak memory	250996 kb
Host	smart-b2364049-9fb5-4b4e-96e6-5d5185eec112
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988642405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3988642405
Directory	/workspace/39.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_post_trans.3656056532
Short name	T486
Test name
Test status
Simulation time	125168768 ps
CPU time	6.1 seconds
Started	Jul 29 05:37:18 PM PDT 24
Finished	Jul 29 05:37:24 PM PDT 24
Peak memory	247004 kb
Host	smart-8b07a4d9-cd88-4770-83bf-2f0679485956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656056532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3656056532
Directory	/workspace/39.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all.2516074837
Short name	T576
Test name
Test status
Simulation time	16417427117 ps
CPU time	49.55 seconds
Started	Jul 29 05:37:26 PM PDT 24
Finished	Jul 29 05:38:16 PM PDT 24
Peak memory	226096 kb
Host	smart-3e7d2ec0-a025-4d65-bdda-ba0c83f537ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516074837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.2516074837
Directory	/workspace/39.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.698274163
Short name	T815
Test name
Test status
Simulation time	93618653 ps
CPU time	0.83 seconds
Started	Jul 29 05:37:20 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	212072 kb
Host	smart-3bd78971-0787-485b-ba9e-ba74c06d0841
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698274163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct rl_volatile_unlock_smoke.698274163
Directory	/workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_alert_test.924221161
Short name	T804
Test name
Test status
Simulation time	70340685 ps
CPU time	1.1 seconds
Started	Jul 29 05:35:21 PM PDT 24
Finished	Jul 29 05:35:23 PM PDT 24
Peak memory	208944 kb
Host	smart-73ef5ff1-0c09-4241-bb21-416f381d6ba8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924221161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.924221161
Directory	/workspace/4.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.lc_ctrl_errors.2975676485
Short name	T831
Test name
Test status
Simulation time	4077623262 ps
CPU time	16.09 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:39 PM PDT 24
Peak memory	219132 kb
Host	smart-bdac58c9-fdc2-4348-851e-e102f9071459
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2975676485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2975676485
Directory	/workspace/4.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_access.3191462141
Short name	T763
Test name
Test status
Simulation time	7592584983 ps
CPU time	7.42 seconds
Started	Jul 29 05:35:27 PM PDT 24
Finished	Jul 29 05:35:34 PM PDT 24
Peak memory	217680 kb
Host	smart-4894193d-15be-4729-b60a-d8afa4287f28
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191462141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3191462141
Directory	/workspace/4.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_errors.1593020718
Short name	T412
Test name
Test status
Simulation time	1970999170 ps
CPU time	18.23 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:41 PM PDT 24
Peak memory	225652 kb
Host	smart-eead034c-d500-400a-8b35-0c1f490a55f0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593020718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er rors.1593020718
Directory	/workspace/4.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_priority.983731525
Short name	T740
Test name
Test status
Simulation time	226301686 ps
CPU time	6.96 seconds
Started	Jul 29 05:35:28 PM PDT 24
Finished	Jul 29 05:35:35 PM PDT 24
Peak memory	217848 kb
Host	smart-2f271604-3603-4fb0-81d4-752141510d11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983731525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.983731525
Directory	/workspace/4.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2777588229
Short name	T616
Test name
Test status
Simulation time	1328260981 ps
CPU time	7.44 seconds
Started	Jul 29 05:35:24 PM PDT 24
Finished	Jul 29 05:35:31 PM PDT 24
Peak memory	218408 kb
Host	smart-4df18e9a-5135-4924-ba63-d68e6ed2420a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777588229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _prog_failure.2777588229
Directory	/workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1288064195
Short name	T327
Test name
Test status
Simulation time	4322489404 ps
CPU time	31.39 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	217804 kb
Host	smart-fa450d84-9f72-400e-a094-2843934fbd18
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288064195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_regwen_during_op.1288064195
Directory	/workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_smoke.3032465950
Short name	T645
Test name
Test status
Simulation time	1135806950 ps
CPU time	5.31 seconds
Started	Jul 29 05:35:23 PM PDT 24
Finished	Jul 29 05:35:28 PM PDT 24
Peak memory	217680 kb
Host	smart-a058caff-c5e3-4470-9c56-b9f78f58636a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032465950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke. 3032465950
Directory	/workspace/4.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3619096269
Short name	T225
Test name
Test status
Simulation time	1793969058 ps
CPU time	42.84 seconds
Started	Jul 29 05:35:24 PM PDT 24
Finished	Jul 29 05:36:07 PM PDT 24
Peak memory	276828 kb
Host	smart-25f1cdc1-3fca-459b-8cd2-51be8f14625a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619096269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta g_state_failure.3619096269
Directory	/workspace/4.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4217256199
Short name	T863
Test name
Test status
Simulation time	1161419166 ps
CPU time	18.67 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:41 PM PDT 24
Peak memory	250672 kb
Host	smart-992bfdbe-6930-4346-9c8f-a0b74bf4f757
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217256199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.4217256199
Directory	/workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_prog_failure.3986066617
Short name	T833
Test name
Test status
Simulation time	423036394 ps
CPU time	4.35 seconds
Started	Jul 29 05:35:28 PM PDT 24
Finished	Jul 29 05:35:32 PM PDT 24
Peak memory	222532 kb
Host	smart-8fcefeda-9679-4b3b-bdde-507023192e6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986066617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3986066617
Directory	/workspace/4.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_regwen_during_op.4041389063
Short name	T62
Test name
Test status
Simulation time	425285320 ps
CPU time	16.08 seconds
Started	Jul 29 05:35:23 PM PDT 24
Finished	Jul 29 05:35:40 PM PDT 24
Peak memory	214076 kb
Host	smart-3b9a7c93-a0b6-4581-8545-50ab58d99d45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4041389063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4041389063
Directory	/workspace/4.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_mubi.2121916904
Short name	T366
Test name
Test status
Simulation time	1688991034 ps
CPU time	15.12 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:38 PM PDT 24
Peak memory	226076 kb
Host	smart-aca79aa3-35f1-44e5-a9f8-42604fb3a053
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121916904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2121916904
Directory	/workspace/4.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_digest.1402775549
Short name	T550
Test name
Test status
Simulation time	3350964327 ps
CPU time	22.38 seconds
Started	Jul 29 05:35:28 PM PDT 24
Finished	Jul 29 05:35:51 PM PDT 24
Peak memory	219072 kb
Host	smart-5dd51c97-2f67-4f0e-98b9-21822f6d929c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402775549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di gest.1402775549
Directory	/workspace/4.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_mux.1653278868
Short name	T856
Test name
Test status
Simulation time	311564345 ps
CPU time	8.11 seconds
Started	Jul 29 05:35:26 PM PDT 24
Finished	Jul 29 05:35:34 PM PDT 24
Peak memory	226056 kb
Host	smart-dd36f5cb-3f06-4860-8dfd-9a1cb3cc8831
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653278868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1 653278868
Directory	/workspace/4.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/4.lc_ctrl_security_escalation.4050404923
Short name	T310
Test name
Test status
Simulation time	3246289118 ps
CPU time	8.29 seconds
Started	Jul 29 05:35:25 PM PDT 24
Finished	Jul 29 05:35:33 PM PDT 24
Peak memory	226224 kb
Host	smart-6a84cdca-9c9e-468e-b5b1-c140adf1eb5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050404923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4050404923
Directory	/workspace/4.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_smoke.1267686301
Short name	T857
Test name
Test status
Simulation time	255979759 ps
CPU time	3.3 seconds
Started	Jul 29 05:35:19 PM PDT 24
Finished	Jul 29 05:35:23 PM PDT 24
Peak memory	217792 kb
Host	smart-9d3cd131-3c3a-4490-8852-902ee5b646f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267686301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1267686301
Directory	/workspace/4.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_failure.3941103832
Short name	T761
Test name
Test status
Simulation time	293844898 ps
CPU time	28.13 seconds
Started	Jul 29 05:35:17 PM PDT 24
Finished	Jul 29 05:35:45 PM PDT 24
Peak memory	250980 kb
Host	smart-7e772478-66c4-4557-a85a-eb0dafc54e02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941103832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3941103832
Directory	/workspace/4.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_post_trans.1094129956
Short name	T453
Test name
Test status
Simulation time	823665739 ps
CPU time	8.02 seconds
Started	Jul 29 05:35:21 PM PDT 24
Finished	Jul 29 05:35:29 PM PDT 24
Peak memory	250992 kb
Host	smart-96063613-8e63-4152-9ca9-48f8cb6c7b61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094129956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1094129956
Directory	/workspace/4.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all.2487234873
Short name	T726
Test name
Test status
Simulation time	6728293476 ps
CPU time	280.12 seconds
Started	Jul 29 05:35:26 PM PDT 24
Finished	Jul 29 05:40:07 PM PDT 24
Peak memory	528316 kb
Host	smart-db21d79f-1ee7-4568-9d5b-9b6921335b50
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487234873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.2487234873
Directory	/workspace/4.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1039341674
Short name	T437
Test name
Test status
Simulation time	21387588 ps
CPU time	0.99 seconds
Started	Jul 29 05:35:19 PM PDT 24
Finished	Jul 29 05:35:20 PM PDT 24
Peak memory	212044 kb
Host	smart-bc728ac6-cfa5-4ab9-b40e-7dd401a462fb
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039341674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_volatile_unlock_smoke.1039341674
Directory	/workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_alert_test.2650689598
Short name	T90
Test name
Test status
Simulation time	176167985 ps
CPU time	1.04 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:27 PM PDT 24
Peak memory	209036 kb
Host	smart-8ed4e49b-6708-466c-a716-1b05c5808cc8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650689598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2650689598
Directory	/workspace/40.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.lc_ctrl_errors.1141800492
Short name	T341
Test name
Test status
Simulation time	231819634 ps
CPU time	9.77 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:34 PM PDT 24
Peak memory	218376 kb
Host	smart-992e0c20-49de-438b-a754-4a51bc302da7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141800492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1141800492
Directory	/workspace/40.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/40.lc_ctrl_jtag_access.532613379
Short name	T864
Test name
Test status
Simulation time	335709345 ps
CPU time	5.2 seconds
Started	Jul 29 05:37:23 PM PDT 24
Finished	Jul 29 05:37:28 PM PDT 24
Peak memory	217400 kb
Host	smart-87236aa0-3729-4aee-897a-1e56029f9654
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532613379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.532613379
Directory	/workspace/40.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/40.lc_ctrl_prog_failure.3697738331
Short name	T600
Test name
Test status
Simulation time	259807165 ps
CPU time	3.58 seconds
Started	Jul 29 05:37:26 PM PDT 24
Finished	Jul 29 05:37:30 PM PDT 24
Peak memory	218264 kb
Host	smart-0513c811-cdec-4bcd-87d3-00df05acc4ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697738331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3697738331
Directory	/workspace/40.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_mubi.573821774
Short name	T583
Test name
Test status
Simulation time	198342988 ps
CPU time	10.67 seconds
Started	Jul 29 05:37:26 PM PDT 24
Finished	Jul 29 05:37:37 PM PDT 24
Peak memory	226176 kb
Host	smart-50514817-b9d2-4d3a-8267-c1f0ca1ea8bc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573821774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.573821774
Directory	/workspace/40.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_digest.1003193960
Short name	T333
Test name
Test status
Simulation time	7375497852 ps
CPU time	13.44 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	226184 kb
Host	smart-26fdeddf-4aad-4d11-b4ad-321bda2d164a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003193960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d igest.1003193960
Directory	/workspace/40.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_mux.165420147
Short name	T623
Test name
Test status
Simulation time	303433263 ps
CPU time	11.62 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	226128 kb
Host	smart-8a3bc987-d3d9-449f-a69b-7f1a2b607ee1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165420147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.165420147
Directory	/workspace/40.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/40.lc_ctrl_security_escalation.2817756927
Short name	T394
Test name
Test status
Simulation time	444171475 ps
CPU time	10.58 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	225780 kb
Host	smart-83e71eea-a7dd-4830-b3e0-8a3b3fe0abdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817756927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2817756927
Directory	/workspace/40.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/40.lc_ctrl_smoke.2484639235
Short name	T275
Test name
Test status
Simulation time	259593730 ps
CPU time	6.98 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:37:32 PM PDT 24
Peak memory	217968 kb
Host	smart-8e39d447-3245-4aef-913f-d55c1bbba20c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484639235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2484639235
Directory	/workspace/40.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_failure.2688892047
Short name	T526
Test name
Test status
Simulation time	1030432026 ps
CPU time	27.67 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:53 PM PDT 24
Peak memory	246044 kb
Host	smart-d13711db-5684-47d8-aec2-f29160ada8d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2688892047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2688892047
Directory	/workspace/40.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_post_trans.3825418792
Short name	T862
Test name
Test status
Simulation time	107482487 ps
CPU time	9.54 seconds
Started	Jul 29 05:37:23 PM PDT 24
Finished	Jul 29 05:37:32 PM PDT 24
Peak memory	246468 kb
Host	smart-87c3f234-1d4d-478d-91d0-123daf5cd275
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825418792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3825418792
Directory	/workspace/40.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all.3369521729
Short name	T810
Test name
Test status
Simulation time	11584133528 ps
CPU time	189.26 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:40:34 PM PDT 24
Peak memory	250936 kb
Host	smart-4f87311b-5780-4c34-8312-64d147753b19
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369521729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.3369521729
Directory	/workspace/40.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3631140893
Short name	T141
Test name
Test status
Simulation time	77166075955 ps
CPU time	606.1 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:47:31 PM PDT 24
Peak memory	294436 kb
Host	smart-6bf74571-bdff-4cd5-954e-320c6f862619
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3631140893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3631140893
Directory	/workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4017148372
Short name	T678
Test name
Test status
Simulation time	40135013 ps
CPU time	0.97 seconds
Started	Jul 29 05:37:25 PM PDT 24
Finished	Jul 29 05:37:27 PM PDT 24
Peak memory	212008 kb
Host	smart-5986f17d-57c3-4c52-8bd7-3433f33aa432
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017148372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c trl_volatile_unlock_smoke.4017148372
Directory	/workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_alert_test.3636219604
Short name	T514
Test name
Test status
Simulation time	36264696 ps
CPU time	1.1 seconds
Started	Jul 29 05:37:28 PM PDT 24
Finished	Jul 29 05:37:29 PM PDT 24
Peak memory	209084 kb
Host	smart-e7f224d1-0a5a-42ef-a4c9-75b10bfb45b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636219604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3636219604
Directory	/workspace/41.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.lc_ctrl_errors.3197960899
Short name	T241
Test name
Test status
Simulation time	253256842 ps
CPU time	10.42 seconds
Started	Jul 29 05:37:30 PM PDT 24
Finished	Jul 29 05:37:41 PM PDT 24
Peak memory	218304 kb
Host	smart-00bdc952-bf6a-463a-a9f0-b897815a4aab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197960899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3197960899
Directory	/workspace/41.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/41.lc_ctrl_jtag_access.3475871337
Short name	T354
Test name
Test status
Simulation time	254748036 ps
CPU time	1.6 seconds
Started	Jul 29 05:37:28 PM PDT 24
Finished	Jul 29 05:37:30 PM PDT 24
Peak memory	217164 kb
Host	smart-b8b0538a-ec14-4cf9-a4a1-ac3ef0ade5dc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475871337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3475871337
Directory	/workspace/41.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/41.lc_ctrl_prog_failure.2339899290
Short name	T454
Test name
Test status
Simulation time	293812529 ps
CPU time	3.17 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:32 PM PDT 24
Peak memory	222584 kb
Host	smart-8d5b1e39-17a7-444c-95fa-a859452cc344
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339899290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2339899290
Directory	/workspace/41.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_mubi.1356596747
Short name	T352
Test name
Test status
Simulation time	198748609 ps
CPU time	10.26 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	226144 kb
Host	smart-c3db3403-1eb3-4c73-8965-eb5800f7bba7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356596747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1356596747
Directory	/workspace/41.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_digest.64287266
Short name	T368
Test name
Test status
Simulation time	609861427 ps
CPU time	7.8 seconds
Started	Jul 29 05:37:31 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	218240 kb
Host	smart-1016c4f6-d326-4d30-8343-1260a7b7b424
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64287266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_dig est.64287266
Directory	/workspace/41.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_mux.2787922418
Short name	T405
Test name
Test status
Simulation time	383221523 ps
CPU time	9.6 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	218332 kb
Host	smart-49d8e3d1-7d5c-4785-8072-d6634b1db388
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787922418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 2787922418
Directory	/workspace/41.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/41.lc_ctrl_security_escalation.2399004820
Short name	T509
Test name
Test status
Simulation time	780201135 ps
CPU time	15.06 seconds
Started	Jul 29 05:37:28 PM PDT 24
Finished	Jul 29 05:37:44 PM PDT 24
Peak memory	226120 kb
Host	smart-7d52d400-3503-48f8-bedc-92d6fcf37ace
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399004820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2399004820
Directory	/workspace/41.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/41.lc_ctrl_smoke.3734016789
Short name	T745
Test name
Test status
Simulation time	53442203 ps
CPU time	3.54 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:32 PM PDT 24
Peak memory	217876 kb
Host	smart-1bbdb5f8-e623-4800-8e7d-e071a2f2badc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734016789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3734016789
Directory	/workspace/41.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_failure.4115925379
Short name	T308
Test name
Test status
Simulation time	365519424 ps
CPU time	21.36 seconds
Started	Jul 29 05:37:27 PM PDT 24
Finished	Jul 29 05:37:48 PM PDT 24
Peak memory	250824 kb
Host	smart-fb65f8c0-38ee-418e-86ff-3374f88f2e00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115925379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4115925379
Directory	/workspace/41.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_post_trans.731619203
Short name	T462
Test name
Test status
Simulation time	264219046 ps
CPU time	9.68 seconds
Started	Jul 29 05:37:26 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	250932 kb
Host	smart-c63c169d-2876-4a5a-b088-ad9aab946488
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731619203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.731619203
Directory	/workspace/41.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all.2619013081
Short name	T495
Test name
Test status
Simulation time	77167935057 ps
CPU time	170.21 seconds
Started	Jul 29 05:37:30 PM PDT 24
Finished	Jul 29 05:40:21 PM PDT 24
Peak memory	283664 kb
Host	smart-44826b46-136f-4cb5-a802-7ad448c525a6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619013081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.2619013081
Directory	/workspace/41.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3641881063
Short name	T15
Test name
Test status
Simulation time	32829778 ps
CPU time	0.85 seconds
Started	Jul 29 05:37:24 PM PDT 24
Finished	Jul 29 05:37:25 PM PDT 24
Peak memory	212104 kb
Host	smart-95493c47-f629-4103-9d87-9568b08ab58b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641881063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c trl_volatile_unlock_smoke.3641881063
Directory	/workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_alert_test.1459597125
Short name	T714
Test name
Test status
Simulation time	99655017 ps
CPU time	1.17 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:30 PM PDT 24
Peak memory	209184 kb
Host	smart-6da33e06-4e2b-404e-949c-65ce2eb92d4f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459597125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1459597125
Directory	/workspace/42.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.lc_ctrl_errors.2335936551
Short name	T562
Test name
Test status
Simulation time	1298695044 ps
CPU time	28.47 seconds
Started	Jul 29 05:37:30 PM PDT 24
Finished	Jul 29 05:37:59 PM PDT 24
Peak memory	218368 kb
Host	smart-38d9ed54-9ca6-4d0b-8607-f45fc65db719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335936551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2335936551
Directory	/workspace/42.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/42.lc_ctrl_jtag_access.3555784649
Short name	T413
Test name
Test status
Simulation time	1568771273 ps
CPU time	7.68 seconds
Started	Jul 29 05:37:28 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	217332 kb
Host	smart-1da075d2-6c36-4eef-9a32-69343f0703ea
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555784649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3555784649
Directory	/workspace/42.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/42.lc_ctrl_prog_failure.1815022930
Short name	T700
Test name
Test status
Simulation time	322386245 ps
CPU time	3.67 seconds
Started	Jul 29 05:37:27 PM PDT 24
Finished	Jul 29 05:37:31 PM PDT 24
Peak memory	218336 kb
Host	smart-910d8e69-3ac6-46c8-b99c-0f8a5b6479f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815022930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1815022930
Directory	/workspace/42.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_mubi.871065001
Short name	T147
Test name
Test status
Simulation time	646400064 ps
CPU time	15.34 seconds
Started	Jul 29 05:37:31 PM PDT 24
Finished	Jul 29 05:37:46 PM PDT 24
Peak memory	226156 kb
Host	smart-23b355fe-8da8-41e9-be63-e43070613079
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871065001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.871065001
Directory	/workspace/42.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_digest.78886305
Short name	T212
Test name
Test status
Simulation time	309597593 ps
CPU time	8.92 seconds
Started	Jul 29 05:37:30 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	226044 kb
Host	smart-2e45ee59-40af-4742-a380-31a60ed50e18
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78886305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_dig est.78886305
Directory	/workspace/42.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_mux.379637797
Short name	T536
Test name
Test status
Simulation time	515966024 ps
CPU time	16.86 seconds
Started	Jul 29 05:37:28 PM PDT 24
Finished	Jul 29 05:37:46 PM PDT 24
Peak memory	218304 kb
Host	smart-cbc40baa-f6a5-495b-9289-5790b1bf4e39
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379637797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.379637797
Directory	/workspace/42.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/42.lc_ctrl_security_escalation.3225754740
Short name	T11
Test name
Test status
Simulation time	917126234 ps
CPU time	9.55 seconds
Started	Jul 29 05:37:31 PM PDT 24
Finished	Jul 29 05:37:40 PM PDT 24
Peak memory	225576 kb
Host	smart-6f556e5a-9c88-4a86-964f-0c398ce9673a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225754740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3225754740
Directory	/workspace/42.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/42.lc_ctrl_smoke.44246227
Short name	T255
Test name
Test status
Simulation time	55268186 ps
CPU time	1.32 seconds
Started	Jul 29 05:37:28 PM PDT 24
Finished	Jul 29 05:37:29 PM PDT 24
Peak memory	213696 kb
Host	smart-00557141-a068-40ea-a096-6c7e015fadf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44246227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.44246227
Directory	/workspace/42.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_failure.3534999157
Short name	T784
Test name
Test status
Simulation time	214755736 ps
CPU time	21.75 seconds
Started	Jul 29 05:37:28 PM PDT 24
Finished	Jul 29 05:37:51 PM PDT 24
Peak memory	251012 kb
Host	smart-28df2ed8-03d8-4242-b005-a31354eb2fd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534999157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3534999157
Directory	/workspace/42.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_post_trans.1670852106
Short name	T698
Test name
Test status
Simulation time	78751229 ps
CPU time	3.86 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:33 PM PDT 24
Peak memory	222388 kb
Host	smart-85583539-dafc-4a6b-8c26-f3d63dd8977f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1670852106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1670852106
Directory	/workspace/42.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all.2465722689
Short name	T461
Test name
Test status
Simulation time	13673242119 ps
CPU time	42.06 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:38:11 PM PDT 24
Peak memory	251004 kb
Host	smart-7abc4f21-ed1d-43d0-bf84-87ffc32604df
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465722689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.2465722689
Directory	/workspace/42.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.578190448
Short name	T140
Test name
Test status
Simulation time	111244003932 ps
CPU time	889.17 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:52:30 PM PDT 24
Peak memory	529692 kb
Host	smart-9e56de23-9b3d-4730-8353-71891bfa799f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=578190448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.578190448
Directory	/workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1621533007
Short name	T398
Test name
Test status
Simulation time	12914702 ps
CPU time	0.9 seconds
Started	Jul 29 05:37:40 PM PDT 24
Finished	Jul 29 05:37:41 PM PDT 24
Peak memory	212076 kb
Host	smart-9980c801-7826-4766-99bb-7711bf3015cc
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621533007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c trl_volatile_unlock_smoke.1621533007
Directory	/workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_alert_test.185880883
Short name	T89
Test name
Test status
Simulation time	84288086 ps
CPU time	0.85 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:34 PM PDT 24
Peak memory	209296 kb
Host	smart-1eed49e8-c90c-40e7-827b-e7eef345683d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185880883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.185880883
Directory	/workspace/43.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.lc_ctrl_errors.224066569
Short name	T812
Test name
Test status
Simulation time	3600713601 ps
CPU time	17.93 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:51 PM PDT 24
Peak memory	218472 kb
Host	smart-1c776925-48dc-4d7d-a0d3-2f806764dbf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224066569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.224066569
Directory	/workspace/43.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/43.lc_ctrl_jtag_access.1092926044
Short name	T35
Test name
Test status
Simulation time	1548371873 ps
CPU time	7.04 seconds
Started	Jul 29 05:37:31 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	217304 kb
Host	smart-1c761521-0ca4-43b7-bce3-1113e0aa362e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092926044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1092926044
Directory	/workspace/43.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/43.lc_ctrl_prog_failure.1672679809
Short name	T631
Test name
Test status
Simulation time	541672806 ps
CPU time	2.77 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	222468 kb
Host	smart-322a08b2-2572-44f1-bd16-8b5033cdc6c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672679809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1672679809
Directory	/workspace/43.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_mubi.1235637517
Short name	T800
Test name
Test status
Simulation time	893696130 ps
CPU time	13.02 seconds
Started	Jul 29 05:37:36 PM PDT 24
Finished	Jul 29 05:37:49 PM PDT 24
Peak memory	226100 kb
Host	smart-ce277a98-670b-4cc4-9f0e-ab0be031cb3f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235637517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1235637517
Directory	/workspace/43.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_digest.777513081
Short name	T575
Test name
Test status
Simulation time	842049611 ps
CPU time	17.98 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:51 PM PDT 24
Peak memory	226104 kb
Host	smart-a0519945-0a99-4d94-a207-a662260e23a3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777513081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di gest.777513081
Directory	/workspace/43.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_mux.874742577
Short name	T26
Test name
Test status
Simulation time	595133287 ps
CPU time	9.59 seconds
Started	Jul 29 05:37:32 PM PDT 24
Finished	Jul 29 05:37:42 PM PDT 24
Peak memory	218208 kb
Host	smart-f769416e-5e0b-402c-85e2-ecd41003dd33
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874742577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.874742577
Directory	/workspace/43.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/43.lc_ctrl_security_escalation.921719288
Short name	T209
Test name
Test status
Simulation time	2384721088 ps
CPU time	12.06 seconds
Started	Jul 29 05:37:34 PM PDT 24
Finished	Jul 29 05:37:46 PM PDT 24
Peak memory	226248 kb
Host	smart-80042e91-0fb4-4185-a864-96d61e8f9cff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921719288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.921719288
Directory	/workspace/43.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/43.lc_ctrl_smoke.2687330242
Short name	T79
Test name
Test status
Simulation time	123165528 ps
CPU time	3.08 seconds
Started	Jul 29 05:37:38 PM PDT 24
Finished	Jul 29 05:37:41 PM PDT 24
Peak memory	214988 kb
Host	smart-46aaada7-949f-4209-a11d-be052ec0df93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687330242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2687330242
Directory	/workspace/43.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_failure.4004568838
Short name	T520
Test name
Test status
Simulation time	277477178 ps
CPU time	26.98 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:56 PM PDT 24
Peak memory	251012 kb
Host	smart-3e37e862-61e8-4841-b51c-a927372bccd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004568838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4004568838
Directory	/workspace/43.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_post_trans.1004911809
Short name	T234
Test name
Test status
Simulation time	79818558 ps
CPU time	6.48 seconds
Started	Jul 29 05:37:32 PM PDT 24
Finished	Jul 29 05:37:38 PM PDT 24
Peak memory	251164 kb
Host	smart-cfb4fb46-c7ac-42b3-b955-0afb2721add7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004911809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1004911809
Directory	/workspace/43.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all.3236529773
Short name	T263
Test name
Test status
Simulation time	605460432 ps
CPU time	20.17 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:38:01 PM PDT 24
Peak memory	250980 kb
Host	smart-cb495a5a-e404-4f6e-8dc5-4e3c5c22ebd9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236529773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.3236529773
Directory	/workspace/43.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2634049549
Short name	T476
Test name
Test status
Simulation time	144546632 ps
CPU time	0.8 seconds
Started	Jul 29 05:37:29 PM PDT 24
Finished	Jul 29 05:37:30 PM PDT 24
Peak memory	211992 kb
Host	smart-0bf0c3a6-7f42-42e1-9867-824354a4881c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634049549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c trl_volatile_unlock_smoke.2634049549
Directory	/workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_alert_test.3366599463
Short name	T175
Test name
Test status
Simulation time	22754239 ps
CPU time	0.96 seconds
Started	Jul 29 05:37:39 PM PDT 24
Finished	Jul 29 05:37:40 PM PDT 24
Peak memory	209020 kb
Host	smart-f11f7916-8dfd-4c59-ae98-d455f2404d0f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366599463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3366599463
Directory	/workspace/44.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.lc_ctrl_errors.535202673
Short name	T500
Test name
Test status
Simulation time	376829374 ps
CPU time	11.64 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:37:52 PM PDT 24
Peak memory	226160 kb
Host	smart-21f001b8-549d-4564-b8be-1131ba975029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535202673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.535202673
Directory	/workspace/44.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/44.lc_ctrl_jtag_access.2380061861
Short name	T739
Test name
Test status
Simulation time	929882416 ps
CPU time	10.66 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:43 PM PDT 24
Peak memory	217484 kb
Host	smart-a77f0198-aff7-4158-ad89-6e96be81b3f1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380061861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2380061861
Directory	/workspace/44.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/44.lc_ctrl_prog_failure.1257453120
Short name	T243
Test name
Test status
Simulation time	148245613 ps
CPU time	1.7 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:35 PM PDT 24
Peak memory	218328 kb
Host	smart-e8d9af04-4940-41ec-83c5-4f5a909706ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257453120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1257453120
Directory	/workspace/44.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_mubi.369755499
Short name	T605
Test name
Test status
Simulation time	367918841 ps
CPU time	11.78 seconds
Started	Jul 29 05:37:32 PM PDT 24
Finished	Jul 29 05:37:44 PM PDT 24
Peak memory	226192 kb
Host	smart-341ab157-5b09-4277-b93a-56bb2a5a0e50
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369755499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.369755499
Directory	/workspace/44.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_digest.2330578391
Short name	T426
Test name
Test status
Simulation time	3752148616 ps
CPU time	19.17 seconds
Started	Jul 29 05:37:36 PM PDT 24
Finished	Jul 29 05:37:55 PM PDT 24
Peak memory	226188 kb
Host	smart-18553363-0cc8-474a-87bb-f6b54c742dee
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330578391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d igest.2330578391
Directory	/workspace/44.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_mux.916936236
Short name	T801
Test name
Test status
Simulation time	1106800500 ps
CPU time	10.78 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:44 PM PDT 24
Peak memory	218320 kb
Host	smart-92bdca7b-8f74-4378-a279-84302017570d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916936236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.916936236
Directory	/workspace/44.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/44.lc_ctrl_security_escalation.3990156978
Short name	T512
Test name
Test status
Simulation time	1497354372 ps
CPU time	10.31 seconds
Started	Jul 29 05:37:33 PM PDT 24
Finished	Jul 29 05:37:43 PM PDT 24
Peak memory	226208 kb
Host	smart-d429e3be-d387-467d-846b-28e41f72da04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990156978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3990156978
Directory	/workspace/44.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/44.lc_ctrl_smoke.1134060573
Short name	T644
Test name
Test status
Simulation time	110741438 ps
CPU time	3.12 seconds
Started	Jul 29 05:37:34 PM PDT 24
Finished	Jul 29 05:37:37 PM PDT 24
Peak memory	223048 kb
Host	smart-d00f6d5d-aacb-4dd6-a4aa-6419aa5bf7a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1134060573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1134060573
Directory	/workspace/44.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_failure.1075480590
Short name	T256
Test name
Test status
Simulation time	2127851251 ps
CPU time	29.17 seconds
Started	Jul 29 05:37:32 PM PDT 24
Finished	Jul 29 05:38:02 PM PDT 24
Peak memory	250984 kb
Host	smart-ffd60493-f856-4597-a8e0-4f57af7d5708
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075480590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1075480590
Directory	/workspace/44.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_post_trans.2288415206
Short name	T768
Test name
Test status
Simulation time	130066743 ps
CPU time	6.42 seconds
Started	Jul 29 05:37:34 PM PDT 24
Finished	Jul 29 05:37:41 PM PDT 24
Peak memory	250544 kb
Host	smart-b9ebf103-f9e8-46d8-a9d4-cdd6f37d200c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288415206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2288415206
Directory	/workspace/44.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all.1464703442
Short name	T848
Test name
Test status
Simulation time	22160009403 ps
CPU time	128.81 seconds
Started	Jul 29 05:37:38 PM PDT 24
Finished	Jul 29 05:39:47 PM PDT 24
Peak memory	250892 kb
Host	smart-6ae7b2bd-3296-40df-99e3-3d509b752aaa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464703442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.1464703442
Directory	/workspace/44.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1304118593
Short name	T679
Test name
Test status
Simulation time	42438549 ps
CPU time	0.89 seconds
Started	Jul 29 05:37:34 PM PDT 24
Finished	Jul 29 05:37:35 PM PDT 24
Peak memory	212964 kb
Host	smart-8aaa088c-631a-40f4-9531-0e6cdf1075d4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304118593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c trl_volatile_unlock_smoke.1304118593
Directory	/workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_alert_test.1824236946
Short name	T169
Test name
Test status
Simulation time	20003340 ps
CPU time	0.84 seconds
Started	Jul 29 05:37:40 PM PDT 24
Finished	Jul 29 05:37:41 PM PDT 24
Peak memory	209180 kb
Host	smart-f9b066c7-2477-468c-b2e3-9c5e10d3f6c2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824236946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1824236946
Directory	/workspace/45.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.lc_ctrl_errors.336815237
Short name	T390
Test name
Test status
Simulation time	1397821288 ps
CPU time	14.67 seconds
Started	Jul 29 05:37:39 PM PDT 24
Finished	Jul 29 05:37:54 PM PDT 24
Peak memory	218300 kb
Host	smart-cb3f49f0-999c-4d2d-9a8d-ebd98cbda23c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336815237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.336815237
Directory	/workspace/45.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/45.lc_ctrl_jtag_access.1555994219
Short name	T459
Test name
Test status
Simulation time	3008673522 ps
CPU time	9.77 seconds
Started	Jul 29 05:37:39 PM PDT 24
Finished	Jul 29 05:37:49 PM PDT 24
Peak memory	217640 kb
Host	smart-df3cf655-f3e0-4b44-a408-3c282be90eb4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555994219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1555994219
Directory	/workspace/45.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/45.lc_ctrl_prog_failure.2831088510
Short name	T235
Test name
Test status
Simulation time	57604089 ps
CPU time	2.28 seconds
Started	Jul 29 05:37:36 PM PDT 24
Finished	Jul 29 05:37:38 PM PDT 24
Peak memory	222340 kb
Host	smart-cbe36dc1-be6b-4b20-bb79-adc96001745e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831088510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2831088510
Directory	/workspace/45.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_mubi.1748093867
Short name	T776
Test name
Test status
Simulation time	176822282 ps
CPU time	8.35 seconds
Started	Jul 29 05:37:36 PM PDT 24
Finished	Jul 29 05:37:44 PM PDT 24
Peak memory	218460 kb
Host	smart-de43ae66-7514-4161-b032-1ab553317a86
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748093867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1748093867
Directory	/workspace/45.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_digest.2228737574
Short name	T594
Test name
Test status
Simulation time	1078730329 ps
CPU time	14.01 seconds
Started	Jul 29 05:37:38 PM PDT 24
Finished	Jul 29 05:37:52 PM PDT 24
Peak memory	218304 kb
Host	smart-e3ab3b44-ab84-4980-8bf8-c7af05a84b37
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228737574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.2228737574
Directory	/workspace/45.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/45.lc_ctrl_security_escalation.4020430983
Short name	T165
Test name
Test status
Simulation time	559864595 ps
CPU time	11.6 seconds
Started	Jul 29 05:37:38 PM PDT 24
Finished	Jul 29 05:37:50 PM PDT 24
Peak memory	218424 kb
Host	smart-4b45cb9e-eeeb-4ad8-993e-2761999149ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020430983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.4020430983
Directory	/workspace/45.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/45.lc_ctrl_smoke.3570480334
Short name	T285
Test name
Test status
Simulation time	26625809 ps
CPU time	1.77 seconds
Started	Jul 29 05:37:39 PM PDT 24
Finished	Jul 29 05:37:40 PM PDT 24
Peak memory	217812 kb
Host	smart-8ad083d9-8852-4f60-8443-3180bbc45e44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570480334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3570480334
Directory	/workspace/45.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_failure.4007115968
Short name	T279
Test name
Test status
Simulation time	359616951 ps
CPU time	22.28 seconds
Started	Jul 29 05:37:39 PM PDT 24
Finished	Jul 29 05:38:02 PM PDT 24
Peak memory	250980 kb
Host	smart-4005e22f-21d8-4fdb-8674-d2646c86063d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007115968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4007115968
Directory	/workspace/45.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_post_trans.2249707153
Short name	T239
Test name
Test status
Simulation time	77681985 ps
CPU time	6.4 seconds
Started	Jul 29 05:37:37 PM PDT 24
Finished	Jul 29 05:37:43 PM PDT 24
Peak memory	250416 kb
Host	smart-307c6a2b-b904-4045-a433-cafd355f42c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249707153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2249707153
Directory	/workspace/45.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all.1055716068
Short name	T751
Test name
Test status
Simulation time	82208143245 ps
CPU time	358.87 seconds
Started	Jul 29 05:37:36 PM PDT 24
Finished	Jul 29 05:43:36 PM PDT 24
Peak memory	315884 kb
Host	smart-ac33c761-2450-4e98-b7b3-ed0191bae7b4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055716068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.1055716068
Directory	/workspace/45.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.218325422
Short name	T39
Test name
Test status
Simulation time	13645747 ps
CPU time	1.07 seconds
Started	Jul 29 05:37:38 PM PDT 24
Finished	Jul 29 05:37:39 PM PDT 24
Peak memory	213076 kb
Host	smart-addcf270-705d-461d-b183-e9a055698ba7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218325422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct rl_volatile_unlock_smoke.218325422
Directory	/workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_alert_test.324702304
Short name	T69
Test name
Test status
Simulation time	22095542 ps
CPU time	1.23 seconds
Started	Jul 29 05:37:42 PM PDT 24
Finished	Jul 29 05:37:43 PM PDT 24
Peak memory	209088 kb
Host	smart-cc62c27c-6433-43eb-8bce-fd343db45591
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324702304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.324702304
Directory	/workspace/46.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.lc_ctrl_errors.472737386
Short name	T666
Test name
Test status
Simulation time	946461947 ps
CPU time	10.64 seconds
Started	Jul 29 05:37:39 PM PDT 24
Finished	Jul 29 05:37:50 PM PDT 24
Peak memory	218288 kb
Host	smart-568f56b6-e73e-4022-b33b-a60e7cbd2a30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472737386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.472737386
Directory	/workspace/46.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/46.lc_ctrl_jtag_access.2294494906
Short name	T431
Test name
Test status
Simulation time	1639256154 ps
CPU time	11.64 seconds
Started	Jul 29 05:37:42 PM PDT 24
Finished	Jul 29 05:37:54 PM PDT 24
Peak memory	217192 kb
Host	smart-53e4e12b-370e-4fe2-8271-78e348b1c0f3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294494906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2294494906
Directory	/workspace/46.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/46.lc_ctrl_prog_failure.3678800443
Short name	T493
Test name
Test status
Simulation time	23477340 ps
CPU time	2.05 seconds
Started	Jul 29 05:37:37 PM PDT 24
Finished	Jul 29 05:37:40 PM PDT 24
Peak memory	222244 kb
Host	smart-c05e598f-ae50-4a4b-a63c-63016907b467
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678800443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3678800443
Directory	/workspace/46.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_mubi.3854062315
Short name	T217
Test name
Test status
Simulation time	1373109981 ps
CPU time	12.64 seconds
Started	Jul 29 05:37:44 PM PDT 24
Finished	Jul 29 05:37:57 PM PDT 24
Peak memory	226104 kb
Host	smart-22bcaccc-db9a-4cfd-be67-e5c1f3cfbed7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854062315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3854062315
Directory	/workspace/46.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_digest.4220484398
Short name	T558
Test name
Test status
Simulation time	1161567077 ps
CPU time	12.91 seconds
Started	Jul 29 05:37:42 PM PDT 24
Finished	Jul 29 05:37:55 PM PDT 24
Peak memory	218296 kb
Host	smart-6dd64245-3d3a-4794-ba58-e40d31eef35c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220484398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d igest.4220484398
Directory	/workspace/46.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_mux.2001352128
Short name	T402
Test name
Test status
Simulation time	706476605 ps
CPU time	7.91 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:37:49 PM PDT 24
Peak memory	218312 kb
Host	smart-e4abadc0-45e8-48b7-9dca-db45f57e75b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001352128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux. 2001352128
Directory	/workspace/46.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/46.lc_ctrl_security_escalation.1650336371
Short name	T326
Test name
Test status
Simulation time	267874169 ps
CPU time	7.83 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:37:49 PM PDT 24
Peak memory	226180 kb
Host	smart-54cba9f0-2f4c-4341-aca9-8d512ab79054
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650336371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1650336371
Directory	/workspace/46.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/46.lc_ctrl_smoke.4179137631
Short name	T720
Test name
Test status
Simulation time	18556439 ps
CPU time	1.44 seconds
Started	Jul 29 05:37:35 PM PDT 24
Finished	Jul 29 05:37:36 PM PDT 24
Peak memory	213776 kb
Host	smart-60b2af80-7402-423d-a82b-849c6b6d8102
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4179137631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4179137631
Directory	/workspace/46.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_failure.443664603
Short name	T319
Test name
Test status
Simulation time	607431255 ps
CPU time	16.9 seconds
Started	Jul 29 05:37:36 PM PDT 24
Finished	Jul 29 05:37:53 PM PDT 24
Peak memory	250984 kb
Host	smart-7fe64e64-3fd1-4810-bc30-9102c95d983d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443664603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.443664603
Directory	/workspace/46.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_post_trans.2840131352
Short name	T731
Test name
Test status
Simulation time	636006504 ps
CPU time	7.19 seconds
Started	Jul 29 05:37:37 PM PDT 24
Finished	Jul 29 05:37:45 PM PDT 24
Peak memory	246660 kb
Host	smart-6be5bc17-b852-4b6d-bf00-3a617578f384
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840131352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2840131352
Directory	/workspace/46.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all.3024866540
Short name	T80
Test name
Test status
Simulation time	10931664916 ps
CPU time	78.91 seconds
Started	Jul 29 05:37:43 PM PDT 24
Finished	Jul 29 05:39:02 PM PDT 24
Peak memory	246504 kb
Host	smart-243bc9e0-a8f3-4410-82e6-84ee8fdb4336
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024866540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.3024866540
Directory	/workspace/46.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2125620429
Short name	T694
Test name
Test status
Simulation time	19275291 ps
CPU time	0.95 seconds
Started	Jul 29 05:37:37 PM PDT 24
Finished	Jul 29 05:37:38 PM PDT 24
Peak memory	211988 kb
Host	smart-24084adb-bc85-4198-b846-4b46116c86f7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125620429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.2125620429
Directory	/workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_alert_test.2637669746
Short name	T237
Test name
Test status
Simulation time	92917953 ps
CPU time	0.97 seconds
Started	Jul 29 05:37:45 PM PDT 24
Finished	Jul 29 05:37:46 PM PDT 24
Peak memory	208936 kb
Host	smart-86979547-7be3-4dbc-a4cc-c69177eb3352
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637669746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2637669746
Directory	/workspace/47.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.lc_ctrl_errors.824723652
Short name	T725
Test name
Test status
Simulation time	878227582 ps
CPU time	10.54 seconds
Started	Jul 29 05:37:43 PM PDT 24
Finished	Jul 29 05:37:54 PM PDT 24
Peak memory	218392 kb
Host	smart-de94e063-9b9a-4ab0-9885-815317f37f6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824723652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.824723652
Directory	/workspace/47.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/47.lc_ctrl_jtag_access.784017685
Short name	T181
Test name
Test status
Simulation time	1681565852 ps
CPU time	5.31 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:37:46 PM PDT 24
Peak memory	217280 kb
Host	smart-f598fe32-773e-4967-b895-71da60b2d14a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784017685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.784017685
Directory	/workspace/47.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/47.lc_ctrl_prog_failure.770595411
Short name	T732
Test name
Test status
Simulation time	400668359 ps
CPU time	3.78 seconds
Started	Jul 29 05:37:44 PM PDT 24
Finished	Jul 29 05:37:48 PM PDT 24
Peak memory	218336 kb
Host	smart-0abb4c5e-82e8-4972-bef4-9e070ed44f16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=770595411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.770595411
Directory	/workspace/47.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_mubi.1548819831
Short name	T705
Test name
Test status
Simulation time	562265824 ps
CPU time	10.54 seconds
Started	Jul 29 05:37:46 PM PDT 24
Finished	Jul 29 05:37:56 PM PDT 24
Peak memory	219012 kb
Host	smart-7e2f272d-e081-4fd8-9c87-67b0f6817aa5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548819831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1548819831
Directory	/workspace/47.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_digest.3866781501
Short name	T345
Test name
Test status
Simulation time	855586158 ps
CPU time	12.47 seconds
Started	Jul 29 05:37:45 PM PDT 24
Finished	Jul 29 05:37:57 PM PDT 24
Peak memory	226116 kb
Host	smart-98a293f6-0ace-4995-8a26-732e27c4c7ff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866781501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d igest.3866781501
Directory	/workspace/47.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_mux.2433184169
Short name	T24
Test name
Test status
Simulation time	270148422 ps
CPU time	9.84 seconds
Started	Jul 29 05:37:46 PM PDT 24
Finished	Jul 29 05:37:56 PM PDT 24
Peak memory	218308 kb
Host	smart-c5104a6c-9f4d-4a27-8c16-6f6dbac60a4b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433184169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux. 2433184169
Directory	/workspace/47.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_security_escalation.2068332438
Short name	T762
Test name
Test status
Simulation time	561050359 ps
CPU time	9.05 seconds
Started	Jul 29 05:37:43 PM PDT 24
Finished	Jul 29 05:37:52 PM PDT 24
Peak memory	218344 kb
Host	smart-14c1a436-8be8-463c-aa27-2220d7277634
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068332438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2068332438
Directory	/workspace/47.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/47.lc_ctrl_smoke.729914548
Short name	T703
Test name
Test status
Simulation time	113742445 ps
CPU time	2.62 seconds
Started	Jul 29 05:37:44 PM PDT 24
Finished	Jul 29 05:37:47 PM PDT 24
Peak memory	214412 kb
Host	smart-0df3cf9f-fc23-4a82-ad42-818df584cf51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729914548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.729914548
Directory	/workspace/47.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_failure.1403206785
Short name	T95
Test name
Test status
Simulation time	876440767 ps
CPU time	23.55 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:38:05 PM PDT 24
Peak memory	250816 kb
Host	smart-9ac3e8aa-f928-4fea-86dd-c944ac854690
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403206785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1403206785
Directory	/workspace/47.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_post_trans.993703581
Short name	T265
Test name
Test status
Simulation time	115962396 ps
CPU time	8.27 seconds
Started	Jul 29 05:37:42 PM PDT 24
Finished	Jul 29 05:37:51 PM PDT 24
Peak memory	250928 kb
Host	smart-63c47901-82ff-47cd-a4d0-6705a0ce7271
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993703581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.993703581
Directory	/workspace/47.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all.3854867697
Short name	T528
Test name
Test status
Simulation time	11983263402 ps
CPU time	223.09 seconds
Started	Jul 29 05:37:47 PM PDT 24
Finished	Jul 29 05:41:31 PM PDT 24
Peak memory	269988 kb
Host	smart-c1069384-1db4-4acd-817a-e75a471ca7fd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854867697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.3854867697
Directory	/workspace/47.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1594238115
Short name	T569
Test name
Test status
Simulation time	41219462 ps
CPU time	0.92 seconds
Started	Jul 29 05:37:41 PM PDT 24
Finished	Jul 29 05:37:42 PM PDT 24
Peak memory	212012 kb
Host	smart-f31d9dd8-d1d0-4ffb-a3e0-df8ce4e6b397
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594238115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c trl_volatile_unlock_smoke.1594238115
Directory	/workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_alert_test.3092353633
Short name	T393
Test name
Test status
Simulation time	34519045 ps
CPU time	1.18 seconds
Started	Jul 29 05:37:46 PM PDT 24
Finished	Jul 29 05:37:47 PM PDT 24
Peak memory	209012 kb
Host	smart-ee7e9f52-b3b0-434a-b4ca-d7e416a8766c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092353633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3092353633
Directory	/workspace/48.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.lc_ctrl_errors.4175179564
Short name	T170
Test name
Test status
Simulation time	1007060638 ps
CPU time	19.79 seconds
Started	Jul 29 05:37:50 PM PDT 24
Finished	Jul 29 05:38:10 PM PDT 24
Peak memory	218460 kb
Host	smart-49d1bd1f-727c-4dd9-9932-f2c3e47aa607
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175179564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.4175179564
Directory	/workspace/48.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/48.lc_ctrl_jtag_access.505170352
Short name	T373
Test name
Test status
Simulation time	522505187 ps
CPU time	3.36 seconds
Started	Jul 29 05:37:48 PM PDT 24
Finished	Jul 29 05:37:51 PM PDT 24
Peak memory	217168 kb
Host	smart-60541a4b-5475-468b-856a-3201d7f9f8a9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505170352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.505170352
Directory	/workspace/48.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/48.lc_ctrl_prog_failure.2490416219
Short name	T541
Test name
Test status
Simulation time	90953791 ps
CPU time	3.17 seconds
Started	Jul 29 05:37:50 PM PDT 24
Finished	Jul 29 05:37:53 PM PDT 24
Peak memory	218304 kb
Host	smart-0e025a62-f15f-4dd4-9fd2-820741178980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490416219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2490416219
Directory	/workspace/48.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_mubi.3847409360
Short name	T160
Test name
Test status
Simulation time	191826742 ps
CPU time	8.4 seconds
Started	Jul 29 05:37:47 PM PDT 24
Finished	Jul 29 05:37:55 PM PDT 24
Peak memory	226144 kb
Host	smart-473b2d95-ca78-4c02-a67a-eb87d859c4fe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847409360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3847409360
Directory	/workspace/48.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_digest.1260958556
Short name	T792
Test name
Test status
Simulation time	1079024546 ps
CPU time	10.18 seconds
Started	Jul 29 05:37:46 PM PDT 24
Finished	Jul 29 05:37:57 PM PDT 24
Peak memory	218392 kb
Host	smart-420f0add-2aac-4bb1-ae5b-96fc3bb73884
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260958556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.1260958556
Directory	/workspace/48.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_mux.2256468887
Short name	T865
Test name
Test status
Simulation time	1374684671 ps
CPU time	9.07 seconds
Started	Jul 29 05:37:47 PM PDT 24
Finished	Jul 29 05:37:56 PM PDT 24
Peak memory	226128 kb
Host	smart-1a155714-ef53-4afd-97d5-f35bb74e0a63
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256468887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 2256468887
Directory	/workspace/48.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/48.lc_ctrl_security_escalation.2022797977
Short name	T418
Test name
Test status
Simulation time	323769628 ps
CPU time	10.5 seconds
Started	Jul 29 05:37:46 PM PDT 24
Finished	Jul 29 05:37:56 PM PDT 24
Peak memory	225372 kb
Host	smart-fe627fb9-3c80-4692-9d7a-cdccd2057217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022797977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2022797977
Directory	/workspace/48.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/48.lc_ctrl_smoke.4127812617
Short name	T320
Test name
Test status
Simulation time	55738802 ps
CPU time	3.06 seconds
Started	Jul 29 05:37:46 PM PDT 24
Finished	Jul 29 05:37:49 PM PDT 24
Peak memory	217736 kb
Host	smart-fc93e563-fb30-493f-b6e5-6654699bdebb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127812617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4127812617
Directory	/workspace/48.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_failure.850539471
Short name	T821
Test name
Test status
Simulation time	214635973 ps
CPU time	26.92 seconds
Started	Jul 29 05:37:48 PM PDT 24
Finished	Jul 29 05:38:15 PM PDT 24
Peak memory	251020 kb
Host	smart-a272c943-a81f-4cff-a327-3bd03f1bacf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850539471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.850539471
Directory	/workspace/48.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_post_trans.2842778136
Short name	T423
Test name
Test status
Simulation time	300234463 ps
CPU time	8.3 seconds
Started	Jul 29 05:37:49 PM PDT 24
Finished	Jul 29 05:37:57 PM PDT 24
Peak memory	251004 kb
Host	smart-56520114-65ce-4c25-99e8-2ff45419f29f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842778136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2842778136
Directory	/workspace/48.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all.2730330965
Short name	T651
Test name
Test status
Simulation time	15988220172 ps
CPU time	87.71 seconds
Started	Jul 29 05:37:50 PM PDT 24
Finished	Jul 29 05:39:18 PM PDT 24
Peak memory	273116 kb
Host	smart-45e447f9-f320-454d-b107-9a13b8665ea5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730330965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.2730330965
Directory	/workspace/48.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2867278940
Short name	T168
Test name
Test status
Simulation time	30139392495 ps
CPU time	1083.32 seconds
Started	Jul 29 05:37:48 PM PDT 24
Finished	Jul 29 05:55:52 PM PDT 24
Peak memory	496932 kb
Host	smart-14200416-10b0-4e28-a096-45507d7a3762
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2867278940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2867278940
Directory	/workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.302704376
Short name	T634
Test name
Test status
Simulation time	12578460 ps
CPU time	1.04 seconds
Started	Jul 29 05:37:46 PM PDT 24
Finished	Jul 29 05:37:48 PM PDT 24
Peak memory	212004 kb
Host	smart-19172afb-f078-4d75-ad11-e0b31791776c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302704376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct rl_volatile_unlock_smoke.302704376
Directory	/workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_alert_test.54703525
Short name	T72
Test name
Test status
Simulation time	18427035 ps
CPU time	0.93 seconds
Started	Jul 29 05:37:51 PM PDT 24
Finished	Jul 29 05:37:52 PM PDT 24
Peak memory	208960 kb
Host	smart-6a9416b4-f9dc-4c1f-9375-50bc1a2c2c5f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54703525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.54703525
Directory	/workspace/49.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.lc_ctrl_errors.4155587851
Short name	T805
Test name
Test status
Simulation time	1149767355 ps
CPU time	13.18 seconds
Started	Jul 29 05:37:47 PM PDT 24
Finished	Jul 29 05:38:00 PM PDT 24
Peak memory	226040 kb
Host	smart-6df925c9-05d1-4c91-a5ca-52ef328d2819
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155587851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4155587851
Directory	/workspace/49.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/49.lc_ctrl_jtag_access.3938743218
Short name	T718
Test name
Test status
Simulation time	167342125 ps
CPU time	5.35 seconds
Started	Jul 29 05:37:49 PM PDT 24
Finished	Jul 29 05:37:54 PM PDT 24
Peak memory	217344 kb
Host	smart-4f262080-d901-4fa5-9278-106f06552929
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938743218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3938743218
Directory	/workspace/49.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/49.lc_ctrl_prog_failure.2827746403
Short name	T652
Test name
Test status
Simulation time	158480784 ps
CPU time	2.61 seconds
Started	Jul 29 05:37:48 PM PDT 24
Finished	Jul 29 05:37:51 PM PDT 24
Peak memory	218356 kb
Host	smart-981d5e66-301b-40b8-a8fa-4bcd805b87e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827746403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2827746403
Directory	/workspace/49.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_mubi.1114743767
Short name	T481
Test name
Test status
Simulation time	294326299 ps
CPU time	9.82 seconds
Started	Jul 29 05:37:47 PM PDT 24
Finished	Jul 29 05:37:57 PM PDT 24
Peak memory	226072 kb
Host	smart-bb78e19c-5a66-420d-8098-98c53574bc10
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114743767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1114743767
Directory	/workspace/49.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_digest.2089309262
Short name	T276
Test name
Test status
Simulation time	1301084626 ps
CPU time	9.41 seconds
Started	Jul 29 05:37:51 PM PDT 24
Finished	Jul 29 05:38:01 PM PDT 24
Peak memory	226132 kb
Host	smart-ff5bbacc-16c1-45c6-95ed-f068d9a46708
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089309262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.2089309262
Directory	/workspace/49.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_mux.1835584992
Short name	T494
Test name
Test status
Simulation time	1611678399 ps
CPU time	9.13 seconds
Started	Jul 29 05:37:52 PM PDT 24
Finished	Jul 29 05:38:02 PM PDT 24
Peak memory	218316 kb
Host	smart-8eaac87c-d385-47f5-b15a-51bd94fdc6f0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835584992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux. 1835584992
Directory	/workspace/49.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/49.lc_ctrl_security_escalation.4207259430
Short name	T473
Test name
Test status
Simulation time	1872689989 ps
CPU time	13.65 seconds
Started	Jul 29 05:37:50 PM PDT 24
Finished	Jul 29 05:38:04 PM PDT 24
Peak memory	225424 kb
Host	smart-b173a2c6-7f34-413c-b1be-7f8f9c3bd42b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4207259430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4207259430
Directory	/workspace/49.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_smoke.53657017
Short name	T397
Test name
Test status
Simulation time	297900265 ps
CPU time	2.74 seconds
Started	Jul 29 05:37:45 PM PDT 24
Finished	Jul 29 05:37:48 PM PDT 24
Peak memory	217812 kb
Host	smart-e3e954da-c5d3-4fbe-8966-e31e1b90a005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=53657017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.53657017
Directory	/workspace/49.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_failure.780428889
Short name	T524
Test name
Test status
Simulation time	583316772 ps
CPU time	20.97 seconds
Started	Jul 29 05:37:48 PM PDT 24
Finished	Jul 29 05:38:10 PM PDT 24
Peak memory	251032 kb
Host	smart-85b54efc-9848-4906-8fd0-32c211b7e195
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780428889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.780428889
Directory	/workspace/49.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_post_trans.4094501198
Short name	T38
Test name
Test status
Simulation time	245432273 ps
CPU time	7.57 seconds
Started	Jul 29 05:37:48 PM PDT 24
Finished	Jul 29 05:37:56 PM PDT 24
Peak memory	251008 kb
Host	smart-4543436b-3e7d-46e1-a1d2-30beb32c5ce2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094501198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.4094501198
Directory	/workspace/49.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all.467021580
Short name	T628
Test name
Test status
Simulation time	36550070594 ps
CPU time	187.21 seconds
Started	Jul 29 05:37:50 PM PDT 24
Finished	Jul 29 05:40:57 PM PDT 24
Peak memory	283788 kb
Host	smart-db4f9770-4979-4da6-8705-5bf114b1cdbc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467021580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.467021580
Directory	/workspace/49.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_alert_test.1309382536
Short name	T685
Test name
Test status
Simulation time	20315224 ps
CPU time	0.98 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:35:35 PM PDT 24
Peak memory	208984 kb
Host	smart-a9425883-621e-48b7-a213-ba55f93333d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309382536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1309382536
Directory	/workspace/5.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.lc_ctrl_errors.3698143556
Short name	T607
Test name
Test status
Simulation time	404564695 ps
CPU time	13.84 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:49 PM PDT 24
Peak memory	226184 kb
Host	smart-2aad91b5-8edd-475d-b7c7-d3d86d1f9b93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698143556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3698143556
Directory	/workspace/5.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_access.152081154
Short name	T824
Test name
Test status
Simulation time	492333279 ps
CPU time	5.42 seconds
Started	Jul 29 05:35:33 PM PDT 24
Finished	Jul 29 05:35:38 PM PDT 24
Peak memory	217420 kb
Host	smart-26720cc6-aa82-4609-9688-6aa2eeaf0f8a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152081154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.152081154
Directory	/workspace/5.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_errors.246502365
Short name	T622
Test name
Test status
Simulation time	7804428135 ps
CPU time	104.72 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:37:21 PM PDT 24
Peak memory	218828 kb
Host	smart-7fa3cfa1-4223-4204-9280-746dc0a5a22f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246502365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err ors.246502365
Directory	/workspace/5.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_priority.428823524
Short name	T382
Test name
Test status
Simulation time	782644543 ps
CPU time	18.82 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	217848 kb
Host	smart-57ddd9ef-34ac-4196-872c-7e640aecb03e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428823524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.428823524
Directory	/workspace/5.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.101909701
Short name	T794
Test name
Test status
Simulation time	319240920 ps
CPU time	6.13 seconds
Started	Jul 29 05:35:32 PM PDT 24
Finished	Jul 29 05:35:38 PM PDT 24
Peak memory	223144 kb
Host	smart-c05041d1-9818-4c87-a147-aef9a20d0329
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101909701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ prog_failure.101909701
Directory	/workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3682832353
Short name	T251
Test name
Test status
Simulation time	2059856124 ps
CPU time	32.18 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:36:07 PM PDT 24
Peak memory	217668 kb
Host	smart-f1075243-33c7-4187-932e-f9aad51a45e9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682832353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_regwen_during_op.3682832353
Directory	/workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_smoke.1155194515
Short name	T818
Test name
Test status
Simulation time	263137868 ps
CPU time	3.25 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:39 PM PDT 24
Peak memory	217636 kb
Host	smart-fdd7dd7c-3477-4d9e-9604-88ae232440ba
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155194515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke. 1155194515
Directory	/workspace/5.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_failure.361182138
Short name	T754
Test name
Test status
Simulation time	7853794079 ps
CPU time	43.73 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:36:22 PM PDT 24
Peak memory	251412 kb
Host	smart-e313fa5f-0332-4985-b961-bb39d49cd873
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361182138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag _state_failure.361182138
Directory	/workspace/5.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2588594981
Short name	T30
Test name
Test status
Simulation time	1797460703 ps
CPU time	16.05 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:52 PM PDT 24
Peak memory	248704 kb
Host	smart-0c7a4733-699b-4e18-a4a2-fe7f6f75d55d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588594981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_state_post_trans.2588594981
Directory	/workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_prog_failure.806512799
Short name	T491
Test name
Test status
Simulation time	25204208 ps
CPU time	1.8 seconds
Started	Jul 29 05:35:33 PM PDT 24
Finished	Jul 29 05:35:35 PM PDT 24
Peak memory	218280 kb
Host	smart-5fca35c9-6f9e-48d0-9e65-b61499901859
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806512799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.806512799
Directory	/workspace/5.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_regwen_during_op.1715740822
Short name	T780
Test name
Test status
Simulation time	579097568 ps
CPU time	7.63 seconds
Started	Jul 29 05:35:32 PM PDT 24
Finished	Jul 29 05:35:40 PM PDT 24
Peak memory	214792 kb
Host	smart-2272fb70-cbfb-41ad-9a96-93ed26f6ba13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715740822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1715740822
Directory	/workspace/5.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_mubi.1870922985
Short name	T215
Test name
Test status
Simulation time	791383495 ps
CPU time	15.82 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	226168 kb
Host	smart-ea22c797-32b2-49a3-b696-ef5acd29d75e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870922985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1870922985
Directory	/workspace/5.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_digest.2399918025
Short name	T610
Test name
Test status
Simulation time	257856971 ps
CPU time	11.07 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:35:45 PM PDT 24
Peak memory	218324 kb
Host	smart-8d13186f-172e-494a-81a5-0d44ec4bfe5c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399918025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di gest.2399918025
Directory	/workspace/5.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_mux.1991070995
Short name	T819
Test name
Test status
Simulation time	299886838 ps
CPU time	9.23 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:46 PM PDT 24
Peak memory	218240 kb
Host	smart-b459a871-2248-42cd-aafa-d21f6c79b646
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991070995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1 991070995
Directory	/workspace/5.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/5.lc_ctrl_security_escalation.3992570716
Short name	T205
Test name
Test status
Simulation time	358483834 ps
CPU time	10.08 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:46 PM PDT 24
Peak memory	218428 kb
Host	smart-ae81ab47-1e49-4665-9cae-f70ddf347ad1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992570716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3992570716
Directory	/workspace/5.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/5.lc_ctrl_smoke.1612823634
Short name	T249
Test name
Test status
Simulation time	200087694 ps
CPU time	2.22 seconds
Started	Jul 29 05:35:24 PM PDT 24
Finished	Jul 29 05:35:26 PM PDT 24
Peak memory	223588 kb
Host	smart-64a00760-a72b-4167-8fe6-13c4570ed3cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612823634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1612823634
Directory	/workspace/5.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_failure.786790860
Short name	T227
Test name
Test status
Simulation time	222232895 ps
CPU time	22.53 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:57 PM PDT 24
Peak memory	250984 kb
Host	smart-6e68cc3c-bfa4-4efc-94ca-67c50fd6c0a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786790860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.786790860
Directory	/workspace/5.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_post_trans.108135662
Short name	T146
Test name
Test status
Simulation time	271981713 ps
CPU time	7.01 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:42 PM PDT 24
Peak memory	247092 kb
Host	smart-112da3ba-3a7b-476a-9f92-5c4a41df83b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108135662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.108135662
Directory	/workspace/5.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all.480356638
Short name	T166
Test name
Test status
Simulation time	78685799195 ps
CPU time	209 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:39:04 PM PDT 24
Peak memory	251020 kb
Host	smart-b612c387-7d2d-4357-9a21-1676a6c134cd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480356638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.480356638
Directory	/workspace/5.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.840575131
Short name	T441
Test name
Test status
Simulation time	12396695 ps
CPU time	1.01 seconds
Started	Jul 29 05:35:22 PM PDT 24
Finished	Jul 29 05:35:23 PM PDT 24
Peak memory	212096 kb
Host	smart-f53841b3-9fd4-41f9-b53b-ef75c5e0cb40
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840575131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr l_volatile_unlock_smoke.840575131
Directory	/workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_alert_test.4011780016
Short name	T671
Test name
Test status
Simulation time	42867494 ps
CPU time	0.86 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:36 PM PDT 24
Peak memory	208860 kb
Host	smart-dec227de-5d09-4744-b8c8-56484d85111d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011780016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4011780016
Directory	/workspace/6.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.lc_ctrl_claim_transition_if.445136022
Short name	T198
Test name
Test status
Simulation time	23334680 ps
CPU time	0.96 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:36 PM PDT 24
Peak memory	208888 kb
Host	smart-7a2e77e5-d6e2-48fe-9454-beba500310d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445136022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.445136022
Directory	/workspace/6.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_errors.155784404
Short name	T361
Test name
Test status
Simulation time	1952685889 ps
CPU time	13.85 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:49 PM PDT 24
Peak memory	226096 kb
Host	smart-4b0fc7b1-7306-4413-915a-faa6e76cf9a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155784404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.155784404
Directory	/workspace/6.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_access.997971102
Short name	T195
Test name
Test status
Simulation time	67153310 ps
CPU time	1.72 seconds
Started	Jul 29 05:35:42 PM PDT 24
Finished	Jul 29 05:35:44 PM PDT 24
Peak memory	217332 kb
Host	smart-9be124f1-fecd-4c73-b1c1-f5d9c0fada37
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997971102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.997971102
Directory	/workspace/6.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_errors.2823331162
Short name	T369
Test name
Test status
Simulation time	3832288320 ps
CPU time	53.02 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:36:31 PM PDT 24
Peak memory	218924 kb
Host	smart-1d52fc1b-7ae7-400e-8fd7-e62d0a184edf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823331162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er rors.2823331162
Directory	/workspace/6.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_priority.4201554055
Short name	T259
Test name
Test status
Simulation time	844106558 ps
CPU time	10.52 seconds
Started	Jul 29 05:35:37 PM PDT 24
Finished	Jul 29 05:35:48 PM PDT 24
Peak memory	217828 kb
Host	smart-48caf961-ff4e-439c-b8ab-3204b6b47239
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201554055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4 201554055
Directory	/workspace/6.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.553823548
Short name	T470
Test name
Test status
Simulation time	546228470 ps
CPU time	8.34 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:35:47 PM PDT 24
Peak memory	218212 kb
Host	smart-1c7765ec-e9c0-41d4-88be-00cf78f5aaa1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553823548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ prog_failure.553823548
Directory	/workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2366289667
Short name	T822
Test name
Test status
Simulation time	5254115805 ps
CPU time	20.55 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:57 PM PDT 24
Peak memory	217956 kb
Host	smart-7af892d7-aeab-4e5d-bf02-b916abadb09e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366289667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_regwen_during_op.2366289667
Directory	/workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_smoke.3487107055
Short name	T760
Test name
Test status
Simulation time	319228167 ps
CPU time	1.86 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:38 PM PDT 24
Peak memory	217732 kb
Host	smart-3fb4d582-5a06-4a61-85e5-57124303d8c0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487107055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 3487107055
Directory	/workspace/6.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3824619598
Short name	T767
Test name
Test status
Simulation time	7017153836 ps
CPU time	46.76 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:36:21 PM PDT 24
Peak memory	283776 kb
Host	smart-4b3f3872-06eb-45f2-8557-b8827cc80f9f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824619598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta g_state_failure.3824619598
Directory	/workspace/6.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2524580564
Short name	T523
Test name
Test status
Simulation time	288010584 ps
CPU time	15.5 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:51 PM PDT 24
Peak memory	250944 kb
Host	smart-c8a92c19-b3e8-4a07-b3a0-bf8441bfb789
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524580564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.2524580564
Directory	/workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_prog_failure.1501092616
Short name	T328
Test name
Test status
Simulation time	58102120 ps
CPU time	3.07 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:35:37 PM PDT 24
Peak memory	218384 kb
Host	smart-e50cac71-ebde-4bbe-8fcb-d3cf6818003c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501092616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1501092616
Directory	/workspace/6.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_regwen_during_op.2267516447
Short name	T866
Test name
Test status
Simulation time	274297749 ps
CPU time	9 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:45 PM PDT 24
Peak memory	214756 kb
Host	smart-5430f4e4-c604-49bf-b9d6-81ac666f58bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267516447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2267516447
Directory	/workspace/6.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_mubi.4288311093
Short name	T432
Test name
Test status
Simulation time	265609291 ps
CPU time	7.78 seconds
Started	Jul 29 05:35:37 PM PDT 24
Finished	Jul 29 05:35:45 PM PDT 24
Peak memory	218944 kb
Host	smart-6542655e-de7e-4024-b651-cf7a39e6212d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288311093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4288311093
Directory	/workspace/6.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_digest.4160998302
Short name	T657
Test name
Test status
Simulation time	1550631855 ps
CPU time	11.26 seconds
Started	Jul 29 05:35:39 PM PDT 24
Finished	Jul 29 05:35:50 PM PDT 24
Peak memory	218208 kb
Host	smart-1afd096c-a0f6-4170-9272-14df8ae30fde
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160998302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di gest.4160998302
Directory	/workspace/6.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_mux.4256020456
Short name	T871
Test name
Test status
Simulation time	1741235290 ps
CPU time	11.26 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:48 PM PDT 24
Peak memory	226272 kb
Host	smart-99cb799c-711f-45a8-8c7b-95d72c151f8c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256020456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4 256020456
Directory	/workspace/6.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/6.lc_ctrl_security_escalation.3948626004
Short name	T825
Test name
Test status
Simulation time	349330001 ps
CPU time	6.28 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:42 PM PDT 24
Peak memory	225020 kb
Host	smart-b8f26531-bb8c-4a18-af75-f14546ae59bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948626004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3948626004
Directory	/workspace/6.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_smoke.3287742011
Short name	T71
Test name
Test status
Simulation time	139620046 ps
CPU time	2.31 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:35:36 PM PDT 24
Peak memory	217796 kb
Host	smart-6e8245c8-04b5-4da2-81ea-cc6858598eac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287742011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3287742011
Directory	/workspace/6.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_failure.1840894094
Short name	T655
Test name
Test status
Simulation time	261988950 ps
CPU time	36.57 seconds
Started	Jul 29 05:35:37 PM PDT 24
Finished	Jul 29 05:36:13 PM PDT 24
Peak memory	251008 kb
Host	smart-598ee835-7529-4c95-959f-e20e8e7acb21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840894094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1840894094
Directory	/workspace/6.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_post_trans.4190398869
Short name	T288
Test name
Test status
Simulation time	148843545 ps
CPU time	3.12 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:35:38 PM PDT 24
Peak memory	222172 kb
Host	smart-418b539f-b5ba-4f6b-8071-5a3afbbe597a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190398869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.4190398869
Directory	/workspace/6.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all.3684926035
Short name	T696
Test name
Test status
Simulation time	16169978220 ps
CPU time	471.02 seconds
Started	Jul 29 05:35:37 PM PDT 24
Finished	Jul 29 05:43:28 PM PDT 24
Peak memory	283832 kb
Host	smart-61ebc6df-5e63-4156-93be-1081bf469e7e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684926035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.3684926035
Directory	/workspace/6.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2142986388
Short name	T567
Test name
Test status
Simulation time	11434944 ps
CPU time	1.03 seconds
Started	Jul 29 05:35:42 PM PDT 24
Finished	Jul 29 05:35:43 PM PDT 24
Peak memory	212108 kb
Host	smart-a8fb9794-09f3-40db-9ffa-68717b3c8e93
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142986388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_volatile_unlock_smoke.2142986388
Directory	/workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_alert_test.1349525665
Short name	T445
Test name
Test status
Simulation time	18078190 ps
CPU time	1.12 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:35:47 PM PDT 24
Peak memory	209072 kb
Host	smart-eebc125c-f608-4b2f-8ef7-29e8a1200ef0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349525665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1349525665
Directory	/workspace/7.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.lc_ctrl_claim_transition_if.2909361817
Short name	T386
Test name
Test status
Simulation time	12610050 ps
CPU time	0.99 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:35:35 PM PDT 24
Peak memory	208816 kb
Host	smart-45b498f4-1f6e-47b6-ae35-79c7a939b950
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909361817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2909361817
Directory	/workspace/7.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/7.lc_ctrl_errors.2867539173
Short name	T677
Test name
Test status
Simulation time	2045299040 ps
CPU time	15.67 seconds
Started	Jul 29 05:35:41 PM PDT 24
Finished	Jul 29 05:35:57 PM PDT 24
Peak memory	226348 kb
Host	smart-81a0d9d2-b27a-444e-b454-18723bc929f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867539173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2867539173
Directory	/workspace/7.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_access.3847634554
Short name	T574
Test name
Test status
Simulation time	2969085177 ps
CPU time	17.78 seconds
Started	Jul 29 05:35:43 PM PDT 24
Finished	Jul 29 05:36:01 PM PDT 24
Peak memory	217820 kb
Host	smart-5d51acf8-2a87-4145-ae03-0a19aaa9d6cf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847634554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3847634554
Directory	/workspace/7.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_errors.796028948
Short name	T305
Test name
Test status
Simulation time	5317726757 ps
CPU time	44.31 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:36:21 PM PDT 24
Peak memory	219028 kb
Host	smart-63bc9c98-3101-4aa8-b5ca-504cde7f321a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796028948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err ors.796028948
Directory	/workspace/7.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_priority.1599138323
Short name	T692
Test name
Test status
Simulation time	306373360 ps
CPU time	1.85 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:35:47 PM PDT 24
Peak memory	217496 kb
Host	smart-e2aa0fce-a940-44ec-97c3-ac513c582e51
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599138323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1 599138323
Directory	/workspace/7.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.630712142
Short name	T823
Test name
Test status
Simulation time	593516219 ps
CPU time	6.05 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:41 PM PDT 24
Peak memory	222968 kb
Host	smart-8980800c-6caf-48cf-a342-d84f37f5c165
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630712142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ prog_failure.630712142
Directory	/workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2107011256
Short name	T323
Test name
Test status
Simulation time	1153009038 ps
CPU time	17.67 seconds
Started	Jul 29 05:35:40 PM PDT 24
Finished	Jul 29 05:35:58 PM PDT 24
Peak memory	217728 kb
Host	smart-1b1df8d7-550f-4f2f-b3c1-ea3fd2ca63d3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107011256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_regwen_during_op.2107011256
Directory	/workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_smoke.2588258253
Short name	T755
Test name
Test status
Simulation time	2126349237 ps
CPU time	14.48 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:50 PM PDT 24
Peak memory	217744 kb
Host	smart-92a60805-f636-4d00-98de-ce908fcc7ef4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588258253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 2588258253
Directory	/workspace/7.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1157158223
Short name	T342
Test name
Test status
Simulation time	3548522299 ps
CPU time	105.66 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:37:20 PM PDT 24
Peak memory	270444 kb
Host	smart-fef4ec3f-6718-4091-b5e6-d7e129136879
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157158223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta g_state_failure.1157158223
Directory	/workspace/7.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2907855712
Short name	T772
Test name
Test status
Simulation time	3689195365 ps
CPU time	17.42 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	251132 kb
Host	smart-d872c15e-7c71-4f77-a75e-b0c9cbda0dad
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907855712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_state_post_trans.2907855712
Directory	/workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_prog_failure.3252651600
Short name	T472
Test name
Test status
Simulation time	133772838 ps
CPU time	3.31 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:35:41 PM PDT 24
Peak memory	218260 kb
Host	smart-8f2ef94f-68a9-4402-a18a-658a6dc0ad7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252651600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3252651600
Directory	/workspace/7.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_regwen_during_op.2999261032
Short name	T577
Test name
Test status
Simulation time	263123492 ps
CPU time	17.27 seconds
Started	Jul 29 05:35:36 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	214204 kb
Host	smart-c8432a63-b3c9-4869-bec4-71b3db8caf3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2999261032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2999261032
Directory	/workspace/7.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_mubi.3990860600
Short name	T63
Test name
Test status
Simulation time	341481095 ps
CPU time	13.8 seconds
Started	Jul 29 05:35:40 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	218376 kb
Host	smart-0a5723fb-c18c-4df0-b320-ad88c32612db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990860600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3990860600
Directory	/workspace/7.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_digest.3839983764
Short name	T391
Test name
Test status
Simulation time	191667725 ps
CPU time	7.4 seconds
Started	Jul 29 05:35:40 PM PDT 24
Finished	Jul 29 05:35:48 PM PDT 24
Peak memory	218328 kb
Host	smart-f90d1f5b-91aa-4d55-9c08-65270803ff19
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839983764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di gest.3839983764
Directory	/workspace/7.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_mux.2302492640
Short name	T591
Test name
Test status
Simulation time	367650521 ps
CPU time	9.16 seconds
Started	Jul 29 05:35:40 PM PDT 24
Finished	Jul 29 05:35:49 PM PDT 24
Peak memory	226116 kb
Host	smart-71ee0cc5-7120-4fa0-8a78-538cd4f6c761
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302492640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2 302492640
Directory	/workspace/7.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/7.lc_ctrl_security_escalation.2624323250
Short name	T771
Test name
Test status
Simulation time	632991585 ps
CPU time	12.44 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:47 PM PDT 24
Peak memory	218420 kb
Host	smart-59ff9882-de1c-47c0-9396-f16d6b796b88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624323250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2624323250
Directory	/workspace/7.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/7.lc_ctrl_smoke.2835213381
Short name	T683
Test name
Test status
Simulation time	117499987 ps
CPU time	2.56 seconds
Started	Jul 29 05:35:41 PM PDT 24
Finished	Jul 29 05:35:43 PM PDT 24
Peak memory	217956 kb
Host	smart-1529db80-d0a2-45bd-b1cd-763b5f3b193a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835213381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2835213381
Directory	/workspace/7.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_failure.941866155
Short name	T301
Test name
Test status
Simulation time	1134167600 ps
CPU time	25.62 seconds
Started	Jul 29 05:35:34 PM PDT 24
Finished	Jul 29 05:36:00 PM PDT 24
Peak memory	250864 kb
Host	smart-eeba955e-cc37-430e-88e3-273f70f01052
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941866155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.941866155
Directory	/workspace/7.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_post_trans.3685158363
Short name	T233
Test name
Test status
Simulation time	58187593 ps
CPU time	7.09 seconds
Started	Jul 29 05:35:40 PM PDT 24
Finished	Jul 29 05:35:47 PM PDT 24
Peak memory	242724 kb
Host	smart-fea697db-0556-4fa8-a7e8-d83a1cefa6a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685158363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3685158363
Directory	/workspace/7.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all.173683713
Short name	T283
Test name
Test status
Simulation time	16625460056 ps
CPU time	108.34 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:37:27 PM PDT 24
Peak memory	278636 kb
Host	smart-14b04c56-9f54-454b-bdcf-91bfdc796163
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173683713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.173683713
Directory	/workspace/7.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1527236402
Short name	T646
Test name
Test status
Simulation time	21585636 ps
CPU time	1.04 seconds
Started	Jul 29 05:35:35 PM PDT 24
Finished	Jul 29 05:35:36 PM PDT 24
Peak memory	217852 kb
Host	smart-7d1d19be-78dd-4590-9382-334cb65790aa
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527236402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.1527236402
Directory	/workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_alert_test.670739292
Short name	T834
Test name
Test status
Simulation time	18009334 ps
CPU time	0.88 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:35:47 PM PDT 24
Peak memory	208936 kb
Host	smart-9c47a3c1-c355-4095-9253-80a3c7751edf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670739292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.670739292
Directory	/workspace/8.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.lc_ctrl_claim_transition_if.366669879
Short name	T203
Test name
Test status
Simulation time	17529136 ps
CPU time	1 seconds
Started	Jul 29 05:35:39 PM PDT 24
Finished	Jul 29 05:35:40 PM PDT 24
Peak memory	208880 kb
Host	smart-c3c4077a-477f-4a30-b88a-0a95d4e4dc90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366669879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.366669879
Directory	/workspace/8.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/8.lc_ctrl_errors.3873552770
Short name	T16
Test name
Test status
Simulation time	1624951525 ps
CPU time	18.59 seconds
Started	Jul 29 05:35:39 PM PDT 24
Finished	Jul 29 05:35:57 PM PDT 24
Peak memory	226180 kb
Host	smart-8288b0e0-ba88-47b4-a620-9ca95ecb44dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873552770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3873552770
Directory	/workspace/8.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_access.3712823403
Short name	T814
Test name
Test status
Simulation time	7019527924 ps
CPU time	9.84 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:35:48 PM PDT 24
Peak memory	217644 kb
Host	smart-db764dce-8df8-43a3-840c-08501d57064a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712823403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3712823403
Directory	/workspace/8.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_errors.1580072574
Short name	T589
Test name
Test status
Simulation time	19559162169 ps
CPU time	75.52 seconds
Started	Jul 29 05:35:39 PM PDT 24
Finished	Jul 29 05:36:55 PM PDT 24
Peak memory	219844 kb
Host	smart-12b0cae1-fbd1-42a8-8f75-260435502687
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580072574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er rors.1580072574
Directory	/workspace/8.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_priority.215724120
Short name	T362
Test name
Test status
Simulation time	2028824163 ps
CPU time	45.33 seconds
Started	Jul 29 05:35:42 PM PDT 24
Finished	Jul 29 05:36:27 PM PDT 24
Peak memory	217844 kb
Host	smart-f06277db-6d61-4c18-8d92-a56782b7699d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215724120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.215724120
Directory	/workspace/8.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3364497258
Short name	T377
Test name
Test status
Simulation time	340518932 ps
CPU time	5.46 seconds
Started	Jul 29 05:35:38 PM PDT 24
Finished	Jul 29 05:35:44 PM PDT 24
Peak memory	218308 kb
Host	smart-1f28ac07-c7c5-4807-97c5-493133a87313
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364497258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _prog_failure.3364497258
Directory	/workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.216103221
Short name	T315
Test name
Test status
Simulation time	3012364403 ps
CPU time	24.81 seconds
Started	Jul 29 05:35:43 PM PDT 24
Finished	Jul 29 05:36:08 PM PDT 24
Peak memory	217780 kb
Host	smart-8c1f79ee-b35e-49c4-83e8-577130ad9d38
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216103221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j tag_regwen_during_op.216103221
Directory	/workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_smoke.13249515
Short name	T499
Test name
Test status
Simulation time	307832026 ps
CPU time	5.79 seconds
Started	Jul 29 05:35:40 PM PDT 24
Finished	Jul 29 05:35:46 PM PDT 24
Peak memory	217692 kb
Host	smart-13623c86-4ac0-4902-9c4e-f4df6a13d4da
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13249515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.13249515
Directory	/workspace/8.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2511052622
Short name	T614
Test name
Test status
Simulation time	14211605197 ps
CPU time	117.88 seconds
Started	Jul 29 05:35:39 PM PDT 24
Finished	Jul 29 05:37:37 PM PDT 24
Peak memory	283756 kb
Host	smart-4cb03501-e4d9-453f-8df4-6f1425fe5472
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511052622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta g_state_failure.2511052622
Directory	/workspace/8.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2578767855
Short name	T522
Test name
Test status
Simulation time	726721375 ps
CPU time	13.05 seconds
Started	Jul 29 05:35:40 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	223160 kb
Host	smart-e73c57a0-3969-401f-bd66-4f0b338eec9d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578767855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_state_post_trans.2578767855
Directory	/workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_prog_failure.1085257874
Short name	T636
Test name
Test status
Simulation time	127835748 ps
CPU time	3.09 seconds
Started	Jul 29 05:35:39 PM PDT 24
Finished	Jul 29 05:35:43 PM PDT 24
Peak memory	218368 kb
Host	smart-6c86edd7-6e31-47bf-9186-4798963abf8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085257874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1085257874
Directory	/workspace/8.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_regwen_during_op.1353731276
Short name	T717
Test name
Test status
Simulation time	1215615124 ps
CPU time	19.17 seconds
Started	Jul 29 05:35:41 PM PDT 24
Finished	Jul 29 05:36:01 PM PDT 24
Peak memory	217956 kb
Host	smart-e034fa79-a7cc-4aa4-95cf-7eddf6a860c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353731276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1353731276
Directory	/workspace/8.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_mubi.1093727540
Short name	T406
Test name
Test status
Simulation time	1577368604 ps
CPU time	14.9 seconds
Started	Jul 29 05:35:41 PM PDT 24
Finished	Jul 29 05:35:56 PM PDT 24
Peak memory	226088 kb
Host	smart-6e352efa-da70-4c70-b3fc-8dc1db74a945
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093727540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1093727540
Directory	/workspace/8.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_digest.3444935655
Short name	T484
Test name
Test status
Simulation time	933698740 ps
CPU time	9.79 seconds
Started	Jul 29 05:35:45 PM PDT 24
Finished	Jul 29 05:35:55 PM PDT 24
Peak memory	218324 kb
Host	smart-d2960d63-062f-4846-b631-11263d52d32a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444935655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di gest.3444935655
Directory	/workspace/8.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_mux.2543052345
Short name	T277
Test name
Test status
Simulation time	1655700646 ps
CPU time	7.98 seconds
Started	Jul 29 05:35:43 PM PDT 24
Finished	Jul 29 05:35:51 PM PDT 24
Peak memory	218304 kb
Host	smart-042f736c-7c27-47d4-8fc6-4bc399eb5423
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543052345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2 543052345
Directory	/workspace/8.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/8.lc_ctrl_security_escalation.3148084215
Short name	T337
Test name
Test status
Simulation time	308136712 ps
CPU time	8.07 seconds
Started	Jul 29 05:35:42 PM PDT 24
Finished	Jul 29 05:35:50 PM PDT 24
Peak memory	226156 kb
Host	smart-15ded10e-18e9-49c7-a563-746db1650067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148084215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3148084215
Directory	/workspace/8.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_smoke.3486201106
Short name	T250
Test name
Test status
Simulation time	149062158 ps
CPU time	8.53 seconds
Started	Jul 29 05:35:41 PM PDT 24
Finished	Jul 29 05:35:50 PM PDT 24
Peak memory	217800 kb
Host	smart-4e3edb90-ed42-41db-8241-deb352e3bd9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486201106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3486201106
Directory	/workspace/8.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_failure.1384092782
Short name	T92
Test name
Test status
Simulation time	242932409 ps
CPU time	24 seconds
Started	Jul 29 05:35:39 PM PDT 24
Finished	Jul 29 05:36:04 PM PDT 24
Peak memory	250932 kb
Host	smart-6195ddd5-49af-4637-9abc-7c59003e57ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384092782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1384092782
Directory	/workspace/8.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_post_trans.1775034403
Short name	T708
Test name
Test status
Simulation time	798802522 ps
CPU time	9.67 seconds
Started	Jul 29 05:35:41 PM PDT 24
Finished	Jul 29 05:35:51 PM PDT 24
Peak memory	251008 kb
Host	smart-9a6ddba0-d54c-4730-ab86-eca683327133
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775034403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1775034403
Directory	/workspace/8.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all.35934864
Short name	T844
Test name
Test status
Simulation time	33445221294 ps
CPU time	290.01 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:40:36 PM PDT 24
Peak memory	270004 kb
Host	smart-a90f2e96-2285-45ac-afc7-e911c6e98040
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35934864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .lc_ctrl_stress_all.35934864
Directory	/workspace/8.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3014082873
Short name	T613
Test name
Test status
Simulation time	24335076 ps
CPU time	0.99 seconds
Started	Jul 29 05:35:41 PM PDT 24
Finished	Jul 29 05:35:42 PM PDT 24
Peak memory	211964 kb
Host	smart-e45e03f4-08b4-4cee-9662-1cc78ccaae64
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014082873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct rl_volatile_unlock_smoke.3014082873
Directory	/workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_alert_test.1301018179
Short name	T851
Test name
Test status
Simulation time	19254100 ps
CPU time	1.07 seconds
Started	Jul 29 05:35:53 PM PDT 24
Finished	Jul 29 05:35:54 PM PDT 24
Peak memory	208916 kb
Host	smart-6898d0a5-85fd-49b3-b9f9-7418c193aff4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301018179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1301018179
Directory	/workspace/9.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.lc_ctrl_claim_transition_if.2863959964
Short name	T201
Test name
Test status
Simulation time	18205469 ps
CPU time	0.82 seconds
Started	Jul 29 05:35:45 PM PDT 24
Finished	Jul 29 05:35:46 PM PDT 24
Peak memory	209160 kb
Host	smart-42491618-ff2f-4677-917c-ee44cb318bd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863959964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2863959964
Directory	/workspace/9.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/9.lc_ctrl_errors.213567072
Short name	T355
Test name
Test status
Simulation time	306036049 ps
CPU time	13.26 seconds
Started	Jul 29 05:35:48 PM PDT 24
Finished	Jul 29 05:36:01 PM PDT 24
Peak memory	218380 kb
Host	smart-f898773e-6fda-4d17-b6b6-49e5a06e52ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213567072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.213567072
Directory	/workspace/9.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_access.3432457929
Short name	T723
Test name
Test status
Simulation time	310191038 ps
CPU time	5.17 seconds
Started	Jul 29 05:35:44 PM PDT 24
Finished	Jul 29 05:35:50 PM PDT 24
Peak memory	217560 kb
Host	smart-ae10dd6c-b6ec-42ae-873a-561a1375268d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432457929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3432457929
Directory	/workspace/9.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_errors.2367519951
Short name	T436
Test name
Test status
Simulation time	1099484499 ps
CPU time	36.6 seconds
Started	Jul 29 05:35:49 PM PDT 24
Finished	Jul 29 05:36:26 PM PDT 24
Peak memory	218984 kb
Host	smart-fd7670a4-4727-4171-b0d7-9816a2fa4658
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367519951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.2367519951
Directory	/workspace/9.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_priority.3880624411
Short name	T5
Test name
Test status
Simulation time	2440058223 ps
CPU time	19.95 seconds
Started	Jul 29 05:35:43 PM PDT 24
Finished	Jul 29 05:36:04 PM PDT 24
Peak memory	217908 kb
Host	smart-6dfe4e78-8d59-40ba-839c-69a29bf7afe3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880624411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3 880624411
Directory	/workspace/9.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3552903036
Short name	T770
Test name
Test status
Simulation time	138297203 ps
CPU time	3.15 seconds
Started	Jul 29 05:35:49 PM PDT 24
Finished	Jul 29 05:35:53 PM PDT 24
Peak memory	218332 kb
Host	smart-69ed7a1a-2741-48a2-b390-0eaf7e7429cd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552903036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _prog_failure.3552903036
Directory	/workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1984018652
Short name	T456
Test name
Test status
Simulation time	2518307154 ps
CPU time	38.43 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:36:25 PM PDT 24
Peak memory	217704 kb
Host	smart-c456b2fa-1584-4b1d-bd9a-f04e233d8c3e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984018652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_regwen_during_op.1984018652
Directory	/workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_smoke.2982985515
Short name	T826
Test name
Test status
Simulation time	354263419 ps
CPU time	2.78 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:35:49 PM PDT 24
Peak memory	217728 kb
Host	smart-9de27e64-239f-45c2-b766-75fcdd8f18cb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982985515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 2982985515
Directory	/workspace/9.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_failure.804714055
Short name	T488
Test name
Test status
Simulation time	1123720536 ps
CPU time	34.14 seconds
Started	Jul 29 05:35:47 PM PDT 24
Finished	Jul 29 05:36:21 PM PDT 24
Peak memory	250948 kb
Host	smart-f4288692-f1d6-49dd-9e29-1ba16646eece
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804714055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _state_failure.804714055
Directory	/workspace/9.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.940389826
Short name	T626
Test name
Test status
Simulation time	333741210 ps
CPU time	18.61 seconds
Started	Jul 29 05:35:47 PM PDT 24
Finished	Jul 29 05:36:05 PM PDT 24
Peak memory	250752 kb
Host	smart-aad12471-3225-4a55-b12a-c4b238d4e7cb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940389826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_state_post_trans.940389826
Directory	/workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_prog_failure.262565224
Short name	T501
Test name
Test status
Simulation time	227760337 ps
CPU time	3.93 seconds
Started	Jul 29 05:35:45 PM PDT 24
Finished	Jul 29 05:35:49 PM PDT 24
Peak memory	218304 kb
Host	smart-22776e36-9754-4ef6-b62d-8f78e0d4bfe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262565224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.262565224
Directory	/workspace/9.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_regwen_during_op.3745585431
Short name	T348
Test name
Test status
Simulation time	386680783 ps
CPU time	14.65 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:36:01 PM PDT 24
Peak memory	214848 kb
Host	smart-30b99ab8-7938-413e-b625-c3b05c8c69ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745585431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3745585431
Directory	/workspace/9.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_mubi.2833645441
Short name	T542
Test name
Test status
Simulation time	5551663721 ps
CPU time	11.12 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:35:57 PM PDT 24
Peak memory	226132 kb
Host	smart-a8de8902-4eb2-46c2-881b-59ef3e2c702e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833645441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2833645441
Directory	/workspace/9.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_digest.3627365739
Short name	T226
Test name
Test status
Simulation time	771251759 ps
CPU time	20.05 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:36:12 PM PDT 24
Peak memory	218360 kb
Host	smart-33c6a74a-ea99-4418-aa37-28cc5b9a3e84
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627365739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di gest.3627365739
Directory	/workspace/9.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_mux.4111085902
Short name	T503
Test name
Test status
Simulation time	372139298 ps
CPU time	12.98 seconds
Started	Jul 29 05:35:52 PM PDT 24
Finished	Jul 29 05:36:05 PM PDT 24
Peak memory	218324 kb
Host	smart-adc68cce-1bd7-4b9d-bffe-2b343ffb5ec9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111085902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.4 111085902
Directory	/workspace/9.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/9.lc_ctrl_security_escalation.2107488609
Short name	T254
Test name
Test status
Simulation time	396142347 ps
CPU time	14.19 seconds
Started	Jul 29 05:35:45 PM PDT 24
Finished	Jul 29 05:36:00 PM PDT 24
Peak memory	226192 kb
Host	smart-be21a661-acfe-46df-bfc9-e19d1b391eeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107488609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2107488609
Directory	/workspace/9.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/9.lc_ctrl_smoke.1011345497
Short name	T471
Test name
Test status
Simulation time	181099781 ps
CPU time	2.43 seconds
Started	Jul 29 05:35:47 PM PDT 24
Finished	Jul 29 05:35:50 PM PDT 24
Peak memory	217724 kb
Host	smart-41e0b20e-49ab-4d8f-a996-661880f08dea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011345497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1011345497
Directory	/workspace/9.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_failure.3744824414
Short name	T25
Test name
Test status
Simulation time	290949930 ps
CPU time	29.93 seconds
Started	Jul 29 05:35:46 PM PDT 24
Finished	Jul 29 05:36:16 PM PDT 24
Peak memory	251168 kb
Host	smart-eeb509f8-6f88-484d-a599-28fddd912e8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744824414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3744824414
Directory	/workspace/9.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_post_trans.589075705
Short name	T150
Test name
Test status
Simulation time	105220378 ps
CPU time	6.26 seconds
Started	Jul 29 05:35:48 PM PDT 24
Finished	Jul 29 05:35:55 PM PDT 24
Peak memory	250588 kb
Host	smart-eb3100fe-3e09-4964-a6c4-c8514f1c2075
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589075705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.589075705
Directory	/workspace/9.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all.3128970302
Short name	T807
Test name
Test status
Simulation time	19900069078 ps
CPU time	138.01 seconds
Started	Jul 29 05:35:51 PM PDT 24
Finished	Jul 29 05:38:09 PM PDT 24
Peak memory	273424 kb
Host	smart-c9adecdf-0064-4fe5-863c-81fdb823cc65
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128970302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.3128970302
Directory	/workspace/9.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.971052786
Short name	T167
Test name
Test status
Simulation time	41044184583 ps
CPU time	714.06 seconds
Started	Jul 29 05:35:50 PM PDT 24
Finished	Jul 29 05:47:45 PM PDT 24
Peak memory	333108 kb
Host	smart-a48dffe0-463c-44d7-a8b8-1677c784da40
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=971052786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.971052786
Directory	/workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.952649920
Short name	T602
Test name
Test status
Simulation time	14262411 ps
CPU time	1.07 seconds
Started	Jul 29 05:35:45 PM PDT 24
Finished	Jul 29 05:35:47 PM PDT 24
Peak memory	211988 kb
Host	smart-b7564a0c-1a9e-47d4-9171-a748bfe69099
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952649920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr l_volatile_unlock_smoke.952649920
Directory	/workspace/9.lc_ctrl_volatile_unlock_smoke/latest

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