Summary for Variable clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53226 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1746 | 
1 | 
 | 
 | 
T5 | 
4 | 
 | 
T6 | 
7 | 
 | 
T13 | 
7 | 
Summary for Variable clk_byp_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54247 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
725 | 
1 | 
 | 
 | 
T9 | 
8 | 
 | 
T22 | 
17 | 
 | 
T18 | 
12 | 
Summary for Variable count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52906 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2066 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T6 | 
22 | 
 | 
T21 | 
1 | 
Summary for Variable count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52987 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1985 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
14 | 
 | 
T21 | 
2 | 
Summary for Variable count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for count_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52955 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2017 | 
1 | 
 | 
 | 
T11 | 
7 | 
 | 
T6 | 
30 | 
 | 
T21 | 
1 | 
Summary for Variable err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
2 | 
0 | 
2 | 
100.00 | 
User Defined Bins for err_inj_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| err_inj | 
50185 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| no_err_inj | 
4787 | 
1 | 
 | 
 | 
T12 | 
1 | 
 | 
T6 | 
20 | 
 | 
T21 | 
8 | 
Summary for Variable flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53102 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1870 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T6 | 
11 | 
 | 
T13 | 
11 | 
Summary for Variable flash_rma_rsp_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54239 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
733 | 
1 | 
 | 
 | 
T9 | 
8 | 
 | 
T22 | 
17 | 
 | 
T18 | 
20 | 
Summary for Variable jtag_csr_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for jtag_csr_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
38888 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
16084 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
Summary for Variable kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52987 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1985 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
21 | 
 | 
T21 | 
1 | 
Summary for Variable lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52931 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2041 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
15 | 
 | 
T21 | 
1 | 
Summary for Variable otp_lc_data_i_valid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52927 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2045 | 
1 | 
 | 
 | 
T11 | 
7 | 
 | 
T6 | 
19 | 
 | 
T38 | 
1 | 
Summary for Variable otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_partition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53131 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1841 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T6 | 
13 | 
 | 
T13 | 
7 | 
Summary for Variable otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_prog_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52632 | 
1 | 
 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
 | 
T9 | 
50 | 
| auto[1] | 
2340 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T6 | 
16 | 
 | 
T55 | 
16 | 
Summary for Variable otp_rma_token_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54243 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
729 | 
1 | 
 | 
 | 
T9 | 
12 | 
 | 
T22 | 
16 | 
 | 
T18 | 
22 | 
Summary for Variable otp_secrets_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54178 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
794 | 
1 | 
 | 
 | 
T9 | 
12 | 
 | 
T22 | 
20 | 
 | 
T18 | 
17 | 
Summary for Variable otp_test_tokens_valid_mubi_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54238 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
734 | 
1 | 
 | 
 | 
T9 | 
10 | 
 | 
T22 | 
26 | 
 | 
T18 | 
17 | 
Summary for Variable post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for post_trans_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52393 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2579 | 
1 | 
 | 
 | 
T21 | 
15 | 
 | 
T30 | 
13 | 
 | 
T38 | 
11 | 
Summary for Variable security_escalation_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for security_escalation_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
51032 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T9 | 
50 | 
| auto[1] | 
3940 | 
1 | 
 | 
 | 
T3 | 
83 | 
 | 
T19 | 
99 | 
 | 
T14 | 
86 | 
Summary for Variable state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_backdoor_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52935 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2037 | 
1 | 
 | 
 | 
T11 | 
8 | 
 | 
T6 | 
18 | 
 | 
T21 | 
1 | 
Summary for Variable state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52934 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2038 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T6 | 
26 | 
 | 
T30 | 
1 | 
Summary for Variable state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for state_illegal_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
52908 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
2064 | 
1 | 
 | 
 | 
T11 | 
4 | 
 | 
T6 | 
26 | 
 | 
T24 | 
12 | 
Summary for Variable token_invalid_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_invalid_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53183 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1789 | 
1 | 
 | 
 | 
T5 | 
7 | 
 | 
T6 | 
11 | 
 | 
T13 | 
7 | 
Summary for Variable token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mismatch_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
49647 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
5325 | 
1 | 
 | 
 | 
T5 | 
9 | 
 | 
T6 | 
14 | 
 | 
T13 | 
13 | 
Summary for Variable token_mux_ctrl_redun_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
51144 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T3 | 
83 | 
 | 
T9 | 
50 | 
| auto[1] | 
3828 | 
1 | 
 | 
 | 
T2 | 
96 | 
 | 
T15 | 
79 | 
 | 
T56 | 
73 | 
Summary for Variable token_mux_digest_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
1 | 
1 | 
50.00  | 
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | 
0 | 
1 | 
1 | 
 | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
54972 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
Summary for Variable token_response_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for token_response_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53175 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1797 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T6 | 
12 | 
 | 
T13 | 
18 | 
Summary for Variable transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_count_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53055 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1917 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T6 | 
11 | 
 | 
T13 | 
4 | 
Summary for Variable transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for transition_err_cp
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
53173 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[1] | 
1799 | 
1 | 
 | 
 | 
T5 | 
5 | 
 | 
T6 | 
8 | 
 | 
T13 | 
13 | 
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
| post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
err_inj | 
48877 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
no_err_inj | 
3516 | 
1 | 
 | 
 | 
T12 | 
1 | 
 | 
T6 | 
20 | 
 | 
T17 | 
6 | 
| auto[1] | 
err_inj | 
1308 | 
1 | 
 | 
 | 
T21 | 
7 | 
 | 
T30 | 
8 | 
 | 
T38 | 
6 | 
| auto[1] | 
no_err_inj | 
1271 | 
1 | 
 | 
 | 
T21 | 
8 | 
 | 
T30 | 
5 | 
 | 
T38 | 
5 | 
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
| post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50495 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1898 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T6 | 
26 | 
 | 
T24 | 
7 | 
| auto[1] | 
auto[0] | 
2439 | 
1 | 
 | 
 | 
T21 | 
15 | 
 | 
T30 | 
12 | 
 | 
T38 | 
11 | 
| auto[1] | 
auto[1] | 
140 | 
1 | 
 | 
 | 
T30 | 
1 | 
 | 
T77 | 
2 | 
 | 
T25 | 
2 | 
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
| post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50491 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1902 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
15 | 
 | 
T24 | 
5 | 
| auto[1] | 
auto[0] | 
2440 | 
1 | 
 | 
 | 
T21 | 
14 | 
 | 
T30 | 
11 | 
 | 
T38 | 
11 | 
| auto[1] | 
auto[1] | 
139 | 
1 | 
 | 
 | 
T21 | 
1 | 
 | 
T30 | 
2 | 
 | 
T25 | 
2 | 
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
| post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50474 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1919 | 
1 | 
 | 
 | 
T11 | 
4 | 
 | 
T6 | 
26 | 
 | 
T24 | 
10 | 
| auto[1] | 
auto[0] | 
2434 | 
1 | 
 | 
 | 
T21 | 
15 | 
 | 
T30 | 
13 | 
 | 
T38 | 
11 | 
| auto[1] | 
auto[1] | 
145 | 
1 | 
 | 
 | 
T24 | 
2 | 
 | 
T25 | 
2 | 
 | 
T26 | 
3 | 
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
| post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50575 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1818 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
14 | 
 | 
T24 | 
18 | 
| auto[1] | 
auto[0] | 
2412 | 
1 | 
 | 
 | 
T21 | 
13 | 
 | 
T30 | 
12 | 
 | 
T38 | 
10 | 
| auto[1] | 
auto[1] | 
167 | 
1 | 
 | 
 | 
T21 | 
2 | 
 | 
T30 | 
1 | 
 | 
T38 | 
1 | 
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
| post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50515 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1878 | 
1 | 
 | 
 | 
T11 | 
7 | 
 | 
T6 | 
30 | 
 | 
T24 | 
12 | 
| auto[1] | 
auto[0] | 
2440 | 
1 | 
 | 
 | 
T21 | 
14 | 
 | 
T30 | 
12 | 
 | 
T38 | 
9 | 
| auto[1] | 
auto[1] | 
139 | 
1 | 
 | 
 | 
T21 | 
1 | 
 | 
T30 | 
1 | 
 | 
T38 | 
2 | 
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
| post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
50480 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1913 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T6 | 
22 | 
 | 
T24 | 
10 | 
| auto[1] | 
auto[0] | 
2426 | 
1 | 
 | 
 | 
T21 | 
14 | 
 | 
T30 | 
10 | 
 | 
T38 | 
10 | 
| auto[1] | 
auto[1] | 
153 | 
1 | 
 | 
 | 
T21 | 
1 | 
 | 
T30 | 
3 | 
 | 
T38 | 
1 | 
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
| jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37810 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1078 | 
1 | 
 | 
 | 
T6 | 
7 | 
 | 
T13 | 
7 | 
 | 
T28 | 
18 | 
| auto[1] | 
auto[0] | 
15416 | 
1 | 
 | 
 | 
T5 | 
53 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
668 | 
1 | 
 | 
 | 
T5 | 
4 | 
 | 
T25 | 
13 | 
 | 
T28 | 
29 | 
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
| jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37755 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1133 | 
1 | 
 | 
 | 
T6 | 
11 | 
 | 
T13 | 
11 | 
 | 
T28 | 
21 | 
| auto[1] | 
auto[0] | 
15347 | 
1 | 
 | 
 | 
T5 | 
49 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
737 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T25 | 
9 | 
 | 
T28 | 
32 | 
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
| jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37568 | 
1 | 
 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
 | 
T9 | 
50 | 
| auto[0] | 
auto[1] | 
1320 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T55 | 
16 | 
 | 
T75 | 
17 | 
| auto[1] | 
auto[0] | 
15064 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
111 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
1020 | 
1 | 
 | 
 | 
T6 | 
16 | 
 | 
T25 | 
3 | 
 | 
T28 | 
134 | 
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
| jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37780 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1108 | 
1 | 
 | 
 | 
T6 | 
13 | 
 | 
T13 | 
7 | 
 | 
T28 | 
21 | 
| auto[1] | 
auto[0] | 
15351 | 
1 | 
 | 
 | 
T5 | 
49 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
733 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T25 | 
15 | 
 | 
T28 | 
37 | 
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
| jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
34279 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
4609 | 
1 | 
 | 
 | 
T6 | 
14 | 
 | 
T13 | 
13 | 
 | 
T16 | 
61 | 
| auto[1] | 
auto[0] | 
15368 | 
1 | 
 | 
 | 
T5 | 
48 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
716 | 
1 | 
 | 
 | 
T5 | 
9 | 
 | 
T25 | 
11 | 
 | 
T28 | 
35 | 
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
| jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37670 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1218 | 
1 | 
 | 
 | 
T11 | 
6 | 
 | 
T6 | 
15 | 
 | 
T30 | 
1 | 
| auto[1] | 
auto[0] | 
15264 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
116 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
820 | 
1 | 
 | 
 | 
T6 | 
11 | 
 | 
T24 | 
7 | 
 | 
T25 | 
1 | 
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
| jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37625 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1263 | 
1 | 
 | 
 | 
T11 | 
8 | 
 | 
T6 | 
9 | 
 | 
T21 | 
1 | 
| auto[1] | 
auto[0] | 
15310 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
118 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
774 | 
1 | 
 | 
 | 
T6 | 
9 | 
 | 
T24 | 
12 | 
 | 
T25 | 
1 | 
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37654 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1234 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
10 | 
 | 
T21 | 
1 | 
| auto[1] | 
auto[0] | 
15277 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
122 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
807 | 
1 | 
 | 
 | 
T6 | 
5 | 
 | 
T24 | 
5 | 
 | 
T25 | 
1 | 
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
| jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37682 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1206 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
11 | 
 | 
T21 | 
1 | 
| auto[1] | 
auto[0] | 
15305 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
117 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
779 | 
1 | 
 | 
 | 
T6 | 
10 | 
 | 
T24 | 
12 | 
 | 
T28 | 
33 | 
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
| jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37717 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1171 | 
1 | 
 | 
 | 
T11 | 
3 | 
 | 
T6 | 
6 | 
 | 
T21 | 
2 | 
| auto[1] | 
auto[0] | 
15270 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
119 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
814 | 
1 | 
 | 
 | 
T6 | 
8 | 
 | 
T24 | 
18 | 
 | 
T26 | 
1 | 
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
| jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37631 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1257 | 
1 | 
 | 
 | 
T11 | 
9 | 
 | 
T6 | 
13 | 
 | 
T21 | 
1 | 
| auto[1] | 
auto[0] | 
15275 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
118 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
809 | 
1 | 
 | 
 | 
T6 | 
9 | 
 | 
T24 | 
10 | 
 | 
T25 | 
1 | 
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
| jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37829 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1059 | 
1 | 
 | 
 | 
T6 | 
8 | 
 | 
T13 | 
13 | 
 | 
T28 | 
30 | 
| auto[1] | 
auto[0] | 
15344 | 
1 | 
 | 
 | 
T5 | 
52 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
740 | 
1 | 
 | 
 | 
T5 | 
5 | 
 | 
T25 | 
9 | 
 | 
T28 | 
26 | 
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
| jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37748 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1140 | 
1 | 
 | 
 | 
T6 | 
11 | 
 | 
T13 | 
4 | 
 | 
T28 | 
23 | 
| auto[1] | 
auto[0] | 
15307 | 
1 | 
 | 
 | 
T5 | 
49 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
777 | 
1 | 
 | 
 | 
T5 | 
8 | 
 | 
T25 | 
17 | 
 | 
T28 | 
36 | 
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
4 | 
0 | 
4 | 
100.00 | 
 | 
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
| jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
auto[0] | 
37454 | 
1 | 
 | 
 | 
T1 | 
17 | 
 | 
T2 | 
96 | 
 | 
T3 | 
83 | 
| auto[0] | 
auto[1] | 
1434 | 
1 | 
 | 
 | 
T21 | 
15 | 
 | 
T30 | 
13 | 
 | 
T38 | 
11 | 
| auto[1] | 
auto[0] | 
14939 | 
1 | 
 | 
 | 
T5 | 
57 | 
 | 
T6 | 
127 | 
 | 
T23 | 
17 | 
| auto[1] | 
auto[1] | 
1145 | 
1 | 
 | 
 | 
T25 | 
10 | 
 | 
T26 | 
12 | 
 | 
T28 | 
31 |