Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105347895

1

T1

6757

T2

36491

T3

38707

auto[1]

1459354

1

T1

792

T3

12646

T9

1287

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105351173

1

T1

6658

T2

36491

T3

37874

auto[1]

1456076

1

T1

891

T3

13479

T9

693

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7635594	1			T1	1904		T2	8621		T3	8513
auto[IdleSt]	22197005	1			T1	1547		T2	9852		T3	7612
auto[ClkMuxSt]	35602	1			T1	17		T2	96		T3	62
auto[CntIncrSt]	35280	1			T1	17		T2	96		T3	59
auto[CntProgSt]	2083290	1			T1	807		T2	1766		T3	12609
auto[TransCheckSt]	27381	1			T2	96		T3	35		T9	30
auto[TokenHashSt]	40803201	1			T2	1023		T3	2669		T9	1447
auto[FlashRmaSt]	36473	1			T2	122		T3	88		T9	70
auto[TokenCheck0St]	12886	1			T2	32		T3	27		T9	24
auto[TokenCheck1St]	9463	1			T2	10		T3	27		T9	17
auto[TransProgSt]	518023	1			T3	585		T9	374		T12	23
auto[PostTransSt]	13056378	1			T1	1056		T2	14777		T3	8
auto[ScrapSt]	233123	1			T23	533		T19	8		T14	16
auto[EscalateSt]	7202586	1			T1	2201		T3	19059		T9	2611
auto[InvalidSt]	12918852	1			T9	927		T11	7003		T6	129269

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2112	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12918852	1			T9	927		T11	7003		T6	129269
EscalateSt	7202586	1			T1	2201		T3	19059		T9	2611
ScrapSt	233123	1			T23	533		T19	8		T14	16
PostTransSt	13056378	1			T1	1056		T2	14777		T3	8
TransProgSt	518023	1			T3	585		T9	374		T12	23
TokenCheck1St	9463	1			T2	10		T3	27		T9	17
TokenCheck0St	12886	1			T2	32		T3	27		T9	24
FlashRmaSt	36473	1			T2	122		T3	88		T9	70
TokenHashSt	40803201	1			T2	1023		T3	2669		T9	1447
TransCheckSt	27381	1			T2	96		T3	35		T9	30
CntProgSt	2083290	1			T1	807		T2	1766		T3	12609
CntIncrSt	35280	1			T1	17		T2	96		T3	59
ClkMuxSt	35602	1			T1	17		T2	96		T3	62
IdleSt	22197005	1			T1	1547		T2	9852		T3	7612
ResetSt	7635594	1			T1	1904		T2	8621		T3	8513
arcs[ResetSt=>IdleSt]	55062	1			T1	18		T2	97		T3	68
arcs[IdleSt=>ScrapSt]	332	1			T23	1		T19	2		T14	4
arcs[IdleSt=>ClkMuxSt]	35321	1			T1	17		T2	96		T3	62
arcs[ClkMuxSt=>CntIncrSt]	35280	1			T1	17		T2	96		T3	59
arcs[CntIncrSt=>PostTransSt]	1919	1			T5	8		T6	11		T13	4
arcs[CntIncrSt=>CntProgSt]	33302	1			T1	17		T2	96		T3	57
arcs[CntProgSt=>PostTransSt]	4778	1			T1	17		T9	8		T5	4
arcs[CntProgSt=>TransCheckSt]	27381	1			T2	96		T3	35		T9	30
arcs[TransCheckSt=>PostTransSt]	3665	1			T2	50		T5	5		T6	8
arcs[TransCheckSt=>TokenHashSt]	23616	1			T2	46		T3	35		T9	30
arcs[TokenHashSt=>PostTransSt]	9869	1			T2	14		T9	6		T10	1
arcs[TokenHashSt=>FlashRmaSt]	12936	1			T2	32		T3	27		T9	24
arcs[FlashRmaSt=>TokenCheck0St]	12886	1			T2	32		T3	27		T9	24
arcs[TokenCheck0St=>PostTransSt]	3360	1			T2	22		T9	7		T5	8
arcs[TokenCheck0St=>TokenCheck1St]	9463	1			T2	10		T3	27		T9	17
arcs[TokenCheck1St=>PostTransSt]	671	1			T2	10		T6	1		T22	1
arcs[TransProgSt=>PostTransSt]	7931	1			T3	2		T9	17		T12	1
arcs[IdleSt=>EscalateSt]	173	1			T3	5		T19	9		T14	2
arcs[ClkMuxSt=>EscalateSt]	41	1			T3	3		T19	2		T14	1
arcs[CntIncrSt=>EscalateSt]	59	1			T3	2		T14	1		T45	2
arcs[CntProgSt=>EscalateSt]	1143	1			T3	22		T19	28		T14	34
arcs[TransCheckSt=>EscalateSt]	100	1			T19	1		T14	1		T50	4
arcs[TokenHashSt=>EscalateSt]	811	1			T3	8		T19	20		T14	11
arcs[FlashRmaSt=>EscalateSt]	50	1			T19	1		T14	3		T46	2
arcs[TokenCheck0St=>EscalateSt]	63	1			T19	1		T14	3		T45	3
arcs[TokenCheck1St=>EscalateSt]	38	1			T19	2		T50	1		T51	1
arcs[TransProgSt=>EscalateSt]	823	1			T3	25		T19	18		T14	18
arcs[PostTransSt=>EscalateSt]	5121	1			T1	17		T3	2		T9	8
arcs[InvalidSt=>EscalateSt]	14971	1			T9	12		T11	39		T6	146

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7635415	1			T1	1904		T2	8621		T3	8500
auto[0]	auto[IdleSt]	22196891	1			T1	1547		T2	9852		T3	7611
auto[0]	auto[ClkMuxSt]	35572	1			T1	17		T2	96		T3	60
auto[0]	auto[CntIncrSt]	35250	1			T1	17		T2	96		T3	58
auto[0]	auto[CntProgSt]	2082525	1			T1	807		T2	1766		T3	12597
auto[0]	auto[TransCheckSt]	27309	1			T2	96		T3	35		T9	30
auto[0]	auto[TokenHashSt]	40802668	1			T2	1023		T3	2661		T9	1447
auto[0]	auto[FlashRmaSt]	36443	1			T2	122		T3	88		T9	70
auto[0]	auto[TokenCheck0St]	12840	1			T2	32		T3	27		T9	24
auto[0]	auto[TokenCheck1St]	9434	1			T2	10		T3	27		T9	17
auto[0]	auto[TransProgSt]	517473	1			T3	570		T9	374		T12	23
auto[0]	auto[PostTransSt]	13053793	1			T1	1048		T2	14777		T3	6
auto[0]	auto[ScrapSt]	233063	1			T23	533		T19	6		T14	14
auto[0]	auto[EscalateSt]	5755770	1			T1	1417		T3	6467		T9	1337
auto[0]	auto[InvalidSt]	12911337	1			T9	920		T11	6981		T6	129196
auto[1]	auto[ResetSt]	179	1			T3	13		T19	7		T14	3
auto[1]	auto[IdleSt]	114	1			T3	1		T19	6		T14	1
auto[1]	auto[ClkMuxSt]	30	1			T3	2		T19	2		T14	1
auto[1]	auto[CntIncrSt]	30	1			T3	1		T14	1		T45	1
auto[1]	auto[CntProgSt]	765	1			T3	12		T19	19		T14	26
auto[1]	auto[TransCheckSt]	72	1			T19	1		T14	1		T50	2
auto[1]	auto[TokenHashSt]	533	1			T3	8		T19	14		T14	5
auto[1]	auto[FlashRmaSt]	30	1			T19	1		T14	2		T46	1
auto[1]	auto[TokenCheck0St]	46	1			T19	1		T14	3		T45	3
auto[1]	auto[TokenCheck1St]	29	1			T19	1		T50	1		T139	1
auto[1]	auto[TransProgSt]	550	1			T3	15		T19	15		T14	14
auto[1]	auto[PostTransSt]	2585	1			T1	8		T3	2		T9	6
auto[1]	auto[ScrapSt]	60	1			T19	2		T14	2		T45	1
auto[1]	auto[EscalateSt]	1446816	1			T1	784		T3	12592		T9	1274
auto[1]	auto[InvalidSt]	7515	1			T9	7		T11	22		T6	73

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7635434	1			T1	1904		T2	8621		T3	8503
auto[0]	auto[IdleSt]	22196884	1			T1	1547		T2	9852		T3	7607
auto[0]	auto[ClkMuxSt]	35577	1			T1	17		T2	96		T3	60
auto[0]	auto[CntIncrSt]	35235	1			T1	17		T2	96		T3	57
auto[0]	auto[CntProgSt]	2082540	1			T1	807		T2	1766		T3	12592
auto[0]	auto[TransCheckSt]	27317	1			T2	96		T3	35		T9	30
auto[0]	auto[TokenHashSt]	40802656	1			T2	1023		T3	2665		T9	1447
auto[0]	auto[FlashRmaSt]	36430	1			T2	122		T3	88		T9	70
auto[0]	auto[TokenCheck0St]	12849	1			T2	32		T3	27		T9	24
auto[0]	auto[TokenCheck1St]	9440	1			T2	10		T3	27		T9	17
auto[0]	auto[TransProgSt]	517472	1			T3	567		T9	374		T12	23
auto[0]	auto[PostTransSt]	13053739	1			T1	1047		T2	14777		T3	7
auto[0]	auto[ScrapSt]	233062	1			T23	533		T19	7		T14	12
auto[0]	auto[EscalateSt]	5759030	1			T1	1319		T3	5639		T9	1925
auto[0]	auto[InvalidSt]	12911396	1			T9	922		T11	6986		T6	129196
auto[1]	auto[ResetSt]	160	1			T3	10		T19	7		T14	3
auto[1]	auto[IdleSt]	121	1			T3	5		T19	7		T14	2
auto[1]	auto[ClkMuxSt]	25	1			T3	2		T46	1		T199	1
auto[1]	auto[CntIncrSt]	45	1			T3	2		T14	1		T45	2
auto[1]	auto[CntProgSt]	750	1			T3	17		T19	16		T14	22
auto[1]	auto[TransCheckSt]	64	1			T19	1		T50	4		T46	1
auto[1]	auto[TokenHashSt]	545	1			T3	4		T19	15		T14	10
auto[1]	auto[FlashRmaSt]	43	1			T19	1		T14	3		T46	2
auto[1]	auto[TokenCheck0St]	37	1			T19	1		T14	1		T45	2
auto[1]	auto[TokenCheck1St]	23	1			T19	2		T50	1		T51	1
auto[1]	auto[TransProgSt]	551	1			T3	18		T19	12		T14	9
auto[1]	auto[PostTransSt]	2639	1			T1	9		T3	1		T9	2
auto[1]	auto[ScrapSt]	61	1			T19	1		T14	4		T45	2
auto[1]	auto[EscalateSt]	1443556	1			T1	882		T3	13420		T9	686
auto[1]	auto[InvalidSt]	7456	1			T9	5		T11	17		T6	73