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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.90 97.92 96.03 93.40 97.62 98.52 98.51 96.29


Total test records in report: 997
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T805 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1332780940 Jul 30 05:22:36 PM PDT 24 Jul 30 05:22:49 PM PDT 24 411784299 ps
T806 /workspace/coverage/default/42.lc_ctrl_alert_test.3825338509 Jul 30 05:24:44 PM PDT 24 Jul 30 05:24:45 PM PDT 24 65358033 ps
T807 /workspace/coverage/default/46.lc_ctrl_state_failure.2903329294 Jul 30 05:24:55 PM PDT 24 Jul 30 05:25:27 PM PDT 24 1190457526 ps
T808 /workspace/coverage/default/40.lc_ctrl_alert_test.2756847922 Jul 30 05:24:35 PM PDT 24 Jul 30 05:24:36 PM PDT 24 20622723 ps
T809 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2714461686 Jul 30 05:22:38 PM PDT 24 Jul 30 05:22:52 PM PDT 24 675087428 ps
T810 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4241988617 Jul 30 05:23:12 PM PDT 24 Jul 30 05:23:31 PM PDT 24 2140435302 ps
T811 /workspace/coverage/default/3.lc_ctrl_smoke.2252612174 Jul 30 05:21:50 PM PDT 24 Jul 30 05:21:52 PM PDT 24 39662003 ps
T812 /workspace/coverage/default/31.lc_ctrl_security_escalation.4198950272 Jul 30 05:24:05 PM PDT 24 Jul 30 05:24:15 PM PDT 24 351438730 ps
T813 /workspace/coverage/default/4.lc_ctrl_smoke.63989777 Jul 30 05:22:03 PM PDT 24 Jul 30 05:22:04 PM PDT 24 52358810 ps
T814 /workspace/coverage/default/6.lc_ctrl_stress_all.2497004625 Jul 30 05:22:18 PM PDT 24 Jul 30 05:23:58 PM PDT 24 3634318519 ps
T815 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1292553374 Jul 30 05:23:12 PM PDT 24 Jul 30 05:23:24 PM PDT 24 365861033 ps
T816 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1396401792 Jul 30 05:22:16 PM PDT 24 Jul 30 05:22:40 PM PDT 24 3938757143 ps
T817 /workspace/coverage/default/18.lc_ctrl_prog_failure.434601366 Jul 30 05:23:18 PM PDT 24 Jul 30 05:23:20 PM PDT 24 89432742 ps
T818 /workspace/coverage/default/25.lc_ctrl_smoke.3196215072 Jul 30 05:23:45 PM PDT 24 Jul 30 05:23:47 PM PDT 24 72974380 ps
T819 /workspace/coverage/default/30.lc_ctrl_stress_all.3498426517 Jul 30 05:24:01 PM PDT 24 Jul 30 05:29:15 PM PDT 24 107127088808 ps
T820 /workspace/coverage/default/25.lc_ctrl_alert_test.3084574343 Jul 30 05:23:50 PM PDT 24 Jul 30 05:23:51 PM PDT 24 20236198 ps
T821 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.222061244 Jul 30 05:22:18 PM PDT 24 Jul 30 05:22:49 PM PDT 24 2057320548 ps
T822 /workspace/coverage/default/27.lc_ctrl_prog_failure.1507949935 Jul 30 05:23:54 PM PDT 24 Jul 30 05:23:57 PM PDT 24 92288409 ps
T823 /workspace/coverage/default/42.lc_ctrl_state_post_trans.348193188 Jul 30 05:24:43 PM PDT 24 Jul 30 05:24:46 PM PDT 24 59989249 ps
T824 /workspace/coverage/default/14.lc_ctrl_jtag_access.161953247 Jul 30 05:23:00 PM PDT 24 Jul 30 05:23:05 PM PDT 24 286898202 ps
T825 /workspace/coverage/default/37.lc_ctrl_state_post_trans.3150959859 Jul 30 05:24:27 PM PDT 24 Jul 30 05:24:33 PM PDT 24 110364226 ps
T826 /workspace/coverage/default/44.lc_ctrl_prog_failure.967154697 Jul 30 05:24:46 PM PDT 24 Jul 30 05:24:49 PM PDT 24 44942078 ps
T827 /workspace/coverage/default/29.lc_ctrl_state_failure.1212207979 Jul 30 05:23:58 PM PDT 24 Jul 30 05:24:29 PM PDT 24 1501578844 ps
T828 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1111169516 Jul 30 05:23:17 PM PDT 24 Jul 30 05:23:21 PM PDT 24 352592240 ps
T829 /workspace/coverage/default/21.lc_ctrl_stress_all.357982005 Jul 30 05:23:30 PM PDT 24 Jul 30 05:25:04 PM PDT 24 4475129281 ps
T830 /workspace/coverage/default/37.lc_ctrl_security_escalation.1334203269 Jul 30 05:24:25 PM PDT 24 Jul 30 05:24:36 PM PDT 24 2429366407 ps
T831 /workspace/coverage/default/35.lc_ctrl_state_failure.1754575778 Jul 30 05:24:18 PM PDT 24 Jul 30 05:24:46 PM PDT 24 427331871 ps
T832 /workspace/coverage/default/33.lc_ctrl_security_escalation.4040225199 Jul 30 05:24:10 PM PDT 24 Jul 30 05:24:22 PM PDT 24 843189870 ps
T833 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2798904085 Jul 30 05:21:51 PM PDT 24 Jul 30 05:22:05 PM PDT 24 4839633269 ps
T834 /workspace/coverage/default/1.lc_ctrl_state_post_trans.2671247213 Jul 30 05:21:43 PM PDT 24 Jul 30 05:21:46 PM PDT 24 221790866 ps
T835 /workspace/coverage/default/49.lc_ctrl_jtag_access.1502936556 Jul 30 05:25:08 PM PDT 24 Jul 30 05:25:16 PM PDT 24 909039924 ps
T836 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.565441583 Jul 30 05:21:51 PM PDT 24 Jul 30 05:21:57 PM PDT 24 299731165 ps
T837 /workspace/coverage/default/13.lc_ctrl_jtag_access.1853523105 Jul 30 05:22:55 PM PDT 24 Jul 30 05:23:09 PM PDT 24 1271761827 ps
T838 /workspace/coverage/default/27.lc_ctrl_security_escalation.3041185989 Jul 30 05:23:51 PM PDT 24 Jul 30 05:24:02 PM PDT 24 1111980293 ps
T839 /workspace/coverage/default/48.lc_ctrl_state_post_trans.4037658643 Jul 30 05:25:01 PM PDT 24 Jul 30 05:25:07 PM PDT 24 55666478 ps
T840 /workspace/coverage/default/0.lc_ctrl_state_failure.140501717 Jul 30 05:21:35 PM PDT 24 Jul 30 05:22:02 PM PDT 24 653990664 ps
T841 /workspace/coverage/default/1.lc_ctrl_errors.2271024125 Jul 30 05:21:48 PM PDT 24 Jul 30 05:22:07 PM PDT 24 738970919 ps
T842 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1621443900 Jul 30 05:21:51 PM PDT 24 Jul 30 05:22:01 PM PDT 24 704386592 ps
T843 /workspace/coverage/default/0.lc_ctrl_stress_all.3657248897 Jul 30 05:21:39 PM PDT 24 Jul 30 05:23:17 PM PDT 24 13401007602 ps
T844 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.660579215 Jul 30 05:22:05 PM PDT 24 Jul 30 05:22:14 PM PDT 24 4693730803 ps
T845 /workspace/coverage/default/6.lc_ctrl_alert_test.1723553805 Jul 30 05:22:21 PM PDT 24 Jul 30 05:22:22 PM PDT 24 18502011 ps
T846 /workspace/coverage/default/2.lc_ctrl_jtag_errors.1923679166 Jul 30 05:21:48 PM PDT 24 Jul 30 05:22:32 PM PDT 24 2868578093 ps
T847 /workspace/coverage/default/47.lc_ctrl_security_escalation.461580545 Jul 30 05:25:01 PM PDT 24 Jul 30 05:25:14 PM PDT 24 436612771 ps
T848 /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1643441535 Jul 30 05:21:44 PM PDT 24 Jul 30 05:21:52 PM PDT 24 498266267 ps
T849 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1349936750 Jul 30 05:24:15 PM PDT 24 Jul 30 05:24:16 PM PDT 24 21884296 ps
T850 /workspace/coverage/default/24.lc_ctrl_stress_all.322118004 Jul 30 05:23:43 PM PDT 24 Jul 30 05:25:45 PM PDT 24 35058507994 ps
T851 /workspace/coverage/default/8.lc_ctrl_smoke.2099233684 Jul 30 05:22:25 PM PDT 24 Jul 30 05:22:26 PM PDT 24 37556886 ps
T852 /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1351432786 Jul 30 05:21:52 PM PDT 24 Jul 30 05:22:01 PM PDT 24 318364501 ps
T853 /workspace/coverage/default/23.lc_ctrl_jtag_access.1411541717 Jul 30 05:23:38 PM PDT 24 Jul 30 05:23:46 PM PDT 24 630159277 ps
T854 /workspace/coverage/default/13.lc_ctrl_state_failure.2000544723 Jul 30 05:22:51 PM PDT 24 Jul 30 05:23:21 PM PDT 24 306777255 ps
T855 /workspace/coverage/default/1.lc_ctrl_state_failure.3040327403 Jul 30 05:21:41 PM PDT 24 Jul 30 05:22:06 PM PDT 24 306853555 ps
T856 /workspace/coverage/default/34.lc_ctrl_state_failure.2047131837 Jul 30 05:24:16 PM PDT 24 Jul 30 05:24:38 PM PDT 24 1006729979 ps
T857 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3388932241 Jul 30 05:24:18 PM PDT 24 Jul 30 05:24:20 PM PDT 24 11811312 ps
T858 /workspace/coverage/default/39.lc_ctrl_errors.1489473345 Jul 30 05:24:31 PM PDT 24 Jul 30 05:24:39 PM PDT 24 995430744 ps
T859 /workspace/coverage/default/17.lc_ctrl_security_escalation.1278562982 Jul 30 05:23:15 PM PDT 24 Jul 30 05:23:27 PM PDT 24 1085532646 ps
T860 /workspace/coverage/default/39.lc_ctrl_smoke.903549578 Jul 30 05:24:32 PM PDT 24 Jul 30 05:24:34 PM PDT 24 26726963 ps
T861 /workspace/coverage/default/10.lc_ctrl_smoke.4019222847 Jul 30 05:22:38 PM PDT 24 Jul 30 05:22:40 PM PDT 24 36102957 ps
T862 /workspace/coverage/default/7.lc_ctrl_stress_all.3358006178 Jul 30 05:22:27 PM PDT 24 Jul 30 05:22:50 PM PDT 24 1229621304 ps
T863 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2820903000 Jul 30 05:23:49 PM PDT 24 Jul 30 05:23:50 PM PDT 24 12867359 ps
T864 /workspace/coverage/default/48.lc_ctrl_stress_all.3703317164 Jul 30 05:25:04 PM PDT 24 Jul 30 05:26:52 PM PDT 24 118295809267 ps
T865 /workspace/coverage/default/31.lc_ctrl_errors.2322307919 Jul 30 05:24:07 PM PDT 24 Jul 30 05:24:17 PM PDT 24 1028381948 ps
T866 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3601001410 Jul 30 05:24:44 PM PDT 24 Jul 30 05:24:46 PM PDT 24 54209746 ps
T99 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3105645419 Jul 30 05:56:27 PM PDT 24 Jul 30 05:56:28 PM PDT 24 50315788 ps
T93 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3317377040 Jul 30 05:56:27 PM PDT 24 Jul 30 05:56:31 PM PDT 24 522817801 ps
T100 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1923360858 Jul 30 05:56:15 PM PDT 24 Jul 30 05:56:19 PM PDT 24 475130952 ps
T90 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.751178399 Jul 30 05:56:37 PM PDT 24 Jul 30 05:56:38 PM PDT 24 70939094 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3147518954 Jul 30 05:56:05 PM PDT 24 Jul 30 05:56:06 PM PDT 24 30319975 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3410906227 Jul 30 05:56:18 PM PDT 24 Jul 30 05:56:29 PM PDT 24 968309657 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1078451339 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:35 PM PDT 24 17473030 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4275781097 Jul 30 05:56:12 PM PDT 24 Jul 30 05:56:13 PM PDT 24 32488474 ps
T147 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3143112083 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:27 PM PDT 24 87632702 ps
T185 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.574454410 Jul 30 05:56:22 PM PDT 24 Jul 30 05:56:24 PM PDT 24 133306985 ps
T94 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.640964056 Jul 30 05:56:31 PM PDT 24 Jul 30 05:56:32 PM PDT 24 89582963 ps
T91 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.296794706 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:37 PM PDT 24 53101546 ps
T92 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1166401764 Jul 30 05:56:04 PM PDT 24 Jul 30 05:56:07 PM PDT 24 124163250 ps
T124 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.826729086 Jul 30 05:56:08 PM PDT 24 Jul 30 05:56:10 PM PDT 24 47994850 ps
T136 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3345954399 Jul 30 05:56:17 PM PDT 24 Jul 30 05:56:18 PM PDT 24 75468482 ps
T157 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174038827 Jul 30 05:56:31 PM PDT 24 Jul 30 05:56:33 PM PDT 24 278714054 ps
T867 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1171910918 Jul 30 05:56:01 PM PDT 24 Jul 30 05:56:10 PM PDT 24 2636381508 ps
T868 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2298972338 Jul 30 05:56:15 PM PDT 24 Jul 30 05:56:18 PM PDT 24 126028327 ps
T123 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2377482497 Jul 30 05:56:02 PM PDT 24 Jul 30 05:56:15 PM PDT 24 1030022370 ps
T95 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545613064 Jul 30 05:56:04 PM PDT 24 Jul 30 05:56:11 PM PDT 24 978083762 ps
T869 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3202982510 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:35 PM PDT 24 47951600 ps
T870 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.802924760 Jul 30 05:56:24 PM PDT 24 Jul 30 05:56:27 PM PDT 24 1570756787 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1964291244 Jul 30 05:56:11 PM PDT 24 Jul 30 05:56:23 PM PDT 24 2474087073 ps
T184 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.253801012 Jul 30 05:56:15 PM PDT 24 Jul 30 05:56:17 PM PDT 24 101091235 ps
T186 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3073850311 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:36 PM PDT 24 17096861 ps
T872 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3975028465 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:22 PM PDT 24 270964942 ps
T873 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2996192724 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:34 PM PDT 24 850816059 ps
T177 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.52423230 Jul 30 05:56:09 PM PDT 24 Jul 30 05:56:11 PM PDT 24 19551254 ps
T96 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3376804700 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:38 PM PDT 24 123926186 ps
T187 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1239302132 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:37 PM PDT 24 82116662 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2694296101 Jul 30 05:56:16 PM PDT 24 Jul 30 05:56:17 PM PDT 24 32408637 ps
T188 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4270962410 Jul 30 05:56:31 PM PDT 24 Jul 30 05:56:33 PM PDT 24 148647226 ps
T189 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3677621112 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:31 PM PDT 24 29539071 ps
T112 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1382486499 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:32 PM PDT 24 40851921 ps
T875 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.35514182 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:16 PM PDT 24 51266885 ps
T114 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.288798868 Jul 30 05:56:10 PM PDT 24 Jul 30 05:56:12 PM PDT 24 27375086 ps
T101 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1418824520 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:38 PM PDT 24 613777980 ps
T876 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3938967163 Jul 30 05:56:32 PM PDT 24 Jul 30 05:56:34 PM PDT 24 30033386 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1534496230 Jul 30 05:56:16 PM PDT 24 Jul 30 05:56:17 PM PDT 24 18466712 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2043010343 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:27 PM PDT 24 494140167 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2968146618 Jul 30 05:56:04 PM PDT 24 Jul 30 05:56:12 PM PDT 24 1678597254 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1222834974 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:16 PM PDT 24 67688047 ps
T110 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2642616959 Jul 30 05:56:05 PM PDT 24 Jul 30 05:56:07 PM PDT 24 125161993 ps
T190 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2455168381 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:35 PM PDT 24 38839906 ps
T178 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.141497851 Jul 30 05:56:23 PM PDT 24 Jul 30 05:56:25 PM PDT 24 38378910 ps
T97 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2532245163 Jul 30 05:56:28 PM PDT 24 Jul 30 05:56:30 PM PDT 24 167829020 ps
T191 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2846365662 Jul 30 05:56:37 PM PDT 24 Jul 30 05:56:38 PM PDT 24 22200036 ps
T881 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4118194391 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:36 PM PDT 24 62198728 ps
T882 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.411187951 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:36 PM PDT 24 24690824 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.473682777 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:15 PM PDT 24 115240957 ps
T884 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3581680847 Jul 30 05:56:13 PM PDT 24 Jul 30 05:56:14 PM PDT 24 13829898 ps
T885 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2581299924 Jul 30 05:56:37 PM PDT 24 Jul 30 05:56:39 PM PDT 24 46480584 ps
T886 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.913841042 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:26 PM PDT 24 51662063 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2184623795 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:15 PM PDT 24 54424184 ps
T111 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2598703069 Jul 30 05:56:12 PM PDT 24 Jul 30 05:56:15 PM PDT 24 1143918241 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2953416999 Jul 30 05:56:26 PM PDT 24 Jul 30 05:56:38 PM PDT 24 876694786 ps
T889 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2063722916 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:33 PM PDT 24 1330543132 ps
T179 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2190832577 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:15 PM PDT 24 16312085 ps
T890 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.244241270 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:22 PM PDT 24 696455222 ps
T180 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2079140289 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:36 PM PDT 24 76466031 ps
T891 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1069150316 Jul 30 05:56:09 PM PDT 24 Jul 30 05:56:11 PM PDT 24 266182789 ps
T892 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.115619241 Jul 30 05:56:28 PM PDT 24 Jul 30 05:56:30 PM PDT 24 102230343 ps
T893 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2729643250 Jul 30 05:56:28 PM PDT 24 Jul 30 05:56:29 PM PDT 24 15292671 ps
T894 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.966845664 Jul 30 05:56:15 PM PDT 24 Jul 30 05:56:17 PM PDT 24 255647552 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1175095736 Jul 30 05:56:18 PM PDT 24 Jul 30 05:56:20 PM PDT 24 294424015 ps
T98 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3584540131 Jul 30 05:56:28 PM PDT 24 Jul 30 05:56:31 PM PDT 24 115030908 ps
T896 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1489731462 Jul 30 05:56:28 PM PDT 24 Jul 30 05:56:29 PM PDT 24 68030125 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4277237288 Jul 30 05:56:11 PM PDT 24 Jul 30 05:56:15 PM PDT 24 477374631 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1444410295 Jul 30 05:56:03 PM PDT 24 Jul 30 05:56:04 PM PDT 24 45194985 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1886670323 Jul 30 05:56:17 PM PDT 24 Jul 30 05:56:19 PM PDT 24 251568807 ps
T102 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1892497490 Jul 30 05:56:27 PM PDT 24 Jul 30 05:56:31 PM PDT 24 127358225 ps
T900 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.187803904 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:31 PM PDT 24 43361541 ps
T901 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3830255208 Jul 30 05:56:28 PM PDT 24 Jul 30 05:56:30 PM PDT 24 60132631 ps
T105 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3837090517 Jul 30 05:56:31 PM PDT 24 Jul 30 05:56:35 PM PDT 24 112773603 ps
T103 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.562598080 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:17 PM PDT 24 88739425 ps
T902 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.184334821 Jul 30 05:56:36 PM PDT 24 Jul 30 05:56:38 PM PDT 24 28870024 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.129616219 Jul 30 05:56:31 PM PDT 24 Jul 30 05:56:32 PM PDT 24 15310816 ps
T106 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1340363183 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:33 PM PDT 24 435003077 ps
T181 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2665674181 Jul 30 05:56:36 PM PDT 24 Jul 30 05:56:37 PM PDT 24 12562175 ps
T904 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2914296628 Jul 30 05:56:08 PM PDT 24 Jul 30 05:56:11 PM PDT 24 90563485 ps
T905 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4072320667 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:35 PM PDT 24 28158919 ps
T109 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2073090374 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:33 PM PDT 24 149655495 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2477522648 Jul 30 05:56:06 PM PDT 24 Jul 30 05:56:09 PM PDT 24 69804020 ps
T907 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3952376887 Jul 30 05:56:23 PM PDT 24 Jul 30 05:56:25 PM PDT 24 75767369 ps
T908 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2036749930 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:30 PM PDT 24 69907024 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3055807019 Jul 30 05:56:10 PM PDT 24 Jul 30 05:56:11 PM PDT 24 130167099 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4177371267 Jul 30 05:56:18 PM PDT 24 Jul 30 05:56:19 PM PDT 24 16140108 ps
T911 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2246101586 Jul 30 05:56:17 PM PDT 24 Jul 30 05:56:18 PM PDT 24 41679743 ps
T912 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.612219646 Jul 30 05:56:24 PM PDT 24 Jul 30 05:56:27 PM PDT 24 276423642 ps
T913 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.795613999 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:38 PM PDT 24 46769929 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4017307741 Jul 30 05:56:24 PM PDT 24 Jul 30 05:56:26 PM PDT 24 326029295 ps
T118 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2978076116 Jul 30 05:56:31 PM PDT 24 Jul 30 05:56:36 PM PDT 24 485317429 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.330236189 Jul 30 05:56:11 PM PDT 24 Jul 30 05:56:12 PM PDT 24 17655294 ps
T916 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.337841066 Jul 30 05:56:32 PM PDT 24 Jul 30 05:56:34 PM PDT 24 23679082 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3357909835 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:31 PM PDT 24 29760533 ps
T918 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2342727145 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:34 PM PDT 24 703978477 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.108761514 Jul 30 05:56:08 PM PDT 24 Jul 30 05:56:10 PM PDT 24 206423940 ps
T920 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3312351235 Jul 30 05:56:17 PM PDT 24 Jul 30 05:56:18 PM PDT 24 12489505 ps
T921 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2752544710 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:36 PM PDT 24 55779587 ps
T117 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.665450665 Jul 30 05:56:37 PM PDT 24 Jul 30 05:56:39 PM PDT 24 414313693 ps
T922 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4062311078 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:16 PM PDT 24 123890537 ps
T923 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.217542837 Jul 30 05:56:31 PM PDT 24 Jul 30 05:56:33 PM PDT 24 42966335 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2204813949 Jul 30 05:56:03 PM PDT 24 Jul 30 05:56:04 PM PDT 24 56156349 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2056881801 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:27 PM PDT 24 110788325 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2948595557 Jul 30 05:56:18 PM PDT 24 Jul 30 05:56:20 PM PDT 24 853639752 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3848344320 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:22 PM PDT 24 108162361 ps
T115 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3115874964 Jul 30 05:56:36 PM PDT 24 Jul 30 05:56:38 PM PDT 24 67344087 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2861746467 Jul 30 05:56:01 PM PDT 24 Jul 30 05:56:04 PM PDT 24 321166297 ps
T929 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2281942797 Jul 30 05:56:22 PM PDT 24 Jul 30 05:56:26 PM PDT 24 164598107 ps
T930 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.24876563 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:32 PM PDT 24 81668933 ps
T931 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3294470117 Jul 30 05:56:05 PM PDT 24 Jul 30 05:56:08 PM PDT 24 789846148 ps
T932 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3910360474 Jul 30 05:56:26 PM PDT 24 Jul 30 05:56:27 PM PDT 24 23705249 ps
T933 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3763794186 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:32 PM PDT 24 58939256 ps
T934 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3810983260 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:27 PM PDT 24 58449455 ps
T935 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3595808025 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:32 PM PDT 24 57454814 ps
T104 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3692839123 Jul 30 05:56:05 PM PDT 24 Jul 30 05:56:08 PM PDT 24 147499527 ps
T936 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2055384428 Jul 30 05:56:04 PM PDT 24 Jul 30 05:56:06 PM PDT 24 43520375 ps
T937 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4005048155 Jul 30 05:56:03 PM PDT 24 Jul 30 05:56:04 PM PDT 24 163551590 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2996526653 Jul 30 05:56:21 PM PDT 24 Jul 30 05:56:23 PM PDT 24 45150753 ps
T182 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3808159575 Jul 30 05:56:22 PM PDT 24 Jul 30 05:56:23 PM PDT 24 41650292 ps
T183 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2504641006 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:35 PM PDT 24 23846112 ps
T939 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.764655814 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:27 PM PDT 24 1111474282 ps
T940 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1571627975 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:32 PM PDT 24 48100041 ps
T107 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3690962000 Jul 30 05:56:18 PM PDT 24 Jul 30 05:56:22 PM PDT 24 554991919 ps
T941 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2091825601 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:31 PM PDT 24 14378202 ps
T942 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2881507258 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:36 PM PDT 24 23661661 ps
T943 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2565582031 Jul 30 05:56:00 PM PDT 24 Jul 30 05:56:02 PM PDT 24 323417393 ps
T944 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3876497239 Jul 30 05:56:15 PM PDT 24 Jul 30 05:56:17 PM PDT 24 385238049 ps
T945 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2333823975 Jul 30 05:56:13 PM PDT 24 Jul 30 05:56:14 PM PDT 24 47490356 ps
T946 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.621408471 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:17 PM PDT 24 510754325 ps
T947 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.384083537 Jul 30 05:56:33 PM PDT 24 Jul 30 05:56:35 PM PDT 24 60596632 ps
T948 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3517051958 Jul 30 05:56:33 PM PDT 24 Jul 30 05:56:34 PM PDT 24 20348958 ps
T949 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4237187757 Jul 30 05:56:11 PM PDT 24 Jul 30 05:56:12 PM PDT 24 40979364 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3708731604 Jul 30 05:56:04 PM PDT 24 Jul 30 05:56:05 PM PDT 24 15677595 ps
T951 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1977647689 Jul 30 05:56:38 PM PDT 24 Jul 30 05:56:39 PM PDT 24 69065341 ps
T952 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4209456790 Jul 30 05:56:13 PM PDT 24 Jul 30 05:56:20 PM PDT 24 490136265 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2094648004 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:26 PM PDT 24 117125959 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2635912174 Jul 30 05:56:08 PM PDT 24 Jul 30 05:56:10 PM PDT 24 66056696 ps
T955 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2250338746 Jul 30 05:56:24 PM PDT 24 Jul 30 05:56:26 PM PDT 24 962061351 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.962898239 Jul 30 05:56:23 PM PDT 24 Jul 30 05:56:27 PM PDT 24 367394695 ps
T957 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1324069868 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:36 PM PDT 24 51453771 ps
T958 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1099767372 Jul 30 05:56:07 PM PDT 24 Jul 30 05:56:09 PM PDT 24 36572898 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.920047273 Jul 30 05:56:20 PM PDT 24 Jul 30 05:56:26 PM PDT 24 1184782849 ps
T960 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.258903368 Jul 30 05:56:14 PM PDT 24 Jul 30 05:56:16 PM PDT 24 155995087 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.720380130 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:21 PM PDT 24 899539557 ps
T962 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1927106286 Jul 30 05:56:22 PM PDT 24 Jul 30 05:56:23 PM PDT 24 22671276 ps
T963 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2158476813 Jul 30 05:56:28 PM PDT 24 Jul 30 05:57:03 PM PDT 24 6299977635 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2653886127 Jul 30 05:56:15 PM PDT 24 Jul 30 05:56:17 PM PDT 24 20451315 ps
T965 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3006484436 Jul 30 05:56:10 PM PDT 24 Jul 30 05:56:22 PM PDT 24 1924309928 ps
T966 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.343114823 Jul 30 05:56:35 PM PDT 24 Jul 30 05:56:35 PM PDT 24 69924930 ps
T967 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2407447731 Jul 30 05:56:33 PM PDT 24 Jul 30 05:56:34 PM PDT 24 83885240 ps
T968 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2375133110 Jul 30 05:56:07 PM PDT 24 Jul 30 05:56:08 PM PDT 24 47198720 ps
T113 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3365610366 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:37 PM PDT 24 45522142 ps
T108 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3725291231 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:22 PM PDT 24 723251830 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3223059432 Jul 30 05:56:13 PM PDT 24 Jul 30 05:56:14 PM PDT 24 152454130 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4211960071 Jul 30 05:56:22 PM PDT 24 Jul 30 05:56:23 PM PDT 24 32815397 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.326416947 Jul 30 05:56:11 PM PDT 24 Jul 30 05:56:13 PM PDT 24 21304347 ps
T972 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4172853762 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:31 PM PDT 24 36083857 ps
T973 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.103173891 Jul 30 05:56:08 PM PDT 24 Jul 30 05:56:09 PM PDT 24 251595007 ps
T119 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3107610648 Jul 30 05:56:39 PM PDT 24 Jul 30 05:56:41 PM PDT 24 46324031 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2907415226 Jul 30 05:56:24 PM PDT 24 Jul 30 05:56:27 PM PDT 24 71583951 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.310686298 Jul 30 05:56:23 PM PDT 24 Jul 30 05:56:24 PM PDT 24 40204791 ps
T976 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2230818589 Jul 30 05:56:30 PM PDT 24 Jul 30 05:56:32 PM PDT 24 229954104 ps
T977 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1513060275 Jul 30 05:56:08 PM PDT 24 Jul 30 05:56:09 PM PDT 24 42494905 ps
T978 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1771989996 Jul 30 05:56:17 PM PDT 24 Jul 30 05:56:18 PM PDT 24 15537703 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.405351638 Jul 30 05:56:06 PM PDT 24 Jul 30 05:56:08 PM PDT 24 195725503 ps
T980 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3021748758 Jul 30 05:56:23 PM PDT 24 Jul 30 05:56:25 PM PDT 24 224220671 ps
T981 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2243198102 Jul 30 05:56:05 PM PDT 24 Jul 30 05:56:06 PM PDT 24 26747448 ps
T982 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3845715409 Jul 30 05:56:33 PM PDT 24 Jul 30 05:56:36 PM PDT 24 213715038 ps
T983 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.150287813 Jul 30 05:56:34 PM PDT 24 Jul 30 05:56:39 PM PDT 24 209749651 ps
T984 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2620587330 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:25 PM PDT 24 2050763906 ps
T985 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3480784413 Jul 30 05:56:24 PM PDT 24 Jul 30 05:56:50 PM PDT 24 1156624871 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1753641374 Jul 30 05:56:10 PM PDT 24 Jul 30 05:56:12 PM PDT 24 244596965 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2814631655 Jul 30 05:56:09 PM PDT 24 Jul 30 05:56:11 PM PDT 24 65545891 ps
T987 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.189872919 Jul 30 05:56:36 PM PDT 24 Jul 30 05:56:38 PM PDT 24 23061975 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2744984597 Jul 30 05:56:16 PM PDT 24 Jul 30 05:56:18 PM PDT 24 57513242 ps
T989 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3672356304 Jul 30 05:56:27 PM PDT 24 Jul 30 05:56:28 PM PDT 24 53631081 ps
T990 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2083403544 Jul 30 05:56:21 PM PDT 24 Jul 30 05:56:23 PM PDT 24 492253980 ps
T991 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2608866860 Jul 30 05:56:09 PM PDT 24 Jul 30 05:56:12 PM PDT 24 806141437 ps
T992 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3061283804 Jul 30 05:56:29 PM PDT 24 Jul 30 05:56:30 PM PDT 24 730321845 ps
T993 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1777874227 Jul 30 05:56:11 PM PDT 24 Jul 30 05:56:16 PM PDT 24 374924386 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1461052059 Jul 30 05:56:12 PM PDT 24 Jul 30 05:56:13 PM PDT 24 89607699 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2945155139 Jul 30 05:56:19 PM PDT 24 Jul 30 05:56:23 PM PDT 24 127858638 ps
T996 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3153367760 Jul 30 05:56:27 PM PDT 24 Jul 30 05:56:28 PM PDT 24 38780728 ps
T997 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1255221245 Jul 30 05:56:25 PM PDT 24 Jul 30 05:56:35 PM PDT 24 1123352730 ps

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1819517275
Short name T6
Test name
Test status
Simulation time 13396838159 ps
CPU time 96.15 seconds
Started Jul 30 05:24:27 PM PDT 24
Finished Jul 30 05:26:04 PM PDT 24
Peak memory 283372 kb
Host smart-61f1260f-120a-45df-a63d-15499592c7e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819517275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1819517275
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1106389363
Short name T14
Test name
Test status
Simulation time 1535807160 ps
CPU time 9.37 seconds
Started Jul 30 05:21:35 PM PDT 24
Finished Jul 30 05:21:45 PM PDT 24
Peak memory 218508 kb
Host smart-316ab3a0-eb90-4d3a-9964-015959e25561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106389363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1106389363
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.591752084
Short name T18
Test name
Test status
Simulation time 299065510 ps
CPU time 13.03 seconds
Started Jul 30 05:22:41 PM PDT 24
Finished Jul 30 05:22:54 PM PDT 24
Peak memory 226236 kb
Host smart-beacbc05-f00b-4d1d-b0f8-981f6d250d1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591752084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.591752084
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.309548595
Short name T28
Test name
Test status
Simulation time 39088062119 ps
CPU time 1375.62 seconds
Started Jul 30 05:24:14 PM PDT 24
Finished Jul 30 05:47:10 PM PDT 24
Peak memory 495976 kb
Host smart-c4b5aaac-2168-42f8-90db-6fd174b69d0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=309548595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.309548595
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.640964056
Short name T94
Test name
Test status
Simulation time 89582963 ps
CPU time 1.84 seconds
Started Jul 30 05:56:31 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 217852 kb
Host smart-e70fb495-f8ce-4587-af85-f596b8e08a0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640964056 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.640964056
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2075293970
Short name T47
Test name
Test status
Simulation time 464130516 ps
CPU time 36.61 seconds
Started Jul 30 05:21:41 PM PDT 24
Finished Jul 30 05:22:18 PM PDT 24
Peak memory 269780 kb
Host smart-841ac88e-095b-4dff-8fd1-a0dfffd848c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075293970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2075293970
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2091714887
Short name T2
Test name
Test status
Simulation time 1824613353 ps
CPU time 14.39 seconds
Started Jul 30 05:23:02 PM PDT 24
Finished Jul 30 05:23:17 PM PDT 24
Peak memory 226148 kb
Host smart-40129efc-92ff-473c-bca6-3f6b960e83bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091714887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2091714887
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4176483111
Short name T19
Test name
Test status
Simulation time 638278884 ps
CPU time 12.92 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:23:47 PM PDT 24
Peak memory 224936 kb
Host smart-95873f65-7204-4c4a-b7d6-a87e22d0a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176483111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4176483111
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3376804700
Short name T96
Test name
Test status
Simulation time 123926186 ps
CPU time 3.06 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 222448 kb
Host smart-d1593ddb-fe76-48c6-9a2f-482469988df8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376804700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3376804700
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.674891557
Short name T32
Test name
Test status
Simulation time 203302480 ps
CPU time 3.42 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:23:29 PM PDT 24
Peak memory 217200 kb
Host smart-9eb5be4b-b334-4226-b697-4e170355204d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674891557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.674891557
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545613064
Short name T95
Test name
Test status
Simulation time 978083762 ps
CPU time 6.32 seconds
Started Jul 30 05:56:04 PM PDT 24
Finished Jul 30 05:56:11 PM PDT 24
Peak memory 219012 kb
Host smart-ec97eb6d-6937-437c-b92a-9fe06dff69d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154561
3064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1545613064
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1078451339
Short name T120
Test name
Test status
Simulation time 17473030 ps
CPU time 1.1 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 209468 kb
Host smart-cf669f33-93bf-40b3-84e8-43b82b479fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078451339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1078451339
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1745092435
Short name T78
Test name
Test status
Simulation time 141005241 ps
CPU time 0.92 seconds
Started Jul 30 05:25:06 PM PDT 24
Finished Jul 30 05:25:07 PM PDT 24
Peak memory 209020 kb
Host smart-3d638e7b-1b03-4fed-aba8-f4a01bd96de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745092435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1745092435
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1679984720
Short name T21
Test name
Test status
Simulation time 240015428 ps
CPU time 7.25 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:42 PM PDT 24
Peak memory 251032 kb
Host smart-9967266b-7838-4d54-8c6a-b08b20ca3389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679984720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1679984720
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3692839123
Short name T104
Test name
Test status
Simulation time 147499527 ps
CPU time 2.73 seconds
Started Jul 30 05:56:05 PM PDT 24
Finished Jul 30 05:56:08 PM PDT 24
Peak memory 213312 kb
Host smart-d56373ad-0591-4d8e-ab55-2b54c49c8809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692839123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3692839123
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.744118668
Short name T282
Test name
Test status
Simulation time 1760632535 ps
CPU time 15.2 seconds
Started Jul 30 05:22:49 PM PDT 24
Finished Jul 30 05:23:05 PM PDT 24
Peak memory 226164 kb
Host smart-cb3ad947-4aa5-4659-a954-f19e5f5b6616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744118668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.744118668
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3668079258
Short name T22
Test name
Test status
Simulation time 1593265709 ps
CPU time 15.2 seconds
Started Jul 30 05:22:57 PM PDT 24
Finished Jul 30 05:23:13 PM PDT 24
Peak memory 226352 kb
Host smart-a21ac1ac-b22d-4194-bd44-b80859745404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668079258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3668079258
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1166401764
Short name T92
Test name
Test status
Simulation time 124163250 ps
CPU time 3.32 seconds
Started Jul 30 05:56:04 PM PDT 24
Finished Jul 30 05:56:07 PM PDT 24
Peak memory 217704 kb
Host smart-92f93008-c5bf-440d-a319-9d1f3dcce162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166401764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1166401764
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.562598080
Short name T103
Test name
Test status
Simulation time 88739425 ps
CPU time 3.71 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 222568 kb
Host smart-c089a4ec-7517-487a-abc8-0bf7e32ae585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562598080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.562598080
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1340363183
Short name T106
Test name
Test status
Simulation time 435003077 ps
CPU time 3.22 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:33 PM PDT 24
Peak memory 217672 kb
Host smart-95b3f982-9bab-4382-851e-5187f7273d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340363183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1340363183
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2532245163
Short name T97
Test name
Test status
Simulation time 167829020 ps
CPU time 1.9 seconds
Started Jul 30 05:56:28 PM PDT 24
Finished Jul 30 05:56:30 PM PDT 24
Peak memory 221340 kb
Host smart-767fc569-3c8c-4ab1-a7be-86e936345df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532245163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2532245163
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3147518954
Short name T122
Test name
Test status
Simulation time 30319975 ps
CPU time 1.16 seconds
Started Jul 30 05:56:05 PM PDT 24
Finished Jul 30 05:56:06 PM PDT 24
Peak memory 209620 kb
Host smart-1c15afdd-eea2-422c-ac0a-19bc980a47e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147518954 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3147518954
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3944483292
Short name T10
Test name
Test status
Simulation time 34669596 ps
CPU time 0.95 seconds
Started Jul 30 05:25:06 PM PDT 24
Finished Jul 30 05:25:07 PM PDT 24
Peak memory 217852 kb
Host smart-1e1b8eec-2498-4027-91ea-1fb36a57ad73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944483292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3944483292
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2978076116
Short name T118
Test name
Test status
Simulation time 485317429 ps
CPU time 4.56 seconds
Started Jul 30 05:56:31 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 217692 kb
Host smart-18c97ae8-3319-4483-9042-63e8e7cb4ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978076116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2978076116
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1892497490
Short name T102
Test name
Test status
Simulation time 127358225 ps
CPU time 3.53 seconds
Started Jul 30 05:56:27 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 222340 kb
Host smart-b2a637f2-5986-41f7-a1b6-6c0e9a1d7650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892497490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1892497490
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2106613671
Short name T193
Test name
Test status
Simulation time 24170322 ps
CPU time 0.82 seconds
Started Jul 30 05:21:44 PM PDT 24
Finished Jul 30 05:21:45 PM PDT 24
Peak memory 208776 kb
Host smart-1a138346-4772-4de0-93e6-0cea10610fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106613671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2106613671
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4199744099
Short name T198
Test name
Test status
Simulation time 36139876 ps
CPU time 0.92 seconds
Started Jul 30 05:21:48 PM PDT 24
Finished Jul 30 05:21:50 PM PDT 24
Peak memory 208916 kb
Host smart-85627ba0-eb29-4e19-9117-a7914efcd5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199744099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4199744099
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.108354152
Short name T194
Test name
Test status
Simulation time 12991053 ps
CPU time 0.86 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:21:54 PM PDT 24
Peak memory 208816 kb
Host smart-bc40c1f7-6a2e-4ea3-b32a-e89e5eb85e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108354152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.108354152
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2889171355
Short name T195
Test name
Test status
Simulation time 40763909 ps
CPU time 0.83 seconds
Started Jul 30 05:22:10 PM PDT 24
Finished Jul 30 05:22:11 PM PDT 24
Peak memory 209204 kb
Host smart-e97f4998-1b8e-4578-aaf5-e18e4cf320c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889171355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2889171355
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2814631655
Short name T116
Test name
Test status
Simulation time 65545891 ps
CPU time 2.16 seconds
Started Jul 30 05:56:09 PM PDT 24
Finished Jul 30 05:56:11 PM PDT 24
Peak memory 222336 kb
Host smart-6fe445b2-df82-4c6a-b3e0-92f99a38ceae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814631655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2814631655
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.665450665
Short name T117
Test name
Test status
Simulation time 414313693 ps
CPU time 2.33 seconds
Started Jul 30 05:56:37 PM PDT 24
Finished Jul 30 05:56:39 PM PDT 24
Peak memory 222568 kb
Host smart-77c4ce64-cc69-454e-934e-e06668afa2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665450665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.665450665
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3690962000
Short name T107
Test name
Test status
Simulation time 554991919 ps
CPU time 3.78 seconds
Started Jul 30 05:56:18 PM PDT 24
Finished Jul 30 05:56:22 PM PDT 24
Peak memory 217740 kb
Host smart-6658ad97-6533-48c6-8651-90c2be2feac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690962000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3690962000
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3058731906
Short name T43
Test name
Test status
Simulation time 14296579265 ps
CPU time 477.06 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:29:50 PM PDT 24
Peak memory 303924 kb
Host smart-aec5720e-0d7f-433b-930d-1bbe9910c66a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058731906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3058731906
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2655059986
Short name T5
Test name
Test status
Simulation time 1491539695 ps
CPU time 26.11 seconds
Started Jul 30 05:22:58 PM PDT 24
Finished Jul 30 05:23:24 PM PDT 24
Peak memory 218176 kb
Host smart-410a2ff0-c1b6-4946-b0f9-1c99de13f90c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655059986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2655059986
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2555808072
Short name T76
Test name
Test status
Simulation time 202859737 ps
CPU time 2.34 seconds
Started Jul 30 05:22:55 PM PDT 24
Finished Jul 30 05:22:57 PM PDT 24
Peak memory 222528 kb
Host smart-9565c2cb-8d4d-42f7-8dee-4e60bc941984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555808072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2555808072
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1444410295
Short name T898
Test name
Test status
Simulation time 45194985 ps
CPU time 1.04 seconds
Started Jul 30 05:56:03 PM PDT 24
Finished Jul 30 05:56:04 PM PDT 24
Peak memory 209572 kb
Host smart-e6ef63f5-3dfd-4478-8451-f6ecb8df9bd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444410295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1444410295
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2477522648
Short name T906
Test name
Test status
Simulation time 69804020 ps
CPU time 2.79 seconds
Started Jul 30 05:56:06 PM PDT 24
Finished Jul 30 05:56:09 PM PDT 24
Peak memory 209512 kb
Host smart-d8c68ed3-1482-47cb-9ceb-03e9864ef9fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477522648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2477522648
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3708731604
Short name T950
Test name
Test status
Simulation time 15677595 ps
CPU time 1.12 seconds
Started Jul 30 05:56:04 PM PDT 24
Finished Jul 30 05:56:05 PM PDT 24
Peak memory 217728 kb
Host smart-4607291b-0a00-4192-96bb-a3676f5d438d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708731604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3708731604
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2243198102
Short name T981
Test name
Test status
Simulation time 26747448 ps
CPU time 1.19 seconds
Started Jul 30 05:56:05 PM PDT 24
Finished Jul 30 05:56:06 PM PDT 24
Peak memory 217844 kb
Host smart-e713a084-a8e0-4b02-929d-6782a346536c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243198102 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2243198102
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2375133110
Short name T968
Test name
Test status
Simulation time 47198720 ps
CPU time 0.95 seconds
Started Jul 30 05:56:07 PM PDT 24
Finished Jul 30 05:56:08 PM PDT 24
Peak memory 209488 kb
Host smart-f9b06ad1-df50-42cf-aade-d201d581cd25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375133110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2375133110
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4005048155
Short name T937
Test name
Test status
Simulation time 163551590 ps
CPU time 1.3 seconds
Started Jul 30 05:56:03 PM PDT 24
Finished Jul 30 05:56:04 PM PDT 24
Peak memory 209300 kb
Host smart-62272376-e014-4148-a74c-a8669835d59d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005048155 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4005048155
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2377482497
Short name T123
Test name
Test status
Simulation time 1030022370 ps
CPU time 12.12 seconds
Started Jul 30 05:56:02 PM PDT 24
Finished Jul 30 05:56:15 PM PDT 24
Peak memory 209296 kb
Host smart-0b37a76e-55ce-4810-9315-f7a5f551eaec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377482497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2377482497
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1171910918
Short name T867
Test name
Test status
Simulation time 2636381508 ps
CPU time 9.58 seconds
Started Jul 30 05:56:01 PM PDT 24
Finished Jul 30 05:56:10 PM PDT 24
Peak memory 208804 kb
Host smart-f8d405e0-a4d7-45ac-8d88-e7852001331e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171910918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1171910918
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2861746467
Short name T928
Test name
Test status
Simulation time 321166297 ps
CPU time 2.73 seconds
Started Jul 30 05:56:01 PM PDT 24
Finished Jul 30 05:56:04 PM PDT 24
Peak memory 210956 kb
Host smart-30995454-a29e-47d1-ae65-de7c0f83317b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861746467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2861746467
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2565582031
Short name T943
Test name
Test status
Simulation time 323417393 ps
CPU time 2.46 seconds
Started Jul 30 05:56:00 PM PDT 24
Finished Jul 30 05:56:02 PM PDT 24
Peak memory 209432 kb
Host smart-a5a96c17-fac6-4498-b316-080670f969d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565582031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2565582031
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2204813949
Short name T924
Test name
Test status
Simulation time 56156349 ps
CPU time 1.17 seconds
Started Jul 30 05:56:03 PM PDT 24
Finished Jul 30 05:56:04 PM PDT 24
Peak memory 209496 kb
Host smart-49a87c67-7b2a-419a-9d18-ac5df8359fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204813949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2204813949
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4275781097
Short name T121
Test name
Test status
Simulation time 32488474 ps
CPU time 1.3 seconds
Started Jul 30 05:56:12 PM PDT 24
Finished Jul 30 05:56:13 PM PDT 24
Peak memory 209552 kb
Host smart-fb626da2-1313-4015-aa50-b640ff1eb0d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275781097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4275781097
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3055807019
Short name T909
Test name
Test status
Simulation time 130167099 ps
CPU time 1.31 seconds
Started Jul 30 05:56:10 PM PDT 24
Finished Jul 30 05:56:11 PM PDT 24
Peak memory 209472 kb
Host smart-3c05b08f-b68f-4859-a015-ce30e8efda1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055807019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3055807019
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.330236189
Short name T915
Test name
Test status
Simulation time 17655294 ps
CPU time 0.93 seconds
Started Jul 30 05:56:11 PM PDT 24
Finished Jul 30 05:56:12 PM PDT 24
Peak memory 209948 kb
Host smart-ebc5a008-1bdc-407b-98ff-4bae75b8d095
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330236189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.330236189
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1099767372
Short name T958
Test name
Test status
Simulation time 36572898 ps
CPU time 1.34 seconds
Started Jul 30 05:56:07 PM PDT 24
Finished Jul 30 05:56:09 PM PDT 24
Peak memory 218888 kb
Host smart-d8af0fe2-fb45-4b3a-bde8-4fc1176c60bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099767372 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1099767372
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.52423230
Short name T177
Test name
Test status
Simulation time 19551254 ps
CPU time 1.02 seconds
Started Jul 30 05:56:09 PM PDT 24
Finished Jul 30 05:56:11 PM PDT 24
Peak memory 209444 kb
Host smart-d9906569-c459-4849-ac5b-187ff7741825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52423230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.52423230
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.473682777
Short name T883
Test name
Test status
Simulation time 115240957 ps
CPU time 1.02 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:15 PM PDT 24
Peak memory 209292 kb
Host smart-75915212-21e1-45bf-8bbc-a93ede6d56b8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473682777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.473682777
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3294470117
Short name T931
Test name
Test status
Simulation time 789846148 ps
CPU time 3.55 seconds
Started Jul 30 05:56:05 PM PDT 24
Finished Jul 30 05:56:08 PM PDT 24
Peak memory 208716 kb
Host smart-9bca8a47-6677-47c2-b5b9-5f63e5c2c00a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294470117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3294470117
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2968146618
Short name T879
Test name
Test status
Simulation time 1678597254 ps
CPU time 7.52 seconds
Started Jul 30 05:56:04 PM PDT 24
Finished Jul 30 05:56:12 PM PDT 24
Peak memory 208172 kb
Host smart-dcee8a5d-5dae-4b59-b412-f83fbc99beed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968146618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2968146618
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.405351638
Short name T979
Test name
Test status
Simulation time 195725503 ps
CPU time 1.37 seconds
Started Jul 30 05:56:06 PM PDT 24
Finished Jul 30 05:56:08 PM PDT 24
Peak memory 210892 kb
Host smart-0e424128-874d-43ad-8d1f-b1fe60f706d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405351638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.405351638
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2642616959
Short name T110
Test name
Test status
Simulation time 125161993 ps
CPU time 2.39 seconds
Started Jul 30 05:56:05 PM PDT 24
Finished Jul 30 05:56:07 PM PDT 24
Peak memory 218880 kb
Host smart-4cc63373-8072-4d5c-9dcf-90ce64581d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264261
6959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2642616959
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.826729086
Short name T124
Test name
Test status
Simulation time 47994850 ps
CPU time 1.78 seconds
Started Jul 30 05:56:08 PM PDT 24
Finished Jul 30 05:56:10 PM PDT 24
Peak memory 209392 kb
Host smart-b5d2088d-9686-4878-b32e-a3a71c402386
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826729086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.826729086
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2055384428
Short name T936
Test name
Test status
Simulation time 43520375 ps
CPU time 1.98 seconds
Started Jul 30 05:56:04 PM PDT 24
Finished Jul 30 05:56:06 PM PDT 24
Peak memory 211648 kb
Host smart-226a122a-a03d-4467-9dd5-7fc441d76f87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055384428 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2055384428
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3223059432
Short name T969
Test name
Test status
Simulation time 152454130 ps
CPU time 1.08 seconds
Started Jul 30 05:56:13 PM PDT 24
Finished Jul 30 05:56:14 PM PDT 24
Peak memory 209460 kb
Host smart-1ce833fb-6b75-4d92-aed8-3d98fd6895b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223059432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3223059432
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.288798868
Short name T114
Test name
Test status
Simulation time 27375086 ps
CPU time 2.1 seconds
Started Jul 30 05:56:10 PM PDT 24
Finished Jul 30 05:56:12 PM PDT 24
Peak memory 218044 kb
Host smart-d231b464-97b0-4a59-8cc3-5136669f27e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288798868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.288798868
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.411187951
Short name T882
Test name
Test status
Simulation time 24690824 ps
CPU time 1.55 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 222024 kb
Host smart-5fcbf8ea-1270-4d72-bf00-096f1955eac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411187951 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.411187951
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2504641006
Short name T183
Test name
Test status
Simulation time 23846112 ps
CPU time 0.98 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 209484 kb
Host smart-2b7cdb3e-c829-4192-b814-75db92c3a91c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504641006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2504641006
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4270962410
Short name T188
Test name
Test status
Simulation time 148647226 ps
CPU time 1.24 seconds
Started Jul 30 05:56:31 PM PDT 24
Finished Jul 30 05:56:33 PM PDT 24
Peak memory 209384 kb
Host smart-57b6c2f5-87e8-4f6a-8ddc-f1398a3b2386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270962410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.4270962410
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.187803904
Short name T900
Test name
Test status
Simulation time 43361541 ps
CPU time 2.15 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 217688 kb
Host smart-aa118c2d-0f16-411b-8d1e-3e20a9548fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187803904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.187803904
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2091825601
Short name T941
Test name
Test status
Simulation time 14378202 ps
CPU time 1.02 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 209504 kb
Host smart-0a0182eb-eb57-4101-ab17-cfef5e045d70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091825601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2091825601
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1489731462
Short name T896
Test name
Test status
Simulation time 68030125 ps
CPU time 1.38 seconds
Started Jul 30 05:56:28 PM PDT 24
Finished Jul 30 05:56:29 PM PDT 24
Peak memory 209520 kb
Host smart-cea77d96-3bdf-4e02-891a-4f539bfc85bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489731462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1489731462
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3830255208
Short name T901
Test name
Test status
Simulation time 60132631 ps
CPU time 2.25 seconds
Started Jul 30 05:56:28 PM PDT 24
Finished Jul 30 05:56:30 PM PDT 24
Peak memory 218040 kb
Host smart-b6ceb105-0557-40d7-a106-3a5141730b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830255208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3830255208
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4172853762
Short name T972
Test name
Test status
Simulation time 36083857 ps
CPU time 1.02 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 220144 kb
Host smart-3f0c9f1b-b720-41f4-8df8-40c6a9683478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172853762 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4172853762
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3517051958
Short name T948
Test name
Test status
Simulation time 20348958 ps
CPU time 0.94 seconds
Started Jul 30 05:56:33 PM PDT 24
Finished Jul 30 05:56:34 PM PDT 24
Peak memory 209416 kb
Host smart-3dddd8b8-45e6-4b1d-828a-cb6a252ba7b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517051958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3517051958
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.115619241
Short name T892
Test name
Test status
Simulation time 102230343 ps
CPU time 1.11 seconds
Started Jul 30 05:56:28 PM PDT 24
Finished Jul 30 05:56:30 PM PDT 24
Peak memory 209492 kb
Host smart-d88e6313-0e5a-4d34-8bbe-8ec03f5c27d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115619241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.115619241
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2230818589
Short name T976
Test name
Test status
Simulation time 229954104 ps
CPU time 2.51 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 217708 kb
Host smart-a4599039-329f-40c6-91e2-9d492bffbf87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230818589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2230818589
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3837090517
Short name T105
Test name
Test status
Simulation time 112773603 ps
CPU time 4.17 seconds
Started Jul 30 05:56:31 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 217684 kb
Host smart-aba06636-6bea-45b0-a7e5-756a2d91fff7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837090517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3837090517
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3938967163
Short name T876
Test name
Test status
Simulation time 30033386 ps
CPU time 1.4 seconds
Started Jul 30 05:56:32 PM PDT 24
Finished Jul 30 05:56:34 PM PDT 24
Peak memory 218712 kb
Host smart-ca88f1be-cbb0-4055-972b-3be612053f96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938967163 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3938967163
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.343114823
Short name T966
Test name
Test status
Simulation time 69924930 ps
CPU time 0.83 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 208924 kb
Host smart-dfbb20e9-21a0-4829-87ae-5196ebdb96a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343114823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.343114823
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4072320667
Short name T905
Test name
Test status
Simulation time 28158919 ps
CPU time 1.14 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 209552 kb
Host smart-3fbb2f49-7af8-4828-bc48-944a93d07f6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072320667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4072320667
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3763794186
Short name T933
Test name
Test status
Simulation time 58939256 ps
CPU time 2.56 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 217728 kb
Host smart-69ef73fe-e50e-499f-a6f9-2e1f3af1eab8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763794186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3763794186
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4118194391
Short name T881
Test name
Test status
Simulation time 62198728 ps
CPU time 1.27 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 217976 kb
Host smart-3003d876-99c6-49fc-b9e1-8a8e34e41e66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118194391 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4118194391
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2455168381
Short name T190
Test name
Test status
Simulation time 38839906 ps
CPU time 0.98 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 209408 kb
Host smart-afe114f0-72d8-43f8-8209-fdeff3543c71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455168381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2455168381
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1239302132
Short name T187
Test name
Test status
Simulation time 82116662 ps
CPU time 1.51 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 211596 kb
Host smart-515422b6-4edd-4c3d-87d8-eb2b8bf17b4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239302132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1239302132
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.150287813
Short name T983
Test name
Test status
Simulation time 209749651 ps
CPU time 4.81 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:39 PM PDT 24
Peak memory 217712 kb
Host smart-0592b274-453a-4855-88ae-00f6a29733c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150287813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.150287813
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3365610366
Short name T113
Test name
Test status
Simulation time 45522142 ps
CPU time 2.34 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 222436 kb
Host smart-a53cadbc-30ce-4727-9611-3c6ffc744572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365610366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3365610366
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2881507258
Short name T942
Test name
Test status
Simulation time 23661661 ps
CPU time 1.41 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 219488 kb
Host smart-6f14faa1-e3c4-4138-88f2-62220975cae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881507258 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2881507258
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3202982510
Short name T869
Test name
Test status
Simulation time 47951600 ps
CPU time 0.87 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 208996 kb
Host smart-d841e5e0-69cf-4a75-9776-fff7067cd133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202982510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3202982510
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2407447731
Short name T967
Test name
Test status
Simulation time 83885240 ps
CPU time 1.05 seconds
Started Jul 30 05:56:33 PM PDT 24
Finished Jul 30 05:56:34 PM PDT 24
Peak memory 209520 kb
Host smart-6b8944d4-027f-40ea-be91-9a9eb861e33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407447731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2407447731
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.337841066
Short name T916
Test name
Test status
Simulation time 23679082 ps
CPU time 1.84 seconds
Started Jul 30 05:56:32 PM PDT 24
Finished Jul 30 05:56:34 PM PDT 24
Peak memory 217824 kb
Host smart-3fa8dd01-b27e-4570-8ebf-74b45c9fa9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337841066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.337841066
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3115874964
Short name T115
Test name
Test status
Simulation time 67344087 ps
CPU time 2.13 seconds
Started Jul 30 05:56:36 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 222168 kb
Host smart-a0207cc9-6fcf-440f-aa2c-1b5429985435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115874964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3115874964
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.384083537
Short name T947
Test name
Test status
Simulation time 60596632 ps
CPU time 1.21 seconds
Started Jul 30 05:56:33 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 218904 kb
Host smart-d6884e1a-5ec3-4bec-b620-3b0d257c634b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384083537 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.384083537
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1324069868
Short name T957
Test name
Test status
Simulation time 51453771 ps
CPU time 1.37 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 211604 kb
Host smart-cd2584af-5d8f-43d3-9185-5f40fbc75cb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324069868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1324069868
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.296794706
Short name T91
Test name
Test status
Simulation time 53101546 ps
CPU time 2.73 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 217788 kb
Host smart-f706fabc-04ff-46b5-9fb7-603415e484eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296794706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.296794706
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3845715409
Short name T982
Test name
Test status
Simulation time 213715038 ps
CPU time 2.85 seconds
Started Jul 30 05:56:33 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 222420 kb
Host smart-c2799496-e38f-4972-aa6a-190d0cf312cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845715409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3845715409
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2581299924
Short name T885
Test name
Test status
Simulation time 46480584 ps
CPU time 1.54 seconds
Started Jul 30 05:56:37 PM PDT 24
Finished Jul 30 05:56:39 PM PDT 24
Peak memory 222180 kb
Host smart-76f82d76-33cc-49f0-9028-87bbdb9d00ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581299924 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2581299924
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3073850311
Short name T186
Test name
Test status
Simulation time 17096861 ps
CPU time 0.92 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 209536 kb
Host smart-edcb7108-fecc-4624-aeb0-a5374119bdf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073850311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3073850311
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2752544710
Short name T921
Test name
Test status
Simulation time 55779587 ps
CPU time 0.99 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 217692 kb
Host smart-093088da-ffe2-465c-9562-01529d05ea4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752544710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2752544710
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.795613999
Short name T913
Test name
Test status
Simulation time 46769929 ps
CPU time 3.08 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 217812 kb
Host smart-33144ac5-6225-496d-b317-ae29747e7708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795613999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.795613999
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1977647689
Short name T951
Test name
Test status
Simulation time 69065341 ps
CPU time 1.26 seconds
Started Jul 30 05:56:38 PM PDT 24
Finished Jul 30 05:56:39 PM PDT 24
Peak memory 217760 kb
Host smart-676d7445-e79c-4f56-b03a-34af9d28aa5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977647689 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1977647689
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2079140289
Short name T180
Test name
Test status
Simulation time 76466031 ps
CPU time 0.9 seconds
Started Jul 30 05:56:35 PM PDT 24
Finished Jul 30 05:56:36 PM PDT 24
Peak memory 209468 kb
Host smart-e16d26d6-016f-44e3-9824-7c3cef337fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079140289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2079140289
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.189872919
Short name T987
Test name
Test status
Simulation time 23061975 ps
CPU time 1.21 seconds
Started Jul 30 05:56:36 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 209216 kb
Host smart-813e83d3-078d-4a08-ac01-b1a181cbea75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189872919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.189872919
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1418824520
Short name T101
Test name
Test status
Simulation time 613777980 ps
CPU time 3.72 seconds
Started Jul 30 05:56:34 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 218720 kb
Host smart-5ceb777a-a147-4368-afd8-5d730d2b8d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418824520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1418824520
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.184334821
Short name T902
Test name
Test status
Simulation time 28870024 ps
CPU time 1.36 seconds
Started Jul 30 05:56:36 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 219160 kb
Host smart-f6bbbc74-a1b8-4314-b113-682919c9ca50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184334821 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.184334821
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2665674181
Short name T181
Test name
Test status
Simulation time 12562175 ps
CPU time 0.89 seconds
Started Jul 30 05:56:36 PM PDT 24
Finished Jul 30 05:56:37 PM PDT 24
Peak memory 209444 kb
Host smart-68ee9d79-58dd-4280-93c1-1e6c8a09a26d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665674181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2665674181
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2846365662
Short name T191
Test name
Test status
Simulation time 22200036 ps
CPU time 1.24 seconds
Started Jul 30 05:56:37 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 209584 kb
Host smart-7d93331a-8f7a-4ec4-8329-d42c3114ad59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846365662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2846365662
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.751178399
Short name T90
Test name
Test status
Simulation time 70939094 ps
CPU time 1.31 seconds
Started Jul 30 05:56:37 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 218788 kb
Host smart-3d4e3948-b76b-432e-82ef-4aa4e6e0ce4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751178399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.751178399
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3107610648
Short name T119
Test name
Test status
Simulation time 46324031 ps
CPU time 2.47 seconds
Started Jul 30 05:56:39 PM PDT 24
Finished Jul 30 05:56:41 PM PDT 24
Peak memory 213304 kb
Host smart-9408712d-66e1-40fa-918b-8af1b87e5d59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107610648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3107610648
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1461052059
Short name T994
Test name
Test status
Simulation time 89607699 ps
CPU time 1.06 seconds
Started Jul 30 05:56:12 PM PDT 24
Finished Jul 30 05:56:13 PM PDT 24
Peak memory 209484 kb
Host smart-53465087-10bf-45b6-8232-9094a6a36a02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461052059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1461052059
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.253801012
Short name T184
Test name
Test status
Simulation time 101091235 ps
CPU time 1.73 seconds
Started Jul 30 05:56:15 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 209264 kb
Host smart-320887b0-7a6c-4cc1-8b5f-77b4dae50b23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253801012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.253801012
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.103173891
Short name T973
Test name
Test status
Simulation time 251595007 ps
CPU time 1 seconds
Started Jul 30 05:56:08 PM PDT 24
Finished Jul 30 05:56:09 PM PDT 24
Peak memory 217700 kb
Host smart-0bde8588-00a6-4c92-b111-d1e65aadee1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103173891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.103173891
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2653886127
Short name T964
Test name
Test status
Simulation time 20451315 ps
CPU time 1.51 seconds
Started Jul 30 05:56:15 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 219872 kb
Host smart-b37a594f-4176-4055-abb1-8116259485ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653886127 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2653886127
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3581680847
Short name T884
Test name
Test status
Simulation time 13829898 ps
CPU time 0.95 seconds
Started Jul 30 05:56:13 PM PDT 24
Finished Jul 30 05:56:14 PM PDT 24
Peak memory 209276 kb
Host smart-5e0fc815-f35b-4c70-bd23-770a32a9a1bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581680847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3581680847
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1753641374
Short name T986
Test name
Test status
Simulation time 244596965 ps
CPU time 2.09 seconds
Started Jul 30 05:56:10 PM PDT 24
Finished Jul 30 05:56:12 PM PDT 24
Peak memory 209288 kb
Host smart-33efe801-1807-46b9-8a7c-7d0f3f307271
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753641374 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1753641374
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1777874227
Short name T993
Test name
Test status
Simulation time 374924386 ps
CPU time 4.87 seconds
Started Jul 30 05:56:11 PM PDT 24
Finished Jul 30 05:56:16 PM PDT 24
Peak memory 209252 kb
Host smart-fe9b4add-3532-4e97-a667-6bc5b578a925
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777874227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1777874227
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3006484436
Short name T965
Test name
Test status
Simulation time 1924309928 ps
CPU time 11.78 seconds
Started Jul 30 05:56:10 PM PDT 24
Finished Jul 30 05:56:22 PM PDT 24
Peak memory 209200 kb
Host smart-d2494bfe-75ba-4e68-b9d1-c1ff6f0a4ebb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006484436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3006484436
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.108761514
Short name T919
Test name
Test status
Simulation time 206423940 ps
CPU time 2.77 seconds
Started Jul 30 05:56:08 PM PDT 24
Finished Jul 30 05:56:10 PM PDT 24
Peak memory 210856 kb
Host smart-6271cae2-9c28-4dcd-b728-f488ba47bdab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108761514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.108761514
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1069150316
Short name T891
Test name
Test status
Simulation time 266182789 ps
CPU time 2.24 seconds
Started Jul 30 05:56:09 PM PDT 24
Finished Jul 30 05:56:11 PM PDT 24
Peak memory 217812 kb
Host smart-7de74d93-c8d2-4e3d-9958-f03d42754b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106915
0316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1069150316
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2635912174
Short name T954
Test name
Test status
Simulation time 66056696 ps
CPU time 1.38 seconds
Started Jul 30 05:56:08 PM PDT 24
Finished Jul 30 05:56:10 PM PDT 24
Peak memory 209412 kb
Host smart-43997308-d07f-420a-9c37-6c94b4583b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635912174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2635912174
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1513060275
Short name T977
Test name
Test status
Simulation time 42494905 ps
CPU time 1.01 seconds
Started Jul 30 05:56:08 PM PDT 24
Finished Jul 30 05:56:09 PM PDT 24
Peak memory 209560 kb
Host smart-355eb875-6ce2-42d1-b646-a0b223c46db2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513060275 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1513060275
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1771989996
Short name T978
Test name
Test status
Simulation time 15537703 ps
CPU time 1.17 seconds
Started Jul 30 05:56:17 PM PDT 24
Finished Jul 30 05:56:18 PM PDT 24
Peak memory 209496 kb
Host smart-d40c583e-6b40-44ee-821e-8a98bbeb1e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771989996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1771989996
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2608866860
Short name T991
Test name
Test status
Simulation time 806141437 ps
CPU time 3.38 seconds
Started Jul 30 05:56:09 PM PDT 24
Finished Jul 30 05:56:12 PM PDT 24
Peak memory 217716 kb
Host smart-09c508eb-e69d-4e8a-b111-d7f44e2a918c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608866860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2608866860
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2914296628
Short name T904
Test name
Test status
Simulation time 90563485 ps
CPU time 2.82 seconds
Started Jul 30 05:56:08 PM PDT 24
Finished Jul 30 05:56:11 PM PDT 24
Peak memory 217632 kb
Host smart-3ae8e099-7397-4f4b-9a28-817f7bb1d205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914296628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2914296628
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2246101586
Short name T911
Test name
Test status
Simulation time 41679743 ps
CPU time 1.04 seconds
Started Jul 30 05:56:17 PM PDT 24
Finished Jul 30 05:56:18 PM PDT 24
Peak memory 209424 kb
Host smart-84b5c0a7-e6e8-46f2-9695-66e36f27f69d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246101586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2246101586
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1222834974
Short name T880
Test name
Test status
Simulation time 67688047 ps
CPU time 1.81 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:16 PM PDT 24
Peak memory 209488 kb
Host smart-d4c7bd0a-5bf9-4c6a-a42d-5f2e93bd2bcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222834974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1222834974
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.326416947
Short name T971
Test name
Test status
Simulation time 21304347 ps
CPU time 1.34 seconds
Started Jul 30 05:56:11 PM PDT 24
Finished Jul 30 05:56:13 PM PDT 24
Peak memory 211596 kb
Host smart-552da62f-fd4f-4219-8d93-cc94e3372eff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326416947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.326416947
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.35514182
Short name T875
Test name
Test status
Simulation time 51266885 ps
CPU time 1.96 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:16 PM PDT 24
Peak memory 218964 kb
Host smart-25c1228e-8e9a-4b2a-a34e-cc2374b423f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35514182 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.35514182
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2190832577
Short name T179
Test name
Test status
Simulation time 16312085 ps
CPU time 0.94 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:15 PM PDT 24
Peak memory 209532 kb
Host smart-e827de8f-750a-4d3b-9b2b-1986eaeab8dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190832577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2190832577
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4062311078
Short name T922
Test name
Test status
Simulation time 123890537 ps
CPU time 1.94 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:16 PM PDT 24
Peak memory 209256 kb
Host smart-de2ad7d4-d5ce-4d20-ae2b-6950f76a466a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062311078 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.4062311078
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4277237288
Short name T897
Test name
Test status
Simulation time 477374631 ps
CPU time 4.17 seconds
Started Jul 30 05:56:11 PM PDT 24
Finished Jul 30 05:56:15 PM PDT 24
Peak memory 208724 kb
Host smart-8c091b4f-6449-417c-941e-07107a521c66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277237288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4277237288
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1964291244
Short name T871
Test name
Test status
Simulation time 2474087073 ps
CPU time 11.65 seconds
Started Jul 30 05:56:11 PM PDT 24
Finished Jul 30 05:56:23 PM PDT 24
Peak memory 209464 kb
Host smart-f4603574-58ee-4b84-986c-2b0b27553691
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964291244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1964291244
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.621408471
Short name T946
Test name
Test status
Simulation time 510754325 ps
CPU time 3.5 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 211008 kb
Host smart-90945dc3-8277-4fac-b4fd-9a63c7e0ad11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621408471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.621408471
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3876497239
Short name T944
Test name
Test status
Simulation time 385238049 ps
CPU time 2.28 seconds
Started Jul 30 05:56:15 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 217796 kb
Host smart-5572796b-ae06-4b49-971d-4f143f4b78e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387649
7239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3876497239
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2333823975
Short name T945
Test name
Test status
Simulation time 47490356 ps
CPU time 1.81 seconds
Started Jul 30 05:56:13 PM PDT 24
Finished Jul 30 05:56:14 PM PDT 24
Peak memory 209356 kb
Host smart-ac74b8cc-4ab1-430d-815a-c434802aae19
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333823975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2333823975
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4237187757
Short name T949
Test name
Test status
Simulation time 40979364 ps
CPU time 1.12 seconds
Started Jul 30 05:56:11 PM PDT 24
Finished Jul 30 05:56:12 PM PDT 24
Peak memory 209160 kb
Host smart-1de291ce-ec9b-47ed-b934-b7b4ac261a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237187757 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.4237187757
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.258903368
Short name T960
Test name
Test status
Simulation time 155995087 ps
CPU time 1.96 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:16 PM PDT 24
Peak memory 209276 kb
Host smart-e4a6edbb-819a-4661-a642-feb30f12f9f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258903368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.258903368
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2598703069
Short name T111
Test name
Test status
Simulation time 1143918241 ps
CPU time 2.74 seconds
Started Jul 30 05:56:12 PM PDT 24
Finished Jul 30 05:56:15 PM PDT 24
Peak memory 217660 kb
Host smart-8b4d7649-e9e8-40b1-8408-c7428836364d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598703069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2598703069
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3345954399
Short name T136
Test name
Test status
Simulation time 75468482 ps
CPU time 1.08 seconds
Started Jul 30 05:56:17 PM PDT 24
Finished Jul 30 05:56:18 PM PDT 24
Peak memory 208820 kb
Host smart-d7f4de44-1715-4589-a84b-178982a30d17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345954399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3345954399
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2298972338
Short name T868
Test name
Test status
Simulation time 126028327 ps
CPU time 2.73 seconds
Started Jul 30 05:56:15 PM PDT 24
Finished Jul 30 05:56:18 PM PDT 24
Peak memory 209448 kb
Host smart-83c7c99d-bd50-4f4f-9dd8-177c49475c91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298972338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2298972338
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2694296101
Short name T874
Test name
Test status
Simulation time 32408637 ps
CPU time 0.92 seconds
Started Jul 30 05:56:16 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 209632 kb
Host smart-2f7f2f03-b484-4479-a3e0-526a3df46c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694296101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2694296101
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1534496230
Short name T877
Test name
Test status
Simulation time 18466712 ps
CPU time 1.06 seconds
Started Jul 30 05:56:16 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 217852 kb
Host smart-2cb0c3b2-33c8-4ec2-8efc-74f839291d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534496230 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1534496230
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3312351235
Short name T920
Test name
Test status
Simulation time 12489505 ps
CPU time 0.96 seconds
Started Jul 30 05:56:17 PM PDT 24
Finished Jul 30 05:56:18 PM PDT 24
Peak memory 209508 kb
Host smart-832f7d15-be72-4270-9122-a4c7cd411860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312351235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3312351235
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2948595557
Short name T926
Test name
Test status
Simulation time 853639752 ps
CPU time 2.06 seconds
Started Jul 30 05:56:18 PM PDT 24
Finished Jul 30 05:56:20 PM PDT 24
Peak memory 209296 kb
Host smart-3e791d93-cf1b-4cfc-ab13-00ca38775fed
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948595557 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2948595557
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2620587330
Short name T984
Test name
Test status
Simulation time 2050763906 ps
CPU time 6.07 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:25 PM PDT 24
Peak memory 209348 kb
Host smart-bc9b979e-1866-4b7d-a5ff-f444e695224b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620587330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2620587330
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4209456790
Short name T952
Test name
Test status
Simulation time 490136265 ps
CPU time 6.34 seconds
Started Jul 30 05:56:13 PM PDT 24
Finished Jul 30 05:56:20 PM PDT 24
Peak memory 209232 kb
Host smart-78bce74f-ba9a-4ab9-94b7-c7872ab3e214
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209456790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4209456790
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2184623795
Short name T887
Test name
Test status
Simulation time 54424184 ps
CPU time 1.33 seconds
Started Jul 30 05:56:14 PM PDT 24
Finished Jul 30 05:56:15 PM PDT 24
Peak memory 210952 kb
Host smart-194a06b9-c5be-439b-ae8f-c4389c8b0fc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184623795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2184623795
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1886670323
Short name T899
Test name
Test status
Simulation time 251568807 ps
CPU time 1.68 seconds
Started Jul 30 05:56:17 PM PDT 24
Finished Jul 30 05:56:19 PM PDT 24
Peak memory 217896 kb
Host smart-338a8d4b-d2fb-4858-8f28-061e8d6fd7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188667
0323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1886670323
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.966845664
Short name T894
Test name
Test status
Simulation time 255647552 ps
CPU time 1.46 seconds
Started Jul 30 05:56:15 PM PDT 24
Finished Jul 30 05:56:17 PM PDT 24
Peak memory 208576 kb
Host smart-d26625ac-f62c-44dc-970b-ba2b43f3c1cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966845664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.966845664
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4177371267
Short name T910
Test name
Test status
Simulation time 16140108 ps
CPU time 1.02 seconds
Started Jul 30 05:56:18 PM PDT 24
Finished Jul 30 05:56:19 PM PDT 24
Peak memory 209388 kb
Host smart-051430bb-b401-4dd9-a558-744d9155517b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177371267 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4177371267
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1175095736
Short name T895
Test name
Test status
Simulation time 294424015 ps
CPU time 2.12 seconds
Started Jul 30 05:56:18 PM PDT 24
Finished Jul 30 05:56:20 PM PDT 24
Peak memory 209564 kb
Host smart-544bc953-83b9-4192-90e8-21ecf5b50a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175095736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1175095736
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3848344320
Short name T927
Test name
Test status
Simulation time 108162361 ps
CPU time 3.12 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:22 PM PDT 24
Peak memory 217724 kb
Host smart-bb1da9f4-d929-42d5-b9b5-3c978a586650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848344320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3848344320
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3952376887
Short name T907
Test name
Test status
Simulation time 75767369 ps
CPU time 1.33 seconds
Started Jul 30 05:56:23 PM PDT 24
Finished Jul 30 05:56:25 PM PDT 24
Peak memory 217948 kb
Host smart-a197dc82-874a-4a70-bc57-1e707fbadebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952376887 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3952376887
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.141497851
Short name T178
Test name
Test status
Simulation time 38378910 ps
CPU time 0.99 seconds
Started Jul 30 05:56:23 PM PDT 24
Finished Jul 30 05:56:25 PM PDT 24
Peak memory 209532 kb
Host smart-e5fb71cf-3c71-4434-a3c6-92474b0fa54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141497851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.141497851
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4211960071
Short name T970
Test name
Test status
Simulation time 32815397 ps
CPU time 1.43 seconds
Started Jul 30 05:56:22 PM PDT 24
Finished Jul 30 05:56:23 PM PDT 24
Peak memory 209168 kb
Host smart-380dc153-3f9e-409d-966e-1daba876719c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211960071 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4211960071
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.764655814
Short name T939
Test name
Test status
Simulation time 1111474282 ps
CPU time 7.84 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 208840 kb
Host smart-91b0350c-980b-47b0-964e-55c4f32b8943
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764655814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.764655814
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3410906227
Short name T125
Test name
Test status
Simulation time 968309657 ps
CPU time 11.1 seconds
Started Jul 30 05:56:18 PM PDT 24
Finished Jul 30 05:56:29 PM PDT 24
Peak memory 208240 kb
Host smart-90974e01-ab02-4927-a4df-df61422f4a61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410906227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3410906227
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1923360858
Short name T100
Test name
Test status
Simulation time 475130952 ps
CPU time 3.43 seconds
Started Jul 30 05:56:15 PM PDT 24
Finished Jul 30 05:56:19 PM PDT 24
Peak memory 211164 kb
Host smart-2995e01b-7b01-455c-aea4-549ca6e047df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923360858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1923360858
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2083403544
Short name T990
Test name
Test status
Simulation time 492253980 ps
CPU time 2.53 seconds
Started Jul 30 05:56:21 PM PDT 24
Finished Jul 30 05:56:23 PM PDT 24
Peak memory 217824 kb
Host smart-a66d0774-31c7-4b53-85da-574fe6939ae5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208340
3544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2083403544
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2744984597
Short name T988
Test name
Test status
Simulation time 57513242 ps
CPU time 1.51 seconds
Started Jul 30 05:56:16 PM PDT 24
Finished Jul 30 05:56:18 PM PDT 24
Peak memory 209416 kb
Host smart-841dd26b-ede5-4cb7-8e9b-dec017fa580b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744984597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2744984597
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.720380130
Short name T961
Test name
Test status
Simulation time 899539557 ps
CPU time 2.13 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:21 PM PDT 24
Peak memory 211556 kb
Host smart-6e9c573f-9c35-4471-81ab-7de880f2808f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720380130 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.720380130
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2996526653
Short name T938
Test name
Test status
Simulation time 45150753 ps
CPU time 1.37 seconds
Started Jul 30 05:56:21 PM PDT 24
Finished Jul 30 05:56:23 PM PDT 24
Peak memory 209404 kb
Host smart-62fd3f0c-abae-4e56-a050-feb10e837755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996526653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2996526653
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2907415226
Short name T974
Test name
Test status
Simulation time 71583951 ps
CPU time 2.8 seconds
Started Jul 30 05:56:24 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 217696 kb
Host smart-2e583bd3-9cff-498c-b1e5-4ce1031da00e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907415226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2907415226
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3021748758
Short name T980
Test name
Test status
Simulation time 224220671 ps
CPU time 2.07 seconds
Started Jul 30 05:56:23 PM PDT 24
Finished Jul 30 05:56:25 PM PDT 24
Peak memory 222176 kb
Host smart-a4a9fc49-a9d1-4725-9ce2-19dee8ebd1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021748758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3021748758
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1927106286
Short name T962
Test name
Test status
Simulation time 22671276 ps
CPU time 1.11 seconds
Started Jul 30 05:56:22 PM PDT 24
Finished Jul 30 05:56:23 PM PDT 24
Peak memory 217816 kb
Host smart-eba5500e-a91d-45dd-97dc-ddfc4e2a4633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927106286 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1927106286
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3808159575
Short name T182
Test name
Test status
Simulation time 41650292 ps
CPU time 1.02 seconds
Started Jul 30 05:56:22 PM PDT 24
Finished Jul 30 05:56:23 PM PDT 24
Peak memory 209536 kb
Host smart-5604a3be-2a64-4c7c-8ee0-30899c5ae4cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808159575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3808159575
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4017307741
Short name T914
Test name
Test status
Simulation time 326029295 ps
CPU time 1.3 seconds
Started Jul 30 05:56:24 PM PDT 24
Finished Jul 30 05:56:26 PM PDT 24
Peak memory 208264 kb
Host smart-30913856-dba4-48f3-ae91-b34a3b6d1f2a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017307741 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4017307741
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.802924760
Short name T870
Test name
Test status
Simulation time 1570756787 ps
CPU time 3.32 seconds
Started Jul 30 05:56:24 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 207996 kb
Host smart-6dd187f9-877c-4b28-b1cf-4d46cc64f4ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802924760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.802924760
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.920047273
Short name T959
Test name
Test status
Simulation time 1184782849 ps
CPU time 5.68 seconds
Started Jul 30 05:56:20 PM PDT 24
Finished Jul 30 05:56:26 PM PDT 24
Peak memory 209248 kb
Host smart-4306d636-f057-488d-8c1d-76c27b91831b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920047273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.920047273
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.962898239
Short name T956
Test name
Test status
Simulation time 367394695 ps
CPU time 3.34 seconds
Started Jul 30 05:56:23 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 211176 kb
Host smart-459c04ce-459b-41d7-8087-f17d5600f9e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962898239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.962898239
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.244241270
Short name T890
Test name
Test status
Simulation time 696455222 ps
CPU time 2.27 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:22 PM PDT 24
Peak memory 218856 kb
Host smart-c7e38e9a-14d4-40de-bcfa-6a9c02479b05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244241
270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.244241270
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3975028465
Short name T872
Test name
Test status
Simulation time 270964942 ps
CPU time 2.24 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:22 PM PDT 24
Peak memory 209308 kb
Host smart-25908435-fa08-42dc-b872-9e90481b29e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975028465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3975028465
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.574454410
Short name T185
Test name
Test status
Simulation time 133306985 ps
CPU time 1.29 seconds
Started Jul 30 05:56:22 PM PDT 24
Finished Jul 30 05:56:24 PM PDT 24
Peak memory 211504 kb
Host smart-afd81b0f-28f0-42f5-8f0d-f6cc327677e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574454410 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.574454410
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.310686298
Short name T975
Test name
Test status
Simulation time 40204791 ps
CPU time 1.3 seconds
Started Jul 30 05:56:23 PM PDT 24
Finished Jul 30 05:56:24 PM PDT 24
Peak memory 209520 kb
Host smart-a1a706ec-0be6-40fd-94e0-a9b2bc4c0ffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310686298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.310686298
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2945155139
Short name T995
Test name
Test status
Simulation time 127858638 ps
CPU time 3.71 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:23 PM PDT 24
Peak memory 218212 kb
Host smart-258cc0fe-6589-4019-8e19-866c6da4e824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945155139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2945155139
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3725291231
Short name T108
Test name
Test status
Simulation time 723251830 ps
CPU time 2.71 seconds
Started Jul 30 05:56:19 PM PDT 24
Finished Jul 30 05:56:22 PM PDT 24
Peak memory 217728 kb
Host smart-09070040-dd43-4947-943a-3cbdd6236c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725291231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3725291231
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3143112083
Short name T147
Test name
Test status
Simulation time 87632702 ps
CPU time 1.56 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 218064 kb
Host smart-a76f0f95-fa21-4d94-a946-49aadee6df8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143112083 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3143112083
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3105645419
Short name T99
Test name
Test status
Simulation time 50315788 ps
CPU time 1.03 seconds
Started Jul 30 05:56:27 PM PDT 24
Finished Jul 30 05:56:28 PM PDT 24
Peak memory 209144 kb
Host smart-54a65fa4-b35a-403c-bb59-98af20aabdd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105645419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3105645419
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.913841042
Short name T886
Test name
Test status
Simulation time 51662063 ps
CPU time 1.47 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:26 PM PDT 24
Peak memory 209428 kb
Host smart-e511b362-bd5e-4e01-a1a8-20cd6b1ffd0c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913841042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.913841042
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3480784413
Short name T985
Test name
Test status
Simulation time 1156624871 ps
CPU time 25.54 seconds
Started Jul 30 05:56:24 PM PDT 24
Finished Jul 30 05:56:50 PM PDT 24
Peak memory 209196 kb
Host smart-82ec4ac2-566e-44f4-ab31-c05ebdcea023
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480784413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3480784413
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1255221245
Short name T997
Test name
Test status
Simulation time 1123352730 ps
CPU time 9.96 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:35 PM PDT 24
Peak memory 208752 kb
Host smart-ff10e4e1-dab2-4a3a-87f3-5a6a79b340ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255221245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1255221245
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2281942797
Short name T929
Test name
Test status
Simulation time 164598107 ps
CPU time 4.29 seconds
Started Jul 30 05:56:22 PM PDT 24
Finished Jul 30 05:56:26 PM PDT 24
Peak memory 211208 kb
Host smart-113fd22b-e95b-4fa0-bf46-82b157833583
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281942797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2281942797
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3317377040
Short name T93
Test name
Test status
Simulation time 522817801 ps
CPU time 3.57 seconds
Started Jul 30 05:56:27 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 222932 kb
Host smart-da45f0a1-9768-406f-940d-b0ac4dd4bb15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331737
7040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3317377040
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2094648004
Short name T953
Test name
Test status
Simulation time 117125959 ps
CPU time 1.39 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:26 PM PDT 24
Peak memory 209444 kb
Host smart-06fb500d-2100-4b86-8dec-55d45513f8e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094648004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2094648004
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3910360474
Short name T932
Test name
Test status
Simulation time 23705249 ps
CPU time 0.98 seconds
Started Jul 30 05:56:26 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 208844 kb
Host smart-7cf0f5fb-0577-47e1-bb3e-82ba687712b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910360474 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3910360474
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3153367760
Short name T996
Test name
Test status
Simulation time 38780728 ps
CPU time 1.46 seconds
Started Jul 30 05:56:27 PM PDT 24
Finished Jul 30 05:56:28 PM PDT 24
Peak memory 209648 kb
Host smart-eee49814-9d38-4eee-af9a-34d6d6fef087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153367760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3153367760
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.612219646
Short name T912
Test name
Test status
Simulation time 276423642 ps
CPU time 2.07 seconds
Started Jul 30 05:56:24 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 217744 kb
Host smart-3131b5c7-10c9-4b7f-824e-5be74b53aa76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612219646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.612219646
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1382486499
Short name T112
Test name
Test status
Simulation time 40851921 ps
CPU time 1.55 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 219768 kb
Host smart-9dc67800-e3b4-4661-890f-8534b6b78d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382486499 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1382486499
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.129616219
Short name T903
Test name
Test status
Simulation time 15310816 ps
CPU time 0.89 seconds
Started Jul 30 05:56:31 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 209480 kb
Host smart-963d9ade-1638-4abf-a1e2-af5cd7b0c420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129616219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.129616219
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3672356304
Short name T989
Test name
Test status
Simulation time 53631081 ps
CPU time 0.95 seconds
Started Jul 30 05:56:27 PM PDT 24
Finished Jul 30 05:56:28 PM PDT 24
Peak memory 208184 kb
Host smart-91bb4aed-94d9-465d-987b-448606cb44b7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672356304 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3672356304
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2953416999
Short name T888
Test name
Test status
Simulation time 876694786 ps
CPU time 11.47 seconds
Started Jul 30 05:56:26 PM PDT 24
Finished Jul 30 05:56:38 PM PDT 24
Peak memory 208712 kb
Host smart-3a060bd0-d18d-4b6c-82ae-ac07a646a64b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953416999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2953416999
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2063722916
Short name T889
Test name
Test status
Simulation time 1330543132 ps
CPU time 8.03 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:33 PM PDT 24
Peak memory 208172 kb
Host smart-13086da0-ed67-45b9-bc93-2090dd1bcf6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063722916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2063722916
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2250338746
Short name T955
Test name
Test status
Simulation time 962061351 ps
CPU time 2.21 seconds
Started Jul 30 05:56:24 PM PDT 24
Finished Jul 30 05:56:26 PM PDT 24
Peak memory 211040 kb
Host smart-392c53eb-49fb-4170-b2ca-b39f4d44e7b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250338746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2250338746
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2043010343
Short name T878
Test name
Test status
Simulation time 494140167 ps
CPU time 2.03 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 217760 kb
Host smart-996ee98f-f206-4f7d-b254-91cb9f8fd4f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204301
0343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2043010343
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2056881801
Short name T925
Test name
Test status
Simulation time 110788325 ps
CPU time 2.11 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 209320 kb
Host smart-f8b68b72-f670-4e40-b3ad-36c793b88121
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056881801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2056881801
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3810983260
Short name T934
Test name
Test status
Simulation time 58449455 ps
CPU time 1.43 seconds
Started Jul 30 05:56:25 PM PDT 24
Finished Jul 30 05:56:27 PM PDT 24
Peak memory 217720 kb
Host smart-4407171f-f86a-459a-a165-6e135524db70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810983260 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3810983260
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1571627975
Short name T940
Test name
Test status
Simulation time 48100041 ps
CPU time 1.53 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 211560 kb
Host smart-35045c79-272d-4c92-9526-216ac341f5f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571627975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1571627975
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.24876563
Short name T930
Test name
Test status
Simulation time 81668933 ps
CPU time 2.93 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 217896 kb
Host smart-214a5014-c550-434e-b7ea-1ea2881d4d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24876563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.24876563
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2073090374
Short name T109
Test name
Test status
Simulation time 149655495 ps
CPU time 3.01 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:33 PM PDT 24
Peak memory 217680 kb
Host smart-b032eb42-47db-4532-82ec-3974f3826772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073090374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2073090374
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3357909835
Short name T917
Test name
Test status
Simulation time 29760533 ps
CPU time 1.03 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 217748 kb
Host smart-5cb71335-41db-4957-9476-c238256b8f38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357909835 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3357909835
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2729643250
Short name T893
Test name
Test status
Simulation time 15292671 ps
CPU time 1.11 seconds
Started Jul 30 05:56:28 PM PDT 24
Finished Jul 30 05:56:29 PM PDT 24
Peak memory 209440 kb
Host smart-862ba89a-7543-45f1-8e23-cda17e984cdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729643250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2729643250
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3595808025
Short name T935
Test name
Test status
Simulation time 57454814 ps
CPU time 2.16 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:32 PM PDT 24
Peak memory 208124 kb
Host smart-cbb69325-aa33-4b04-ad72-f6632d5b59a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595808025 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3595808025
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2342727145
Short name T918
Test name
Test status
Simulation time 703978477 ps
CPU time 3.86 seconds
Started Jul 30 05:56:30 PM PDT 24
Finished Jul 30 05:56:34 PM PDT 24
Peak memory 209272 kb
Host smart-b9ae3aa7-4e32-4fed-b3bc-ba40a44255a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342727145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2342727145
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2158476813
Short name T963
Test name
Test status
Simulation time 6299977635 ps
CPU time 34.97 seconds
Started Jul 30 05:56:28 PM PDT 24
Finished Jul 30 05:57:03 PM PDT 24
Peak memory 209520 kb
Host smart-4e9a84a5-fd2a-4f95-b928-ae718d12524c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158476813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2158476813
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2996192724
Short name T873
Test name
Test status
Simulation time 850816059 ps
CPU time 5.23 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:34 PM PDT 24
Peak memory 211128 kb
Host smart-5bdbc0d3-bde3-4e25-a124-c146ec2fe315
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996192724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2996192724
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174038827
Short name T157
Test name
Test status
Simulation time 278714054 ps
CPU time 1.5 seconds
Started Jul 30 05:56:31 PM PDT 24
Finished Jul 30 05:56:33 PM PDT 24
Peak memory 218652 kb
Host smart-5a5e0f10-df9c-457d-913b-6c09e016c45f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217403
8827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174038827
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3061283804
Short name T992
Test name
Test status
Simulation time 730321845 ps
CPU time 1.13 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:30 PM PDT 24
Peak memory 209448 kb
Host smart-17e214de-18f7-4afa-ab20-ac3de44fe9bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061283804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3061283804
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2036749930
Short name T908
Test name
Test status
Simulation time 69907024 ps
CPU time 1.33 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:30 PM PDT 24
Peak memory 209444 kb
Host smart-d5540862-63ba-4615-aa23-c07d7fe56073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036749930 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2036749930
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3677621112
Short name T189
Test name
Test status
Simulation time 29539071 ps
CPU time 1.19 seconds
Started Jul 30 05:56:29 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 209016 kb
Host smart-ea920bdf-2444-4cee-b646-c19699f67790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677621112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3677621112
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.217542837
Short name T923
Test name
Test status
Simulation time 42966335 ps
CPU time 1.57 seconds
Started Jul 30 05:56:31 PM PDT 24
Finished Jul 30 05:56:33 PM PDT 24
Peak memory 218668 kb
Host smart-ba483dae-22d5-4338-9bd8-049db6c8eb79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217542837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.217542837
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3584540131
Short name T98
Test name
Test status
Simulation time 115030908 ps
CPU time 3.01 seconds
Started Jul 30 05:56:28 PM PDT 24
Finished Jul 30 05:56:31 PM PDT 24
Peak memory 222408 kb
Host smart-514e7ebc-07fb-4bd2-9802-377470255dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584540131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3584540131
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1657939035
Short name T320
Test name
Test status
Simulation time 123042035 ps
CPU time 1.09 seconds
Started Jul 30 05:21:42 PM PDT 24
Finished Jul 30 05:21:43 PM PDT 24
Peak memory 209200 kb
Host smart-50512024-df4c-4670-b2c2-ec64350df1b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657939035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1657939035
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2510387689
Short name T85
Test name
Test status
Simulation time 15120308 ps
CPU time 0.84 seconds
Started Jul 30 05:21:37 PM PDT 24
Finished Jul 30 05:21:38 PM PDT 24
Peak memory 209236 kb
Host smart-d35a9899-5940-4293-adc9-3d040fa52725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510387689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2510387689
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3893419615
Short name T402
Test name
Test status
Simulation time 1184785705 ps
CPU time 13.93 seconds
Started Jul 30 05:21:33 PM PDT 24
Finished Jul 30 05:21:47 PM PDT 24
Peak memory 218400 kb
Host smart-d85dc774-7f1b-46b0-a204-46690303855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893419615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3893419615
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1187930416
Short name T417
Test name
Test status
Simulation time 256299386 ps
CPU time 2.49 seconds
Started Jul 30 05:21:39 PM PDT 24
Finished Jul 30 05:21:42 PM PDT 24
Peak memory 217304 kb
Host smart-a2221cf9-ea68-404e-89f9-301c7c80a2a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187930416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1187930416
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2163302635
Short name T507
Test name
Test status
Simulation time 10202373534 ps
CPU time 38.85 seconds
Started Jul 30 05:21:39 PM PDT 24
Finished Jul 30 05:22:18 PM PDT 24
Peak memory 218896 kb
Host smart-248fdeb1-8cae-4d95-9e81-c68379b933c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163302635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2163302635
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.960157388
Short name T743
Test name
Test status
Simulation time 309837004 ps
CPU time 8.3 seconds
Started Jul 30 05:21:39 PM PDT 24
Finished Jul 30 05:21:47 PM PDT 24
Peak memory 217888 kb
Host smart-e13ce3f7-a036-44b0-bcd7-23090c535a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960157388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.960157388
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.255640531
Short name T613
Test name
Test status
Simulation time 528422844 ps
CPU time 3.31 seconds
Started Jul 30 05:21:41 PM PDT 24
Finished Jul 30 05:21:45 PM PDT 24
Peak memory 218372 kb
Host smart-f4f84885-5a83-4e99-874f-b30ba0dc3a1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255640531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.255640531
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4017455196
Short name T522
Test name
Test status
Simulation time 1789142254 ps
CPU time 22.88 seconds
Started Jul 30 05:21:42 PM PDT 24
Finished Jul 30 05:22:05 PM PDT 24
Peak memory 217736 kb
Host smart-22da0d14-5728-4e03-8cc2-6697a5032f02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017455196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.4017455196
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2576438968
Short name T236
Test name
Test status
Simulation time 243270052 ps
CPU time 4.56 seconds
Started Jul 30 05:21:35 PM PDT 24
Finished Jul 30 05:21:39 PM PDT 24
Peak memory 217772 kb
Host smart-9a54ccf0-ee81-4f8d-aeed-e2f7bf2f57b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576438968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2576438968
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1071590150
Short name T701
Test name
Test status
Simulation time 2885778044 ps
CPU time 39.81 seconds
Started Jul 30 05:21:38 PM PDT 24
Finished Jul 30 05:22:18 PM PDT 24
Peak memory 275612 kb
Host smart-86b16150-7478-4128-ac94-dbc53c5716d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071590150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1071590150
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.646763246
Short name T252
Test name
Test status
Simulation time 1386844893 ps
CPU time 18.64 seconds
Started Jul 30 05:21:39 PM PDT 24
Finished Jul 30 05:21:58 PM PDT 24
Peak memory 251012 kb
Host smart-8fc4adb5-a597-49b2-94fa-7496da8f1f2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646763246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.646763246
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3715021739
Short name T797
Test name
Test status
Simulation time 354592964 ps
CPU time 2.49 seconds
Started Jul 30 05:21:35 PM PDT 24
Finished Jul 30 05:21:38 PM PDT 24
Peak memory 218444 kb
Host smart-7ac7b1f4-3671-430a-9963-a99d6003f7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715021739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3715021739
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.514650468
Short name T372
Test name
Test status
Simulation time 283610728 ps
CPU time 10.99 seconds
Started Jul 30 05:21:37 PM PDT 24
Finished Jul 30 05:21:48 PM PDT 24
Peak memory 217820 kb
Host smart-6c956c71-e5eb-4826-b60c-621833c0da7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514650468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.514650468
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1446944811
Short name T398
Test name
Test status
Simulation time 255568704 ps
CPU time 11.54 seconds
Started Jul 30 05:21:40 PM PDT 24
Finished Jul 30 05:21:52 PM PDT 24
Peak memory 226356 kb
Host smart-6c5421be-643b-46c1-9e70-f852980978db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446944811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1446944811
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3418709373
Short name T430
Test name
Test status
Simulation time 2971962472 ps
CPU time 13.74 seconds
Started Jul 30 05:21:41 PM PDT 24
Finished Jul 30 05:21:55 PM PDT 24
Peak memory 218404 kb
Host smart-ffc27d17-1f6e-4d3f-b7de-a61fe778c7d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418709373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3418709373
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1848696232
Short name T607
Test name
Test status
Simulation time 313607095 ps
CPU time 10.89 seconds
Started Jul 30 05:21:38 PM PDT 24
Finished Jul 30 05:21:49 PM PDT 24
Peak memory 218328 kb
Host smart-f911ff25-44a5-4a20-96b7-f0c4f09d3f6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848696232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
848696232
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2806437631
Short name T740
Test name
Test status
Simulation time 107197085 ps
CPU time 2.5 seconds
Started Jul 30 05:21:36 PM PDT 24
Finished Jul 30 05:21:39 PM PDT 24
Peak memory 223508 kb
Host smart-41e3cf75-e8a9-46df-81e1-4f7441600315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806437631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2806437631
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.140501717
Short name T840
Test name
Test status
Simulation time 653990664 ps
CPU time 26.76 seconds
Started Jul 30 05:21:35 PM PDT 24
Finished Jul 30 05:22:02 PM PDT 24
Peak memory 251152 kb
Host smart-05ec497d-7c7a-462f-8b97-d9179777f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140501717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.140501717
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1542183928
Short name T220
Test name
Test status
Simulation time 106949276 ps
CPU time 3.81 seconds
Started Jul 30 05:21:33 PM PDT 24
Finished Jul 30 05:21:37 PM PDT 24
Peak memory 222936 kb
Host smart-2525ff54-e8bd-44d2-8d8e-c92f9de6253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542183928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1542183928
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3657248897
Short name T843
Test name
Test status
Simulation time 13401007602 ps
CPU time 97.34 seconds
Started Jul 30 05:21:39 PM PDT 24
Finished Jul 30 05:23:17 PM PDT 24
Peak memory 248176 kb
Host smart-abeaec3b-f1ab-409a-bc5d-0f03de2ed0a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657248897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3657248897
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2809404050
Short name T63
Test name
Test status
Simulation time 133020977998 ps
CPU time 523.82 seconds
Started Jul 30 05:21:40 PM PDT 24
Finished Jul 30 05:30:24 PM PDT 24
Peak memory 447696 kb
Host smart-d7836f0b-c5a8-4ec2-b621-8fd9adcdaa7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2809404050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2809404050
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3571508210
Short name T298
Test name
Test status
Simulation time 31349430 ps
CPU time 0.96 seconds
Started Jul 30 05:21:36 PM PDT 24
Finished Jul 30 05:21:38 PM PDT 24
Peak memory 212008 kb
Host smart-74078b36-9113-4962-be64-4f44fbe0e12f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571508210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3571508210
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.249952033
Short name T212
Test name
Test status
Simulation time 16782576 ps
CPU time 0.96 seconds
Started Jul 30 05:21:49 PM PDT 24
Finished Jul 30 05:21:50 PM PDT 24
Peak memory 208996 kb
Host smart-b40d737a-c488-4c00-bad1-680eaca4b317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249952033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.249952033
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2271024125
Short name T841
Test name
Test status
Simulation time 738970919 ps
CPU time 18.49 seconds
Started Jul 30 05:21:48 PM PDT 24
Finished Jul 30 05:22:07 PM PDT 24
Peak memory 218272 kb
Host smart-8735e1ba-a2e8-490f-b37c-a3b640bcfaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271024125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2271024125
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.815404219
Short name T518
Test name
Test status
Simulation time 895250056 ps
CPU time 5.39 seconds
Started Jul 30 05:21:43 PM PDT 24
Finished Jul 30 05:21:49 PM PDT 24
Peak memory 217396 kb
Host smart-20968615-aa6c-42dd-b2b0-23ab208354cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815404219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.815404219
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3717608146
Short name T284
Test name
Test status
Simulation time 2459882232 ps
CPU time 21.77 seconds
Started Jul 30 05:21:45 PM PDT 24
Finished Jul 30 05:22:07 PM PDT 24
Peak memory 218476 kb
Host smart-beca40ee-584f-4870-be12-eecf7f627081
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717608146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3717608146
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3370132434
Short name T779
Test name
Test status
Simulation time 223198944 ps
CPU time 3.71 seconds
Started Jul 30 05:21:47 PM PDT 24
Finished Jul 30 05:21:50 PM PDT 24
Peak memory 217876 kb
Host smart-6f97eb23-e947-428c-ba8d-382dee469559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370132434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
370132434
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1643441535
Short name T848
Test name
Test status
Simulation time 498266267 ps
CPU time 7.79 seconds
Started Jul 30 05:21:44 PM PDT 24
Finished Jul 30 05:21:52 PM PDT 24
Peak memory 218336 kb
Host smart-eab633f9-a47a-4bd7-a83d-ebd3c7128523
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643441535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1643441535
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1898467101
Short name T721
Test name
Test status
Simulation time 4735968075 ps
CPU time 31.55 seconds
Started Jul 30 05:21:42 PM PDT 24
Finished Jul 30 05:22:14 PM PDT 24
Peak memory 217804 kb
Host smart-35ae5d84-5b71-41b9-99e8-582a082c0b8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898467101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1898467101
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1176351219
Short name T65
Test name
Test status
Simulation time 2234302991 ps
CPU time 11.02 seconds
Started Jul 30 05:21:43 PM PDT 24
Finished Jul 30 05:21:54 PM PDT 24
Peak memory 217832 kb
Host smart-23c6978d-cf78-48dc-94a1-4e863244e6c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176351219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1176351219
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2559299428
Short name T538
Test name
Test status
Simulation time 964549169 ps
CPU time 33.89 seconds
Started Jul 30 05:21:46 PM PDT 24
Finished Jul 30 05:22:20 PM PDT 24
Peak memory 267196 kb
Host smart-893e75d7-37b9-42e4-9db6-9cc1449f3a1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559299428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2559299428
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2339439362
Short name T655
Test name
Test status
Simulation time 279358875 ps
CPU time 9.75 seconds
Started Jul 30 05:21:42 PM PDT 24
Finished Jul 30 05:21:53 PM PDT 24
Peak memory 226380 kb
Host smart-b1454a5c-dbfd-45bc-9d0e-d73732b16569
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339439362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2339439362
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1844395397
Short name T410
Test name
Test status
Simulation time 70354699 ps
CPU time 2.21 seconds
Started Jul 30 05:21:43 PM PDT 24
Finished Jul 30 05:21:45 PM PDT 24
Peak memory 218396 kb
Host smart-c76bbec0-c464-4052-829f-a1e2a79d86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844395397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1844395397
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1594924892
Short name T440
Test name
Test status
Simulation time 1490066966 ps
CPU time 19.41 seconds
Started Jul 30 05:21:46 PM PDT 24
Finished Jul 30 05:22:05 PM PDT 24
Peak memory 214812 kb
Host smart-79349ea6-64c5-4300-8563-4c0e8f2fcd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594924892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1594924892
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2093872601
Short name T48
Test name
Test status
Simulation time 1536763283 ps
CPU time 25.55 seconds
Started Jul 30 05:21:48 PM PDT 24
Finished Jul 30 05:22:14 PM PDT 24
Peak memory 284104 kb
Host smart-43f5187c-0bfc-41ae-9624-885e42bbbd89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093872601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2093872601
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2467956448
Short name T557
Test name
Test status
Simulation time 766212716 ps
CPU time 9.58 seconds
Started Jul 30 05:21:44 PM PDT 24
Finished Jul 30 05:21:53 PM PDT 24
Peak memory 218468 kb
Host smart-81e7d920-5c28-45fa-9228-ff98ed26e324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467956448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2467956448
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3947473339
Short name T351
Test name
Test status
Simulation time 1762446406 ps
CPU time 11.83 seconds
Started Jul 30 05:21:48 PM PDT 24
Finished Jul 30 05:22:00 PM PDT 24
Peak memory 226072 kb
Host smart-d90417a5-1110-4f7a-9a6d-c9a465211e06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947473339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3947473339
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1351432786
Short name T852
Test name
Test status
Simulation time 318364501 ps
CPU time 9.08 seconds
Started Jul 30 05:21:52 PM PDT 24
Finished Jul 30 05:22:01 PM PDT 24
Peak memory 218340 kb
Host smart-57f2f77e-4095-4ceb-b52a-e9a1d80c6636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351432786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
351432786
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4091287564
Short name T499
Test name
Test status
Simulation time 1376113170 ps
CPU time 11.81 seconds
Started Jul 30 05:21:46 PM PDT 24
Finished Jul 30 05:21:58 PM PDT 24
Peak memory 226144 kb
Host smart-c4ed76d8-68e0-43ad-bba2-3f9f0ddcb430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091287564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4091287564
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.51872847
Short name T623
Test name
Test status
Simulation time 38745452 ps
CPU time 1.53 seconds
Started Jul 30 05:21:41 PM PDT 24
Finished Jul 30 05:21:42 PM PDT 24
Peak memory 217820 kb
Host smart-773ccf07-a642-4118-abd1-c1232843c4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51872847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.51872847
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3040327403
Short name T855
Test name
Test status
Simulation time 306853555 ps
CPU time 25.31 seconds
Started Jul 30 05:21:41 PM PDT 24
Finished Jul 30 05:22:06 PM PDT 24
Peak memory 251188 kb
Host smart-83f8cf01-771d-4b0f-b15d-18598a3221b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040327403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3040327403
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2671247213
Short name T834
Test name
Test status
Simulation time 221790866 ps
CPU time 3.34 seconds
Started Jul 30 05:21:43 PM PDT 24
Finished Jul 30 05:21:46 PM PDT 24
Peak memory 222456 kb
Host smart-3daee11e-f733-4264-b8e6-0c580372faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671247213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2671247213
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.457057651
Short name T455
Test name
Test status
Simulation time 143226871 ps
CPU time 0.92 seconds
Started Jul 30 05:21:43 PM PDT 24
Finished Jul 30 05:21:45 PM PDT 24
Peak memory 212144 kb
Host smart-c1f31c05-16e4-4787-b315-9d2ba979e1e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457057651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.457057651
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.938570281
Short name T483
Test name
Test status
Simulation time 17495360 ps
CPU time 1.01 seconds
Started Jul 30 05:22:45 PM PDT 24
Finished Jul 30 05:22:46 PM PDT 24
Peak memory 208864 kb
Host smart-5d0b1660-237e-425d-9dd8-cd71a43cc574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938570281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.938570281
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.915196905
Short name T454
Test name
Test status
Simulation time 2292449743 ps
CPU time 17.63 seconds
Started Jul 30 05:22:39 PM PDT 24
Finished Jul 30 05:22:57 PM PDT 24
Peak memory 226248 kb
Host smart-4ce25f28-8e03-40b9-862c-d706a6a7990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915196905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.915196905
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1269093988
Short name T768
Test name
Test status
Simulation time 1960062812 ps
CPU time 7.03 seconds
Started Jul 30 05:22:42 PM PDT 24
Finished Jul 30 05:22:49 PM PDT 24
Peak memory 217288 kb
Host smart-2cef10e5-85de-49ca-bfae-431cd223446b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269093988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1269093988
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1921259252
Short name T559
Test name
Test status
Simulation time 1352286178 ps
CPU time 25.48 seconds
Started Jul 30 05:22:38 PM PDT 24
Finished Jul 30 05:23:03 PM PDT 24
Peak memory 218388 kb
Host smart-43ff0890-b834-4725-a982-4a06423b9f89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921259252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1921259252
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1332780940
Short name T805
Test name
Test status
Simulation time 411784299 ps
CPU time 12.38 seconds
Started Jul 30 05:22:36 PM PDT 24
Finished Jul 30 05:22:49 PM PDT 24
Peak memory 218332 kb
Host smart-d3404bb2-1415-4ffb-bba8-67e9bde72bd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332780940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1332780940
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1549344785
Short name T234
Test name
Test status
Simulation time 1105097942 ps
CPU time 7.02 seconds
Started Jul 30 05:22:37 PM PDT 24
Finished Jul 30 05:22:44 PM PDT 24
Peak memory 217796 kb
Host smart-77445e2b-88a7-4418-a9be-13fb3e5ce49a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549344785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1549344785
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2170148495
Short name T434
Test name
Test status
Simulation time 2595815469 ps
CPU time 62.87 seconds
Started Jul 30 05:22:38 PM PDT 24
Finished Jul 30 05:23:40 PM PDT 24
Peak memory 279980 kb
Host smart-07bd3f96-dd99-4fde-9993-ecf50adac5f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170148495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2170148495
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.629554283
Short name T749
Test name
Test status
Simulation time 354071529 ps
CPU time 12.03 seconds
Started Jul 30 05:22:37 PM PDT 24
Finished Jul 30 05:22:49 PM PDT 24
Peak memory 251024 kb
Host smart-0f069fe2-b73a-4e1a-9c44-398ba5ca9617
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629554283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.629554283
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2002404792
Short name T630
Test name
Test status
Simulation time 60172241 ps
CPU time 2.75 seconds
Started Jul 30 05:22:37 PM PDT 24
Finished Jul 30 05:22:40 PM PDT 24
Peak memory 218436 kb
Host smart-a07b6a8b-ca2a-4fd1-b233-4d56d2ea4d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002404792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2002404792
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3305419660
Short name T633
Test name
Test status
Simulation time 403660109 ps
CPU time 11.02 seconds
Started Jul 30 05:22:43 PM PDT 24
Finished Jul 30 05:22:54 PM PDT 24
Peak memory 218344 kb
Host smart-6bea82f8-f152-44f8-8bbb-bb19d1ab904a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305419660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3305419660
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1791729321
Short name T488
Test name
Test status
Simulation time 390311628 ps
CPU time 8.01 seconds
Started Jul 30 05:22:42 PM PDT 24
Finished Jul 30 05:22:50 PM PDT 24
Peak memory 225120 kb
Host smart-a081abdf-591b-48dd-ae0c-fbb713d4f1b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791729321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1791729321
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2305167525
Short name T677
Test name
Test status
Simulation time 782662328 ps
CPU time 9.8 seconds
Started Jul 30 05:22:38 PM PDT 24
Finished Jul 30 05:22:48 PM PDT 24
Peak memory 226228 kb
Host smart-61d218a9-808c-44aa-9851-37d80da9219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305167525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2305167525
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.4019222847
Short name T861
Test name
Test status
Simulation time 36102957 ps
CPU time 2.68 seconds
Started Jul 30 05:22:38 PM PDT 24
Finished Jul 30 05:22:40 PM PDT 24
Peak memory 214612 kb
Host smart-cccb8d6c-aae9-4b28-8297-c10df1b2147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019222847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.4019222847
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1621631150
Short name T595
Test name
Test status
Simulation time 539659559 ps
CPU time 25.84 seconds
Started Jul 30 05:22:39 PM PDT 24
Finished Jul 30 05:23:05 PM PDT 24
Peak memory 250880 kb
Host smart-ef8ecdfb-68ac-4ff7-8522-09c73d73de5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621631150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1621631150
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4053627860
Short name T257
Test name
Test status
Simulation time 130997278 ps
CPU time 8.15 seconds
Started Jul 30 05:22:40 PM PDT 24
Finished Jul 30 05:22:48 PM PDT 24
Peak memory 250856 kb
Host smart-8ed13d52-e078-4517-8798-3b0200b4f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053627860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4053627860
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.162839482
Short name T219
Test name
Test status
Simulation time 17247290750 ps
CPU time 256.17 seconds
Started Jul 30 05:22:41 PM PDT 24
Finished Jul 30 05:26:58 PM PDT 24
Peak memory 283648 kb
Host smart-4ca4e4b7-1779-4e1e-97f7-00c2f80f6ccb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162839482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.162839482
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1679069477
Short name T89
Test name
Test status
Simulation time 50455797351 ps
CPU time 2813.01 seconds
Started Jul 30 05:22:43 PM PDT 24
Finished Jul 30 06:09:37 PM PDT 24
Peak memory 912952 kb
Host smart-4db2c251-b134-4405-917d-6b491570a3be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1679069477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1679069477
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.692049023
Short name T560
Test name
Test status
Simulation time 24019377 ps
CPU time 0.86 seconds
Started Jul 30 05:22:38 PM PDT 24
Finished Jul 30 05:22:39 PM PDT 24
Peak memory 213008 kb
Host smart-77f4e1b4-b17c-4164-807d-dd230fa5f329
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692049023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.692049023
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1409371142
Short name T640
Test name
Test status
Simulation time 63089780 ps
CPU time 1.29 seconds
Started Jul 30 05:22:46 PM PDT 24
Finished Jul 30 05:22:47 PM PDT 24
Peak memory 209112 kb
Host smart-279ed889-1737-41ae-a24e-4a353e0b9010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409371142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1409371142
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1224233410
Short name T758
Test name
Test status
Simulation time 2442268740 ps
CPU time 15.41 seconds
Started Jul 30 05:22:41 PM PDT 24
Finished Jul 30 05:22:57 PM PDT 24
Peak memory 219064 kb
Host smart-4e96bb33-8541-4a41-9dd1-304a445952ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224233410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1224233410
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.247842502
Short name T568
Test name
Test status
Simulation time 1535689108 ps
CPU time 7.45 seconds
Started Jul 30 05:22:45 PM PDT 24
Finished Jul 30 05:22:53 PM PDT 24
Peak memory 217608 kb
Host smart-2303aeec-1b32-46ca-9fd0-c7de8fe955de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247842502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.247842502
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2993728616
Short name T593
Test name
Test status
Simulation time 18794443402 ps
CPU time 57.66 seconds
Started Jul 30 05:22:48 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 226208 kb
Host smart-ad603145-b0ec-4cef-a5bc-db9fb7201497
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993728616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2993728616
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1799136339
Short name T420
Test name
Test status
Simulation time 4157102735 ps
CPU time 4.52 seconds
Started Jul 30 05:22:45 PM PDT 24
Finished Jul 30 05:22:50 PM PDT 24
Peak memory 218400 kb
Host smart-a0a12b28-2db4-4278-acc3-e88c4350c423
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799136339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1799136339
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1330671204
Short name T695
Test name
Test status
Simulation time 747304907 ps
CPU time 6.47 seconds
Started Jul 30 05:22:49 PM PDT 24
Finished Jul 30 05:22:55 PM PDT 24
Peak memory 217756 kb
Host smart-b78bc708-19ba-486e-b344-8577aadf5c5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330671204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1330671204
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1996984843
Short name T699
Test name
Test status
Simulation time 24869680367 ps
CPU time 58.77 seconds
Started Jul 30 05:22:50 PM PDT 24
Finished Jul 30 05:23:49 PM PDT 24
Peak memory 279996 kb
Host smart-c2e6f9d8-3bd9-4f20-a6d6-1a6d2a9336ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996984843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1996984843
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3722081939
Short name T588
Test name
Test status
Simulation time 1941983964 ps
CPU time 14.87 seconds
Started Jul 30 05:22:47 PM PDT 24
Finished Jul 30 05:23:02 PM PDT 24
Peak memory 218340 kb
Host smart-d84689c8-4389-489a-895b-0dd79ef42a82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722081939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3722081939
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3078701759
Short name T452
Test name
Test status
Simulation time 135792546 ps
CPU time 2.08 seconds
Started Jul 30 05:22:41 PM PDT 24
Finished Jul 30 05:22:43 PM PDT 24
Peak memory 222236 kb
Host smart-247558e1-01df-4bf5-bb1d-280e845cb107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078701759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3078701759
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1674781763
Short name T509
Test name
Test status
Simulation time 315816418 ps
CPU time 14.49 seconds
Started Jul 30 05:22:47 PM PDT 24
Finished Jul 30 05:23:01 PM PDT 24
Peak memory 226108 kb
Host smart-d1fbc72f-2c79-44ce-9e67-17f20bc87984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674781763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1674781763
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2840203724
Short name T304
Test name
Test status
Simulation time 1309099013 ps
CPU time 9.5 seconds
Started Jul 30 05:22:46 PM PDT 24
Finished Jul 30 05:22:55 PM PDT 24
Peak memory 218344 kb
Host smart-04c63160-239b-4dab-8254-e833b11ee4a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840203724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2840203724
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.32840820
Short name T405
Test name
Test status
Simulation time 1934370886 ps
CPU time 9.27 seconds
Started Jul 30 05:22:49 PM PDT 24
Finished Jul 30 05:22:59 PM PDT 24
Peak memory 226148 kb
Host smart-70b4d87d-71b4-4cd2-8ff2-ef5ef8817e58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.32840820
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3420331436
Short name T17
Test name
Test status
Simulation time 58730182 ps
CPU time 2.21 seconds
Started Jul 30 05:22:43 PM PDT 24
Finished Jul 30 05:22:46 PM PDT 24
Peak memory 217888 kb
Host smart-3299a6d9-9cb7-4d55-abb2-cd9747e8ac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420331436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3420331436
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.82433155
Short name T764
Test name
Test status
Simulation time 780330669 ps
CPU time 18.4 seconds
Started Jul 30 05:22:43 PM PDT 24
Finished Jul 30 05:23:02 PM PDT 24
Peak memory 251104 kb
Host smart-841c2eb1-5f80-4ffe-89eb-7b72fa2c2849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82433155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.82433155
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1531876494
Short name T554
Test name
Test status
Simulation time 230370661 ps
CPU time 6.51 seconds
Started Jul 30 05:22:43 PM PDT 24
Finished Jul 30 05:22:49 PM PDT 24
Peak memory 246764 kb
Host smart-bb9d7897-0a1d-4072-a4cc-58fadc91a7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531876494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1531876494
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2125988275
Short name T39
Test name
Test status
Simulation time 8493735286 ps
CPU time 68.04 seconds
Started Jul 30 05:22:48 PM PDT 24
Finished Jul 30 05:23:56 PM PDT 24
Peak memory 272220 kb
Host smart-f056494c-a244-481b-9626-27041da15d35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125988275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2125988275
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3288638976
Short name T722
Test name
Test status
Simulation time 146886669382 ps
CPU time 7280.63 seconds
Started Jul 30 05:22:47 PM PDT 24
Finished Jul 30 07:24:09 PM PDT 24
Peak memory 1201520 kb
Host smart-dca625d2-35be-4dcf-bff7-894e6e01bd9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3288638976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3288638976
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3957191743
Short name T309
Test name
Test status
Simulation time 31066462 ps
CPU time 0.87 seconds
Started Jul 30 05:22:43 PM PDT 24
Finished Jul 30 05:22:44 PM PDT 24
Peak memory 211980 kb
Host smart-ac23d00c-8675-4562-be42-4430729da4c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957191743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3957191743
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3458089745
Short name T431
Test name
Test status
Simulation time 100083965 ps
CPU time 1.27 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:22:53 PM PDT 24
Peak memory 209120 kb
Host smart-4d4c6aa8-110d-46d6-9179-a9069345a8a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458089745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3458089745
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.218420328
Short name T762
Test name
Test status
Simulation time 773800668 ps
CPU time 10.12 seconds
Started Jul 30 05:22:47 PM PDT 24
Finished Jul 30 05:22:58 PM PDT 24
Peak memory 218536 kb
Host smart-4f884fef-0c3d-4992-abba-d1ee775752cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218420328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.218420328
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1903845118
Short name T585
Test name
Test status
Simulation time 379423776 ps
CPU time 3.2 seconds
Started Jul 30 05:22:49 PM PDT 24
Finished Jul 30 05:22:52 PM PDT 24
Peak memory 217164 kb
Host smart-ca588695-0450-4b0c-b87b-18a938424993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903845118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1903845118
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1051763905
Short name T395
Test name
Test status
Simulation time 6003773229 ps
CPU time 23.01 seconds
Started Jul 30 05:22:51 PM PDT 24
Finished Jul 30 05:23:14 PM PDT 24
Peak memory 219044 kb
Host smart-31cd9785-2c11-4315-aa8f-4c83e4346a58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051763905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1051763905
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2918000022
Short name T418
Test name
Test status
Simulation time 606326037 ps
CPU time 18.56 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:23:11 PM PDT 24
Peak memory 218360 kb
Host smart-6524c4ce-937a-4fd3-a841-1b4f1bc72cbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918000022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2918000022
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.549835495
Short name T589
Test name
Test status
Simulation time 468119432 ps
CPU time 2.01 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:22:54 PM PDT 24
Peak memory 217764 kb
Host smart-5ded4c25-8db3-4f73-9a2a-d57dd0d92672
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549835495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
549835495
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2329505003
Short name T253
Test name
Test status
Simulation time 1528991577 ps
CPU time 62.8 seconds
Started Jul 30 05:23:07 PM PDT 24
Finished Jul 30 05:24:09 PM PDT 24
Peak memory 275488 kb
Host smart-cffd2e93-910b-43b8-afd3-dcd38179a612
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329505003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2329505003
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1345905527
Short name T215
Test name
Test status
Simulation time 430741810 ps
CPU time 6.71 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:22:59 PM PDT 24
Peak memory 223184 kb
Host smart-84888e40-e61d-4de8-a6a6-7fbb0197c1a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345905527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1345905527
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4127281381
Short name T327
Test name
Test status
Simulation time 33963394 ps
CPU time 2.16 seconds
Started Jul 30 05:22:47 PM PDT 24
Finished Jul 30 05:22:50 PM PDT 24
Peak memory 222112 kb
Host smart-319ef96f-d449-4630-b7aa-54b4577171f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127281381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4127281381
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1980546750
Short name T551
Test name
Test status
Simulation time 697243685 ps
CPU time 21.06 seconds
Started Jul 30 05:22:51 PM PDT 24
Finished Jul 30 05:23:12 PM PDT 24
Peak memory 226348 kb
Host smart-e266c568-ca04-466f-8d64-31b436b47d66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980546750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1980546750
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1368601049
Short name T505
Test name
Test status
Simulation time 661193986 ps
CPU time 12.59 seconds
Started Jul 30 05:22:51 PM PDT 24
Finished Jul 30 05:23:04 PM PDT 24
Peak memory 226156 kb
Host smart-2b97a1d5-0acc-4724-8011-8bd0d535883c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368601049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1368601049
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3605684603
Short name T137
Test name
Test status
Simulation time 1427664270 ps
CPU time 11.49 seconds
Started Jul 30 05:22:51 PM PDT 24
Finished Jul 30 05:23:02 PM PDT 24
Peak memory 218408 kb
Host smart-bd427a3a-f9aa-4be0-bb09-a218f2e9b6c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605684603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3605684603
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3223958358
Short name T139
Test name
Test status
Simulation time 692563423 ps
CPU time 7.74 seconds
Started Jul 30 05:22:53 PM PDT 24
Finished Jul 30 05:23:01 PM PDT 24
Peak memory 225196 kb
Host smart-5dcbf777-72ca-4b64-8d63-829df366d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223958358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3223958358
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2714077125
Short name T227
Test name
Test status
Simulation time 559461631 ps
CPU time 8.31 seconds
Started Jul 30 05:22:47 PM PDT 24
Finished Jul 30 05:22:55 PM PDT 24
Peak memory 217824 kb
Host smart-e1c4353e-4dc0-4a0b-8e7e-db6c5b79d377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714077125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2714077125
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.722097156
Short name T760
Test name
Test status
Simulation time 755720495 ps
CPU time 23.32 seconds
Started Jul 30 05:22:47 PM PDT 24
Finished Jul 30 05:23:10 PM PDT 24
Peak memory 251104 kb
Host smart-0c56498c-44ff-4941-9f6d-c3d8e1e6279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722097156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.722097156
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.741863011
Short name T685
Test name
Test status
Simulation time 91528180 ps
CPU time 7.16 seconds
Started Jul 30 05:22:45 PM PDT 24
Finished Jul 30 05:22:53 PM PDT 24
Peak memory 250596 kb
Host smart-aef9cc4b-6507-48bd-8c2b-00729163b41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741863011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.741863011
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2504831191
Short name T314
Test name
Test status
Simulation time 2431289526 ps
CPU time 64.75 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:23:57 PM PDT 24
Peak memory 267432 kb
Host smart-4001f0cb-e64a-4b81-892d-0a84ad659682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504831191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2504831191
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2670736072
Short name T778
Test name
Test status
Simulation time 20997697280 ps
CPU time 473.87 seconds
Started Jul 30 05:22:49 PM PDT 24
Finished Jul 30 05:30:43 PM PDT 24
Peak memory 284016 kb
Host smart-9ea5161d-37be-4d91-bfdc-f4407f1b7be1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2670736072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2670736072
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3165696336
Short name T626
Test name
Test status
Simulation time 13109570 ps
CPU time 1.04 seconds
Started Jul 30 05:22:48 PM PDT 24
Finished Jul 30 05:22:50 PM PDT 24
Peak memory 212068 kb
Host smart-51887b7c-6d13-4982-8fed-748c50b7b68c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165696336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3165696336
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.4115113821
Short name T765
Test name
Test status
Simulation time 16188310 ps
CPU time 1.11 seconds
Started Jul 30 05:22:54 PM PDT 24
Finished Jul 30 05:22:56 PM PDT 24
Peak memory 209052 kb
Host smart-ab5d6c40-d7e8-42c3-87b8-f89668c77b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115113821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4115113821
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3408214618
Short name T40
Test name
Test status
Simulation time 262262726 ps
CPU time 11.21 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:23:03 PM PDT 24
Peak memory 218392 kb
Host smart-c6c20d56-221e-4159-bec7-b8b8371c82ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408214618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3408214618
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1853523105
Short name T837
Test name
Test status
Simulation time 1271761827 ps
CPU time 14.8 seconds
Started Jul 30 05:22:55 PM PDT 24
Finished Jul 30 05:23:09 PM PDT 24
Peak memory 217332 kb
Host smart-44835fe8-3e95-4239-92c8-5abb55c442bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853523105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1853523105
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3658627897
Short name T795
Test name
Test status
Simulation time 602682436 ps
CPU time 6.27 seconds
Started Jul 30 05:22:54 PM PDT 24
Finished Jul 30 05:23:00 PM PDT 24
Peak memory 223208 kb
Host smart-94845580-9d9a-4fa3-9ff9-52abd4f9a2b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658627897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3658627897
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.347292896
Short name T58
Test name
Test status
Simulation time 140482113 ps
CPU time 2.58 seconds
Started Jul 30 05:22:56 PM PDT 24
Finished Jul 30 05:22:59 PM PDT 24
Peak memory 217728 kb
Host smart-ba4bf69b-dbdb-4738-b309-a201066fc63d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347292896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
347292896
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2247613619
Short name T310
Test name
Test status
Simulation time 2179621891 ps
CPU time 48.36 seconds
Started Jul 30 05:22:54 PM PDT 24
Finished Jul 30 05:23:43 PM PDT 24
Peak memory 275680 kb
Host smart-f3e00088-b907-4212-9d11-4559b7ece331
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247613619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2247613619
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1790530270
Short name T272
Test name
Test status
Simulation time 1221411112 ps
CPU time 13.03 seconds
Started Jul 30 05:22:56 PM PDT 24
Finished Jul 30 05:23:09 PM PDT 24
Peak memory 251032 kb
Host smart-de56bc9e-8a6a-46ab-8e18-49437d11791e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790530270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1790530270
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3376605413
Short name T733
Test name
Test status
Simulation time 58237340 ps
CPU time 2.62 seconds
Started Jul 30 05:22:50 PM PDT 24
Finished Jul 30 05:22:53 PM PDT 24
Peak memory 218320 kb
Host smart-04e11b58-e58f-4ea2-98f9-c99fa93e9724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376605413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3376605413
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1888331876
Short name T582
Test name
Test status
Simulation time 1278100806 ps
CPU time 12.96 seconds
Started Jul 30 05:22:58 PM PDT 24
Finished Jul 30 05:23:11 PM PDT 24
Peak memory 218288 kb
Host smart-41da5ddd-5683-4ddf-9de8-4ab23be33a6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888331876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1888331876
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3016329668
Short name T279
Test name
Test status
Simulation time 3687611411 ps
CPU time 9.35 seconds
Started Jul 30 05:22:55 PM PDT 24
Finished Jul 30 05:23:04 PM PDT 24
Peak memory 218448 kb
Host smart-0c2c405b-5b1f-4c13-93de-ac5c364f0bf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016329668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3016329668
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1085132498
Short name T484
Test name
Test status
Simulation time 936607670 ps
CPU time 8.36 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:23:01 PM PDT 24
Peak memory 218572 kb
Host smart-8f2b4674-7061-4684-a0d4-bc72e19081fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085132498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1085132498
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2472636390
Short name T693
Test name
Test status
Simulation time 142329031 ps
CPU time 4.3 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:22:56 PM PDT 24
Peak memory 217828 kb
Host smart-b826077c-4041-40f2-9367-8e3ded9ba69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472636390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2472636390
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2000544723
Short name T854
Test name
Test status
Simulation time 306777255 ps
CPU time 29.28 seconds
Started Jul 30 05:22:51 PM PDT 24
Finished Jul 30 05:23:21 PM PDT 24
Peak memory 251028 kb
Host smart-7f307cd8-9f0c-409a-9bc2-a4d059bfeae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000544723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2000544723
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1007652347
Short name T487
Test name
Test status
Simulation time 56280843 ps
CPU time 6.95 seconds
Started Jul 30 05:22:52 PM PDT 24
Finished Jul 30 05:22:59 PM PDT 24
Peak memory 242948 kb
Host smart-1bbc542a-4823-4214-938f-693b69cfaae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007652347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1007652347
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2383775168
Short name T675
Test name
Test status
Simulation time 1635843663 ps
CPU time 51.63 seconds
Started Jul 30 05:22:55 PM PDT 24
Finished Jul 30 05:23:47 PM PDT 24
Peak memory 251052 kb
Host smart-86ac948a-c11d-4929-990e-0720ffbc2181
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383775168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2383775168
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.708589070
Short name T379
Test name
Test status
Simulation time 45511191 ps
CPU time 0.85 seconds
Started Jul 30 05:22:53 PM PDT 24
Finished Jul 30 05:22:54 PM PDT 24
Peak memory 212116 kb
Host smart-9ad2eb9f-c1fb-42a8-8c97-9a6939b528ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708589070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.708589070
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3090940475
Short name T79
Test name
Test status
Simulation time 17529740 ps
CPU time 0.91 seconds
Started Jul 30 05:22:59 PM PDT 24
Finished Jul 30 05:23:00 PM PDT 24
Peak memory 208880 kb
Host smart-b924e980-27ae-47d6-9020-f573270aa289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090940475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3090940475
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.219188748
Short name T296
Test name
Test status
Simulation time 442795332 ps
CPU time 11.08 seconds
Started Jul 30 05:22:55 PM PDT 24
Finished Jul 30 05:23:06 PM PDT 24
Peak memory 218424 kb
Host smart-394e6404-9473-49d3-aa62-0b89e0cf7ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219188748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.219188748
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.161953247
Short name T824
Test name
Test status
Simulation time 286898202 ps
CPU time 5.41 seconds
Started Jul 30 05:23:00 PM PDT 24
Finished Jul 30 05:23:05 PM PDT 24
Peak memory 217656 kb
Host smart-ac81b85d-6cc9-4fdd-87b2-b2f8131c1c05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161953247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.161953247
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1324307103
Short name T155
Test name
Test status
Simulation time 10147050627 ps
CPU time 137.3 seconds
Started Jul 30 05:23:02 PM PDT 24
Finished Jul 30 05:25:19 PM PDT 24
Peak memory 221044 kb
Host smart-a75c9769-23b3-468b-96a9-4946f5300276
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324307103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1324307103
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2934574109
Short name T444
Test name
Test status
Simulation time 156712134 ps
CPU time 3.28 seconds
Started Jul 30 05:23:00 PM PDT 24
Finished Jul 30 05:23:03 PM PDT 24
Peak memory 221564 kb
Host smart-aafcdb54-41b1-4c47-9890-588ad3a8e917
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934574109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2934574109
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.930067205
Short name T612
Test name
Test status
Simulation time 147312197 ps
CPU time 2.78 seconds
Started Jul 30 05:23:03 PM PDT 24
Finished Jul 30 05:23:06 PM PDT 24
Peak memory 217664 kb
Host smart-c86f0a6d-a919-4689-b312-c0ec8ab3074a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930067205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
930067205
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.792179369
Short name T435
Test name
Test status
Simulation time 5054716401 ps
CPU time 62.55 seconds
Started Jul 30 05:23:03 PM PDT 24
Finished Jul 30 05:24:06 PM PDT 24
Peak memory 251456 kb
Host smart-438959b7-5bb6-43e5-a67a-48a2499562e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792179369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.792179369
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.897790477
Short name T419
Test name
Test status
Simulation time 957867678 ps
CPU time 11.54 seconds
Started Jul 30 05:22:58 PM PDT 24
Finished Jul 30 05:23:09 PM PDT 24
Peak memory 243084 kb
Host smart-8117463d-0b32-466b-a0cf-a3acb2d389fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897790477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.897790477
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.4084745966
Short name T240
Test name
Test status
Simulation time 271533541 ps
CPU time 10.77 seconds
Started Jul 30 05:23:01 PM PDT 24
Finished Jul 30 05:23:12 PM PDT 24
Peak memory 219064 kb
Host smart-6d055848-7bad-49d5-81f9-9065a3310df3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084745966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4084745966
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3673368022
Short name T358
Test name
Test status
Simulation time 365501776 ps
CPU time 10 seconds
Started Jul 30 05:23:03 PM PDT 24
Finished Jul 30 05:23:13 PM PDT 24
Peak memory 218340 kb
Host smart-b589ef2f-e464-4ef8-bc26-55c6f302aa15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673368022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3673368022
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3277178173
Short name T323
Test name
Test status
Simulation time 525899673 ps
CPU time 10.61 seconds
Started Jul 30 05:22:59 PM PDT 24
Finished Jul 30 05:23:10 PM PDT 24
Peak memory 218352 kb
Host smart-879d7288-870b-49f8-8ec6-2ff18d4a14ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277178173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3277178173
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2894078291
Short name T45
Test name
Test status
Simulation time 1017869853 ps
CPU time 8.43 seconds
Started Jul 30 05:22:56 PM PDT 24
Finished Jul 30 05:23:05 PM PDT 24
Peak memory 218476 kb
Host smart-aa5e3fc1-5f04-4ae3-bf1d-d442ef9b72b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894078291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2894078291
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.4088596173
Short name T458
Test name
Test status
Simulation time 74919599 ps
CPU time 1.82 seconds
Started Jul 30 05:22:55 PM PDT 24
Finished Jul 30 05:22:57 PM PDT 24
Peak memory 214276 kb
Host smart-5bdc896f-58df-497c-a99f-2b4b2766b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088596173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4088596173
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2804431537
Short name T11
Test name
Test status
Simulation time 2384820559 ps
CPU time 28.29 seconds
Started Jul 30 05:22:58 PM PDT 24
Finished Jul 30 05:23:26 PM PDT 24
Peak memory 251056 kb
Host smart-7c90edcd-67d2-4a27-ad3f-3569f8ca64a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804431537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2804431537
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1650211966
Short name T579
Test name
Test status
Simulation time 129254536 ps
CPU time 7.05 seconds
Started Jul 30 05:22:55 PM PDT 24
Finished Jul 30 05:23:02 PM PDT 24
Peak memory 242676 kb
Host smart-584aea3c-abae-4eee-9909-75f52a9b4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650211966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1650211966
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2485327320
Short name T543
Test name
Test status
Simulation time 5294152705 ps
CPU time 203.51 seconds
Started Jul 30 05:22:59 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 279560 kb
Host smart-54838357-dcbf-4080-9286-1d68e4167418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485327320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2485327320
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.784558112
Short name T127
Test name
Test status
Simulation time 56644126807 ps
CPU time 5898.08 seconds
Started Jul 30 05:23:00 PM PDT 24
Finished Jul 30 07:01:19 PM PDT 24
Peak memory 1185104 kb
Host smart-af545292-4d53-4a4a-b479-dfda1d44d914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=784558112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.784558112
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.886598777
Short name T748
Test name
Test status
Simulation time 48112687 ps
CPU time 0.96 seconds
Started Jul 30 05:22:54 PM PDT 24
Finished Jul 30 05:22:55 PM PDT 24
Peak memory 211916 kb
Host smart-dbe21854-3e88-4617-898d-700c40830235
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886598777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.886598777
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2197753238
Short name T550
Test name
Test status
Simulation time 54416079 ps
CPU time 1.06 seconds
Started Jul 30 05:23:08 PM PDT 24
Finished Jul 30 05:23:10 PM PDT 24
Peak memory 209124 kb
Host smart-6d42ccac-a248-4269-80e7-9cb2ed91177c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197753238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2197753238
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1726671824
Short name T482
Test name
Test status
Simulation time 695374560 ps
CPU time 19.25 seconds
Started Jul 30 05:23:05 PM PDT 24
Finished Jul 30 05:23:25 PM PDT 24
Peak memory 218292 kb
Host smart-8ddab5a6-056a-48b0-b642-698c596514fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726671824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1726671824
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2265422460
Short name T7
Test name
Test status
Simulation time 846502603 ps
CPU time 5.24 seconds
Started Jul 30 05:23:07 PM PDT 24
Finished Jul 30 05:23:12 PM PDT 24
Peak memory 217244 kb
Host smart-dee5d6bc-3fbf-47b9-b58e-a440858ff073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265422460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2265422460
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2199945185
Short name T152
Test name
Test status
Simulation time 3118626416 ps
CPU time 38.48 seconds
Started Jul 30 05:23:04 PM PDT 24
Finished Jul 30 05:23:42 PM PDT 24
Peak memory 226232 kb
Host smart-0cedcf36-a1d7-4e10-b137-91a4ebcdad53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199945185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2199945185
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.673320100
Short name T774
Test name
Test status
Simulation time 346696291 ps
CPU time 6.69 seconds
Started Jul 30 05:23:06 PM PDT 24
Finished Jul 30 05:23:12 PM PDT 24
Peak memory 223276 kb
Host smart-adfbd409-a473-4ab5-9b23-76671da4b33c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673320100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.673320100
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3813095137
Short name T384
Test name
Test status
Simulation time 2610783025 ps
CPU time 8.71 seconds
Started Jul 30 05:23:05 PM PDT 24
Finished Jul 30 05:23:14 PM PDT 24
Peak memory 217916 kb
Host smart-15803009-f481-46c1-8a2c-43f8c819b8f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813095137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3813095137
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3183690806
Short name T445
Test name
Test status
Simulation time 4953329428 ps
CPU time 44.34 seconds
Started Jul 30 05:23:05 PM PDT 24
Finished Jul 30 05:23:50 PM PDT 24
Peak memory 275940 kb
Host smart-ca20f7dd-f109-4d69-8576-a088bd015589
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183690806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3183690806
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.259661716
Short name T427
Test name
Test status
Simulation time 4003396249 ps
CPU time 31.16 seconds
Started Jul 30 05:23:04 PM PDT 24
Finished Jul 30 05:23:35 PM PDT 24
Peak memory 247576 kb
Host smart-92f89bed-08fd-4e0b-826a-39857527cc71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259661716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.259661716
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3672905285
Short name T429
Test name
Test status
Simulation time 373397688 ps
CPU time 3.56 seconds
Started Jul 30 05:23:04 PM PDT 24
Finished Jul 30 05:23:08 PM PDT 24
Peak memory 218384 kb
Host smart-b03cff79-1282-477e-b6cf-ba33919ed969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672905285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3672905285
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3323629567
Short name T348
Test name
Test status
Simulation time 335310340 ps
CPU time 14.43 seconds
Started Jul 30 05:23:05 PM PDT 24
Finished Jul 30 05:23:20 PM PDT 24
Peak memory 226176 kb
Host smart-869bc31d-d474-4c2f-a61f-2c105fd5a111
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323629567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3323629567
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.445712101
Short name T203
Test name
Test status
Simulation time 764754343 ps
CPU time 10.59 seconds
Started Jul 30 05:23:06 PM PDT 24
Finished Jul 30 05:23:17 PM PDT 24
Peak memory 226048 kb
Host smart-f328a68c-a806-4526-9037-719b4e4c70f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445712101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.445712101
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2412999641
Short name T730
Test name
Test status
Simulation time 1338755158 ps
CPU time 9.67 seconds
Started Jul 30 05:23:03 PM PDT 24
Finished Jul 30 05:23:13 PM PDT 24
Peak memory 218544 kb
Host smart-0fd5b54b-a765-45da-b0f9-ab74c668cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412999641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2412999641
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2801881547
Short name T396
Test name
Test status
Simulation time 271854782 ps
CPU time 3.85 seconds
Started Jul 30 05:23:04 PM PDT 24
Finished Jul 30 05:23:08 PM PDT 24
Peak memory 217884 kb
Host smart-6c2de334-88fa-4524-868f-de03341073e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801881547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2801881547
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.115390519
Short name T504
Test name
Test status
Simulation time 278772740 ps
CPU time 18.18 seconds
Started Jul 30 05:23:05 PM PDT 24
Finished Jul 30 05:23:23 PM PDT 24
Peak memory 250876 kb
Host smart-4c038bdb-f5dc-463d-b30a-953bc3250f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115390519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.115390519
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2084296245
Short name T235
Test name
Test status
Simulation time 82260996 ps
CPU time 7.28 seconds
Started Jul 30 05:23:03 PM PDT 24
Finished Jul 30 05:23:11 PM PDT 24
Peak memory 251048 kb
Host smart-082172ae-497b-499d-baba-e2d3f9157647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084296245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2084296245
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1434663655
Short name T491
Test name
Test status
Simulation time 38249383 ps
CPU time 0.95 seconds
Started Jul 30 05:23:05 PM PDT 24
Finished Jul 30 05:23:07 PM PDT 24
Peak memory 212052 kb
Host smart-c30d85ca-ad3f-4028-ba27-c722496a405e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434663655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1434663655
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.606704584
Short name T347
Test name
Test status
Simulation time 76788534 ps
CPU time 0.92 seconds
Started Jul 30 05:23:13 PM PDT 24
Finished Jul 30 05:23:14 PM PDT 24
Peak memory 209016 kb
Host smart-69cbadcb-41e9-4647-8d67-804457c8a959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606704584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.606704584
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.411062247
Short name T201
Test name
Test status
Simulation time 667500906 ps
CPU time 9.22 seconds
Started Jul 30 05:23:07 PM PDT 24
Finished Jul 30 05:23:16 PM PDT 24
Peak memory 218268 kb
Host smart-eb1064fa-3abb-4c61-91f3-0e4886ff2798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411062247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.411062247
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1680607123
Short name T671
Test name
Test status
Simulation time 134857032 ps
CPU time 1.4 seconds
Started Jul 30 05:23:11 PM PDT 24
Finished Jul 30 05:23:12 PM PDT 24
Peak memory 217172 kb
Host smart-5c8a58ba-2fcf-4cd5-aa45-57f156001806
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680607123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1680607123
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.4019123832
Short name T787
Test name
Test status
Simulation time 12049724050 ps
CPU time 32.61 seconds
Started Jul 30 05:23:07 PM PDT 24
Finished Jul 30 05:23:40 PM PDT 24
Peak memory 226108 kb
Host smart-0b8f38ff-faf4-4a60-99a1-4a12a43846d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019123832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.4019123832
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4125893876
Short name T495
Test name
Test status
Simulation time 351683602 ps
CPU time 2.43 seconds
Started Jul 30 05:23:08 PM PDT 24
Finished Jul 30 05:23:11 PM PDT 24
Peak memory 218336 kb
Host smart-ebd1d232-c1af-4454-9a47-844051327369
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125893876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4125893876
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3687472782
Short name T59
Test name
Test status
Simulation time 249553663 ps
CPU time 4.47 seconds
Started Jul 30 05:23:08 PM PDT 24
Finished Jul 30 05:23:12 PM PDT 24
Peak memory 217764 kb
Host smart-a306049b-4039-428f-b3f5-5bdc295ae004
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687472782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3687472782
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.671271041
Short name T731
Test name
Test status
Simulation time 14594784212 ps
CPU time 110.31 seconds
Started Jul 30 05:23:09 PM PDT 24
Finished Jul 30 05:25:00 PM PDT 24
Peak memory 283616 kb
Host smart-f471fc9a-6211-4eb9-9cad-4243f36402e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671271041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.671271041
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3524928804
Short name T540
Test name
Test status
Simulation time 1633055500 ps
CPU time 10.77 seconds
Started Jul 30 05:23:08 PM PDT 24
Finished Jul 30 05:23:18 PM PDT 24
Peak memory 250548 kb
Host smart-5e2006a8-41f8-4080-a74d-11841e24e00a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524928804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3524928804
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3434829608
Short name T168
Test name
Test status
Simulation time 370925723 ps
CPU time 3.53 seconds
Started Jul 30 05:23:11 PM PDT 24
Finished Jul 30 05:23:15 PM PDT 24
Peak memory 218452 kb
Host smart-ff7fe7d6-3199-44ff-b2da-acc2765eaf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434829608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3434829608
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.4029939505
Short name T750
Test name
Test status
Simulation time 965515797 ps
CPU time 11.52 seconds
Started Jul 30 05:23:08 PM PDT 24
Finished Jul 30 05:23:19 PM PDT 24
Peak memory 219092 kb
Host smart-a2cc22ca-23a9-4a49-93bf-a9e432650a94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029939505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.4029939505
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3047521330
Short name T130
Test name
Test status
Simulation time 386308186 ps
CPU time 10.3 seconds
Started Jul 30 05:23:11 PM PDT 24
Finished Jul 30 05:23:21 PM PDT 24
Peak memory 218348 kb
Host smart-36a51beb-1743-42de-a137-7b8da1bf6c76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047521330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3047521330
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2972384368
Short name T591
Test name
Test status
Simulation time 274593168 ps
CPU time 10.47 seconds
Started Jul 30 05:23:10 PM PDT 24
Finished Jul 30 05:23:21 PM PDT 24
Peak memory 218348 kb
Host smart-dc31e2cb-867f-4061-a951-91b0f6f3e7a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972384368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2972384368
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1974086897
Short name T642
Test name
Test status
Simulation time 663072623 ps
CPU time 14.59 seconds
Started Jul 30 05:23:09 PM PDT 24
Finished Jul 30 05:23:24 PM PDT 24
Peak memory 226144 kb
Host smart-787fb665-adf5-4c54-a5e8-4f50fc418fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974086897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1974086897
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.92896819
Short name T326
Test name
Test status
Simulation time 13408166 ps
CPU time 1.13 seconds
Started Jul 30 05:23:09 PM PDT 24
Finished Jul 30 05:23:11 PM PDT 24
Peak memory 212196 kb
Host smart-8cebbdf4-678e-402a-a90f-0c04253f6e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92896819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.92896819
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3178045850
Short name T533
Test name
Test status
Simulation time 2115836737 ps
CPU time 26.87 seconds
Started Jul 30 05:23:08 PM PDT 24
Finished Jul 30 05:23:35 PM PDT 24
Peak memory 251152 kb
Host smart-3653d649-9e02-4aff-aabc-f3a58afeed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178045850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3178045850
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1678945502
Short name T411
Test name
Test status
Simulation time 160594047 ps
CPU time 6.75 seconds
Started Jul 30 05:23:08 PM PDT 24
Finished Jul 30 05:23:15 PM PDT 24
Peak memory 246800 kb
Host smart-8661e73f-80c7-4d6c-9d06-f86f2201dc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678945502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1678945502
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1483206390
Short name T565
Test name
Test status
Simulation time 777496485 ps
CPU time 34.66 seconds
Started Jul 30 05:23:09 PM PDT 24
Finished Jul 30 05:23:43 PM PDT 24
Peak memory 251008 kb
Host smart-72bd24fd-c12f-4b01-9241-f46f4f765b56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483206390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1483206390
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1202443804
Short name T706
Test name
Test status
Simulation time 26685087 ps
CPU time 0.88 seconds
Started Jul 30 05:23:10 PM PDT 24
Finished Jul 30 05:23:11 PM PDT 24
Peak memory 212076 kb
Host smart-38256d61-e749-4680-9766-ea2309df5933
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202443804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1202443804
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2547565442
Short name T446
Test name
Test status
Simulation time 103055246 ps
CPU time 0.95 seconds
Started Jul 30 05:23:20 PM PDT 24
Finished Jul 30 05:23:21 PM PDT 24
Peak memory 209100 kb
Host smart-c280342c-8664-4ff6-88b6-3c186446385b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547565442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2547565442
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.397193459
Short name T297
Test name
Test status
Simulation time 1462805983 ps
CPU time 14.16 seconds
Started Jul 30 05:23:18 PM PDT 24
Finished Jul 30 05:23:32 PM PDT 24
Peak memory 218392 kb
Host smart-e4b25f86-f5ac-47b8-b859-630423cc5961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397193459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.397193459
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.58421208
Short name T596
Test name
Test status
Simulation time 821422468 ps
CPU time 5.21 seconds
Started Jul 30 05:23:14 PM PDT 24
Finished Jul 30 05:23:19 PM PDT 24
Peak memory 217772 kb
Host smart-1a2645e1-8d74-408a-8774-2f7f0b6488f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58421208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.58421208
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.101829295
Short name T656
Test name
Test status
Simulation time 5049987269 ps
CPU time 40.88 seconds
Started Jul 30 05:23:12 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 218288 kb
Host smart-045e65d3-dade-4468-8046-37966ef0223a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101829295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.101829295
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.706867977
Short name T735
Test name
Test status
Simulation time 445656040 ps
CPU time 3.56 seconds
Started Jul 30 05:23:15 PM PDT 24
Finished Jul 30 05:23:18 PM PDT 24
Peak memory 221828 kb
Host smart-ebcf5615-661b-4583-9c39-ed909362b2b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706867977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.706867977
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1991212455
Short name T689
Test name
Test status
Simulation time 760129111 ps
CPU time 17.7 seconds
Started Jul 30 05:23:14 PM PDT 24
Finished Jul 30 05:23:32 PM PDT 24
Peak memory 217768 kb
Host smart-0779d3d4-40ab-4640-8563-ff9037fa5f05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991212455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1991212455
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.958864443
Short name T636
Test name
Test status
Simulation time 1160114683 ps
CPU time 41.6 seconds
Started Jul 30 05:23:18 PM PDT 24
Finished Jul 30 05:23:59 PM PDT 24
Peak memory 267400 kb
Host smart-dc1c2436-8fbd-4613-bfd9-bd347cd43ac3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958864443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.958864443
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4241988617
Short name T810
Test name
Test status
Simulation time 2140435302 ps
CPU time 18.96 seconds
Started Jul 30 05:23:12 PM PDT 24
Finished Jul 30 05:23:31 PM PDT 24
Peak memory 250516 kb
Host smart-4593acbc-9e9c-482f-a0d3-06b2aa185013
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241988617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.4241988617
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1643025898
Short name T644
Test name
Test status
Simulation time 86184558 ps
CPU time 2.59 seconds
Started Jul 30 05:23:12 PM PDT 24
Finished Jul 30 05:23:15 PM PDT 24
Peak memory 218352 kb
Host smart-0b1df38a-3e2e-4ecd-90f8-8c5a2b57dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643025898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1643025898
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3434573859
Short name T237
Test name
Test status
Simulation time 4500410368 ps
CPU time 12.85 seconds
Started Jul 30 05:23:11 PM PDT 24
Finished Jul 30 05:23:24 PM PDT 24
Peak memory 218768 kb
Host smart-01a6e0c8-ede0-4be3-8a6d-b9278e86f2cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434573859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3434573859
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3481839267
Short name T746
Test name
Test status
Simulation time 970723722 ps
CPU time 10.47 seconds
Started Jul 30 05:23:12 PM PDT 24
Finished Jul 30 05:23:22 PM PDT 24
Peak memory 218312 kb
Host smart-6553ce01-6cc6-4c1b-88d5-6ab4f888c901
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481839267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3481839267
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1292553374
Short name T815
Test name
Test status
Simulation time 365861033 ps
CPU time 11.1 seconds
Started Jul 30 05:23:12 PM PDT 24
Finished Jul 30 05:23:24 PM PDT 24
Peak memory 225516 kb
Host smart-00c52b7e-7142-4602-9e21-56db6183e497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292553374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1292553374
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1278562982
Short name T859
Test name
Test status
Simulation time 1085532646 ps
CPU time 11.51 seconds
Started Jul 30 05:23:15 PM PDT 24
Finished Jul 30 05:23:27 PM PDT 24
Peak memory 218376 kb
Host smart-681dedb2-f2bd-4974-98e5-261427f8b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278562982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1278562982
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1580649920
Short name T676
Test name
Test status
Simulation time 67935343 ps
CPU time 4.21 seconds
Started Jul 30 05:23:14 PM PDT 24
Finished Jul 30 05:23:18 PM PDT 24
Peak memory 217920 kb
Host smart-0e06d698-cb5a-404c-83cd-b21e8e9edb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580649920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1580649920
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1299455203
Short name T552
Test name
Test status
Simulation time 2177650297 ps
CPU time 19.64 seconds
Started Jul 30 05:23:13 PM PDT 24
Finished Jul 30 05:23:33 PM PDT 24
Peak memory 251076 kb
Host smart-eb635217-e30a-467d-b090-eed41bf61ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299455203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1299455203
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.53819379
Short name T786
Test name
Test status
Simulation time 360227267 ps
CPU time 6.88 seconds
Started Jul 30 05:23:12 PM PDT 24
Finished Jul 30 05:23:19 PM PDT 24
Peak memory 247548 kb
Host smart-26ae43b8-8912-4614-81da-1eff705cf31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53819379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.53819379
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2235671133
Short name T293
Test name
Test status
Simulation time 25777540 ps
CPU time 1.01 seconds
Started Jul 30 05:23:14 PM PDT 24
Finished Jul 30 05:23:15 PM PDT 24
Peak memory 213124 kb
Host smart-b07e03c4-2d58-4276-918c-462d316aa926
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235671133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2235671133
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3855686330
Short name T290
Test name
Test status
Simulation time 82723004 ps
CPU time 0.85 seconds
Started Jul 30 05:23:26 PM PDT 24
Finished Jul 30 05:23:27 PM PDT 24
Peak memory 209288 kb
Host smart-4fa3b4ae-6747-4689-b265-3d7c9b63792a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855686330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3855686330
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2248279769
Short name T654
Test name
Test status
Simulation time 1877352705 ps
CPU time 14.35 seconds
Started Jul 30 05:23:20 PM PDT 24
Finished Jul 30 05:23:34 PM PDT 24
Peak memory 226224 kb
Host smart-0e396f3a-f400-4615-81a5-da349ee6ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248279769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2248279769
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3028236002
Short name T371
Test name
Test status
Simulation time 716849610 ps
CPU time 10.35 seconds
Started Jul 30 05:23:17 PM PDT 24
Finished Jul 30 05:23:27 PM PDT 24
Peak memory 217524 kb
Host smart-53fdb381-c77d-440f-ad4d-8f6c92901f52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028236002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3028236002
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2276543968
Short name T665
Test name
Test status
Simulation time 5327492684 ps
CPU time 41.71 seconds
Started Jul 30 05:23:16 PM PDT 24
Finished Jul 30 05:23:58 PM PDT 24
Peak memory 218844 kb
Host smart-c781e021-46d6-45d9-a010-c313ea89134b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276543968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2276543968
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3910400489
Short name T687
Test name
Test status
Simulation time 1321098165 ps
CPU time 9.21 seconds
Started Jul 30 05:23:19 PM PDT 24
Finished Jul 30 05:23:28 PM PDT 24
Peak memory 218208 kb
Host smart-091bff59-e361-48c1-b18c-5c66aebe09f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910400489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3910400489
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1111169516
Short name T828
Test name
Test status
Simulation time 352592240 ps
CPU time 3.88 seconds
Started Jul 30 05:23:17 PM PDT 24
Finished Jul 30 05:23:21 PM PDT 24
Peak memory 217768 kb
Host smart-dc5999fb-fde8-4d6a-9a48-0eb38ad4c048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111169516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1111169516
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.588361054
Short name T331
Test name
Test status
Simulation time 21448248829 ps
CPU time 60.63 seconds
Started Jul 30 05:23:23 PM PDT 24
Finished Jul 30 05:24:24 PM PDT 24
Peak memory 251020 kb
Host smart-c3174bc4-a23b-469d-931f-604f6b629253
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588361054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.588361054
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2116002667
Short name T350
Test name
Test status
Simulation time 942056705 ps
CPU time 19.87 seconds
Started Jul 30 05:23:17 PM PDT 24
Finished Jul 30 05:23:37 PM PDT 24
Peak memory 250856 kb
Host smart-1048bb0d-5dc1-4684-8984-561a8ec274a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116002667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2116002667
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.434601366
Short name T817
Test name
Test status
Simulation time 89432742 ps
CPU time 1.93 seconds
Started Jul 30 05:23:18 PM PDT 24
Finished Jul 30 05:23:20 PM PDT 24
Peak memory 218404 kb
Host smart-36b1996c-5302-402e-9dd0-8eb1e5517541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434601366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.434601366
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3663332007
Short name T165
Test name
Test status
Simulation time 664387278 ps
CPU time 17.38 seconds
Started Jul 30 05:23:16 PM PDT 24
Finished Jul 30 05:23:33 PM PDT 24
Peak memory 226188 kb
Host smart-78056edb-48a5-4454-b962-3b0296f70386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663332007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3663332007
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.313374569
Short name T584
Test name
Test status
Simulation time 1808702629 ps
CPU time 12.9 seconds
Started Jul 30 05:23:26 PM PDT 24
Finished Jul 30 05:23:39 PM PDT 24
Peak memory 226140 kb
Host smart-9f1ee210-a66b-4b5d-b71b-fcca294ec9db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313374569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.313374569
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.579191207
Short name T586
Test name
Test status
Simulation time 915932016 ps
CPU time 8.17 seconds
Started Jul 30 05:23:22 PM PDT 24
Finished Jul 30 05:23:30 PM PDT 24
Peak memory 218400 kb
Host smart-97ef9271-143b-414c-b126-0a4f71dd710e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579191207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.579191207
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3088676945
Short name T702
Test name
Test status
Simulation time 1123530100 ps
CPU time 8.74 seconds
Started Jul 30 05:23:16 PM PDT 24
Finished Jul 30 05:23:25 PM PDT 24
Peak memory 226216 kb
Host smart-e844546f-e972-4995-8d68-56e10151daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088676945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3088676945
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.861519595
Short name T708
Test name
Test status
Simulation time 169609141 ps
CPU time 2.85 seconds
Started Jul 30 05:23:17 PM PDT 24
Finished Jul 30 05:23:20 PM PDT 24
Peak memory 214900 kb
Host smart-f0986123-ff50-4121-9500-a12359cd3708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861519595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.861519595
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3979556975
Short name T744
Test name
Test status
Simulation time 324701551 ps
CPU time 23.83 seconds
Started Jul 30 05:23:17 PM PDT 24
Finished Jul 30 05:23:41 PM PDT 24
Peak memory 250924 kb
Host smart-deb7da33-f5bd-40aa-aaa7-779958510b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979556975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3979556975
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.4095346276
Short name T308
Test name
Test status
Simulation time 84326972 ps
CPU time 3.54 seconds
Started Jul 30 05:23:20 PM PDT 24
Finished Jul 30 05:23:23 PM PDT 24
Peak memory 222388 kb
Host smart-4f9b9366-8eea-4dc3-a9e8-3470bda25ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095346276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4095346276
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1886736050
Short name T637
Test name
Test status
Simulation time 1144578110 ps
CPU time 40.81 seconds
Started Jul 30 05:23:23 PM PDT 24
Finished Jul 30 05:24:04 PM PDT 24
Peak memory 245804 kb
Host smart-5efdc7e8-e064-42d4-98f4-ed8ad114bc92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886736050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1886736050
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.313514370
Short name T490
Test name
Test status
Simulation time 13546671 ps
CPU time 1.06 seconds
Started Jul 30 05:23:16 PM PDT 24
Finished Jul 30 05:23:17 PM PDT 24
Peak memory 212088 kb
Host smart-80df8ec2-943b-4d4a-8c81-dbcc6ab5281c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313514370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.313514370
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2629705519
Short name T562
Test name
Test status
Simulation time 25064200 ps
CPU time 1.29 seconds
Started Jul 30 05:23:27 PM PDT 24
Finished Jul 30 05:23:29 PM PDT 24
Peak memory 209216 kb
Host smart-357dc6ed-85ab-4088-9bf3-02bed6a0c640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629705519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2629705519
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.4036367159
Short name T263
Test name
Test status
Simulation time 2817443859 ps
CPU time 19.48 seconds
Started Jul 30 05:23:26 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 226116 kb
Host smart-4847e490-907e-4b0e-9eb2-886e3613b7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036367159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.4036367159
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3548095116
Short name T638
Test name
Test status
Simulation time 1988326903 ps
CPU time 33.88 seconds
Started Jul 30 05:23:20 PM PDT 24
Finished Jul 30 05:23:54 PM PDT 24
Peak memory 218320 kb
Host smart-3a1ac0a9-4f2d-4894-8f35-787ec7c69773
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548095116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3548095116
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1726352579
Short name T344
Test name
Test status
Simulation time 1512888584 ps
CPU time 11.84 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:23:33 PM PDT 24
Peak memory 218348 kb
Host smart-7e39a17d-0e77-498a-9a94-6f0fa32c2c13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726352579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1726352579
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2043482980
Short name T360
Test name
Test status
Simulation time 1382795708 ps
CPU time 9.04 seconds
Started Jul 30 05:23:23 PM PDT 24
Finished Jul 30 05:23:33 PM PDT 24
Peak memory 217784 kb
Host smart-12d63ffc-d4c3-4f3e-94e8-3780c34f436f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043482980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2043482980
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1681733038
Short name T391
Test name
Test status
Simulation time 2349809876 ps
CPU time 87.01 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:24:48 PM PDT 24
Peak memory 283872 kb
Host smart-a695851a-9f3e-4b6f-943c-8ccb63381f76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681733038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1681733038
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4131604589
Short name T510
Test name
Test status
Simulation time 1318080503 ps
CPU time 39.73 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 248748 kb
Host smart-6c8c9f26-6354-41fa-9c13-cc87a21f7ed8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131604589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4131604589
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3640605501
Short name T317
Test name
Test status
Simulation time 71458469 ps
CPU time 3.28 seconds
Started Jul 30 05:23:22 PM PDT 24
Finished Jul 30 05:23:26 PM PDT 24
Peak memory 218504 kb
Host smart-b837e8e8-f644-441b-9a50-60da004f6b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640605501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3640605501
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3078326375
Short name T756
Test name
Test status
Simulation time 338060949 ps
CPU time 11.28 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:23:32 PM PDT 24
Peak memory 219108 kb
Host smart-00a4e2ad-1017-4054-b485-d47ad0e7df49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078326375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3078326375
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2514907710
Short name T451
Test name
Test status
Simulation time 1340979836 ps
CPU time 14.25 seconds
Started Jul 30 05:23:24 PM PDT 24
Finished Jul 30 05:23:39 PM PDT 24
Peak memory 218340 kb
Host smart-2e5fa9e5-2e2f-4e02-abc4-382817eba760
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514907710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2514907710
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3899433754
Short name T333
Test name
Test status
Simulation time 1386822779 ps
CPU time 9.55 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:23:31 PM PDT 24
Peak memory 218368 kb
Host smart-26d99d0d-73d5-4489-bfc0-27a229ce0990
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899433754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3899433754
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1443598737
Short name T606
Test name
Test status
Simulation time 703416309 ps
CPU time 6.77 seconds
Started Jul 30 05:23:22 PM PDT 24
Finished Jul 30 05:23:28 PM PDT 24
Peak memory 224940 kb
Host smart-2a4b5396-2500-4d68-9299-942811771f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443598737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1443598737
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3706890060
Short name T512
Test name
Test status
Simulation time 707857487 ps
CPU time 5.73 seconds
Started Jul 30 05:23:20 PM PDT 24
Finished Jul 30 05:23:26 PM PDT 24
Peak memory 217784 kb
Host smart-e89db280-61a6-4b63-b43e-b4b43d9f9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706890060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3706890060
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3196102091
Short name T318
Test name
Test status
Simulation time 532848078 ps
CPU time 25.2 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:23:47 PM PDT 24
Peak memory 245608 kb
Host smart-cecbbb6c-36bd-413a-9b30-44c7006a9cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196102091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3196102091
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4188958732
Short name T77
Test name
Test status
Simulation time 237276654 ps
CPU time 7.75 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:23:28 PM PDT 24
Peak memory 246120 kb
Host smart-6224c9e1-519f-44d5-be0c-d683725d90bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188958732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4188958732
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.849149678
Short name T171
Test name
Test status
Simulation time 34886619776 ps
CPU time 113.24 seconds
Started Jul 30 05:23:27 PM PDT 24
Finished Jul 30 05:25:20 PM PDT 24
Peak memory 277552 kb
Host smart-ad2d22db-5ae7-413b-a6d6-f280b6152de0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849149678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.849149678
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2662928326
Short name T383
Test name
Test status
Simulation time 20476813104 ps
CPU time 182.53 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:26:28 PM PDT 24
Peak memory 283976 kb
Host smart-afeda46f-1344-4ccd-aba1-dbe0c024d739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2662928326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2662928326
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3900307408
Short name T725
Test name
Test status
Simulation time 13509787 ps
CPU time 1.04 seconds
Started Jul 30 05:23:21 PM PDT 24
Finished Jul 30 05:23:22 PM PDT 24
Peak memory 211972 kb
Host smart-b3ed6e1c-002f-4b81-b898-18bfc1bff599
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900307408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3900307408
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3045617400
Short name T621
Test name
Test status
Simulation time 46787237 ps
CPU time 1 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:21:55 PM PDT 24
Peak memory 209028 kb
Host smart-ee78e532-9424-4868-96ec-9301527ce0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045617400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3045617400
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2412082864
Short name T13
Test name
Test status
Simulation time 296024557 ps
CPU time 13.7 seconds
Started Jul 30 05:21:49 PM PDT 24
Finished Jul 30 05:22:03 PM PDT 24
Peak memory 218392 kb
Host smart-037ede60-0966-47b0-ac23-ba8f1937087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412082864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2412082864
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2040937017
Short name T674
Test name
Test status
Simulation time 618916688 ps
CPU time 4.94 seconds
Started Jul 30 05:21:50 PM PDT 24
Finished Jul 30 05:21:55 PM PDT 24
Peak memory 217448 kb
Host smart-1beca59e-81c9-45a4-95a4-ea1c76447cb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040937017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2040937017
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1923679166
Short name T846
Test name
Test status
Simulation time 2868578093 ps
CPU time 44.73 seconds
Started Jul 30 05:21:48 PM PDT 24
Finished Jul 30 05:22:32 PM PDT 24
Peak memory 226044 kb
Host smart-2a5d3a08-f7bb-4da3-8903-14f21754389d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923679166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1923679166
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2241009666
Short name T355
Test name
Test status
Simulation time 10113553944 ps
CPU time 10.47 seconds
Started Jul 30 05:21:49 PM PDT 24
Finished Jul 30 05:22:00 PM PDT 24
Peak memory 217944 kb
Host smart-84a2e2fd-69d1-4405-a225-fc388c4dc485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241009666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
241009666
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.565441583
Short name T836
Test name
Test status
Simulation time 299731165 ps
CPU time 5.85 seconds
Started Jul 30 05:21:51 PM PDT 24
Finished Jul 30 05:21:57 PM PDT 24
Peak memory 223144 kb
Host smart-4668958a-617b-4a04-8396-be0a0559dd09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565441583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.565441583
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1621443900
Short name T842
Test name
Test status
Simulation time 704386592 ps
CPU time 9.99 seconds
Started Jul 30 05:21:51 PM PDT 24
Finished Jul 30 05:22:01 PM PDT 24
Peak memory 217724 kb
Host smart-e5efaf24-c0fc-4327-9973-00e57ccc6e09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621443900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1621443900
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1172714843
Short name T23
Test name
Test status
Simulation time 1432061085 ps
CPU time 11.15 seconds
Started Jul 30 05:21:50 PM PDT 24
Finished Jul 30 05:22:01 PM PDT 24
Peak memory 217768 kb
Host smart-a24fcddd-e722-41a6-a326-3c83370f3b82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172714843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1172714843
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1388077960
Short name T217
Test name
Test status
Simulation time 1135856337 ps
CPU time 39.43 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:22:33 PM PDT 24
Peak memory 275556 kb
Host smart-3d873818-96aa-447c-bfd0-bfbb2adcae08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388077960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1388077960
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1266204101
Short name T399
Test name
Test status
Simulation time 432729461 ps
CPU time 21.29 seconds
Started Jul 30 05:21:51 PM PDT 24
Finished Jul 30 05:22:13 PM PDT 24
Peak memory 250936 kb
Host smart-e9807ad2-d58e-4ba6-91ce-a16a5f7ffedb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266204101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1266204101
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3013899585
Short name T55
Test name
Test status
Simulation time 336942696 ps
CPU time 3.82 seconds
Started Jul 30 05:21:49 PM PDT 24
Finished Jul 30 05:21:53 PM PDT 24
Peak memory 218368 kb
Host smart-7e538cf3-1376-45c6-b8ed-fed44577bbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013899585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3013899585
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2798904085
Short name T833
Test name
Test status
Simulation time 4839633269 ps
CPU time 14.67 seconds
Started Jul 30 05:21:51 PM PDT 24
Finished Jul 30 05:22:05 PM PDT 24
Peak memory 215404 kb
Host smart-e1a81212-da87-4b26-a4f9-2d22be8c55e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798904085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2798904085
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.101950311
Short name T82
Test name
Test status
Simulation time 210745904 ps
CPU time 39.17 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:22:32 PM PDT 24
Peak memory 269576 kb
Host smart-351b3fa9-fa9c-42ad-a42a-6036f2496024
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101950311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.101950311
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2231891371
Short name T20
Test name
Test status
Simulation time 1050398477 ps
CPU time 9.67 seconds
Started Jul 30 05:21:52 PM PDT 24
Finished Jul 30 05:22:02 PM PDT 24
Peak memory 226276 kb
Host smart-8cdd6880-fa5c-4775-819c-1342fc170c84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231891371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2231891371
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3582250496
Short name T493
Test name
Test status
Simulation time 1766742302 ps
CPU time 7.98 seconds
Started Jul 30 05:21:51 PM PDT 24
Finished Jul 30 05:21:59 PM PDT 24
Peak memory 218340 kb
Host smart-9c55463f-44b4-49c7-9126-69381bb94e9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582250496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3582250496
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1432918598
Short name T646
Test name
Test status
Simulation time 281096213 ps
CPU time 8.15 seconds
Started Jul 30 05:21:52 PM PDT 24
Finished Jul 30 05:22:00 PM PDT 24
Peak memory 218384 kb
Host smart-7f6ebe17-05f3-4f02-b78d-3c020acd3414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432918598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
432918598
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3308831497
Short name T492
Test name
Test status
Simulation time 266103188 ps
CPU time 12.55 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:22:06 PM PDT 24
Peak memory 226208 kb
Host smart-35316053-0c8b-485a-a968-8edddaca694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308831497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3308831497
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3342567334
Short name T609
Test name
Test status
Simulation time 74852481 ps
CPU time 2.03 seconds
Started Jul 30 05:21:49 PM PDT 24
Finished Jul 30 05:21:51 PM PDT 24
Peak memory 214236 kb
Host smart-0738b8aa-5408-43b2-bb86-42b535f59ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342567334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3342567334
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.717911801
Short name T737
Test name
Test status
Simulation time 256837674 ps
CPU time 28.67 seconds
Started Jul 30 05:21:51 PM PDT 24
Finished Jul 30 05:22:20 PM PDT 24
Peak memory 251020 kb
Host smart-865886c8-da06-4c92-9532-e2b036914d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717911801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.717911801
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3308090305
Short name T131
Test name
Test status
Simulation time 120696175 ps
CPU time 8.88 seconds
Started Jul 30 05:21:47 PM PDT 24
Finished Jul 30 05:21:56 PM PDT 24
Peak memory 250640 kb
Host smart-56ffd953-df46-499d-9fa0-bc27ba5a1ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308090305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3308090305
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.473420526
Short name T307
Test name
Test status
Simulation time 1901920617 ps
CPU time 38.72 seconds
Started Jul 30 05:21:55 PM PDT 24
Finished Jul 30 05:22:34 PM PDT 24
Peak memory 226028 kb
Host smart-6d063873-90f2-46c7-804e-0980e0f11b43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473420526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.473420526
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2515914298
Short name T128
Test name
Test status
Simulation time 82068746591 ps
CPU time 443.95 seconds
Started Jul 30 05:21:54 PM PDT 24
Finished Jul 30 05:29:18 PM PDT 24
Peak memory 294896 kb
Host smart-e9f5fba4-1126-48d5-925e-c0f6937cdef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2515914298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2515914298
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.187430329
Short name T700
Test name
Test status
Simulation time 23333612 ps
CPU time 1.01 seconds
Started Jul 30 05:21:52 PM PDT 24
Finished Jul 30 05:21:54 PM PDT 24
Peak memory 212104 kb
Host smart-22e6eced-2e6b-44b8-9903-05f56fa34f94
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187430329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.187430329
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2724584295
Short name T61
Test name
Test status
Simulation time 14657822 ps
CPU time 0.82 seconds
Started Jul 30 05:23:29 PM PDT 24
Finished Jul 30 05:23:30 PM PDT 24
Peak memory 208840 kb
Host smart-e8a2dd12-905b-4433-b665-a27a2de93628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724584295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2724584295
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3593235539
Short name T245
Test name
Test status
Simulation time 1138029996 ps
CPU time 14.6 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:23:40 PM PDT 24
Peak memory 226156 kb
Host smart-14bdd8db-3a12-40e3-a0ff-a2b0efa4d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593235539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3593235539
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1411030096
Short name T772
Test name
Test status
Simulation time 684006942 ps
CPU time 9.34 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:23:34 PM PDT 24
Peak memory 217804 kb
Host smart-12c1fbd2-542e-492a-97b0-b0737d26fdf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411030096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1411030096
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2921460561
Short name T374
Test name
Test status
Simulation time 28628760 ps
CPU time 2.14 seconds
Started Jul 30 05:23:26 PM PDT 24
Finished Jul 30 05:23:28 PM PDT 24
Peak memory 222136 kb
Host smart-14fb777f-7a6c-4f48-9596-d4671a1fa368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921460561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2921460561
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1921018852
Short name T645
Test name
Test status
Simulation time 2584267356 ps
CPU time 15 seconds
Started Jul 30 05:23:29 PM PDT 24
Finished Jul 30 05:23:44 PM PDT 24
Peak memory 226300 kb
Host smart-69cbdc6b-5da1-4a07-be20-41d74cb7c7e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921018852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1921018852
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3096953843
Short name T516
Test name
Test status
Simulation time 353743999 ps
CPU time 13.59 seconds
Started Jul 30 05:23:26 PM PDT 24
Finished Jul 30 05:23:40 PM PDT 24
Peak memory 218388 kb
Host smart-0e330428-add4-4413-a622-5b4df78e98cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096953843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3096953843
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2874052841
Short name T322
Test name
Test status
Simulation time 1404640071 ps
CPU time 10.35 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:23:36 PM PDT 24
Peak memory 218276 kb
Host smart-f2274669-eff2-4151-8601-5e229cd22ddb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874052841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2874052841
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2850004058
Short name T3
Test name
Test status
Simulation time 8559208588 ps
CPU time 11.14 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:23:36 PM PDT 24
Peak memory 226280 kb
Host smart-a87c7181-a123-4463-bc2a-0accbddb0d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850004058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2850004058
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3634572383
Short name T66
Test name
Test status
Simulation time 129203637 ps
CPU time 2.73 seconds
Started Jul 30 05:23:26 PM PDT 24
Finished Jul 30 05:23:29 PM PDT 24
Peak memory 217836 kb
Host smart-cd3fee2d-5ffa-4911-81cf-167095f4c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634572383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3634572383
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3150998540
Short name T254
Test name
Test status
Simulation time 654333543 ps
CPU time 32.81 seconds
Started Jul 30 05:23:26 PM PDT 24
Finished Jul 30 05:23:59 PM PDT 24
Peak memory 246732 kb
Host smart-4227c0e3-178c-4d6e-9a2b-a7e45f7aa489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150998540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3150998540
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1235699341
Short name T156
Test name
Test status
Simulation time 81464941 ps
CPU time 3.7 seconds
Started Jul 30 05:23:30 PM PDT 24
Finished Jul 30 05:23:33 PM PDT 24
Peak memory 222208 kb
Host smart-791e7835-46dc-4895-80e6-44ea43fb0510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235699341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1235699341
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2860607827
Short name T754
Test name
Test status
Simulation time 1920948489 ps
CPU time 76.01 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:24:41 PM PDT 24
Peak memory 266124 kb
Host smart-98a335cc-06bb-47db-9717-7a605e2bcf4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860607827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2860607827
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2117395780
Short name T755
Test name
Test status
Simulation time 14492769 ps
CPU time 1.09 seconds
Started Jul 30 05:23:25 PM PDT 24
Finished Jul 30 05:23:26 PM PDT 24
Peak memory 212108 kb
Host smart-ba89ed8e-c564-48b9-abcb-b92fc06dd1ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117395780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2117395780
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4230118128
Short name T281
Test name
Test status
Simulation time 50121370 ps
CPU time 1.16 seconds
Started Jul 30 05:23:29 PM PDT 24
Finished Jul 30 05:23:30 PM PDT 24
Peak memory 209096 kb
Host smart-bdef45b0-f4d2-4d96-ada3-290259450908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230118128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4230118128
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.143118890
Short name T570
Test name
Test status
Simulation time 282279100 ps
CPU time 11.89 seconds
Started Jul 30 05:23:35 PM PDT 24
Finished Jul 30 05:23:47 PM PDT 24
Peak memory 218428 kb
Host smart-5d47e288-5d94-4c41-838f-0c99d5d4c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143118890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.143118890
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.4037514819
Short name T37
Test name
Test status
Simulation time 108424134 ps
CPU time 2.16 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:23:36 PM PDT 24
Peak memory 217184 kb
Host smart-825183e2-e0b3-4fb7-b24d-932cc081f2d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037514819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.4037514819
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1443140057
Short name T496
Test name
Test status
Simulation time 822458047 ps
CPU time 2.71 seconds
Started Jul 30 05:23:31 PM PDT 24
Finished Jul 30 05:23:34 PM PDT 24
Peak memory 218400 kb
Host smart-41a16105-c39c-4a8d-b535-b5e3c580efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443140057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1443140057
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2690725152
Short name T9
Test name
Test status
Simulation time 725470280 ps
CPU time 7.49 seconds
Started Jul 30 05:23:29 PM PDT 24
Finished Jul 30 05:23:37 PM PDT 24
Peak memory 218376 kb
Host smart-07ff5c66-2fac-4ccb-a3a2-4d7367c67007
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690725152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2690725152
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2317652848
Short name T319
Test name
Test status
Simulation time 234191904 ps
CPU time 7.81 seconds
Started Jul 30 05:23:37 PM PDT 24
Finished Jul 30 05:23:45 PM PDT 24
Peak memory 218348 kb
Host smart-f10b157d-53f6-4914-b93f-10e197face16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317652848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2317652848
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3414827625
Short name T366
Test name
Test status
Simulation time 1105468793 ps
CPU time 9.28 seconds
Started Jul 30 05:23:31 PM PDT 24
Finished Jul 30 05:23:40 PM PDT 24
Peak memory 218324 kb
Host smart-13296ff1-8653-4250-be38-8faad429c850
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414827625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3414827625
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.665364045
Short name T683
Test name
Test status
Simulation time 840895202 ps
CPU time 7.83 seconds
Started Jul 30 05:23:29 PM PDT 24
Finished Jul 30 05:23:37 PM PDT 24
Peak memory 225040 kb
Host smart-73964716-d7ca-497a-a04f-0502d9d586a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665364045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.665364045
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1995339841
Short name T255
Test name
Test status
Simulation time 38399641 ps
CPU time 1.15 seconds
Started Jul 30 05:23:34 PM PDT 24
Finished Jul 30 05:23:35 PM PDT 24
Peak memory 217828 kb
Host smart-24afb7ea-19fd-4e80-a1d7-e34fe8fd94c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995339841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1995339841
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2183093583
Short name T531
Test name
Test status
Simulation time 951947777 ps
CPU time 26.5 seconds
Started Jul 30 05:23:29 PM PDT 24
Finished Jul 30 05:23:56 PM PDT 24
Peak memory 251024 kb
Host smart-7a706f8b-0106-4ca7-935f-acf4bc720175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183093583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2183093583
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3500045599
Short name T741
Test name
Test status
Simulation time 286557775 ps
CPU time 4.04 seconds
Started Jul 30 05:23:29 PM PDT 24
Finished Jul 30 05:23:33 PM PDT 24
Peak memory 226404 kb
Host smart-52852a74-608f-4dc3-9c39-d3a55e0a1465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500045599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3500045599
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.357982005
Short name T829
Test name
Test status
Simulation time 4475129281 ps
CPU time 93.51 seconds
Started Jul 30 05:23:30 PM PDT 24
Finished Jul 30 05:25:04 PM PDT 24
Peak memory 282024 kb
Host smart-6f9aeb02-1bb5-4bf5-8ed6-e963403563f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357982005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.357982005
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2349349980
Short name T573
Test name
Test status
Simulation time 13198983 ps
CPU time 1.04 seconds
Started Jul 30 05:23:31 PM PDT 24
Finished Jul 30 05:23:32 PM PDT 24
Peak memory 212088 kb
Host smart-1e8d96b8-ba3f-4313-a36c-0ad4833f1eee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349349980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2349349980
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2519912400
Short name T233
Test name
Test status
Simulation time 60770964 ps
CPU time 0.94 seconds
Started Jul 30 05:23:36 PM PDT 24
Finished Jul 30 05:23:37 PM PDT 24
Peak memory 209044 kb
Host smart-b7b2f279-85b3-4b78-b2a4-b762979fd99e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519912400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2519912400
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.247296298
Short name T370
Test name
Test status
Simulation time 269850681 ps
CPU time 9.15 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:23:42 PM PDT 24
Peak memory 218328 kb
Host smart-832fbd22-4dac-4c25-8d43-1ada891c0b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247296298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.247296298
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.720137396
Short name T176
Test name
Test status
Simulation time 503211521 ps
CPU time 11.92 seconds
Started Jul 30 05:23:37 PM PDT 24
Finished Jul 30 05:23:49 PM PDT 24
Peak memory 217504 kb
Host smart-1f618e01-ecb2-499b-b3b4-f9114f043711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720137396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.720137396
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2874389909
Short name T316
Test name
Test status
Simulation time 98392646 ps
CPU time 1.57 seconds
Started Jul 30 05:23:34 PM PDT 24
Finished Jul 30 05:23:36 PM PDT 24
Peak memory 221788 kb
Host smart-b675d926-1fd8-4d5c-a712-d456a9f2e4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874389909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2874389909
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2345576511
Short name T521
Test name
Test status
Simulation time 6846097466 ps
CPU time 19.82 seconds
Started Jul 30 05:23:34 PM PDT 24
Finished Jul 30 05:23:54 PM PDT 24
Peak memory 226332 kb
Host smart-5117cd45-2856-4b12-8995-19bdfe05f2f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345576511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2345576511
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2667972331
Short name T249
Test name
Test status
Simulation time 420282601 ps
CPU time 12.79 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 218328 kb
Host smart-4d14be45-ade0-478a-8b38-25091fc39f52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667972331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2667972331
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1605735314
Short name T598
Test name
Test status
Simulation time 813862781 ps
CPU time 9.96 seconds
Started Jul 30 05:23:36 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 218368 kb
Host smart-127cbf5d-a1c9-43b7-a377-f96426a2a8db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605735314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1605735314
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1183326896
Short name T715
Test name
Test status
Simulation time 551154871 ps
CPU time 7.1 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:23:40 PM PDT 24
Peak memory 225752 kb
Host smart-74b713b8-aaa3-4d33-92b7-70dd62627617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183326896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1183326896
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1594238928
Short name T618
Test name
Test status
Simulation time 73820299 ps
CPU time 3.06 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:23:36 PM PDT 24
Peak memory 215184 kb
Host smart-4714cdc4-ea28-4291-9629-7cbb9d9695ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594238928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1594238928
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4190285848
Short name T354
Test name
Test status
Simulation time 1066581381 ps
CPU time 25.57 seconds
Started Jul 30 05:23:34 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 246132 kb
Host smart-b1a0bdd0-601c-475c-a93c-838e1950e5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190285848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4190285848
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2854687761
Short name T209
Test name
Test status
Simulation time 60950588 ps
CPU time 6.57 seconds
Started Jul 30 05:23:31 PM PDT 24
Finished Jul 30 05:23:37 PM PDT 24
Peak memory 242760 kb
Host smart-90df61cc-ca46-456d-9bfa-07d60e66a4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854687761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2854687761
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2772522057
Short name T587
Test name
Test status
Simulation time 27675727068 ps
CPU time 129.44 seconds
Started Jul 30 05:23:35 PM PDT 24
Finished Jul 30 05:25:45 PM PDT 24
Peak memory 279752 kb
Host smart-13beb2ce-0c97-456e-b91a-7eb5d5e04ee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772522057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2772522057
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1326090107
Short name T328
Test name
Test status
Simulation time 47945389 ps
CPU time 0.97 seconds
Started Jul 30 05:23:30 PM PDT 24
Finished Jul 30 05:23:31 PM PDT 24
Peak memory 211984 kb
Host smart-58085eb5-a346-4a88-a225-1d13243d66e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326090107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1326090107
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.904739538
Short name T442
Test name
Test status
Simulation time 64232006 ps
CPU time 0.89 seconds
Started Jul 30 05:23:37 PM PDT 24
Finished Jul 30 05:23:37 PM PDT 24
Peak memory 208900 kb
Host smart-28397a02-56cf-44b9-a64a-9aee2938fb76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904739538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.904739538
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1165639679
Short name T666
Test name
Test status
Simulation time 552046809 ps
CPU time 20.38 seconds
Started Jul 30 05:23:32 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 226212 kb
Host smart-2b635685-518e-4bd3-9b70-395c35454559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165639679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1165639679
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1411541717
Short name T853
Test name
Test status
Simulation time 630159277 ps
CPU time 7.58 seconds
Started Jul 30 05:23:38 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 217600 kb
Host smart-6a9ce4e9-e43c-4902-8209-3b45239440ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411541717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1411541717
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1443836280
Short name T553
Test name
Test status
Simulation time 373965312 ps
CPU time 3.93 seconds
Started Jul 30 05:23:35 PM PDT 24
Finished Jul 30 05:23:39 PM PDT 24
Peak memory 222784 kb
Host smart-a2a9c652-1920-421b-b82b-79c8c3fedd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443836280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1443836280
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4063274151
Short name T620
Test name
Test status
Simulation time 985245746 ps
CPU time 12.45 seconds
Started Jul 30 05:23:38 PM PDT 24
Finished Jul 30 05:23:51 PM PDT 24
Peak memory 218428 kb
Host smart-c2b66dec-dfed-4ab1-965d-f96749a61e61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063274151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4063274151
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2188159003
Short name T408
Test name
Test status
Simulation time 1221850540 ps
CPU time 14.27 seconds
Started Jul 30 05:23:40 PM PDT 24
Finished Jul 30 05:23:55 PM PDT 24
Peak memory 218368 kb
Host smart-28af4ab3-d517-4876-8232-633d0800b849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188159003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2188159003
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1662517392
Short name T218
Test name
Test status
Simulation time 2006930569 ps
CPU time 9.97 seconds
Started Jul 30 05:23:37 PM PDT 24
Finished Jul 30 05:23:48 PM PDT 24
Peak memory 218268 kb
Host smart-d97172cf-fb83-4a96-88ec-632e7c7beccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662517392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1662517392
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1203873043
Short name T64
Test name
Test status
Simulation time 112491552 ps
CPU time 1.58 seconds
Started Jul 30 05:23:35 PM PDT 24
Finished Jul 30 05:23:36 PM PDT 24
Peak memory 214240 kb
Host smart-739df0a4-88f3-44bf-b33f-50a5afe982b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203873043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1203873043
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.337509915
Short name T362
Test name
Test status
Simulation time 244035724 ps
CPU time 35.3 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:24:08 PM PDT 24
Peak memory 251048 kb
Host smart-ebee7bcd-43a5-4cc1-b789-bda11224d40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337509915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.337509915
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2517272485
Short name T421
Test name
Test status
Simulation time 342370760 ps
CPU time 7.7 seconds
Started Jul 30 05:23:35 PM PDT 24
Finished Jul 30 05:23:43 PM PDT 24
Peak memory 246848 kb
Host smart-e0c5bd7d-08f8-40a8-b908-e089e564ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517272485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2517272485
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2591734685
Short name T616
Test name
Test status
Simulation time 10398420340 ps
CPU time 59.49 seconds
Started Jul 30 05:23:39 PM PDT 24
Finished Jul 30 05:24:39 PM PDT 24
Peak memory 222544 kb
Host smart-820da430-8b77-43cd-a631-b0721e141e75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591734685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2591734685
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.805404826
Short name T135
Test name
Test status
Simulation time 235029592632 ps
CPU time 3356.99 seconds
Started Jul 30 05:23:39 PM PDT 24
Finished Jul 30 06:19:37 PM PDT 24
Peak memory 1595924 kb
Host smart-6011bccc-0e2a-49b2-8574-54d81788a874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=805404826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.805404826
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3004176479
Short name T520
Test name
Test status
Simulation time 15633923 ps
CPU time 0.87 seconds
Started Jul 30 05:23:33 PM PDT 24
Finished Jul 30 05:23:34 PM PDT 24
Peak memory 211964 kb
Host smart-2d80c123-822a-4907-9d17-49173c37c596
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004176479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3004176479
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1657758642
Short name T769
Test name
Test status
Simulation time 201205545 ps
CPU time 1.13 seconds
Started Jul 30 05:23:45 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 208940 kb
Host smart-e3797a81-3051-4505-8147-46bcebfd11cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657758642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1657758642
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.4136587234
Short name T569
Test name
Test status
Simulation time 1177875704 ps
CPU time 11.49 seconds
Started Jul 30 05:23:37 PM PDT 24
Finished Jul 30 05:23:49 PM PDT 24
Peak memory 218352 kb
Host smart-e0ae33d5-1b26-4b71-9844-35fc6fc416a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136587234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.4136587234
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.893832217
Short name T8
Test name
Test status
Simulation time 732783551 ps
CPU time 17.89 seconds
Started Jul 30 05:23:42 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 217512 kb
Host smart-5266ec45-ebb2-45dc-9d16-6fd6319d1717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893832217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.893832217
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3817918532
Short name T632
Test name
Test status
Simulation time 64211042 ps
CPU time 2.23 seconds
Started Jul 30 05:23:40 PM PDT 24
Finished Jul 30 05:23:42 PM PDT 24
Peak memory 218488 kb
Host smart-9efe735c-472d-4d88-b1b8-75d6972d04eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817918532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3817918532
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1623924557
Short name T709
Test name
Test status
Simulation time 861459835 ps
CPU time 7.92 seconds
Started Jul 30 05:23:40 PM PDT 24
Finished Jul 30 05:23:48 PM PDT 24
Peak memory 226112 kb
Host smart-3a896a69-1e50-4037-b0ee-f806bd8010b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623924557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1623924557
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3939153816
Short name T441
Test name
Test status
Simulation time 708875495 ps
CPU time 10.14 seconds
Started Jul 30 05:23:43 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 218344 kb
Host smart-352d3b16-4327-478d-b599-0cff58d6a439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939153816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3939153816
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1561113882
Short name T401
Test name
Test status
Simulation time 656937304 ps
CPU time 7.14 seconds
Started Jul 30 05:23:39 PM PDT 24
Finished Jul 30 05:23:46 PM PDT 24
Peak memory 224936 kb
Host smart-c642ee8a-3de7-46eb-8e2c-1d337d2eba8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561113882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1561113882
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.4206920283
Short name T46
Test name
Test status
Simulation time 923978733 ps
CPU time 8.84 seconds
Started Jul 30 05:23:39 PM PDT 24
Finished Jul 30 05:23:48 PM PDT 24
Peak memory 226264 kb
Host smart-a3fca492-9855-4ae9-a2bb-f5e38120e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206920283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.4206920283
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.39415081
Short name T717
Test name
Test status
Simulation time 650990970 ps
CPU time 9.26 seconds
Started Jul 30 05:23:39 PM PDT 24
Finished Jul 30 05:23:48 PM PDT 24
Peak memory 217840 kb
Host smart-47c33cd4-4a72-49bf-bef3-013e1dce66c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39415081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.39415081
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1624272738
Short name T736
Test name
Test status
Simulation time 765128728 ps
CPU time 32.25 seconds
Started Jul 30 05:23:37 PM PDT 24
Finished Jul 30 05:24:10 PM PDT 24
Peak memory 251048 kb
Host smart-33fa8049-1e54-452d-a174-91f84645536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624272738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1624272738
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.66698601
Short name T264
Test name
Test status
Simulation time 61584010 ps
CPU time 7.2 seconds
Started Jul 30 05:23:42 PM PDT 24
Finished Jul 30 05:23:49 PM PDT 24
Peak memory 250876 kb
Host smart-1cae32e6-0895-4f8c-b663-762aa0338002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66698601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.66698601
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.322118004
Short name T850
Test name
Test status
Simulation time 35058507994 ps
CPU time 122.09 seconds
Started Jul 30 05:23:43 PM PDT 24
Finished Jul 30 05:25:45 PM PDT 24
Peak memory 226324 kb
Host smart-5384b4e6-733d-4bda-b5a1-a3a74331e2ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322118004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.322118004
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2982346723
Short name T777
Test name
Test status
Simulation time 29178309 ps
CPU time 0.81 seconds
Started Jul 30 05:23:42 PM PDT 24
Finished Jul 30 05:23:42 PM PDT 24
Peak memory 212040 kb
Host smart-50141e56-34f7-4228-b60e-e774fd64a6e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982346723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2982346723
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3084574343
Short name T820
Test name
Test status
Simulation time 20236198 ps
CPU time 0.99 seconds
Started Jul 30 05:23:50 PM PDT 24
Finished Jul 30 05:23:51 PM PDT 24
Peak memory 208964 kb
Host smart-682c12ab-7620-4d5d-a60e-fc213f7ca4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084574343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3084574343
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3063443858
Short name T544
Test name
Test status
Simulation time 520108647 ps
CPU time 15.72 seconds
Started Jul 30 05:23:42 PM PDT 24
Finished Jul 30 05:23:58 PM PDT 24
Peak memory 226260 kb
Host smart-69b52fc1-246e-432e-96d6-5d6ba44f527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063443858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3063443858
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1203346403
Short name T669
Test name
Test status
Simulation time 353557634 ps
CPU time 2.69 seconds
Started Jul 30 05:23:41 PM PDT 24
Finished Jul 30 05:23:44 PM PDT 24
Peak memory 217212 kb
Host smart-477d3b94-d40d-491c-8cda-8fd01c929946
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203346403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1203346403
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2826195676
Short name T143
Test name
Test status
Simulation time 392636878 ps
CPU time 3.88 seconds
Started Jul 30 05:23:45 PM PDT 24
Finished Jul 30 05:23:49 PM PDT 24
Peak memory 222564 kb
Host smart-a30b11fe-8050-4f6e-835d-4351ca005efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826195676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2826195676
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2868839754
Short name T678
Test name
Test status
Simulation time 304157263 ps
CPU time 11.92 seconds
Started Jul 30 05:23:44 PM PDT 24
Finished Jul 30 05:23:56 PM PDT 24
Peak memory 218396 kb
Host smart-95eb52a1-2adc-4b2e-a143-9ffafcbeace0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868839754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2868839754
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1871919956
Short name T428
Test name
Test status
Simulation time 868545047 ps
CPU time 9.35 seconds
Started Jul 30 05:23:44 PM PDT 24
Finished Jul 30 05:23:54 PM PDT 24
Peak memory 218340 kb
Host smart-a1863cfb-76b4-4d22-91de-641e28966eea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871919956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1871919956
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2391577422
Short name T138
Test name
Test status
Simulation time 2493895912 ps
CPU time 14.19 seconds
Started Jul 30 05:23:44 PM PDT 24
Finished Jul 30 05:23:58 PM PDT 24
Peak memory 218352 kb
Host smart-c89e39ea-cc76-43b0-98be-be93eb7bee04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391577422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2391577422
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.361475824
Short name T738
Test name
Test status
Simulation time 2490751163 ps
CPU time 8.93 seconds
Started Jul 30 05:23:44 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 218564 kb
Host smart-d9d93e69-5575-4e02-a41a-a1b222a8561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361475824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.361475824
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3196215072
Short name T818
Test name
Test status
Simulation time 72974380 ps
CPU time 1.57 seconds
Started Jul 30 05:23:45 PM PDT 24
Finished Jul 30 05:23:47 PM PDT 24
Peak memory 213928 kb
Host smart-b5258cd2-c033-4013-9987-8d679a8e2dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196215072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3196215072
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3835038868
Short name T761
Test name
Test status
Simulation time 290068970 ps
CPU time 26.7 seconds
Started Jul 30 05:23:43 PM PDT 24
Finished Jul 30 05:24:10 PM PDT 24
Peak memory 251040 kb
Host smart-e20c06a3-7a5e-46f6-b27f-3439be42e18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835038868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3835038868
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3369746825
Short name T226
Test name
Test status
Simulation time 2598781960 ps
CPU time 8.5 seconds
Started Jul 30 05:23:46 PM PDT 24
Finished Jul 30 05:23:55 PM PDT 24
Peak memory 251040 kb
Host smart-fbf4b35b-0e0b-4310-9ac4-7d271dfa6751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369746825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3369746825
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2381084132
Short name T26
Test name
Test status
Simulation time 5211817414 ps
CPU time 149.84 seconds
Started Jul 30 05:23:43 PM PDT 24
Finished Jul 30 05:26:13 PM PDT 24
Peak memory 251928 kb
Host smart-de5ce251-687f-47ec-8397-ff3d13383a4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381084132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2381084132
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2459104903
Short name T133
Test name
Test status
Simulation time 13900091344 ps
CPU time 274.34 seconds
Started Jul 30 05:23:43 PM PDT 24
Finished Jul 30 05:28:17 PM PDT 24
Peak memory 277176 kb
Host smart-30a8fe5c-c574-427e-9006-30eaa67b5c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2459104903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2459104903
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2864957260
Short name T546
Test name
Test status
Simulation time 45732313 ps
CPU time 1 seconds
Started Jul 30 05:23:43 PM PDT 24
Finished Jul 30 05:23:44 PM PDT 24
Peak memory 217868 kb
Host smart-3ddaad48-4d8d-4bbc-840f-5fbb10c7acdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864957260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2864957260
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4145463689
Short name T790
Test name
Test status
Simulation time 56552326 ps
CPU time 1.04 seconds
Started Jul 30 05:23:49 PM PDT 24
Finished Jul 30 05:23:51 PM PDT 24
Peak memory 209052 kb
Host smart-70fef28c-2540-49b2-a6f4-94663fa048d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145463689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4145463689
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.503068092
Short name T672
Test name
Test status
Simulation time 314658579 ps
CPU time 12.53 seconds
Started Jul 30 05:23:47 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 218424 kb
Host smart-50610851-3f11-42df-a6a1-24b3dfe017d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503068092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.503068092
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1436550736
Short name T691
Test name
Test status
Simulation time 435573557 ps
CPU time 11.79 seconds
Started Jul 30 05:23:48 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 217908 kb
Host smart-c31c8154-521d-448a-be38-3146e0125c35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436550736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1436550736
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3936203113
Short name T688
Test name
Test status
Simulation time 22273521 ps
CPU time 1.83 seconds
Started Jul 30 05:23:50 PM PDT 24
Finished Jul 30 05:23:52 PM PDT 24
Peak memory 218392 kb
Host smart-9957b4c8-369d-4e1c-a30e-df565d9b23ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936203113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3936203113
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1018844021
Short name T460
Test name
Test status
Simulation time 770257583 ps
CPU time 15.9 seconds
Started Jul 30 05:23:49 PM PDT 24
Finished Jul 30 05:24:05 PM PDT 24
Peak memory 226268 kb
Host smart-4554a233-4ff1-4e73-b55d-d3887dda7e39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018844021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1018844021
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.986666410
Short name T517
Test name
Test status
Simulation time 1210134697 ps
CPU time 8.78 seconds
Started Jul 30 05:23:51 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 218320 kb
Host smart-e4d3fd60-d08e-4d08-98cb-b18190e3bd1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986666410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.986666410
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.241252035
Short name T659
Test name
Test status
Simulation time 576615092 ps
CPU time 10.89 seconds
Started Jul 30 05:23:51 PM PDT 24
Finished Jul 30 05:24:02 PM PDT 24
Peak memory 226156 kb
Host smart-d40d3097-1199-448d-b98d-d07fb1371c86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241252035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.241252035
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4160011254
Short name T619
Test name
Test status
Simulation time 1456576425 ps
CPU time 8.61 seconds
Started Jul 30 05:23:51 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 218588 kb
Host smart-1ea0c51a-31f2-4387-a75f-46633e837df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160011254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4160011254
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1257792633
Short name T12
Test name
Test status
Simulation time 14607656 ps
CPU time 1.13 seconds
Started Jul 30 05:23:52 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 217796 kb
Host smart-441485f3-e995-41c3-a11d-98252f231775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257792633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1257792633
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2222754484
Short name T718
Test name
Test status
Simulation time 1145934429 ps
CPU time 30.36 seconds
Started Jul 30 05:23:50 PM PDT 24
Finished Jul 30 05:24:20 PM PDT 24
Peak memory 250932 kb
Host smart-bd9ad704-cd92-499d-8b62-1fe5b9c7cc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222754484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2222754484
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.102427078
Short name T524
Test name
Test status
Simulation time 199409202 ps
CPU time 3.5 seconds
Started Jul 30 05:23:46 PM PDT 24
Finished Jul 30 05:23:50 PM PDT 24
Peak memory 222808 kb
Host smart-b43faeb2-6070-4001-9253-a6f7c1233f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102427078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.102427078
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2482437559
Short name T703
Test name
Test status
Simulation time 6956398526 ps
CPU time 94.61 seconds
Started Jul 30 05:23:49 PM PDT 24
Finished Jul 30 05:25:24 PM PDT 24
Peak memory 276260 kb
Host smart-7099eb22-9f25-4e10-a73e-4cf51956471d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482437559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2482437559
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.464679278
Short name T751
Test name
Test status
Simulation time 37632078252 ps
CPU time 214.72 seconds
Started Jul 30 05:23:49 PM PDT 24
Finished Jul 30 05:27:24 PM PDT 24
Peak memory 267608 kb
Host smart-a2184b0a-5b35-4fe7-a3af-7bfdbde39315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=464679278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.464679278
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2820903000
Short name T863
Test name
Test status
Simulation time 12867359 ps
CPU time 1.04 seconds
Started Jul 30 05:23:49 PM PDT 24
Finished Jul 30 05:23:50 PM PDT 24
Peak memory 212128 kb
Host smart-1c9f255b-3ce4-49bb-add4-b1539f675489
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820903000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2820903000
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.478998407
Short name T457
Test name
Test status
Simulation time 63728023 ps
CPU time 1.07 seconds
Started Jul 30 05:23:52 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 209072 kb
Host smart-a665c699-105b-4eb6-b10c-1a0e201618b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478998407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.478998407
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1481524896
Short name T228
Test name
Test status
Simulation time 335731686 ps
CPU time 11.01 seconds
Started Jul 30 05:23:52 PM PDT 24
Finished Jul 30 05:24:03 PM PDT 24
Peak memory 226252 kb
Host smart-240055db-7c54-416c-bce3-3f7dd4bde48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481524896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1481524896
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1042225397
Short name T377
Test name
Test status
Simulation time 733144090 ps
CPU time 8.15 seconds
Started Jul 30 05:23:53 PM PDT 24
Finished Jul 30 05:24:01 PM PDT 24
Peak memory 217352 kb
Host smart-9b242da5-e950-4f31-b3aa-0f38b2f6b55c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042225397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1042225397
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1507949935
Short name T822
Test name
Test status
Simulation time 92288409 ps
CPU time 2.62 seconds
Started Jul 30 05:23:54 PM PDT 24
Finished Jul 30 05:23:57 PM PDT 24
Peak memory 218400 kb
Host smart-7707a9c1-51e2-4c50-a66e-e2c564e8f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507949935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1507949935
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2281311579
Short name T614
Test name
Test status
Simulation time 253874751 ps
CPU time 8.97 seconds
Started Jul 30 05:23:54 PM PDT 24
Finished Jul 30 05:24:03 PM PDT 24
Peak memory 226212 kb
Host smart-5b6a67a0-58b9-49de-a832-f784e41fd6e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281311579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2281311579
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2675444425
Short name T404
Test name
Test status
Simulation time 1878514709 ps
CPU time 12.78 seconds
Started Jul 30 05:23:56 PM PDT 24
Finished Jul 30 05:24:09 PM PDT 24
Peak memory 218336 kb
Host smart-bed524e9-985e-4031-9923-a47721c386b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675444425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2675444425
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3480611619
Short name T56
Test name
Test status
Simulation time 1674589690 ps
CPU time 9.18 seconds
Started Jul 30 05:23:53 PM PDT 24
Finished Jul 30 05:24:02 PM PDT 24
Peak memory 218340 kb
Host smart-8833d245-ce67-41b1-81c9-099d01a2aff4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480611619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3480611619
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3041185989
Short name T838
Test name
Test status
Simulation time 1111980293 ps
CPU time 11.67 seconds
Started Jul 30 05:23:51 PM PDT 24
Finished Jul 30 05:24:02 PM PDT 24
Peak memory 225300 kb
Host smart-beaeb714-272d-4e02-88c0-695aed3e0607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041185989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3041185989
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1484379303
Short name T564
Test name
Test status
Simulation time 275239146 ps
CPU time 3.04 seconds
Started Jul 30 05:23:50 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 222720 kb
Host smart-0edc27f9-06f3-4a61-bae4-d58d826af07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484379303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1484379303
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3791764637
Short name T489
Test name
Test status
Simulation time 190811207 ps
CPU time 29.84 seconds
Started Jul 30 05:23:50 PM PDT 24
Finished Jul 30 05:24:20 PM PDT 24
Peak memory 250928 kb
Host smart-72df9418-af3d-4001-8a8f-df78facaadb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791764637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3791764637
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.314577826
Short name T400
Test name
Test status
Simulation time 254066884 ps
CPU time 6.32 seconds
Started Jul 30 05:23:49 PM PDT 24
Finished Jul 30 05:23:56 PM PDT 24
Peak memory 243596 kb
Host smart-6d9e0135-e7f6-4583-969a-4556e23592a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314577826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.314577826
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1486537269
Short name T173
Test name
Test status
Simulation time 3868168269 ps
CPU time 131.6 seconds
Started Jul 30 05:23:53 PM PDT 24
Finished Jul 30 05:26:05 PM PDT 24
Peak memory 229868 kb
Host smart-cdd90b5d-4f6c-48e1-901a-381bb2c162af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486537269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1486537269
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2130628040
Short name T681
Test name
Test status
Simulation time 11850249 ps
CPU time 0.99 seconds
Started Jul 30 05:23:51 PM PDT 24
Finished Jul 30 05:23:52 PM PDT 24
Peak memory 212132 kb
Host smart-c3c50ea9-4996-4504-a6c8-08b426a8e5ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130628040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2130628040
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1255313511
Short name T303
Test name
Test status
Simulation time 68822661 ps
CPU time 1.14 seconds
Started Jul 30 05:23:59 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 209116 kb
Host smart-dacf7d45-a832-44ae-9f31-2da8662c7e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255313511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1255313511
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1611777857
Short name T424
Test name
Test status
Simulation time 1339968288 ps
CPU time 12.22 seconds
Started Jul 30 05:23:55 PM PDT 24
Finished Jul 30 05:24:08 PM PDT 24
Peak memory 226252 kb
Host smart-0cd02a7d-7f98-4b46-bd0c-dc0f0f2f075f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611777857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1611777857
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1473564459
Short name T57
Test name
Test status
Simulation time 106612053 ps
CPU time 1.18 seconds
Started Jul 30 05:23:59 PM PDT 24
Finished Jul 30 05:24:00 PM PDT 24
Peak memory 217320 kb
Host smart-bee1e03e-cc75-4381-ba2f-db3fbba124ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473564459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1473564459
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3362904215
Short name T321
Test name
Test status
Simulation time 47841420 ps
CPU time 2.04 seconds
Started Jul 30 05:23:52 PM PDT 24
Finished Jul 30 05:23:54 PM PDT 24
Peak memory 222248 kb
Host smart-c30a9a03-4fdf-41d4-b699-174d6d03ac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362904215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3362904215
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2171414843
Short name T380
Test name
Test status
Simulation time 976856289 ps
CPU time 18.8 seconds
Started Jul 30 05:23:58 PM PDT 24
Finished Jul 30 05:24:17 PM PDT 24
Peak memory 218452 kb
Host smart-0b156806-ed03-47b8-bb2b-b70187d1d13b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171414843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2171414843
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3663295169
Short name T300
Test name
Test status
Simulation time 823778625 ps
CPU time 7.86 seconds
Started Jul 30 05:23:57 PM PDT 24
Finished Jul 30 05:24:05 PM PDT 24
Peak memory 218336 kb
Host smart-15ec8d45-a75b-4ff8-8398-b12601b6a9f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663295169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3663295169
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1373276280
Short name T798
Test name
Test status
Simulation time 2252334574 ps
CPU time 17.09 seconds
Started Jul 30 05:23:56 PM PDT 24
Finished Jul 30 05:24:14 PM PDT 24
Peak memory 218340 kb
Host smart-435f524a-16f7-4003-9e80-7350d83bddc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373276280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1373276280
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.4290597427
Short name T476
Test name
Test status
Simulation time 211329325 ps
CPU time 8.63 seconds
Started Jul 30 05:23:53 PM PDT 24
Finished Jul 30 05:24:01 PM PDT 24
Peak memory 218472 kb
Host smart-cd6558c6-115f-43f0-bf0f-3d39c7382c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290597427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4290597427
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3360952314
Short name T403
Test name
Test status
Simulation time 138308210 ps
CPU time 3.2 seconds
Started Jul 30 05:23:53 PM PDT 24
Finished Jul 30 05:23:56 PM PDT 24
Peak memory 215088 kb
Host smart-a15e8ebb-dadb-4930-99d3-c770a10c14e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360952314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3360952314
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1769842894
Short name T387
Test name
Test status
Simulation time 243612816 ps
CPU time 27.66 seconds
Started Jul 30 05:23:53 PM PDT 24
Finished Jul 30 05:24:21 PM PDT 24
Peak memory 246004 kb
Host smart-f6c39d22-5897-460a-bbe1-310f7226a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769842894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1769842894
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2157665194
Short name T334
Test name
Test status
Simulation time 305356740 ps
CPU time 4.25 seconds
Started Jul 30 05:23:52 PM PDT 24
Finished Jul 30 05:23:57 PM PDT 24
Peak memory 223120 kb
Host smart-757dfd73-b14c-4e52-9ec6-5b5f7d22e5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157665194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2157665194
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2793015248
Short name T86
Test name
Test status
Simulation time 4478961889 ps
CPU time 164.63 seconds
Started Jul 30 05:23:58 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 251224 kb
Host smart-7cd3e627-9c59-4b06-9167-c752860c53b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793015248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2793015248
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2787827703
Short name T345
Test name
Test status
Simulation time 57072752 ps
CPU time 0.98 seconds
Started Jul 30 05:23:52 PM PDT 24
Finished Jul 30 05:23:53 PM PDT 24
Peak memory 211952 kb
Host smart-0169c1af-2045-493e-9b27-e686c715551b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787827703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2787827703
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3430703806
Short name T150
Test name
Test status
Simulation time 57758376 ps
CPU time 0.96 seconds
Started Jul 30 05:24:04 PM PDT 24
Finished Jul 30 05:24:05 PM PDT 24
Peak memory 209060 kb
Host smart-1ecb2c29-37f2-41eb-8577-c744e1f85834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430703806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3430703806
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1036881287
Short name T650
Test name
Test status
Simulation time 837531654 ps
CPU time 8.06 seconds
Started Jul 30 05:23:57 PM PDT 24
Finished Jul 30 05:24:05 PM PDT 24
Peak memory 218308 kb
Host smart-9cd8f8d9-77b0-4deb-8a81-1a6ceda36977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036881287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1036881287
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.289090517
Short name T4
Test name
Test status
Simulation time 331200866 ps
CPU time 4.6 seconds
Started Jul 30 05:23:58 PM PDT 24
Finished Jul 30 05:24:03 PM PDT 24
Peak memory 217332 kb
Host smart-3108cb25-74d1-4b74-9387-d8e260e4f142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289090517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.289090517
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3818394565
Short name T158
Test name
Test status
Simulation time 100000211 ps
CPU time 2.89 seconds
Started Jul 30 05:23:56 PM PDT 24
Finished Jul 30 05:23:59 PM PDT 24
Peak memory 222396 kb
Host smart-0d3e557f-eea1-45dd-bd7a-248de3180a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818394565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3818394565
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1141308093
Short name T473
Test name
Test status
Simulation time 270554124 ps
CPU time 14.81 seconds
Started Jul 30 05:24:01 PM PDT 24
Finished Jul 30 05:24:16 PM PDT 24
Peak memory 219136 kb
Host smart-00788e56-3d07-4fc1-a3f3-2e7b4b29ab4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141308093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1141308093
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3279843840
Short name T301
Test name
Test status
Simulation time 1077598132 ps
CPU time 20.54 seconds
Started Jul 30 05:24:05 PM PDT 24
Finished Jul 30 05:24:26 PM PDT 24
Peak memory 226144 kb
Host smart-de2abccb-73cb-4528-8e55-3e0c871cf51a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279843840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3279843840
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.344857474
Short name T386
Test name
Test status
Simulation time 1660572733 ps
CPU time 9.55 seconds
Started Jul 30 05:24:06 PM PDT 24
Finished Jul 30 05:24:16 PM PDT 24
Peak memory 226144 kb
Host smart-7a55bb20-2bfb-45e6-9268-622405dffbdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344857474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.344857474
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2699256375
Short name T752
Test name
Test status
Simulation time 248019526 ps
CPU time 11.65 seconds
Started Jul 30 05:23:55 PM PDT 24
Finished Jul 30 05:24:07 PM PDT 24
Peak memory 225948 kb
Host smart-9c05b4e2-fd47-4c72-9a79-062ed8e209e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699256375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2699256375
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1391866012
Short name T474
Test name
Test status
Simulation time 269202653 ps
CPU time 2.62 seconds
Started Jul 30 05:23:57 PM PDT 24
Finished Jul 30 05:23:59 PM PDT 24
Peak memory 214596 kb
Host smart-613e8c66-3b2a-4f8a-8290-fe095520f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391866012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1391866012
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1212207979
Short name T827
Test name
Test status
Simulation time 1501578844 ps
CPU time 31.2 seconds
Started Jul 30 05:23:58 PM PDT 24
Finished Jul 30 05:24:29 PM PDT 24
Peak memory 250988 kb
Host smart-7ab70567-3ced-47a2-a654-6127a764f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212207979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1212207979
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1466108475
Short name T712
Test name
Test status
Simulation time 148456737 ps
CPU time 9.16 seconds
Started Jul 30 05:23:58 PM PDT 24
Finished Jul 30 05:24:07 PM PDT 24
Peak memory 251172 kb
Host smart-79973c05-b4dc-4136-97be-efab4bb221f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466108475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1466108475
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3575384559
Short name T271
Test name
Test status
Simulation time 6496134009 ps
CPU time 246.83 seconds
Started Jul 30 05:24:04 PM PDT 24
Finished Jul 30 05:28:11 PM PDT 24
Peak memory 272552 kb
Host smart-608097eb-4a26-4e9e-a9b5-c753dae38c06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575384559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3575384559
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3873491913
Short name T535
Test name
Test status
Simulation time 15608599 ps
CPU time 0.92 seconds
Started Jul 30 05:23:56 PM PDT 24
Finished Jul 30 05:23:57 PM PDT 24
Peak memory 212144 kb
Host smart-cc17c00a-664e-48fa-800f-5b2c842bf11c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873491913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3873491913
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2582329212
Short name T241
Test name
Test status
Simulation time 17666798 ps
CPU time 0.92 seconds
Started Jul 30 05:22:01 PM PDT 24
Finished Jul 30 05:22:02 PM PDT 24
Peak memory 208932 kb
Host smart-5ca10a42-2387-4667-b9f8-9d965cfea60f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582329212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2582329212
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3711821634
Short name T628
Test name
Test status
Simulation time 779546818 ps
CPU time 7.95 seconds
Started Jul 30 05:21:52 PM PDT 24
Finished Jul 30 05:22:00 PM PDT 24
Peak memory 218368 kb
Host smart-9505a4c0-5c3c-4400-94e8-47650800c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711821634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3711821634
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1496617432
Short name T35
Test name
Test status
Simulation time 851347475 ps
CPU time 6.04 seconds
Started Jul 30 05:21:57 PM PDT 24
Finished Jul 30 05:22:03 PM PDT 24
Peak memory 217356 kb
Host smart-da52b8e0-f505-463c-818f-15db954b7aaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496617432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1496617432
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.454442670
Short name T581
Test name
Test status
Simulation time 1259887999 ps
CPU time 39.17 seconds
Started Jul 30 05:21:58 PM PDT 24
Finished Jul 30 05:22:37 PM PDT 24
Peak memory 218400 kb
Host smart-8f8f0930-c77a-48ad-b71b-651b5dc048db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454442670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.454442670
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2825034474
Short name T649
Test name
Test status
Simulation time 194542553 ps
CPU time 5.87 seconds
Started Jul 30 05:21:58 PM PDT 24
Finished Jul 30 05:22:04 PM PDT 24
Peak memory 217592 kb
Host smart-b0636ea7-1210-4e97-8ecf-e7509d87b3d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825034474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
825034474
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4261409030
Short name T597
Test name
Test status
Simulation time 5169256894 ps
CPU time 26.08 seconds
Started Jul 30 05:21:58 PM PDT 24
Finished Jul 30 05:22:24 PM PDT 24
Peak memory 219076 kb
Host smart-73f78922-9d3d-43e0-8fd8-378f8c807859
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261409030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4261409030
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.23464333
Short name T788
Test name
Test status
Simulation time 7584221405 ps
CPU time 37.41 seconds
Started Jul 30 05:21:57 PM PDT 24
Finished Jul 30 05:22:34 PM PDT 24
Peak memory 217852 kb
Host smart-bc62c1af-0a12-476a-b3d3-19ac399bb47e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23464333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_regwen_during_op.23464333
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.675031219
Short name T432
Test name
Test status
Simulation time 166157186 ps
CPU time 1.88 seconds
Started Jul 30 05:21:56 PM PDT 24
Finished Jul 30 05:21:58 PM PDT 24
Peak memory 217868 kb
Host smart-87a88dc6-36ca-4507-b5f3-516b7b31824b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675031219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.675031219
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2751564317
Short name T244
Test name
Test status
Simulation time 7958757578 ps
CPU time 67.22 seconds
Started Jul 30 05:21:59 PM PDT 24
Finished Jul 30 05:23:06 PM PDT 24
Peak memory 268560 kb
Host smart-a6de9321-42ee-482e-ad2f-a36d82dedb81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751564317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2751564317
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4250724753
Short name T480
Test name
Test status
Simulation time 2571568719 ps
CPU time 12.1 seconds
Started Jul 30 05:21:57 PM PDT 24
Finished Jul 30 05:22:09 PM PDT 24
Peak memory 222220 kb
Host smart-29916d16-c688-458a-8c42-6d43548fb55b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250724753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4250724753
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3843421389
Short name T204
Test name
Test status
Simulation time 353266978 ps
CPU time 3.33 seconds
Started Jul 30 05:21:54 PM PDT 24
Finished Jul 30 05:21:57 PM PDT 24
Peak memory 218484 kb
Host smart-c2394da9-c2f7-48f1-8fec-69dfa7bf400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843421389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3843421389
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.791828389
Short name T742
Test name
Test status
Simulation time 2204854835 ps
CPU time 7.62 seconds
Started Jul 30 05:21:51 PM PDT 24
Finished Jul 30 05:21:59 PM PDT 24
Peak memory 217984 kb
Host smart-53d7a8ca-0807-487a-9d66-4b5914fd9635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791828389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.791828389
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.254177769
Short name T69
Test name
Test status
Simulation time 462876246 ps
CPU time 25.78 seconds
Started Jul 30 05:22:02 PM PDT 24
Finished Jul 30 05:22:28 PM PDT 24
Peak memory 284364 kb
Host smart-7d58974a-3dc8-4979-876e-622ae1ecbadd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254177769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.254177769
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.722894231
Short name T149
Test name
Test status
Simulation time 2260866077 ps
CPU time 17.04 seconds
Started Jul 30 05:22:02 PM PDT 24
Finished Jul 30 05:22:19 PM PDT 24
Peak memory 219132 kb
Host smart-6e1f00fc-b532-4f56-b2ae-c3cbfba64589
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722894231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.722894231
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3366376903
Short name T313
Test name
Test status
Simulation time 1890897815 ps
CPU time 12.58 seconds
Started Jul 30 05:22:04 PM PDT 24
Finished Jul 30 05:22:16 PM PDT 24
Peak memory 218308 kb
Host smart-7ba7a5d6-ecd5-45ab-9755-2735c5181e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366376903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3366376903
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3977337500
Short name T611
Test name
Test status
Simulation time 579214771 ps
CPU time 6.83 seconds
Started Jul 30 05:22:03 PM PDT 24
Finished Jul 30 05:22:10 PM PDT 24
Peak memory 224868 kb
Host smart-63aab8a7-5004-4078-8247-7dcdead424ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977337500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
977337500
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.644513334
Short name T794
Test name
Test status
Simulation time 366159573 ps
CPU time 9.26 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:22:03 PM PDT 24
Peak memory 226152 kb
Host smart-8dfee7ba-66e4-4ef5-b26c-fea1879b8679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644513334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.644513334
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2252612174
Short name T811
Test name
Test status
Simulation time 39662003 ps
CPU time 1.99 seconds
Started Jul 30 05:21:50 PM PDT 24
Finished Jul 30 05:21:52 PM PDT 24
Peak memory 214032 kb
Host smart-05ca5eb7-1710-46af-8e48-0573c724915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252612174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2252612174
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3684094192
Short name T793
Test name
Test status
Simulation time 329394124 ps
CPU time 21.52 seconds
Started Jul 30 05:21:53 PM PDT 24
Finished Jul 30 05:22:15 PM PDT 24
Peak memory 251088 kb
Host smart-cd4ef486-6ac3-45d3-8c0e-596b5786809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684094192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3684094192
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2271169882
Short name T393
Test name
Test status
Simulation time 260772667 ps
CPU time 7.97 seconds
Started Jul 30 05:21:52 PM PDT 24
Finished Jul 30 05:22:00 PM PDT 24
Peak memory 251076 kb
Host smart-ede3deb7-17c8-4f9c-8fd4-92823893a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271169882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2271169882
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3560242645
Short name T622
Test name
Test status
Simulation time 7969212890 ps
CPU time 69.74 seconds
Started Jul 30 05:22:01 PM PDT 24
Finished Jul 30 05:23:11 PM PDT 24
Peak memory 273608 kb
Host smart-f5efbefa-6d70-409a-933c-cecaf267d0ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560242645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3560242645
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1059176637
Short name T357
Test name
Test status
Simulation time 19287448 ps
CPU time 1.14 seconds
Started Jul 30 05:21:52 PM PDT 24
Finished Jul 30 05:21:53 PM PDT 24
Peak memory 213204 kb
Host smart-e66de2a5-acd4-479c-9109-3df3cd455f93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059176637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1059176637
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2896434814
Short name T567
Test name
Test status
Simulation time 17570243 ps
CPU time 1.13 seconds
Started Jul 30 05:24:06 PM PDT 24
Finished Jul 30 05:24:07 PM PDT 24
Peak memory 209132 kb
Host smart-d4b727d1-5b00-4889-aa8c-21fff67c0ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896434814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2896434814
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1951996886
Short name T42
Test name
Test status
Simulation time 448372050 ps
CPU time 13.82 seconds
Started Jul 30 05:24:01 PM PDT 24
Finished Jul 30 05:24:15 PM PDT 24
Peak memory 218368 kb
Host smart-1137fa2a-ffdb-4f82-a388-36b6b4e0e9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951996886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1951996886
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3308373072
Short name T34
Test name
Test status
Simulation time 354016527 ps
CPU time 4.57 seconds
Started Jul 30 05:24:01 PM PDT 24
Finished Jul 30 05:24:05 PM PDT 24
Peak memory 217192 kb
Host smart-ed9f0c6f-b8b6-4502-abb3-fb82790ebefb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308373072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3308373072
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1569029189
Short name T667
Test name
Test status
Simulation time 185989531 ps
CPU time 2.95 seconds
Started Jul 30 05:24:03 PM PDT 24
Finished Jul 30 05:24:06 PM PDT 24
Peak memory 218380 kb
Host smart-a769cdea-2476-4440-b2c9-92ca8c31e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569029189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1569029189
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1650774961
Short name T713
Test name
Test status
Simulation time 2493807469 ps
CPU time 14.15 seconds
Started Jul 30 05:24:07 PM PDT 24
Finished Jul 30 05:24:21 PM PDT 24
Peak memory 219416 kb
Host smart-b1df0d04-c831-496f-af36-08d6173ee35a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650774961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1650774961
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2761848980
Short name T229
Test name
Test status
Simulation time 1565027774 ps
CPU time 9.46 seconds
Started Jul 30 05:24:01 PM PDT 24
Finished Jul 30 05:24:11 PM PDT 24
Peak memory 218372 kb
Host smart-f62fd862-e37a-435c-84b8-18b5ffa6eba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761848980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2761848980
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2449791952
Short name T720
Test name
Test status
Simulation time 268458333 ps
CPU time 8.43 seconds
Started Jul 30 05:24:00 PM PDT 24
Finished Jul 30 05:24:09 PM PDT 24
Peak memory 226128 kb
Host smart-8972bd43-3d96-410e-8758-6883218444db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449791952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2449791952
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1274816027
Short name T343
Test name
Test status
Simulation time 466617137 ps
CPU time 12.22 seconds
Started Jul 30 05:24:01 PM PDT 24
Finished Jul 30 05:24:14 PM PDT 24
Peak memory 225568 kb
Host smart-3ff02336-9bb9-4ca9-97ab-5282ed5f23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274816027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1274816027
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2212117653
Short name T466
Test name
Test status
Simulation time 248799350 ps
CPU time 3.02 seconds
Started Jul 30 05:24:02 PM PDT 24
Finished Jul 30 05:24:05 PM PDT 24
Peak memory 214932 kb
Host smart-31100ee5-6435-443b-94c3-163e5ea5410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212117653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2212117653
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3126902269
Short name T208
Test name
Test status
Simulation time 771745124 ps
CPU time 18.69 seconds
Started Jul 30 05:24:00 PM PDT 24
Finished Jul 30 05:24:18 PM PDT 24
Peak memory 250980 kb
Host smart-588df642-1468-4dec-a221-cde5722fe5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126902269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3126902269
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2562044125
Short name T161
Test name
Test status
Simulation time 681786197 ps
CPU time 7.14 seconds
Started Jul 30 05:24:01 PM PDT 24
Finished Jul 30 05:24:09 PM PDT 24
Peak memory 251048 kb
Host smart-f6369798-1ced-47d9-8f78-21395b05939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562044125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2562044125
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3498426517
Short name T819
Test name
Test status
Simulation time 107127088808 ps
CPU time 314.04 seconds
Started Jul 30 05:24:01 PM PDT 24
Finished Jul 30 05:29:15 PM PDT 24
Peak memory 251144 kb
Host smart-7fa9818f-6b41-4151-aded-452c6a37e61d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498426517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3498426517
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3686973763
Short name T88
Test name
Test status
Simulation time 82449932938 ps
CPU time 9130.62 seconds
Started Jul 30 05:24:07 PM PDT 24
Finished Jul 30 07:56:19 PM PDT 24
Peak memory 1184252 kb
Host smart-3b1e531e-54c3-478b-8c69-52a9bf3d1b9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3686973763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3686973763
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3872602372
Short name T766
Test name
Test status
Simulation time 20996028 ps
CPU time 0.88 seconds
Started Jul 30 05:24:03 PM PDT 24
Finished Jul 30 05:24:04 PM PDT 24
Peak memory 212204 kb
Host smart-7c58c7ac-cbf2-4b43-881a-e7f7dadf6eaa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872602372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3872602372
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.973408186
Short name T486
Test name
Test status
Simulation time 197679359 ps
CPU time 0.82 seconds
Started Jul 30 05:24:10 PM PDT 24
Finished Jul 30 05:24:11 PM PDT 24
Peak memory 209116 kb
Host smart-ca428d5e-56e4-47fd-be24-7545ac23ca37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973408186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.973408186
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2322307919
Short name T865
Test name
Test status
Simulation time 1028381948 ps
CPU time 10.06 seconds
Started Jul 30 05:24:07 PM PDT 24
Finished Jul 30 05:24:17 PM PDT 24
Peak memory 218256 kb
Host smart-fc3fa6c1-a003-401b-be9a-68c8b0e82fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322307919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2322307919
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.766645731
Short name T174
Test name
Test status
Simulation time 517007021 ps
CPU time 13.04 seconds
Started Jul 30 05:24:06 PM PDT 24
Finished Jul 30 05:24:19 PM PDT 24
Peak memory 217304 kb
Host smart-f91afe59-8310-4352-ad7a-1f8e279e06d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766645731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.766645731
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.199679743
Short name T498
Test name
Test status
Simulation time 120929720 ps
CPU time 5.27 seconds
Started Jul 30 05:24:07 PM PDT 24
Finished Jul 30 05:24:13 PM PDT 24
Peak memory 218400 kb
Host smart-bc2fb592-a974-4928-817f-b4e270cff1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199679743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.199679743
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1523107306
Short name T791
Test name
Test status
Simulation time 1149606841 ps
CPU time 10.69 seconds
Started Jul 30 05:24:05 PM PDT 24
Finished Jul 30 05:24:16 PM PDT 24
Peak memory 218372 kb
Host smart-5f76b230-fe8c-4e68-a369-2fbc7546179c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523107306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1523107306
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2600066883
Short name T337
Test name
Test status
Simulation time 800898924 ps
CPU time 10.73 seconds
Started Jul 30 05:24:07 PM PDT 24
Finished Jul 30 05:24:18 PM PDT 24
Peak memory 218344 kb
Host smart-09659335-e034-4127-b945-2cb937b2e9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600066883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2600066883
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.581343242
Short name T471
Test name
Test status
Simulation time 485602124 ps
CPU time 11.63 seconds
Started Jul 30 05:24:08 PM PDT 24
Finished Jul 30 05:24:20 PM PDT 24
Peak memory 218308 kb
Host smart-9fad0c5c-8582-45ba-af02-fbdf98ccfdd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581343242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.581343242
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.4198950272
Short name T812
Test name
Test status
Simulation time 351438730 ps
CPU time 9.83 seconds
Started Jul 30 05:24:05 PM PDT 24
Finished Jul 30 05:24:15 PM PDT 24
Peak memory 225068 kb
Host smart-4c793ba8-e936-4415-85b2-3e18cb98f775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198950272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.4198950272
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1925373065
Short name T449
Test name
Test status
Simulation time 38820736 ps
CPU time 2.52 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:24:13 PM PDT 24
Peak memory 217668 kb
Host smart-4b924a0b-045d-4deb-888d-dec54933f300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925373065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1925373065
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2094520726
Short name T526
Test name
Test status
Simulation time 1088467320 ps
CPU time 25.06 seconds
Started Jul 30 05:24:07 PM PDT 24
Finished Jul 30 05:24:33 PM PDT 24
Peak memory 250948 kb
Host smart-e1cbfc5a-2696-49b7-a25c-4746cd77eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094520726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2094520726
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3638328034
Short name T661
Test name
Test status
Simulation time 183952232 ps
CPU time 7.77 seconds
Started Jul 30 05:24:07 PM PDT 24
Finished Jul 30 05:24:15 PM PDT 24
Peak memory 251072 kb
Host smart-62fd1a0d-c61e-4510-b4d1-fdfc14779a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638328034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3638328034
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.883193935
Short name T785
Test name
Test status
Simulation time 3253537522 ps
CPU time 60.29 seconds
Started Jul 30 05:24:05 PM PDT 24
Finished Jul 30 05:25:05 PM PDT 24
Peak memory 251092 kb
Host smart-2f7fb0c5-54a9-4007-a431-e69c0de645f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883193935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.883193935
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2754015074
Short name T146
Test name
Test status
Simulation time 14097401579 ps
CPU time 343.1 seconds
Started Jul 30 05:24:08 PM PDT 24
Finished Jul 30 05:29:51 PM PDT 24
Peak memory 389472 kb
Host smart-da4ae55b-1a10-4775-8b6c-ef14665bb8b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2754015074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2754015074
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3468836250
Short name T378
Test name
Test status
Simulation time 14982550 ps
CPU time 1.11 seconds
Started Jul 30 05:24:06 PM PDT 24
Finished Jul 30 05:24:07 PM PDT 24
Peak memory 212068 kb
Host smart-e64ce302-229d-424e-b29a-6a3f1c73fdb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468836250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3468836250
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.775542310
Short name T269
Test name
Test status
Simulation time 35692136 ps
CPU time 1.09 seconds
Started Jul 30 05:24:15 PM PDT 24
Finished Jul 30 05:24:16 PM PDT 24
Peak memory 209064 kb
Host smart-193da111-51b4-45b1-98f9-6060f10fa84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775542310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.775542310
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2460167315
Short name T467
Test name
Test status
Simulation time 4130023416 ps
CPU time 20.36 seconds
Started Jul 30 05:24:10 PM PDT 24
Finished Jul 30 05:24:31 PM PDT 24
Peak memory 219132 kb
Host smart-01103bb3-ae26-4197-bf64-53d3d4c20b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460167315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2460167315
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1014012487
Short name T479
Test name
Test status
Simulation time 936713973 ps
CPU time 9.29 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:24:21 PM PDT 24
Peak memory 217556 kb
Host smart-a08a2352-3e76-4271-8979-9429f12cfc8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014012487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1014012487
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3100920138
Short name T390
Test name
Test status
Simulation time 105449929 ps
CPU time 1.8 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:24:13 PM PDT 24
Peak memory 222144 kb
Host smart-075cc128-4f36-4adf-be37-cbb5410fae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100920138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3100920138
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1691964155
Short name T716
Test name
Test status
Simulation time 575192586 ps
CPU time 14.81 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:24:26 PM PDT 24
Peak memory 226208 kb
Host smart-b8441a99-9aa8-48b9-bca7-ab45ab1a6ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691964155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1691964155
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1379830870
Short name T335
Test name
Test status
Simulation time 1083199721 ps
CPU time 23.86 seconds
Started Jul 30 05:24:12 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 218336 kb
Host smart-dafbb5a2-33d2-4300-95ce-b9a4a44b36c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379830870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1379830870
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2330076579
Short name T729
Test name
Test status
Simulation time 1113352558 ps
CPU time 13.26 seconds
Started Jul 30 05:24:12 PM PDT 24
Finished Jul 30 05:24:25 PM PDT 24
Peak memory 226164 kb
Host smart-e884797e-25d1-442d-8fd9-3471f4f06309
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330076579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2330076579
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2903024021
Short name T456
Test name
Test status
Simulation time 3836305883 ps
CPU time 8.2 seconds
Started Jul 30 05:24:10 PM PDT 24
Finished Jul 30 05:24:18 PM PDT 24
Peak memory 226296 kb
Host smart-29cf81a7-6e45-41c4-b60c-0277984ac41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903024021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2903024021
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1700439648
Short name T68
Test name
Test status
Simulation time 47749688 ps
CPU time 2.53 seconds
Started Jul 30 05:24:05 PM PDT 24
Finished Jul 30 05:24:08 PM PDT 24
Peak memory 217892 kb
Host smart-918c5786-b02d-4f42-8d51-69e3fb29df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700439648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1700439648
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2057904832
Short name T792
Test name
Test status
Simulation time 436723848 ps
CPU time 19.9 seconds
Started Jul 30 05:24:12 PM PDT 24
Finished Jul 30 05:24:32 PM PDT 24
Peak memory 250880 kb
Host smart-e67d19b6-b06e-4fdd-8c72-f5150551d093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057904832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2057904832
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.887837698
Short name T169
Test name
Test status
Simulation time 84810971 ps
CPU time 7.79 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:24:21 PM PDT 24
Peak memory 250408 kb
Host smart-dd702750-7463-414c-bc31-8732ad756980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887837698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.887837698
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2409507907
Short name T601
Test name
Test status
Simulation time 4624148720 ps
CPU time 105.84 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:25:59 PM PDT 24
Peak memory 283844 kb
Host smart-5f8335fb-a0af-4afd-b58d-409c1181d6f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409507907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2409507907
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1272834865
Short name T247
Test name
Test status
Simulation time 12644084 ps
CPU time 1.02 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:24:14 PM PDT 24
Peak memory 212140 kb
Host smart-5a742c09-0928-4b28-80fb-3bc74ce05a9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272834865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1272834865
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.4174364744
Short name T469
Test name
Test status
Simulation time 26202523 ps
CPU time 0.91 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:24:14 PM PDT 24
Peak memory 209000 kb
Host smart-d705859f-6ca1-461a-9ac6-9a293dd7c01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174364744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.4174364744
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1477985694
Short name T697
Test name
Test status
Simulation time 1016913960 ps
CPU time 13.63 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:24:25 PM PDT 24
Peak memory 226228 kb
Host smart-ef3affee-062e-4222-90e0-40f5eaa657e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477985694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1477985694
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2374815942
Short name T682
Test name
Test status
Simulation time 1602262677 ps
CPU time 11.12 seconds
Started Jul 30 05:24:10 PM PDT 24
Finished Jul 30 05:24:22 PM PDT 24
Peak memory 217572 kb
Host smart-700f5b98-4b01-4518-bf2b-cff1f4a18a74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374815942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2374815942
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2078864126
Short name T549
Test name
Test status
Simulation time 82212737 ps
CPU time 3.3 seconds
Started Jul 30 05:24:14 PM PDT 24
Finished Jul 30 05:24:17 PM PDT 24
Peak memory 222600 kb
Host smart-e380c0e6-38e8-41f2-803f-b81c21b81720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078864126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2078864126
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.19939803
Short name T332
Test name
Test status
Simulation time 177255150 ps
CPU time 9.53 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:24:22 PM PDT 24
Peak memory 226236 kb
Host smart-7441c0f1-fbac-4583-9cef-2cb130b43049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19939803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.19939803
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1993395781
Short name T497
Test name
Test status
Simulation time 460422133 ps
CPU time 8.49 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:24:19 PM PDT 24
Peak memory 218260 kb
Host smart-b77286f5-6f7b-4076-9690-0e31a7d1558c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993395781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1993395781
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2302023122
Short name T277
Test name
Test status
Simulation time 942455635 ps
CPU time 9.18 seconds
Started Jul 30 05:24:10 PM PDT 24
Finished Jul 30 05:24:19 PM PDT 24
Peak memory 218252 kb
Host smart-28ff0331-f8d4-437b-bebf-9106ef6520d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302023122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2302023122
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4040225199
Short name T832
Test name
Test status
Simulation time 843189870 ps
CPU time 11.7 seconds
Started Jul 30 05:24:10 PM PDT 24
Finished Jul 30 05:24:22 PM PDT 24
Peak memory 225692 kb
Host smart-7ca2d713-5a17-4874-bba4-679023d778a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040225199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4040225199
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2005863401
Short name T719
Test name
Test status
Simulation time 85123705 ps
CPU time 1.93 seconds
Started Jul 30 05:24:12 PM PDT 24
Finished Jul 30 05:24:14 PM PDT 24
Peak memory 214324 kb
Host smart-6ca265cf-f3c9-4efa-9fe7-5a75f9bdf774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005863401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2005863401
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3230862160
Short name T447
Test name
Test status
Simulation time 200817739 ps
CPU time 25.46 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 251032 kb
Host smart-7818b783-bf80-4272-b9ea-3419b84b68c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230862160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3230862160
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3605119748
Short name T770
Test name
Test status
Simulation time 251357301 ps
CPU time 8.29 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:24:22 PM PDT 24
Peak memory 251024 kb
Host smart-6c16960c-d4c4-4dd4-8405-12b5c9eea5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605119748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3605119748
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.373886948
Short name T530
Test name
Test status
Simulation time 69153752540 ps
CPU time 498.76 seconds
Started Jul 30 05:24:11 PM PDT 24
Finished Jul 30 05:32:30 PM PDT 24
Peak memory 270820 kb
Host smart-9144b392-4f5a-45d9-a675-306f63aea1dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373886948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.373886948
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4133207659
Short name T213
Test name
Test status
Simulation time 21661569 ps
CPU time 1.06 seconds
Started Jul 30 05:24:10 PM PDT 24
Finished Jul 30 05:24:11 PM PDT 24
Peak memory 217924 kb
Host smart-d4dcb9f2-906f-41a6-aebe-dbae277d93ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133207659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.4133207659
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1637632703
Short name T250
Test name
Test status
Simulation time 78353549 ps
CPU time 0.94 seconds
Started Jul 30 05:24:17 PM PDT 24
Finished Jul 30 05:24:18 PM PDT 24
Peak memory 208968 kb
Host smart-b8ac30bf-bce5-4201-8d98-81b4cd6b2b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637632703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1637632703
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.771328976
Short name T231
Test name
Test status
Simulation time 437505000 ps
CPU time 14 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:24:27 PM PDT 24
Peak memory 218396 kb
Host smart-efbf0291-55e3-49ae-a820-146f9656fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771328976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.771328976
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3860250724
Short name T36
Test name
Test status
Simulation time 390028839 ps
CPU time 2.21 seconds
Started Jul 30 05:24:17 PM PDT 24
Finished Jul 30 05:24:20 PM PDT 24
Peak memory 217176 kb
Host smart-89ee1340-ca40-4d98-82cb-575a1752b5c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860250724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3860250724
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1195213655
Short name T523
Test name
Test status
Simulation time 114277772 ps
CPU time 3.17 seconds
Started Jul 30 05:24:16 PM PDT 24
Finished Jul 30 05:24:19 PM PDT 24
Peak memory 222636 kb
Host smart-fda98fd5-dfe7-4b01-b2c0-13dcd14c3371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195213655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1195213655
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1157406727
Short name T273
Test name
Test status
Simulation time 10254187557 ps
CPU time 25.89 seconds
Started Jul 30 05:24:15 PM PDT 24
Finished Jul 30 05:24:41 PM PDT 24
Peak memory 226320 kb
Host smart-4706379c-8685-4939-be80-c83c823a7b1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157406727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1157406727
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1948171468
Short name T159
Test name
Test status
Simulation time 581204356 ps
CPU time 9.36 seconds
Started Jul 30 05:24:13 PM PDT 24
Finished Jul 30 05:24:22 PM PDT 24
Peak memory 218324 kb
Host smart-53f00df5-4662-49bf-b1db-35a8032b959b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948171468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1948171468
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3546397875
Short name T15
Test name
Test status
Simulation time 3450077708 ps
CPU time 8.51 seconds
Started Jul 30 05:24:16 PM PDT 24
Finished Jul 30 05:24:24 PM PDT 24
Peak memory 218468 kb
Host smart-c39ac1d4-bab4-4177-89e7-2618ad5f80e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546397875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3546397875
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.182306308
Short name T365
Test name
Test status
Simulation time 1766162251 ps
CPU time 8.59 seconds
Started Jul 30 05:24:14 PM PDT 24
Finished Jul 30 05:24:23 PM PDT 24
Peak memory 226196 kb
Host smart-9e709573-c94b-4258-b77f-1fdba20f32f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182306308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.182306308
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2555253234
Short name T739
Test name
Test status
Simulation time 274234105 ps
CPU time 1.9 seconds
Started Jul 30 05:24:15 PM PDT 24
Finished Jul 30 05:24:17 PM PDT 24
Peak memory 222584 kb
Host smart-dfc3e302-03fc-4b32-81fb-21d872c67ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555253234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2555253234
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2047131837
Short name T856
Test name
Test status
Simulation time 1006729979 ps
CPU time 21.96 seconds
Started Jul 30 05:24:16 PM PDT 24
Finished Jul 30 05:24:38 PM PDT 24
Peak memory 245388 kb
Host smart-d2f52f7b-f4bd-4175-b67d-ba991ef328be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047131837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2047131837
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1180308594
Short name T463
Test name
Test status
Simulation time 189623886 ps
CPU time 9.01 seconds
Started Jul 30 05:24:16 PM PDT 24
Finished Jul 30 05:24:25 PM PDT 24
Peak memory 251052 kb
Host smart-925af5aa-f83a-4ab8-811b-1ecc6dc0feb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180308594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1180308594
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.295653190
Short name T315
Test name
Test status
Simulation time 3056164123 ps
CPU time 81.37 seconds
Started Jul 30 05:24:16 PM PDT 24
Finished Jul 30 05:25:37 PM PDT 24
Peak memory 279188 kb
Host smart-cba8decb-f1b9-4bd2-b1fc-c6bd0fd53840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295653190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.295653190
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1349936750
Short name T849
Test name
Test status
Simulation time 21884296 ps
CPU time 1.03 seconds
Started Jul 30 05:24:15 PM PDT 24
Finished Jul 30 05:24:16 PM PDT 24
Peak memory 212196 kb
Host smart-3545b317-609a-4ea5-b45a-da9c07a2e1c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349936750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1349936750
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1990371290
Short name T615
Test name
Test status
Simulation time 75977625 ps
CPU time 1.05 seconds
Started Jul 30 05:24:20 PM PDT 24
Finished Jul 30 05:24:21 PM PDT 24
Peak memory 209064 kb
Host smart-137316d9-98b7-41b3-866f-c602bc5118ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990371290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1990371290
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2201680839
Short name T438
Test name
Test status
Simulation time 321783603 ps
CPU time 12.11 seconds
Started Jul 30 05:24:19 PM PDT 24
Finished Jul 30 05:24:32 PM PDT 24
Peak memory 218332 kb
Host smart-1003357d-2044-4511-b714-d066b1c96e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201680839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2201680839
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2693595877
Short name T413
Test name
Test status
Simulation time 190102210 ps
CPU time 5.88 seconds
Started Jul 30 05:24:19 PM PDT 24
Finished Jul 30 05:24:25 PM PDT 24
Peak memory 217336 kb
Host smart-285f01bd-3f25-469c-a380-f807e261b492
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693595877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2693595877
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1267710677
Short name T251
Test name
Test status
Simulation time 120347148 ps
CPU time 3.43 seconds
Started Jul 30 05:24:20 PM PDT 24
Finished Jul 30 05:24:24 PM PDT 24
Peak memory 222312 kb
Host smart-feb56575-2f9c-4dc7-92a5-d6561a48ab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267710677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1267710677
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.717733753
Short name T462
Test name
Test status
Simulation time 1504985289 ps
CPU time 13.83 seconds
Started Jul 30 05:24:21 PM PDT 24
Finished Jul 30 05:24:35 PM PDT 24
Peak memory 218472 kb
Host smart-05be28af-4c2d-44de-bad9-586bc9d5ac47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717733753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.717733753
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2721101566
Short name T660
Test name
Test status
Simulation time 771736217 ps
CPU time 17.55 seconds
Started Jul 30 05:24:19 PM PDT 24
Finished Jul 30 05:24:37 PM PDT 24
Peak memory 218264 kb
Host smart-502dae9d-476f-46c1-ab16-27e5a79d3690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721101566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2721101566
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2993443776
Short name T599
Test name
Test status
Simulation time 382939739 ps
CPU time 10.61 seconds
Started Jul 30 05:24:20 PM PDT 24
Finished Jul 30 05:24:31 PM PDT 24
Peak memory 218352 kb
Host smart-beb2c344-829a-46f8-b8df-4aff50c800fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993443776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2993443776
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3165936617
Short name T464
Test name
Test status
Simulation time 583713796 ps
CPU time 16.02 seconds
Started Jul 30 05:24:19 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 218448 kb
Host smart-55da10f4-b982-43cb-9a24-58e78ba45426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165936617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3165936617
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.352425262
Short name T342
Test name
Test status
Simulation time 227060739 ps
CPU time 3.72 seconds
Started Jul 30 05:24:18 PM PDT 24
Finished Jul 30 05:24:21 PM PDT 24
Peak memory 217804 kb
Host smart-6da1aa27-8f0b-4c69-b2bc-ec7e5f3516af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352425262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.352425262
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1754575778
Short name T831
Test name
Test status
Simulation time 427331871 ps
CPU time 28.03 seconds
Started Jul 30 05:24:18 PM PDT 24
Finished Jul 30 05:24:46 PM PDT 24
Peak memory 247212 kb
Host smart-c7ec9fea-b9b0-41ae-81b9-2d2f66954f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754575778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1754575778
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2387935798
Short name T528
Test name
Test status
Simulation time 187556536 ps
CPU time 7.51 seconds
Started Jul 30 05:24:22 PM PDT 24
Finished Jul 30 05:24:29 PM PDT 24
Peak memory 251036 kb
Host smart-0ae9a466-d38c-4e7f-ae95-e723e955790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387935798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2387935798
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.224464749
Short name T41
Test name
Test status
Simulation time 3004537743 ps
CPU time 58.1 seconds
Started Jul 30 05:24:22 PM PDT 24
Finished Jul 30 05:25:20 PM PDT 24
Peak memory 220260 kb
Host smart-2a6351bf-27d6-40a5-b10e-7733a6193b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224464749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.224464749
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.4031186166
Short name T81
Test name
Test status
Simulation time 202423773151 ps
CPU time 1086.58 seconds
Started Jul 30 05:24:23 PM PDT 24
Finished Jul 30 05:42:30 PM PDT 24
Peak memory 464204 kb
Host smart-97d08d37-27bd-43a5-a867-8ac4ab3cddfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4031186166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.4031186166
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3946248183
Short name T631
Test name
Test status
Simulation time 12630439 ps
CPU time 0.98 seconds
Started Jul 30 05:24:12 PM PDT 24
Finished Jul 30 05:24:14 PM PDT 24
Peak memory 212084 kb
Host smart-e8c1be74-eece-44ee-8c5e-7159e61d7147
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946248183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3946248183
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3818991368
Short name T624
Test name
Test status
Simulation time 18876457 ps
CPU time 0.96 seconds
Started Jul 30 05:24:27 PM PDT 24
Finished Jul 30 05:24:28 PM PDT 24
Peak memory 209172 kb
Host smart-cefc1c77-27c7-4f0e-88f3-f35a9b989fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818991368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3818991368
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.49601816
Short name T514
Test name
Test status
Simulation time 1034849887 ps
CPU time 12.52 seconds
Started Jul 30 05:24:22 PM PDT 24
Finished Jul 30 05:24:35 PM PDT 24
Peak memory 218392 kb
Host smart-cfa05c27-ecd6-4ea0-8eae-86a4cbed0fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49601816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.49601816
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1468196244
Short name T651
Test name
Test status
Simulation time 1257183376 ps
CPU time 26 seconds
Started Jul 30 05:24:22 PM PDT 24
Finished Jul 30 05:24:49 PM PDT 24
Peak memory 217312 kb
Host smart-cf21737f-c8c2-49c6-87e7-51ebd6d63e44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468196244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1468196244
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1948250853
Short name T781
Test name
Test status
Simulation time 101059156 ps
CPU time 3.6 seconds
Started Jul 30 05:24:22 PM PDT 24
Finished Jul 30 05:24:26 PM PDT 24
Peak memory 222720 kb
Host smart-088b1b52-a14f-43d5-9573-de62b473021f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948250853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1948250853
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4141434852
Short name T704
Test name
Test status
Simulation time 718634684 ps
CPU time 16.67 seconds
Started Jul 30 05:24:25 PM PDT 24
Finished Jul 30 05:24:42 PM PDT 24
Peak memory 220120 kb
Host smart-5b14fecb-c237-4a0b-911e-7f657761fb5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141434852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4141434852
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.313634531
Short name T453
Test name
Test status
Simulation time 2456355387 ps
CPU time 20.6 seconds
Started Jul 30 05:24:28 PM PDT 24
Finished Jul 30 05:24:49 PM PDT 24
Peak memory 226044 kb
Host smart-e2e543d1-ad7c-4c3b-b7c5-fcc0c375df37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313634531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.313634531
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1533188786
Short name T465
Test name
Test status
Simulation time 290530673 ps
CPU time 9.11 seconds
Started Jul 30 05:24:26 PM PDT 24
Finished Jul 30 05:24:35 PM PDT 24
Peak memory 218316 kb
Host smart-b40a81d7-3953-41a4-b3e2-623d8a9548da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533188786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1533188786
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2334055491
Short name T478
Test name
Test status
Simulation time 1508047916 ps
CPU time 12.95 seconds
Started Jul 30 05:24:20 PM PDT 24
Finished Jul 30 05:24:33 PM PDT 24
Peak memory 226216 kb
Host smart-681f5634-e452-42d8-812b-3653c843edd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334055491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2334055491
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.785373474
Short name T475
Test name
Test status
Simulation time 22001034 ps
CPU time 1.72 seconds
Started Jul 30 05:24:23 PM PDT 24
Finished Jul 30 05:24:25 PM PDT 24
Peak memory 214096 kb
Host smart-e7d02d55-c209-4682-b7e1-77147ed418ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785373474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.785373474
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2414604710
Short name T698
Test name
Test status
Simulation time 709593116 ps
CPU time 34.86 seconds
Started Jul 30 05:24:24 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 251064 kb
Host smart-ecc66045-d85f-4c0b-9a0f-a750ce6d9716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414604710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2414604710
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4101265208
Short name T686
Test name
Test status
Simulation time 300519221 ps
CPU time 9.59 seconds
Started Jul 30 05:24:26 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 251052 kb
Host smart-df1297a6-9c70-474b-bdab-1db1cdecb711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101265208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4101265208
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3281486332
Short name T287
Test name
Test status
Simulation time 9718848713 ps
CPU time 138.04 seconds
Started Jul 30 05:24:25 PM PDT 24
Finished Jul 30 05:26:43 PM PDT 24
Peak memory 251108 kb
Host smart-34210d79-c259-41fe-a1d9-64b2b29dbb73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281486332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3281486332
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.229636445
Short name T74
Test name
Test status
Simulation time 78415016085 ps
CPU time 321.3 seconds
Started Jul 30 05:24:23 PM PDT 24
Finished Jul 30 05:29:45 PM PDT 24
Peak memory 309872 kb
Host smart-6839f85b-a6ce-4ef5-8065-18820fb744f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=229636445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.229636445
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3388932241
Short name T857
Test name
Test status
Simulation time 11811312 ps
CPU time 0.87 seconds
Started Jul 30 05:24:18 PM PDT 24
Finished Jul 30 05:24:20 PM PDT 24
Peak memory 212004 kb
Host smart-bd1692e2-14dc-4f67-b647-068a19490da4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388932241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3388932241
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2817790112
Short name T503
Test name
Test status
Simulation time 22575040 ps
CPU time 0.95 seconds
Started Jul 30 05:24:27 PM PDT 24
Finished Jul 30 05:24:28 PM PDT 24
Peak memory 208964 kb
Host smart-42b082a9-1c92-45b6-a342-292242989912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817790112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2817790112
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2693995893
Short name T397
Test name
Test status
Simulation time 524663177 ps
CPU time 11.38 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:42 PM PDT 24
Peak memory 218388 kb
Host smart-4a6cf585-ca65-45dd-a086-40cf62e65922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693995893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2693995893
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2716442274
Short name T389
Test name
Test status
Simulation time 1195133088 ps
CPU time 4.53 seconds
Started Jul 30 05:24:26 PM PDT 24
Finished Jul 30 05:24:30 PM PDT 24
Peak memory 217152 kb
Host smart-a5329f23-7642-40a3-90e2-7c127388c69c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716442274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2716442274
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1753163386
Short name T727
Test name
Test status
Simulation time 60214306 ps
CPU time 2.81 seconds
Started Jul 30 05:24:25 PM PDT 24
Finished Jul 30 05:24:28 PM PDT 24
Peak memory 218316 kb
Host smart-771514c7-dd39-40c2-b3f9-09d86589dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753163386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1753163386
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2797782540
Short name T339
Test name
Test status
Simulation time 1582469602 ps
CPU time 13.78 seconds
Started Jul 30 05:24:26 PM PDT 24
Finished Jul 30 05:24:39 PM PDT 24
Peak memory 226196 kb
Host smart-e1e753a7-8a4d-4ac2-b42f-cb42e2d68627
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797782540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2797782540
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2582100003
Short name T256
Test name
Test status
Simulation time 540812963 ps
CPU time 14.34 seconds
Started Jul 30 05:24:29 PM PDT 24
Finished Jul 30 05:24:44 PM PDT 24
Peak memory 218316 kb
Host smart-6bce9ee6-a01e-4471-8ea1-f1f93a1bf97e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582100003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2582100003
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2334570078
Short name T771
Test name
Test status
Simulation time 198255782 ps
CPU time 8.13 seconds
Started Jul 30 05:24:28 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 218240 kb
Host smart-2248cea9-fb0f-4d9e-bf4d-78856dda6206
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334570078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2334570078
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1334203269
Short name T830
Test name
Test status
Simulation time 2429366407 ps
CPU time 11.45 seconds
Started Jul 30 05:24:25 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 218540 kb
Host smart-776811ef-5cc5-4039-a6e6-e4c69239bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334203269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1334203269
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.4190323662
Short name T726
Test name
Test status
Simulation time 147268072 ps
CPU time 1.48 seconds
Started Jul 30 05:24:27 PM PDT 24
Finished Jul 30 05:24:29 PM PDT 24
Peak memory 214072 kb
Host smart-a14f0bfb-8a09-4e28-9d9a-e3314c4ce80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190323662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4190323662
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1291774682
Short name T200
Test name
Test status
Simulation time 957501029 ps
CPU time 20.13 seconds
Started Jul 30 05:24:24 PM PDT 24
Finished Jul 30 05:24:44 PM PDT 24
Peak memory 251112 kb
Host smart-76b9ad09-d2ec-40e9-bc21-67da0d09d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291774682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1291774682
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3150959859
Short name T825
Test name
Test status
Simulation time 110364226 ps
CPU time 6.58 seconds
Started Jul 30 05:24:27 PM PDT 24
Finished Jul 30 05:24:33 PM PDT 24
Peak memory 250488 kb
Host smart-fad66907-cf52-4b43-8208-cd82c0282617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150959859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3150959859
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.4182785735
Short name T629
Test name
Test status
Simulation time 27140895353 ps
CPU time 524.09 seconds
Started Jul 30 05:24:26 PM PDT 24
Finished Jul 30 05:33:10 PM PDT 24
Peak memory 388824 kb
Host smart-0fec2b07-7e09-483b-84cf-d9472286cdd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4182785735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.4182785735
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.901141656
Short name T494
Test name
Test status
Simulation time 63860695 ps
CPU time 1.08 seconds
Started Jul 30 05:24:26 PM PDT 24
Finished Jul 30 05:24:27 PM PDT 24
Peak memory 217884 kb
Host smart-4d3e17d2-cfbd-491f-bdd9-7dac318e843e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901141656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.901141656
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2377225052
Short name T62
Test name
Test status
Simulation time 26449923 ps
CPU time 1.1 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:33 PM PDT 24
Peak memory 209000 kb
Host smart-5c55f633-d464-44d4-8d0d-f4380844fc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377225052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2377225052
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1002461449
Short name T278
Test name
Test status
Simulation time 1779405547 ps
CPU time 13.78 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:45 PM PDT 24
Peak memory 226220 kb
Host smart-c2994277-07e0-4bc4-8b1d-befd02dec24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002461449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1002461449
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2515619620
Short name T33
Test name
Test status
Simulation time 3278269431 ps
CPU time 9.02 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:40 PM PDT 24
Peak memory 217888 kb
Host smart-2ea7e5fd-f4df-4912-a571-a4c46d904f31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515619620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2515619620
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3306813642
Short name T207
Test name
Test status
Simulation time 1049004277 ps
CPU time 3.52 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 222600 kb
Host smart-bcd29747-0dcb-46f0-8379-a2651f3b2528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306813642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3306813642
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4229863870
Short name T373
Test name
Test status
Simulation time 242388202 ps
CPU time 8.82 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:41 PM PDT 24
Peak memory 226176 kb
Host smart-bf6f957f-6c6a-4df5-a246-561c68c8d284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229863870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4229863870
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1105849771
Short name T261
Test name
Test status
Simulation time 424326903 ps
CPU time 12.8 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:44 PM PDT 24
Peak memory 218340 kb
Host smart-936aa79a-f928-448b-aa59-6b19dac64ee4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105849771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1105849771
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2791764840
Short name T415
Test name
Test status
Simulation time 485391687 ps
CPU time 9.18 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:40 PM PDT 24
Peak memory 218320 kb
Host smart-9dcc8bd6-d600-4a26-9299-eb31c4c07f28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791764840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2791764840
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2941372366
Short name T199
Test name
Test status
Simulation time 419065914 ps
CPU time 14.74 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:46 PM PDT 24
Peak memory 226148 kb
Host smart-322b2386-3412-4ed2-bfea-814208250dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941372366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2941372366
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.874370227
Short name T280
Test name
Test status
Simulation time 114217570 ps
CPU time 2.13 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:35 PM PDT 24
Peak memory 217652 kb
Host smart-c284ec31-a620-45a9-8b67-afbd68bd1001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874370227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.874370227
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.169983558
Short name T572
Test name
Test status
Simulation time 374383485 ps
CPU time 29.87 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:25:05 PM PDT 24
Peak memory 251044 kb
Host smart-8dd9d2a5-359a-4f10-8eb6-4b4d3b91b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169983558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.169983558
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.650285073
Short name T38
Test name
Test status
Simulation time 241424558 ps
CPU time 6.95 seconds
Started Jul 30 05:24:30 PM PDT 24
Finished Jul 30 05:24:37 PM PDT 24
Peak memory 251024 kb
Host smart-185dfb24-19f1-4403-9dbd-6c1b6bc8de43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650285073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.650285073
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.838935592
Short name T600
Test name
Test status
Simulation time 24543737639 ps
CPU time 85.29 seconds
Started Jul 30 05:24:34 PM PDT 24
Finished Jul 30 05:26:00 PM PDT 24
Peak memory 275204 kb
Host smart-22fb15df-95e1-4f49-9db2-4759de81f247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838935592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.838935592
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2835051773
Short name T134
Test name
Test status
Simulation time 259251748791 ps
CPU time 1248.79 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:45:20 PM PDT 24
Peak memory 298712 kb
Host smart-96faec55-cddf-4c00-bed3-0922643a66d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2835051773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2835051773
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3527515915
Short name T513
Test name
Test status
Simulation time 13910042 ps
CPU time 1.02 seconds
Started Jul 30 05:24:30 PM PDT 24
Finished Jul 30 05:24:31 PM PDT 24
Peak memory 212068 kb
Host smart-7b4b69b6-ee2b-446e-a307-fc53549c8a7a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527515915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3527515915
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.370372423
Short name T576
Test name
Test status
Simulation time 17536613 ps
CPU time 0.91 seconds
Started Jul 30 05:24:34 PM PDT 24
Finished Jul 30 05:24:35 PM PDT 24
Peak memory 208968 kb
Host smart-d63dca90-9aa3-4b90-994b-7424e68d4bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370372423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.370372423
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1489473345
Short name T858
Test name
Test status
Simulation time 995430744 ps
CPU time 8.19 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:39 PM PDT 24
Peak memory 226108 kb
Host smart-1911a6e4-7685-47c4-8b5d-40bd63e11984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489473345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1489473345
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.271818784
Short name T423
Test name
Test status
Simulation time 1202938571 ps
CPU time 4.99 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:40 PM PDT 24
Peak memory 217440 kb
Host smart-56c0157c-0f4f-4083-9e29-cf9ba199a293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271818784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.271818784
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1453239451
Short name T422
Test name
Test status
Simulation time 62299707 ps
CPU time 2.57 seconds
Started Jul 30 05:24:30 PM PDT 24
Finished Jul 30 05:24:33 PM PDT 24
Peak memory 218388 kb
Host smart-8dc1b33f-e499-44fa-9ffa-7995671f3247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453239451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1453239451
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.664747536
Short name T302
Test name
Test status
Simulation time 233407100 ps
CPU time 9.31 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:42 PM PDT 24
Peak memory 219100 kb
Host smart-86d9f24c-bd93-41fe-a84e-40a1aac9a7dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664747536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.664747536
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3527826754
Short name T692
Test name
Test status
Simulation time 1307391487 ps
CPU time 13.06 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:45 PM PDT 24
Peak memory 218356 kb
Host smart-45104d00-773c-47dd-a4d3-8a5a789f7ed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527826754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3527826754
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3680493332
Short name T541
Test name
Test status
Simulation time 549274759 ps
CPU time 9.78 seconds
Started Jul 30 05:24:34 PM PDT 24
Finished Jul 30 05:24:44 PM PDT 24
Peak memory 218352 kb
Host smart-0a184336-993a-45d2-a67a-78689246fe94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680493332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3680493332
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3548576118
Short name T259
Test name
Test status
Simulation time 654108013 ps
CPU time 7.53 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:39 PM PDT 24
Peak memory 225184 kb
Host smart-d669ba1c-27f1-4a9b-899a-964357273a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548576118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3548576118
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.903549578
Short name T860
Test name
Test status
Simulation time 26726963 ps
CPU time 1.58 seconds
Started Jul 30 05:24:32 PM PDT 24
Finished Jul 30 05:24:34 PM PDT 24
Peak memory 217852 kb
Host smart-24154d7c-eba6-4fb4-8d24-b63124511a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903549578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.903549578
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.82843080
Short name T502
Test name
Test status
Simulation time 834740132 ps
CPU time 27.7 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 251012 kb
Host smart-46b79632-5c93-4845-83e0-5e7279f018ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82843080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.82843080
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.100754590
Short name T25
Test name
Test status
Simulation time 55443502318 ps
CPU time 166.26 seconds
Started Jul 30 05:24:33 PM PDT 24
Finished Jul 30 05:27:19 PM PDT 24
Peak memory 251164 kb
Host smart-13e235bc-b1e1-4c12-8f3f-0fd4ec598301
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100754590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.100754590
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2689708798
Short name T299
Test name
Test status
Simulation time 11558707 ps
CPU time 0.91 seconds
Started Jul 30 05:24:31 PM PDT 24
Finished Jul 30 05:24:32 PM PDT 24
Peak memory 211964 kb
Host smart-9eac5f2e-724a-4327-8ace-54d30e807c02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689708798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2689708798
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3426823927
Short name T747
Test name
Test status
Simulation time 59552326 ps
CPU time 1.01 seconds
Started Jul 30 05:22:08 PM PDT 24
Finished Jul 30 05:22:09 PM PDT 24
Peak memory 209084 kb
Host smart-f1ab7ed1-473c-4bea-b371-82f6d160dd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426823927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3426823927
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2833450783
Short name T192
Test name
Test status
Simulation time 10812587 ps
CPU time 0.84 seconds
Started Jul 30 05:22:02 PM PDT 24
Finished Jul 30 05:22:03 PM PDT 24
Peak memory 208720 kb
Host smart-04c940c4-d008-4478-8b83-2ad942014850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833450783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2833450783
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2705176669
Short name T578
Test name
Test status
Simulation time 301191558 ps
CPU time 9.11 seconds
Started Jul 30 05:22:02 PM PDT 24
Finished Jul 30 05:22:11 PM PDT 24
Peak memory 218380 kb
Host smart-06c66fd6-57eb-4644-a01c-b3e5fce0825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705176669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2705176669
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1154100342
Short name T802
Test name
Test status
Simulation time 408798372 ps
CPU time 5.5 seconds
Started Jul 30 05:22:02 PM PDT 24
Finished Jul 30 05:22:08 PM PDT 24
Peak memory 217444 kb
Host smart-8c1dda67-dd97-46b9-963a-768c50a2d1ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154100342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1154100342
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3903092325
Short name T583
Test name
Test status
Simulation time 4611848392 ps
CPU time 38.78 seconds
Started Jul 30 05:22:05 PM PDT 24
Finished Jul 30 05:22:44 PM PDT 24
Peak memory 218888 kb
Host smart-91549188-5fc9-439f-827c-a06c9c6bc02b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903092325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3903092325
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.510776141
Short name T472
Test name
Test status
Simulation time 19725288637 ps
CPU time 13.77 seconds
Started Jul 30 05:22:01 PM PDT 24
Finished Jul 30 05:22:15 PM PDT 24
Peak memory 217888 kb
Host smart-80e9ede3-b0d6-474c-9221-be49b0e8b4c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510776141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.510776141
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.603847943
Short name T635
Test name
Test status
Simulation time 1254173822 ps
CPU time 6.34 seconds
Started Jul 30 05:22:02 PM PDT 24
Finished Jul 30 05:22:09 PM PDT 24
Peak memory 222104 kb
Host smart-d3e32347-832f-4471-b968-1f6145a7afad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603847943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.603847943
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3245810999
Short name T796
Test name
Test status
Simulation time 4512800377 ps
CPU time 16.52 seconds
Started Jul 30 05:22:08 PM PDT 24
Finished Jul 30 05:22:24 PM PDT 24
Peak memory 217744 kb
Host smart-cfed784a-f507-48b3-8915-b70805f1e920
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245810999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3245810999
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.206505811
Short name T324
Test name
Test status
Simulation time 313021410 ps
CPU time 10.42 seconds
Started Jul 30 05:22:03 PM PDT 24
Finished Jul 30 05:22:13 PM PDT 24
Peak memory 217708 kb
Host smart-14463a40-dc53-4e4e-8c85-2ac2327efdff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206505811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.206505811
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3588932977
Short name T394
Test name
Test status
Simulation time 2022996097 ps
CPU time 54.04 seconds
Started Jul 30 05:22:03 PM PDT 24
Finished Jul 30 05:22:58 PM PDT 24
Peak memory 283848 kb
Host smart-f8c3d581-2e4e-410a-b23b-a61f9653fffa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588932977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3588932977
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1885451964
Short name T443
Test name
Test status
Simulation time 2783293929 ps
CPU time 14.02 seconds
Started Jul 30 05:22:05 PM PDT 24
Finished Jul 30 05:22:19 PM PDT 24
Peak memory 248608 kb
Host smart-03c97163-d010-4fd8-b17a-d3ae3d3ceecd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885451964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1885451964
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1538878165
Short name T1
Test name
Test status
Simulation time 82975051 ps
CPU time 4.04 seconds
Started Jul 30 05:22:06 PM PDT 24
Finished Jul 30 05:22:10 PM PDT 24
Peak memory 218384 kb
Host smart-9460050a-0d18-4739-95da-961d80dbefd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538878165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1538878165
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.660579215
Short name T844
Test name
Test status
Simulation time 4693730803 ps
CPU time 8.91 seconds
Started Jul 30 05:22:05 PM PDT 24
Finished Jul 30 05:22:14 PM PDT 24
Peak memory 215304 kb
Host smart-58af38b7-a565-4099-9c55-bffb408c042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660579215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.660579215
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1998165867
Short name T49
Test name
Test status
Simulation time 122418245 ps
CPU time 21.48 seconds
Started Jul 30 05:22:09 PM PDT 24
Finished Jul 30 05:22:31 PM PDT 24
Peak memory 268432 kb
Host smart-3be87139-a3ed-40ab-ab32-c16f7099cc88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998165867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1998165867
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.38388959
Short name T214
Test name
Test status
Simulation time 723249061 ps
CPU time 11.12 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:22:22 PM PDT 24
Peak memory 226212 kb
Host smart-d6512240-4425-486a-9590-668289b293e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.38388959
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1537918342
Short name T392
Test name
Test status
Simulation time 1258968707 ps
CPU time 14.3 seconds
Started Jul 30 05:22:09 PM PDT 24
Finished Jul 30 05:22:23 PM PDT 24
Peak memory 226120 kb
Host smart-c84f2214-8d0e-4122-85da-c6fff1bb2843
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537918342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1537918342
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.339038732
Short name T52
Test name
Test status
Simulation time 2123309907 ps
CPU time 9.88 seconds
Started Jul 30 05:22:06 PM PDT 24
Finished Jul 30 05:22:16 PM PDT 24
Peak memory 218184 kb
Host smart-7e3538eb-bbef-47d6-82a7-6db8e4e113ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339038732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.339038732
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.999007254
Short name T500
Test name
Test status
Simulation time 299218474 ps
CPU time 8.73 seconds
Started Jul 30 05:22:01 PM PDT 24
Finished Jul 30 05:22:10 PM PDT 24
Peak memory 226176 kb
Host smart-308179a7-7fe9-4da7-a378-716ddd8c6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999007254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.999007254
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.63989777
Short name T813
Test name
Test status
Simulation time 52358810 ps
CPU time 1.6 seconds
Started Jul 30 05:22:03 PM PDT 24
Finished Jul 30 05:22:04 PM PDT 24
Peak memory 214076 kb
Host smart-adc1e729-4910-48ff-8b42-63d2159e0a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63989777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.63989777
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1279568192
Short name T515
Test name
Test status
Simulation time 1242296043 ps
CPU time 26.46 seconds
Started Jul 30 05:22:02 PM PDT 24
Finished Jul 30 05:22:29 PM PDT 24
Peak memory 251180 kb
Host smart-25693e22-1af1-43d9-bfe5-37c5025457cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279568192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1279568192
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3361695180
Short name T283
Test name
Test status
Simulation time 125680424 ps
CPU time 8.65 seconds
Started Jul 30 05:22:05 PM PDT 24
Finished Jul 30 05:22:13 PM PDT 24
Peak memory 251088 kb
Host smart-67325eee-ff17-4dc9-a937-68a9d566362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361695180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3361695180
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3015096921
Short name T658
Test name
Test status
Simulation time 15820965421 ps
CPU time 296.99 seconds
Started Jul 30 05:22:06 PM PDT 24
Finished Jul 30 05:27:03 PM PDT 24
Peak memory 251100 kb
Host smart-39a880dd-70a4-4fc7-b421-be19b24f8600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015096921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3015096921
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.762778754
Short name T225
Test name
Test status
Simulation time 17692947 ps
CPU time 1.15 seconds
Started Jul 30 05:22:05 PM PDT 24
Finished Jul 30 05:22:06 PM PDT 24
Peak memory 213036 kb
Host smart-ecbb9249-ed96-4936-aa01-21d85d0240a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762778754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.762778754
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2756847922
Short name T808
Test name
Test status
Simulation time 20622723 ps
CPU time 1.19 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:36 PM PDT 24
Peak memory 209112 kb
Host smart-3dee5ef7-8717-472b-8c92-b8f86bfaabaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756847922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2756847922
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2582408721
Short name T412
Test name
Test status
Simulation time 401307165 ps
CPU time 12.49 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:47 PM PDT 24
Peak memory 218392 kb
Host smart-b1ca91de-6287-4170-a598-f8a7c3c0e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582408721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2582408721
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2241106623
Short name T329
Test name
Test status
Simulation time 108982061 ps
CPU time 3.67 seconds
Started Jul 30 05:24:34 PM PDT 24
Finished Jul 30 05:24:39 PM PDT 24
Peak memory 217192 kb
Host smart-3450200c-9aab-4ac8-8f84-a4257a409599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241106623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2241106623
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.195076657
Short name T246
Test name
Test status
Simulation time 414806010 ps
CPU time 4.48 seconds
Started Jul 30 05:24:42 PM PDT 24
Finished Jul 30 05:24:46 PM PDT 24
Peak memory 218232 kb
Host smart-08f7cb12-63b3-40d2-8e76-fca10a08257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195076657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.195076657
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3491857169
Short name T670
Test name
Test status
Simulation time 1245197590 ps
CPU time 13.33 seconds
Started Jul 30 05:24:42 PM PDT 24
Finished Jul 30 05:24:55 PM PDT 24
Peak memory 218896 kb
Host smart-8cb0c3d6-3f9e-421e-a0e0-be48fffc3114
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491857169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3491857169
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2914240003
Short name T696
Test name
Test status
Simulation time 302015296 ps
CPU time 8.38 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:44 PM PDT 24
Peak memory 218340 kb
Host smart-a3400693-c9cb-4c6d-adcf-0c2e44dee675
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914240003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2914240003
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.511253123
Short name T258
Test name
Test status
Simulation time 345481316 ps
CPU time 9.97 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:45 PM PDT 24
Peak memory 226148 kb
Host smart-ff9093c9-2b95-4731-920a-3f41ebe2da04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511253123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.511253123
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3807647475
Short name T312
Test name
Test status
Simulation time 3926421210 ps
CPU time 11.21 seconds
Started Jul 30 05:24:42 PM PDT 24
Finished Jul 30 05:24:53 PM PDT 24
Peak memory 226100 kb
Host smart-bc17c9ea-9f07-473e-90ad-0380bdfc3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807647475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3807647475
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3041922501
Short name T426
Test name
Test status
Simulation time 948899414 ps
CPU time 4.49 seconds
Started Jul 30 05:24:37 PM PDT 24
Finished Jul 30 05:24:42 PM PDT 24
Peak memory 217884 kb
Host smart-ac27b8e2-495e-4acc-836b-e1d7746695cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041922501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3041922501
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.263822684
Short name T148
Test name
Test status
Simulation time 417826666 ps
CPU time 21.97 seconds
Started Jul 30 05:24:41 PM PDT 24
Finished Jul 30 05:25:03 PM PDT 24
Peak memory 250848 kb
Host smart-3da21c56-d347-454b-b707-327bb33522da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263822684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.263822684
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.4083614773
Short name T145
Test name
Test status
Simulation time 138666598 ps
CPU time 8.13 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:44 PM PDT 24
Peak memory 250920 kb
Host smart-03facacc-d47a-421e-b5ff-2f97e801661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083614773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4083614773
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1593741717
Short name T763
Test name
Test status
Simulation time 3865160840 ps
CPU time 90.61 seconds
Started Jul 30 05:24:41 PM PDT 24
Finished Jul 30 05:26:12 PM PDT 24
Peak memory 226108 kb
Host smart-1e288781-45b0-4501-ba5b-cd042f36c3a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593741717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1593741717
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3683563132
Short name T153
Test name
Test status
Simulation time 23169760 ps
CPU time 0.91 seconds
Started Jul 30 05:24:42 PM PDT 24
Finished Jul 30 05:24:43 PM PDT 24
Peak memory 217748 kb
Host smart-efbbb3c4-9b44-486a-960e-1b6ffd5069c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683563132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3683563132
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3130984725
Short name T311
Test name
Test status
Simulation time 50035387 ps
CPU time 1.07 seconds
Started Jul 30 05:24:37 PM PDT 24
Finished Jul 30 05:24:38 PM PDT 24
Peak memory 209108 kb
Host smart-2b1df5b8-39b8-4aca-9e60-ce34f4c7f712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130984725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3130984725
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2552979927
Short name T361
Test name
Test status
Simulation time 918984360 ps
CPU time 15.43 seconds
Started Jul 30 05:24:38 PM PDT 24
Finished Jul 30 05:24:54 PM PDT 24
Peak memory 218448 kb
Host smart-fbcb7da6-7e50-49ed-af57-d7f422f6511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552979927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2552979927
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1874552962
Short name T590
Test name
Test status
Simulation time 649855408 ps
CPU time 7.06 seconds
Started Jul 30 05:24:35 PM PDT 24
Finished Jul 30 05:24:43 PM PDT 24
Peak memory 217388 kb
Host smart-454bd485-1567-464c-9a9f-0df073792809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874552962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1874552962
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.436664507
Short name T151
Test name
Test status
Simulation time 66654480 ps
CPU time 3.2 seconds
Started Jul 30 05:24:39 PM PDT 24
Finished Jul 30 05:24:42 PM PDT 24
Peak memory 218404 kb
Host smart-d1977119-4232-4275-8ede-7ad82b508eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436664507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.436664507
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1529714973
Short name T356
Test name
Test status
Simulation time 347048264 ps
CPU time 14 seconds
Started Jul 30 05:24:39 PM PDT 24
Finished Jul 30 05:24:54 PM PDT 24
Peak memory 219072 kb
Host smart-b8392b9f-5a3c-4688-9a90-cdb25d60d3a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529714973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1529714973
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1432726661
Short name T555
Test name
Test status
Simulation time 834448064 ps
CPU time 8.63 seconds
Started Jul 30 05:24:37 PM PDT 24
Finished Jul 30 05:24:45 PM PDT 24
Peak memory 218352 kb
Host smart-a93d707e-e754-4b9f-94aa-ad244efd17ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432726661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1432726661
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.302221523
Short name T707
Test name
Test status
Simulation time 3585186626 ps
CPU time 8.39 seconds
Started Jul 30 05:24:37 PM PDT 24
Finished Jul 30 05:24:46 PM PDT 24
Peak memory 219052 kb
Host smart-7caf1bfa-56e0-49ab-ace6-1d9c36853066
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302221523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.302221523
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.657387218
Short name T51
Test name
Test status
Simulation time 1930617475 ps
CPU time 13.66 seconds
Started Jul 30 05:24:37 PM PDT 24
Finished Jul 30 05:24:50 PM PDT 24
Peak memory 226204 kb
Host smart-1db02c24-1d71-4890-8162-292e9b152a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657387218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.657387218
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1888645433
Short name T532
Test name
Test status
Simulation time 217411967 ps
CPU time 3.84 seconds
Started Jul 30 05:24:38 PM PDT 24
Finished Jul 30 05:24:42 PM PDT 24
Peak memory 217880 kb
Host smart-21ff1c3d-ed14-4a97-8b61-b501a330c4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888645433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1888645433
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2198720340
Short name T222
Test name
Test status
Simulation time 212429113 ps
CPU time 22.96 seconds
Started Jul 30 05:24:39 PM PDT 24
Finished Jul 30 05:25:02 PM PDT 24
Peak memory 244420 kb
Host smart-9cea3c6f-cae8-461a-a2c5-d4b7fa4a9836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198720340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2198720340
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3265481706
Short name T711
Test name
Test status
Simulation time 78143838 ps
CPU time 7.82 seconds
Started Jul 30 05:24:40 PM PDT 24
Finished Jul 30 05:24:48 PM PDT 24
Peak memory 251040 kb
Host smart-3034156e-8dba-42b2-a5d6-302820a5faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265481706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3265481706
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.4178313434
Short name T724
Test name
Test status
Simulation time 1085049072 ps
CPU time 33.45 seconds
Started Jul 30 05:24:37 PM PDT 24
Finished Jul 30 05:25:11 PM PDT 24
Peak memory 250636 kb
Host smart-63c96792-8555-4096-89b4-970e9feb5c06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178313434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.4178313434
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.4047411534
Short name T126
Test name
Test status
Simulation time 32314659012 ps
CPU time 444.38 seconds
Started Jul 30 05:24:36 PM PDT 24
Finished Jul 30 05:32:00 PM PDT 24
Peak memory 283940 kb
Host smart-396913dc-1665-4d88-8a83-858d9bb4280b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4047411534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.4047411534
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2701382060
Short name T363
Test name
Test status
Simulation time 38703428 ps
CPU time 0.85 seconds
Started Jul 30 05:24:39 PM PDT 24
Finished Jul 30 05:24:40 PM PDT 24
Peak memory 212088 kb
Host smart-345601b9-f65c-446e-90fc-48719d028e93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701382060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2701382060
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3825338509
Short name T806
Test name
Test status
Simulation time 65358033 ps
CPU time 1 seconds
Started Jul 30 05:24:44 PM PDT 24
Finished Jul 30 05:24:45 PM PDT 24
Peak memory 209104 kb
Host smart-7f4a59b2-b462-4672-be3d-d45f05124c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825338509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3825338509
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4066551150
Short name T545
Test name
Test status
Simulation time 2723811111 ps
CPU time 27.08 seconds
Started Jul 30 05:24:41 PM PDT 24
Finished Jul 30 05:25:08 PM PDT 24
Peak memory 226184 kb
Host smart-01203b1c-8105-476e-88b3-e082bf4be951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066551150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4066551150
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4242830178
Short name T537
Test name
Test status
Simulation time 3249083174 ps
CPU time 15.64 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:08 PM PDT 24
Peak memory 217840 kb
Host smart-47048e44-dfd8-47fa-9c0c-cfb0573e5993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242830178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4242830178
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1036813235
Short name T561
Test name
Test status
Simulation time 397101188 ps
CPU time 4.72 seconds
Started Jul 30 05:24:43 PM PDT 24
Finished Jul 30 05:24:48 PM PDT 24
Peak memory 222664 kb
Host smart-14c4e2d7-1161-4b33-95c8-8eea8f2c6961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036813235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1036813235
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4278125807
Short name T634
Test name
Test status
Simulation time 242059974 ps
CPU time 12.37 seconds
Started Jul 30 05:24:43 PM PDT 24
Finished Jul 30 05:24:56 PM PDT 24
Peak memory 226228 kb
Host smart-8b5ec6c5-be49-4862-aa66-edffce07422a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278125807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4278125807
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3192309932
Short name T262
Test name
Test status
Simulation time 734086155 ps
CPU time 8.86 seconds
Started Jul 30 05:24:43 PM PDT 24
Finished Jul 30 05:24:52 PM PDT 24
Peak memory 218296 kb
Host smart-d04cc286-4042-4cfc-aa7e-fa261d2be69b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192309932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3192309932
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2405324463
Short name T375
Test name
Test status
Simulation time 220385381 ps
CPU time 9.75 seconds
Started Jul 30 05:24:43 PM PDT 24
Finished Jul 30 05:24:52 PM PDT 24
Peak memory 218300 kb
Host smart-69345563-4208-44ad-b789-f79a8b354671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405324463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2405324463
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2567462430
Short name T292
Test name
Test status
Simulation time 369401466 ps
CPU time 14.76 seconds
Started Jul 30 05:24:44 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 226220 kb
Host smart-819cb566-6b3d-4eb5-9ae7-b913f966793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567462430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2567462430
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3812171794
Short name T206
Test name
Test status
Simulation time 122975903 ps
CPU time 3.92 seconds
Started Jul 30 05:24:39 PM PDT 24
Finished Jul 30 05:24:43 PM PDT 24
Peak memory 217828 kb
Host smart-7d9067b4-bd75-4a56-8052-f330256367d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812171794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3812171794
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4056372706
Short name T652
Test name
Test status
Simulation time 1219188860 ps
CPU time 28.29 seconds
Started Jul 30 05:24:39 PM PDT 24
Finished Jul 30 05:25:07 PM PDT 24
Peak memory 251048 kb
Host smart-de2f9bfb-dcbc-4c64-8de3-160b5613a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056372706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4056372706
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.348193188
Short name T823
Test name
Test status
Simulation time 59989249 ps
CPU time 3.22 seconds
Started Jul 30 05:24:43 PM PDT 24
Finished Jul 30 05:24:46 PM PDT 24
Peak memory 226492 kb
Host smart-f8f25d72-b637-4755-a26d-7bf5a45bfe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348193188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.348193188
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.320600230
Short name T592
Test name
Test status
Simulation time 1482267459 ps
CPU time 64.16 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:57 PM PDT 24
Peak memory 275812 kb
Host smart-fdce9df3-894c-464b-bd05-5d1b5ea5ed28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320600230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.320600230
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.856704356
Short name T625
Test name
Test status
Simulation time 142177583 ps
CPU time 0.92 seconds
Started Jul 30 05:24:47 PM PDT 24
Finished Jul 30 05:24:47 PM PDT 24
Peak memory 209064 kb
Host smart-d9d32b4c-9539-400f-bb7a-aa98fcb1e9db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856704356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.856704356
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3760022568
Short name T364
Test name
Test status
Simulation time 1306040234 ps
CPU time 11.56 seconds
Started Jul 30 05:24:48 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 218472 kb
Host smart-ca389df1-f9a1-4a97-8bbf-39478f884641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760022568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3760022568
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1991326936
Short name T714
Test name
Test status
Simulation time 573982350 ps
CPU time 7.08 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:00 PM PDT 24
Peak memory 217592 kb
Host smart-46cb1331-9d5b-40ef-a28e-eb2e9ec62188
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991326936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1991326936
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.915778463
Short name T776
Test name
Test status
Simulation time 96206708 ps
CPU time 2.23 seconds
Started Jul 30 05:24:45 PM PDT 24
Finished Jul 30 05:24:48 PM PDT 24
Peak memory 218388 kb
Host smart-b6b20d11-6de9-49e2-9347-6c568d403354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915778463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.915778463
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1925033055
Short name T205
Test name
Test status
Simulation time 343977944 ps
CPU time 13.45 seconds
Started Jul 30 05:24:46 PM PDT 24
Finished Jul 30 05:25:00 PM PDT 24
Peak memory 226184 kb
Host smart-d6a5535e-84d4-4062-ad4a-e82451bfde8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925033055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1925033055
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3065579848
Short name T16
Test name
Test status
Simulation time 1378023172 ps
CPU time 14.66 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:07 PM PDT 24
Peak memory 218372 kb
Host smart-7b969add-9bed-4435-8cde-c6206b0e0a02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065579848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3065579848
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4146977469
Short name T459
Test name
Test status
Simulation time 1155785670 ps
CPU time 18.42 seconds
Started Jul 30 05:24:45 PM PDT 24
Finished Jul 30 05:25:04 PM PDT 24
Peak memory 218272 kb
Host smart-ca35d8e9-81e8-47da-896d-cad1f1227eee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146977469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4146977469
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2863197974
Short name T477
Test name
Test status
Simulation time 269399969 ps
CPU time 9.96 seconds
Started Jul 30 05:24:45 PM PDT 24
Finished Jul 30 05:24:55 PM PDT 24
Peak memory 225128 kb
Host smart-ff4dec75-d6da-43f0-b588-739b6807eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863197974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2863197974
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.525973190
Short name T72
Test name
Test status
Simulation time 53595913 ps
CPU time 2.98 seconds
Started Jul 30 05:24:41 PM PDT 24
Finished Jul 30 05:24:44 PM PDT 24
Peak memory 217804 kb
Host smart-785f01f3-be7e-452c-a08d-9f93665f2b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525973190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.525973190
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.807108686
Short name T548
Test name
Test status
Simulation time 447562852 ps
CPU time 32.86 seconds
Started Jul 30 05:24:42 PM PDT 24
Finished Jul 30 05:25:15 PM PDT 24
Peak memory 251192 kb
Host smart-3113dfd5-9771-43fc-8354-f2cc0f907ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807108686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.807108686
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2588666503
Short name T728
Test name
Test status
Simulation time 64089593 ps
CPU time 8.41 seconds
Started Jul 30 05:24:48 PM PDT 24
Finished Jul 30 05:24:56 PM PDT 24
Peak memory 251028 kb
Host smart-122d4891-8f70-4686-b0ba-414b958fcba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588666503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2588666503
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.760469048
Short name T663
Test name
Test status
Simulation time 38389486614 ps
CPU time 275.13 seconds
Started Jul 30 05:24:47 PM PDT 24
Finished Jul 30 05:29:22 PM PDT 24
Peak memory 269732 kb
Host smart-8c1f8183-717b-42d7-bde6-daf39eb01398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760469048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.760469048
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3601001410
Short name T866
Test name
Test status
Simulation time 54209746 ps
CPU time 1.3 seconds
Started Jul 30 05:24:44 PM PDT 24
Finished Jul 30 05:24:46 PM PDT 24
Peak memory 218092 kb
Host smart-d5043ec4-5630-4dd3-90b3-a7eb76cd29ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601001410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3601001410
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2536702344
Short name T529
Test name
Test status
Simulation time 33521175 ps
CPU time 1.14 seconds
Started Jul 30 05:24:51 PM PDT 24
Finished Jul 30 05:24:53 PM PDT 24
Peak memory 209232 kb
Host smart-5c5f5ed6-7dc5-465f-9870-28183b4d4b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536702344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2536702344
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1931142163
Short name T340
Test name
Test status
Simulation time 776801355 ps
CPU time 13.67 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:06 PM PDT 24
Peak memory 226248 kb
Host smart-4fa53820-fd21-4a4a-861e-befd3e9fe821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931142163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1931142163
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.600824775
Short name T346
Test name
Test status
Simulation time 500482149 ps
CPU time 11.12 seconds
Started Jul 30 05:24:51 PM PDT 24
Finished Jul 30 05:25:02 PM PDT 24
Peak memory 217376 kb
Host smart-53decd6e-16bc-4383-a989-6bf1b3ef34a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600824775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.600824775
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.967154697
Short name T826
Test name
Test status
Simulation time 44942078 ps
CPU time 2.65 seconds
Started Jul 30 05:24:46 PM PDT 24
Finished Jul 30 05:24:49 PM PDT 24
Peak memory 222432 kb
Host smart-a7f6025c-ce6c-439b-b9c7-541598535eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967154697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.967154697
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3390842080
Short name T144
Test name
Test status
Simulation time 627545151 ps
CPU time 15.77 seconds
Started Jul 30 05:24:53 PM PDT 24
Finished Jul 30 05:25:09 PM PDT 24
Peak memory 226244 kb
Host smart-7cd50e08-3186-45a3-9a32-110e88734bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390842080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3390842080
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2640774760
Short name T414
Test name
Test status
Simulation time 739084798 ps
CPU time 27.31 seconds
Started Jul 30 05:24:49 PM PDT 24
Finished Jul 30 05:25:16 PM PDT 24
Peak memory 218348 kb
Host smart-2fc46918-76bc-46cd-82f2-2f97851ca741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640774760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2640774760
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.800352062
Short name T566
Test name
Test status
Simulation time 2127459985 ps
CPU time 9.66 seconds
Started Jul 30 05:24:50 PM PDT 24
Finished Jul 30 05:25:00 PM PDT 24
Peak memory 226148 kb
Host smart-840fcede-12d9-41f8-993c-b9b98e241511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800352062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.800352062
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1623226532
Short name T425
Test name
Test status
Simulation time 1378420949 ps
CPU time 8.14 seconds
Started Jul 30 05:24:47 PM PDT 24
Finished Jul 30 05:24:55 PM PDT 24
Peak memory 224992 kb
Host smart-6237c534-1eb1-45bb-9209-5148a22099a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623226532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1623226532
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4191037653
Short name T775
Test name
Test status
Simulation time 44488903 ps
CPU time 2.59 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:24:55 PM PDT 24
Peak memory 217860 kb
Host smart-29722f09-a8ba-4455-9ade-d0fab3d5d85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191037653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4191037653
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2623197108
Short name T224
Test name
Test status
Simulation time 1017040035 ps
CPU time 33.37 seconds
Started Jul 30 05:24:46 PM PDT 24
Finished Jul 30 05:25:19 PM PDT 24
Peak memory 246856 kb
Host smart-586f8594-f130-49f5-ae75-3470e16c1507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623197108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2623197108
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2164226095
Short name T575
Test name
Test status
Simulation time 84254382 ps
CPU time 7.54 seconds
Started Jul 30 05:25:03 PM PDT 24
Finished Jul 30 05:25:11 PM PDT 24
Peak memory 246764 kb
Host smart-d4fe97be-6e01-4226-bb40-970586aa1493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164226095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2164226095
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.792248001
Short name T24
Test name
Test status
Simulation time 24217327236 ps
CPU time 183.77 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:27:56 PM PDT 24
Peak memory 283788 kb
Host smart-ad38fb27-203b-471c-939c-7d98f17592db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792248001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.792248001
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2219246120
Short name T757
Test name
Test status
Simulation time 9831904 ps
CPU time 0.75 seconds
Started Jul 30 05:24:46 PM PDT 24
Finished Jul 30 05:24:47 PM PDT 24
Peak memory 207276 kb
Host smart-867d4620-b47b-49ab-add0-f399ab136525
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219246120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2219246120
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.520851083
Short name T745
Test name
Test status
Simulation time 75960126 ps
CPU time 0.89 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:06 PM PDT 24
Peak memory 208844 kb
Host smart-ac2b2791-27ea-427d-af94-63bbfa799c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520851083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.520851083
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.227696481
Short name T330
Test name
Test status
Simulation time 887916272 ps
CPU time 7.68 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:00 PM PDT 24
Peak memory 218360 kb
Host smart-f59f7d1e-1882-4a55-88b0-7e3b35e05be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227696481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.227696481
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1823890864
Short name T368
Test name
Test status
Simulation time 799275887 ps
CPU time 1.21 seconds
Started Jul 30 05:24:51 PM PDT 24
Finished Jul 30 05:24:52 PM PDT 24
Peak memory 217180 kb
Host smart-f7f41079-4847-4db4-9ac0-fcfa665084b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823890864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1823890864
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1398928717
Short name T468
Test name
Test status
Simulation time 79772851 ps
CPU time 3.68 seconds
Started Jul 30 05:24:48 PM PDT 24
Finished Jul 30 05:24:52 PM PDT 24
Peak memory 218392 kb
Host smart-6a1bb3ee-297b-44c4-997b-f0e00c9a4010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398928717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1398928717
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1239810368
Short name T783
Test name
Test status
Simulation time 268615476 ps
CPU time 11.46 seconds
Started Jul 30 05:24:50 PM PDT 24
Finished Jul 30 05:25:02 PM PDT 24
Peak memory 226236 kb
Host smart-0c427ed5-c545-4c79-99c3-9476dc76e25a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239810368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1239810368
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3063772657
Short name T767
Test name
Test status
Simulation time 799081762 ps
CPU time 11.28 seconds
Started Jul 30 05:24:53 PM PDT 24
Finished Jul 30 05:25:05 PM PDT 24
Peak memory 218296 kb
Host smart-3cf9a22f-cbfb-4dab-8e15-6fcb80466d64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063772657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3063772657
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2115318126
Short name T129
Test name
Test status
Simulation time 381347896 ps
CPU time 9.56 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:01 PM PDT 24
Peak memory 218360 kb
Host smart-0e6b6984-bcd0-423b-9dd9-58897f12762f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115318126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2115318126
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.100906799
Short name T352
Test name
Test status
Simulation time 522072683 ps
CPU time 11.21 seconds
Started Jul 30 05:24:52 PM PDT 24
Finished Jul 30 05:25:03 PM PDT 24
Peak memory 226256 kb
Host smart-593038b0-4f36-4a02-9082-ec2fe1d5b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100906799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.100906799
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3707044137
Short name T73
Test name
Test status
Simulation time 149546375 ps
CPU time 2.19 seconds
Started Jul 30 05:24:51 PM PDT 24
Finished Jul 30 05:24:53 PM PDT 24
Peak memory 214448 kb
Host smart-4e9b69f0-553b-4c0e-b59d-446b0488574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707044137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3707044137
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1020008419
Short name T87
Test name
Test status
Simulation time 791547185 ps
CPU time 23.56 seconds
Started Jul 30 05:24:50 PM PDT 24
Finished Jul 30 05:25:14 PM PDT 24
Peak memory 251068 kb
Host smart-0675e4e4-75f3-4a01-b994-27035acd4d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020008419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1020008419
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2938355492
Short name T773
Test name
Test status
Simulation time 76200556 ps
CPU time 7.06 seconds
Started Jul 30 05:24:50 PM PDT 24
Finished Jul 30 05:24:57 PM PDT 24
Peak memory 251068 kb
Host smart-bc655779-bcef-4af6-a32d-6dd98ea41e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938355492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2938355492
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1139559191
Short name T539
Test name
Test status
Simulation time 18552315977 ps
CPU time 157.69 seconds
Started Jul 30 05:24:49 PM PDT 24
Finished Jul 30 05:27:27 PM PDT 24
Peak memory 274164 kb
Host smart-fe68a998-5af7-44c5-904b-230a96740a34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139559191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1139559191
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2842284200
Short name T594
Test name
Test status
Simulation time 16440363994 ps
CPU time 348.61 seconds
Started Jul 30 05:24:53 PM PDT 24
Finished Jul 30 05:30:42 PM PDT 24
Peak memory 349536 kb
Host smart-11952082-356a-4be8-b33e-201b41fd79c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2842284200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2842284200
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4109077389
Short name T519
Test name
Test status
Simulation time 30290850 ps
CPU time 0.98 seconds
Started Jul 30 05:24:58 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 217868 kb
Host smart-a266bfd4-0f6d-4a6e-b371-1bad4acf0603
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109077389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4109077389
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1619621840
Short name T154
Test name
Test status
Simulation time 85469541 ps
CPU time 0.89 seconds
Started Jul 30 05:24:58 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 208756 kb
Host smart-cddf7376-8708-4ba0-a5da-dfb61153946b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619621840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1619621840
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2703704394
Short name T267
Test name
Test status
Simulation time 4301990993 ps
CPU time 15.24 seconds
Started Jul 30 05:24:55 PM PDT 24
Finished Jul 30 05:25:10 PM PDT 24
Peak memory 219132 kb
Host smart-7406a683-76c1-4fda-b2ac-13ff7a28b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703704394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2703704394
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1265033640
Short name T172
Test name
Test status
Simulation time 6919143691 ps
CPU time 5.17 seconds
Started Jul 30 05:24:56 PM PDT 24
Finished Jul 30 05:25:01 PM PDT 24
Peak memory 217880 kb
Host smart-0103e06a-36bc-4c73-b0cc-4f698ab82cd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265033640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1265033640
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4131767286
Short name T527
Test name
Test status
Simulation time 25791307 ps
CPU time 1.78 seconds
Started Jul 30 05:24:55 PM PDT 24
Finished Jul 30 05:24:57 PM PDT 24
Peak memory 218392 kb
Host smart-0bd50386-a4c0-4d05-9bff-d3cff67e38c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131767286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4131767286
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3237756517
Short name T84
Test name
Test status
Simulation time 175759234 ps
CPU time 8.31 seconds
Started Jul 30 05:24:58 PM PDT 24
Finished Jul 30 05:25:06 PM PDT 24
Peak memory 225592 kb
Host smart-37737ada-83fe-46fd-b62e-8960ccd3a265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237756517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3237756517
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3951362543
Short name T270
Test name
Test status
Simulation time 3652981627 ps
CPU time 13.06 seconds
Started Jul 30 05:24:55 PM PDT 24
Finished Jul 30 05:25:09 PM PDT 24
Peak memory 226224 kb
Host smart-ad90d719-b44a-4ba7-b067-8c10b0d2ecfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951362543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3951362543
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1251701928
Short name T53
Test name
Test status
Simulation time 618387512 ps
CPU time 11.67 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:16 PM PDT 24
Peak memory 226052 kb
Host smart-71504026-ce09-4a48-a29f-2d67e36b1433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251701928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1251701928
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3739910626
Short name T694
Test name
Test status
Simulation time 1079176806 ps
CPU time 11.6 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:16 PM PDT 24
Peak memory 226096 kb
Host smart-27b5c4ac-8a27-4e5d-978f-14a95019cd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739910626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3739910626
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3138926939
Short name T800
Test name
Test status
Simulation time 76469927 ps
CPU time 2.9 seconds
Started Jul 30 05:24:56 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 217792 kb
Host smart-ac4c5fe4-fd09-4bd2-8a03-19f2bd4ecf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138926939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3138926939
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2903329294
Short name T807
Test name
Test status
Simulation time 1190457526 ps
CPU time 32.01 seconds
Started Jul 30 05:24:55 PM PDT 24
Finished Jul 30 05:25:27 PM PDT 24
Peak memory 250932 kb
Host smart-c81b8eb1-74a9-4463-8b60-2c8014ab26d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903329294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2903329294
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4137816704
Short name T668
Test name
Test status
Simulation time 250657021 ps
CPU time 5.77 seconds
Started Jul 30 05:24:53 PM PDT 24
Finished Jul 30 05:24:59 PM PDT 24
Peak memory 246848 kb
Host smart-ee35e8e4-e889-4887-b930-3038f1680fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137816704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4137816704
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3192892206
Short name T353
Test name
Test status
Simulation time 1762647433 ps
CPU time 71.39 seconds
Started Jul 30 05:24:56 PM PDT 24
Finished Jul 30 05:26:08 PM PDT 24
Peak memory 267412 kb
Host smart-0b35f3cc-ec99-4278-aeff-e403d9393de7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192892206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3192892206
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3115254889
Short name T617
Test name
Test status
Simulation time 15612129 ps
CPU time 0.89 seconds
Started Jul 30 05:24:57 PM PDT 24
Finished Jul 30 05:24:58 PM PDT 24
Peak memory 213132 kb
Host smart-b64da048-c9f7-4817-8507-aa6abb8d76da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115254889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3115254889
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.757871258
Short name T80
Test name
Test status
Simulation time 29977391 ps
CPU time 0.93 seconds
Started Jul 30 05:25:01 PM PDT 24
Finished Jul 30 05:25:02 PM PDT 24
Peak memory 208948 kb
Host smart-bec29703-f328-4d8c-806d-19e002372d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757871258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.757871258
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.733219375
Short name T804
Test name
Test status
Simulation time 216884827 ps
CPU time 10.78 seconds
Started Jul 30 05:24:56 PM PDT 24
Finished Jul 30 05:25:07 PM PDT 24
Peak memory 218440 kb
Host smart-556775ad-8f31-4be2-b52d-ec0b1bbf6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733219375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.733219375
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.29328044
Short name T31
Test name
Test status
Simulation time 235176379 ps
CPU time 3.42 seconds
Started Jul 30 05:25:00 PM PDT 24
Finished Jul 30 05:25:03 PM PDT 24
Peak memory 217276 kb
Host smart-ee3d4561-0ae0-4765-81c3-d83602ebbcb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29328044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.29328044
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1847301270
Short name T723
Test name
Test status
Simulation time 154094944 ps
CPU time 2.29 seconds
Started Jul 30 05:24:55 PM PDT 24
Finished Jul 30 05:24:58 PM PDT 24
Peak memory 218320 kb
Host smart-d336e2ba-21ea-4bab-813c-6b7d75486227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847301270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1847301270
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1330300775
Short name T275
Test name
Test status
Simulation time 437787664 ps
CPU time 16.13 seconds
Started Jul 30 05:25:00 PM PDT 24
Finished Jul 30 05:25:17 PM PDT 24
Peak memory 226144 kb
Host smart-2cafbb57-604d-4061-be1a-fec9950b8d47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330300775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1330300775
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3565096701
Short name T132
Test name
Test status
Simulation time 212933687 ps
CPU time 9.82 seconds
Started Jul 30 05:24:58 PM PDT 24
Finished Jul 30 05:25:08 PM PDT 24
Peak memory 218332 kb
Host smart-ab795e14-38ab-4bc2-975f-4e81993a5d12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565096701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3565096701
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1023406614
Short name T759
Test name
Test status
Simulation time 1208513082 ps
CPU time 7.92 seconds
Started Jul 30 05:25:00 PM PDT 24
Finished Jul 30 05:25:08 PM PDT 24
Peak memory 218284 kb
Host smart-e680d966-66f0-457b-8cab-5d93662c2021
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023406614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1023406614
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.461580545
Short name T847
Test name
Test status
Simulation time 436612771 ps
CPU time 12.8 seconds
Started Jul 30 05:25:01 PM PDT 24
Finished Jul 30 05:25:14 PM PDT 24
Peak memory 218468 kb
Host smart-d4084bc3-c404-486d-a57c-9e9dadc4c66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461580545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.461580545
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3925169230
Short name T160
Test name
Test status
Simulation time 472147677 ps
CPU time 2.5 seconds
Started Jul 30 05:24:55 PM PDT 24
Finished Jul 30 05:24:58 PM PDT 24
Peak memory 214644 kb
Host smart-afd9e9c3-a2f4-4020-babd-c18992446e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925169230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3925169230
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1451092928
Short name T506
Test name
Test status
Simulation time 371633647 ps
CPU time 16.8 seconds
Started Jul 30 05:24:58 PM PDT 24
Finished Jul 30 05:25:15 PM PDT 24
Peak memory 250880 kb
Host smart-2e2419a3-b012-4614-bf5a-7cf10724aa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451092928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1451092928
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1782598358
Short name T336
Test name
Test status
Simulation time 73975105 ps
CPU time 8.88 seconds
Started Jul 30 05:24:56 PM PDT 24
Finished Jul 30 05:25:05 PM PDT 24
Peak memory 243504 kb
Host smart-f89c006e-df54-4efa-9af7-708f280c3732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782598358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1782598358
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.425517625
Short name T170
Test name
Test status
Simulation time 25105372622 ps
CPU time 175.62 seconds
Started Jul 30 05:25:00 PM PDT 24
Finished Jul 30 05:27:56 PM PDT 24
Peak memory 267476 kb
Host smart-bebf942f-47ce-43f9-9d4c-7325e6e4ff21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425517625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.425517625
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3741407511
Short name T211
Test name
Test status
Simulation time 12874900 ps
CPU time 1.01 seconds
Started Jul 30 05:24:55 PM PDT 24
Finished Jul 30 05:24:56 PM PDT 24
Peak memory 212040 kb
Host smart-76048e5e-a904-4961-a07c-fa6a87ae213b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741407511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3741407511
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.651215841
Short name T238
Test name
Test status
Simulation time 487349790 ps
CPU time 12.16 seconds
Started Jul 30 05:24:58 PM PDT 24
Finished Jul 30 05:25:10 PM PDT 24
Peak memory 226184 kb
Host smart-a801dc45-5b79-4f56-af33-8ba9e19a21b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651215841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.651215841
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2109264443
Short name T349
Test name
Test status
Simulation time 2189917776 ps
CPU time 7.18 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:12 PM PDT 24
Peak memory 217180 kb
Host smart-8571c02c-582d-4e06-950e-88d2ff5c79ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109264443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2109264443
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3828951889
Short name T653
Test name
Test status
Simulation time 322705648 ps
CPU time 2.54 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:07 PM PDT 24
Peak memory 218356 kb
Host smart-749898aa-dc28-4a03-be11-4ba84d6962bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828951889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3828951889
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3764323286
Short name T657
Test name
Test status
Simulation time 2748323209 ps
CPU time 17.87 seconds
Started Jul 30 05:25:00 PM PDT 24
Finished Jul 30 05:25:18 PM PDT 24
Peak memory 226272 kb
Host smart-919ba7e5-9de8-42bb-8092-079f52efda6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764323286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3764323286
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1104546047
Short name T230
Test name
Test status
Simulation time 564723058 ps
CPU time 8.49 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:14 PM PDT 24
Peak memory 218340 kb
Host smart-6f1abbf1-487e-4b24-8274-ab3fee2a2935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104546047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1104546047
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2450341215
Short name T341
Test name
Test status
Simulation time 789595881 ps
CPU time 15.11 seconds
Started Jul 30 05:25:03 PM PDT 24
Finished Jul 30 05:25:19 PM PDT 24
Peak memory 218292 kb
Host smart-0157720b-f756-4a35-8bf6-d3decf5ebbd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450341215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2450341215
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1548813707
Short name T50
Test name
Test status
Simulation time 292616697 ps
CPU time 11.73 seconds
Started Jul 30 05:24:58 PM PDT 24
Finished Jul 30 05:25:10 PM PDT 24
Peak memory 226212 kb
Host smart-0e3c7615-9b86-4b8b-9d9e-76f3ba119781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548813707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1548813707
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3731318229
Short name T54
Test name
Test status
Simulation time 376708454 ps
CPU time 2.35 seconds
Started Jul 30 05:24:59 PM PDT 24
Finished Jul 30 05:25:02 PM PDT 24
Peak memory 217904 kb
Host smart-159a5cc3-f059-4608-aff6-8cff9117e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731318229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3731318229
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2043006990
Short name T83
Test name
Test status
Simulation time 553496338 ps
CPU time 28.57 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:33 PM PDT 24
Peak memory 250940 kb
Host smart-d0496de0-4c8b-4036-9640-dcbe9a7540c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043006990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2043006990
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.4037658643
Short name T839
Test name
Test status
Simulation time 55666478 ps
CPU time 5.67 seconds
Started Jul 30 05:25:01 PM PDT 24
Finished Jul 30 05:25:07 PM PDT 24
Peak memory 247212 kb
Host smart-b314bce9-0e62-486d-ab73-1544350cd447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037658643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.4037658643
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3703317164
Short name T864
Test name
Test status
Simulation time 118295809267 ps
CPU time 108.41 seconds
Started Jul 30 05:25:04 PM PDT 24
Finished Jul 30 05:26:52 PM PDT 24
Peak memory 226264 kb
Host smart-fc5faa76-0635-4944-87bf-ee761864b3be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703317164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3703317164
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.4100028272
Short name T44
Test name
Test status
Simulation time 249295180457 ps
CPU time 2601.57 seconds
Started Jul 30 05:25:06 PM PDT 24
Finished Jul 30 06:08:28 PM PDT 24
Peak memory 660876 kb
Host smart-961277a8-22b1-43c9-9aa5-50f8a956186e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4100028272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.4100028272
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1745920731
Short name T627
Test name
Test status
Simulation time 41687384 ps
CPU time 0.84 seconds
Started Jul 30 05:25:00 PM PDT 24
Finished Jul 30 05:25:01 PM PDT 24
Peak memory 211972 kb
Host smart-905f4cdb-ba7a-41ab-aa02-b0264bf16d9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745920731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1745920731
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.996407534
Short name T547
Test name
Test status
Simulation time 14484160 ps
CPU time 1.05 seconds
Started Jul 30 05:25:07 PM PDT 24
Finished Jul 30 05:25:08 PM PDT 24
Peak memory 208928 kb
Host smart-00f6f2df-e642-42e1-9c05-1701d8b20365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996407534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.996407534
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3882466778
Short name T705
Test name
Test status
Simulation time 1668881459 ps
CPU time 11.55 seconds
Started Jul 30 05:25:02 PM PDT 24
Finished Jul 30 05:25:13 PM PDT 24
Peak memory 218340 kb
Host smart-09e827e3-5773-4944-bbeb-a567b93a305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882466778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3882466778
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1502936556
Short name T835
Test name
Test status
Simulation time 909039924 ps
CPU time 8.08 seconds
Started Jul 30 05:25:08 PM PDT 24
Finished Jul 30 05:25:16 PM PDT 24
Peak memory 217668 kb
Host smart-9d2b66b8-6418-43f0-aa82-129350f981f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502936556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1502936556
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.563364107
Short name T223
Test name
Test status
Simulation time 308215877 ps
CPU time 3.03 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:08 PM PDT 24
Peak memory 218424 kb
Host smart-9052b2fb-2bc8-4716-9c20-b0281cc2ebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563364107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.563364107
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.59392999
Short name T406
Test name
Test status
Simulation time 1535784908 ps
CPU time 14.85 seconds
Started Jul 30 05:25:11 PM PDT 24
Finished Jul 30 05:25:26 PM PDT 24
Peak memory 226168 kb
Host smart-eaffa030-9a42-4ba7-91ab-d0df1a85967d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59392999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.59392999
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.807962764
Short name T673
Test name
Test status
Simulation time 382358559 ps
CPU time 9.37 seconds
Started Jul 30 05:25:09 PM PDT 24
Finished Jul 30 05:25:18 PM PDT 24
Peak memory 218288 kb
Host smart-c3b1f9b1-42e1-4ade-9e6c-b9689209a776
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807962764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.807962764
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.553199427
Short name T248
Test name
Test status
Simulation time 299218893 ps
CPU time 11.75 seconds
Started Jul 30 05:25:09 PM PDT 24
Finished Jul 30 05:25:21 PM PDT 24
Peak memory 218292 kb
Host smart-85a91ab6-6056-409e-9a0c-e67225f04709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553199427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.553199427
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2965176982
Short name T734
Test name
Test status
Simulation time 1699547371 ps
CPU time 10.45 seconds
Started Jul 30 05:25:04 PM PDT 24
Finished Jul 30 05:25:15 PM PDT 24
Peak memory 218548 kb
Host smart-29900218-0d5b-43cb-9097-f10ada5906be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965176982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2965176982
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.116562194
Short name T563
Test name
Test status
Simulation time 26464554 ps
CPU time 1.14 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:06 PM PDT 24
Peak memory 217848 kb
Host smart-168b725c-2248-4a4b-a397-c1becff65ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116562194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.116562194
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.957832711
Short name T164
Test name
Test status
Simulation time 241525172 ps
CPU time 22.71 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:28 PM PDT 24
Peak memory 251044 kb
Host smart-6bf26a8a-dcc3-4c1c-b5fe-e516f7f8fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957832711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.957832711
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.569006765
Short name T534
Test name
Test status
Simulation time 102136354 ps
CPU time 5.42 seconds
Started Jul 30 05:25:05 PM PDT 24
Finished Jul 30 05:25:11 PM PDT 24
Peak memory 226596 kb
Host smart-43dc7574-096a-44f4-9266-740d10348e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569006765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.569006765
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2897104516
Short name T276
Test name
Test status
Simulation time 1384998671 ps
CPU time 67.14 seconds
Started Jul 30 05:25:09 PM PDT 24
Finished Jul 30 05:26:16 PM PDT 24
Peak memory 276092 kb
Host smart-dbd8e7ad-73b8-412e-8f81-c69ad7a7c54b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897104516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2897104516
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3550353151
Short name T385
Test name
Test status
Simulation time 27847159 ps
CPU time 1.02 seconds
Started Jul 30 05:22:14 PM PDT 24
Finished Jul 30 05:22:15 PM PDT 24
Peak memory 208404 kb
Host smart-80bf249c-c578-45de-962e-a0c7d5434f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550353151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3550353151
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1720405441
Short name T789
Test name
Test status
Simulation time 229600133 ps
CPU time 10.65 seconds
Started Jul 30 05:22:07 PM PDT 24
Finished Jul 30 05:22:17 PM PDT 24
Peak memory 218356 kb
Host smart-a6995240-30f2-4993-a5f6-0f27da2d4325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720405441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1720405441
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2203519016
Short name T608
Test name
Test status
Simulation time 1404443512 ps
CPU time 4.7 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:17 PM PDT 24
Peak memory 217340 kb
Host smart-a4505311-f0b3-4ef0-ab6f-df79661a3126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203519016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2203519016
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.845487138
Short name T140
Test name
Test status
Simulation time 1977318020 ps
CPU time 40.81 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:53 PM PDT 24
Peak memory 226148 kb
Host smart-9880e597-cdf3-4e3f-834f-3aa3aaf72dde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845487138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.845487138
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2588298547
Short name T210
Test name
Test status
Simulation time 721698307 ps
CPU time 16.93 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:22:28 PM PDT 24
Peak memory 217912 kb
Host smart-64d160ad-22e3-4c05-94a8-eaa79094f22f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588298547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
588298547
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1303323556
Short name T508
Test name
Test status
Simulation time 73466997 ps
CPU time 2.08 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:22:13 PM PDT 24
Peak memory 221944 kb
Host smart-81b9ab48-5f44-4daf-9301-ba8c1bb6f40c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303323556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1303323556
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1151028316
Short name T571
Test name
Test status
Simulation time 2870464289 ps
CPU time 21.1 seconds
Started Jul 30 05:22:13 PM PDT 24
Finished Jul 30 05:22:34 PM PDT 24
Peak memory 217776 kb
Host smart-23839705-eba5-4554-8ee5-360c4c18813f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151028316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1151028316
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.749182671
Short name T556
Test name
Test status
Simulation time 2203790599 ps
CPU time 7.52 seconds
Started Jul 30 05:22:08 PM PDT 24
Finished Jul 30 05:22:15 PM PDT 24
Peak memory 217836 kb
Host smart-7bcfef5f-640e-41f0-a2b0-72c6c823617e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749182671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.749182671
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4231664887
Short name T295
Test name
Test status
Simulation time 4004680289 ps
CPU time 60.28 seconds
Started Jul 30 05:22:08 PM PDT 24
Finished Jul 30 05:23:08 PM PDT 24
Peak memory 267480 kb
Host smart-3dfc5125-e27b-41d1-be37-71c1ba63dcc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231664887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.4231664887
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2016338591
Short name T216
Test name
Test status
Simulation time 2684804664 ps
CPU time 13.44 seconds
Started Jul 30 05:22:08 PM PDT 24
Finished Jul 30 05:22:21 PM PDT 24
Peak memory 251044 kb
Host smart-b790a022-3070-4139-bc79-8388248030af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016338591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2016338591
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3712416325
Short name T485
Test name
Test status
Simulation time 355942989 ps
CPU time 1.95 seconds
Started Jul 30 05:22:06 PM PDT 24
Finished Jul 30 05:22:08 PM PDT 24
Peak memory 222404 kb
Host smart-06cba298-531a-4132-b9bb-e2b6997fbf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712416325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3712416325
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.981738178
Short name T67
Test name
Test status
Simulation time 158141566 ps
CPU time 10.94 seconds
Started Jul 30 05:22:07 PM PDT 24
Finished Jul 30 05:22:18 PM PDT 24
Peak memory 214620 kb
Host smart-a0a4d763-e0e6-4742-9dff-81c456d408ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981738178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.981738178
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2822349859
Short name T294
Test name
Test status
Simulation time 863199632 ps
CPU time 14.44 seconds
Started Jul 30 05:22:14 PM PDT 24
Finished Jul 30 05:22:28 PM PDT 24
Peak memory 225816 kb
Host smart-428790ae-123b-4ec9-b66d-73fa35c6a9e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822349859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2822349859
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3023984467
Short name T260
Test name
Test status
Simulation time 2824327433 ps
CPU time 9.56 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:22 PM PDT 24
Peak memory 226220 kb
Host smart-b51641f9-f33d-48c2-81ea-88784988e45d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023984467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3023984467
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1854205447
Short name T602
Test name
Test status
Simulation time 1082159482 ps
CPU time 10.03 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:22 PM PDT 24
Peak memory 225984 kb
Host smart-a20e18f0-8629-4b1d-8183-cce9a2a0a86a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854205447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
854205447
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1342431439
Short name T664
Test name
Test status
Simulation time 417358467 ps
CPU time 15.47 seconds
Started Jul 30 05:22:10 PM PDT 24
Finished Jul 30 05:22:25 PM PDT 24
Peak memory 226204 kb
Host smart-73875df0-a719-4fe9-8bd1-e95152af50e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342431439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1342431439
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3740942650
Short name T799
Test name
Test status
Simulation time 145875264 ps
CPU time 2.96 seconds
Started Jul 30 05:22:07 PM PDT 24
Finished Jul 30 05:22:10 PM PDT 24
Peak memory 217808 kb
Host smart-71d2ee9a-44a0-45bc-88bb-ed5215fa2d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740942650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3740942650
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1795554906
Short name T803
Test name
Test status
Simulation time 2091655196 ps
CPU time 25.76 seconds
Started Jul 30 05:22:07 PM PDT 24
Finished Jul 30 05:22:33 PM PDT 24
Peak memory 247516 kb
Host smart-5253f260-6b60-4e92-98fa-38598c719d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795554906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1795554906
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2579038542
Short name T639
Test name
Test status
Simulation time 218614158 ps
CPU time 3.23 seconds
Started Jul 30 05:22:05 PM PDT 24
Finished Jul 30 05:22:09 PM PDT 24
Peak memory 222388 kb
Host smart-cec6a813-66c0-4e43-9c55-c71801d09a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579038542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2579038542
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2317904861
Short name T647
Test name
Test status
Simulation time 15377838730 ps
CPU time 167 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:24:58 PM PDT 24
Peak memory 370256 kb
Host smart-4c0db280-705d-42c3-9764-ab9a0db813eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317904861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2317904861
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.244109953
Short name T167
Test name
Test status
Simulation time 103855218 ps
CPU time 1.1 seconds
Started Jul 30 05:22:09 PM PDT 24
Finished Jul 30 05:22:10 PM PDT 24
Peak memory 217808 kb
Host smart-bc06f81b-d42b-46ce-8adf-a30217bf8183
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244109953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.244109953
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1723553805
Short name T845
Test name
Test status
Simulation time 18502011 ps
CPU time 1.12 seconds
Started Jul 30 05:22:21 PM PDT 24
Finished Jul 30 05:22:22 PM PDT 24
Peak memory 209176 kb
Host smart-125cd697-28ac-4a8b-b19b-e1ca0eee60be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723553805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1723553805
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3488373077
Short name T196
Test name
Test status
Simulation time 32027371 ps
CPU time 0.84 seconds
Started Jul 30 05:22:10 PM PDT 24
Finished Jul 30 05:22:10 PM PDT 24
Peak memory 209228 kb
Host smart-f18f4100-44ef-46d6-9336-6aba81763a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488373077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3488373077
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.467856109
Short name T437
Test name
Test status
Simulation time 3850339802 ps
CPU time 25.56 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:22:37 PM PDT 24
Peak memory 219136 kb
Host smart-b8d41e5e-8a92-46a1-b38f-29858cd8877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467856109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.467856109
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1986918514
Short name T433
Test name
Test status
Simulation time 2847908566 ps
CPU time 17.46 seconds
Started Jul 30 05:22:20 PM PDT 24
Finished Jul 30 05:22:37 PM PDT 24
Peak memory 217692 kb
Host smart-c9404cd7-2729-4c6e-b518-ab504b389bb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986918514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1986918514
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1800182370
Short name T359
Test name
Test status
Simulation time 1301323560 ps
CPU time 22.4 seconds
Started Jul 30 05:22:16 PM PDT 24
Finished Jul 30 05:22:38 PM PDT 24
Peak memory 226136 kb
Host smart-ff3ae8a9-4d82-4b35-ae86-535cc5ea5652
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800182370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1800182370
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.741775560
Short name T60
Test name
Test status
Simulation time 15835886178 ps
CPU time 26.88 seconds
Started Jul 30 05:22:15 PM PDT 24
Finished Jul 30 05:22:42 PM PDT 24
Peak memory 217948 kb
Host smart-28553473-0bf7-418a-8513-c9d679b32131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741775560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.741775560
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4168628756
Short name T604
Test name
Test status
Simulation time 315980841 ps
CPU time 6.84 seconds
Started Jul 30 05:22:13 PM PDT 24
Finished Jul 30 05:22:20 PM PDT 24
Peak memory 218316 kb
Host smart-078b2b88-a3e2-49aa-b5c0-51ad37d95630
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168628756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4168628756
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1145411583
Short name T605
Test name
Test status
Simulation time 3244645507 ps
CPU time 22.35 seconds
Started Jul 30 05:22:14 PM PDT 24
Finished Jul 30 05:22:37 PM PDT 24
Peak memory 217836 kb
Host smart-48796673-4e54-4d6f-b185-aa43c2e182b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145411583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1145411583
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2408519270
Short name T202
Test name
Test status
Simulation time 2606458158 ps
CPU time 16.48 seconds
Started Jul 30 05:22:18 PM PDT 24
Finished Jul 30 05:22:34 PM PDT 24
Peak memory 217824 kb
Host smart-cf671584-c594-4fb4-89c3-744c0181967a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408519270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2408519270
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1949405560
Short name T29
Test name
Test status
Simulation time 25726100321 ps
CPU time 101.16 seconds
Started Jul 30 05:22:16 PM PDT 24
Finished Jul 30 05:23:57 PM PDT 24
Peak memory 282324 kb
Host smart-c2080310-6494-440f-b1b0-7685e35bea05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949405560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1949405560
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2359126621
Short name T679
Test name
Test status
Simulation time 510912282 ps
CPU time 12.77 seconds
Started Jul 30 05:22:15 PM PDT 24
Finished Jul 30 05:22:28 PM PDT 24
Peak memory 250992 kb
Host smart-5e3a4083-ad91-40e0-b98e-7fb07209689b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359126621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2359126621
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2826533381
Short name T286
Test name
Test status
Simulation time 125666526 ps
CPU time 1.82 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:14 PM PDT 24
Peak memory 218372 kb
Host smart-47546a86-4a9f-4333-bff9-ff9cc74bd19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826533381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2826533381
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3854894947
Short name T643
Test name
Test status
Simulation time 1149086431 ps
CPU time 9.22 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:21 PM PDT 24
Peak memory 214248 kb
Host smart-3745a5f7-c00c-44b8-8fc4-159e25a2f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854894947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3854894947
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1482227667
Short name T436
Test name
Test status
Simulation time 925181274 ps
CPU time 13.73 seconds
Started Jul 30 05:22:17 PM PDT 24
Finished Jul 30 05:22:31 PM PDT 24
Peak memory 226280 kb
Host smart-8c545a78-b12b-497d-acea-d0d9c2e1e0cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482227667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1482227667
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1396401792
Short name T816
Test name
Test status
Simulation time 3938757143 ps
CPU time 23.98 seconds
Started Jul 30 05:22:16 PM PDT 24
Finished Jul 30 05:22:40 PM PDT 24
Peak memory 226276 kb
Host smart-f19f79c6-4dc6-4c03-8653-1e3989598575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396401792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1396401792
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.936500850
Short name T680
Test name
Test status
Simulation time 249508133 ps
CPU time 7.07 seconds
Started Jul 30 05:22:19 PM PDT 24
Finished Jul 30 05:22:26 PM PDT 24
Peak memory 218348 kb
Host smart-746aa0fb-4d9b-40c1-b3c5-f4ee2b40eb41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936500850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.936500850
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.727905350
Short name T285
Test name
Test status
Simulation time 950543548 ps
CPU time 7.38 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:22:18 PM PDT 24
Peak memory 226264 kb
Host smart-81caa6fe-7437-4c66-b1ce-b3dec01d4420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727905350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.727905350
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.731140370
Short name T784
Test name
Test status
Simulation time 221766956 ps
CPU time 4.19 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:22:15 PM PDT 24
Peak memory 215400 kb
Host smart-b8972751-b158-4569-bd72-ba6a9cec042b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731140370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.731140370
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1061168675
Short name T305
Test name
Test status
Simulation time 1249846859 ps
CPU time 25.97 seconds
Started Jul 30 05:22:11 PM PDT 24
Finished Jul 30 05:22:37 PM PDT 24
Peak memory 251040 kb
Host smart-dfcdc6c6-d3d8-4b29-9095-a5564108c5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061168675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1061168675
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3561170228
Short name T501
Test name
Test status
Simulation time 78471944 ps
CPU time 6.37 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:18 PM PDT 24
Peak memory 250508 kb
Host smart-43653fc0-6e19-4ee2-b319-b847b945fe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561170228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3561170228
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2497004625
Short name T814
Test name
Test status
Simulation time 3634318519 ps
CPU time 99.98 seconds
Started Jul 30 05:22:18 PM PDT 24
Finished Jul 30 05:23:58 PM PDT 24
Peak memory 280168 kb
Host smart-f2171f66-64fe-4cf8-8d92-b803a5ab10f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497004625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2497004625
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3672032705
Short name T662
Test name
Test status
Simulation time 38765837 ps
CPU time 0.89 seconds
Started Jul 30 05:22:12 PM PDT 24
Finished Jul 30 05:22:13 PM PDT 24
Peak memory 213076 kb
Host smart-0e33d901-4289-4872-86d5-58128fa6bae5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672032705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3672032705
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1878668526
Short name T684
Test name
Test status
Simulation time 73332504 ps
CPU time 1.09 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:22:26 PM PDT 24
Peak memory 209136 kb
Host smart-120ff356-440b-45ff-afed-c928c956ddec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878668526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1878668526
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1498821247
Short name T70
Test name
Test status
Simulation time 13095565 ps
CPU time 1.04 seconds
Started Jul 30 05:22:20 PM PDT 24
Finished Jul 30 05:22:21 PM PDT 24
Peak memory 208968 kb
Host smart-467ec098-e623-4c10-b9a0-9f5ba1b28aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498821247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1498821247
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1551095841
Short name T801
Test name
Test status
Simulation time 254488069 ps
CPU time 12.41 seconds
Started Jul 30 05:22:19 PM PDT 24
Finished Jul 30 05:22:32 PM PDT 24
Peak memory 226184 kb
Host smart-8b3cf112-cef9-46cf-8543-2f439f50bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551095841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1551095841
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4106995768
Short name T175
Test name
Test status
Simulation time 483450737 ps
CPU time 12.37 seconds
Started Jul 30 05:22:26 PM PDT 24
Finished Jul 30 05:22:39 PM PDT 24
Peak memory 217532 kb
Host smart-60a18287-4987-4c5f-a4c0-26a102a02e93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106995768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4106995768
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.121963223
Short name T610
Test name
Test status
Simulation time 10497605483 ps
CPU time 30.48 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:22:56 PM PDT 24
Peak memory 218888 kb
Host smart-7cd46c66-3c6a-4bcc-aaa8-160b612b7217
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121963223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.121963223
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2027976816
Short name T27
Test name
Test status
Simulation time 158253678 ps
CPU time 5.22 seconds
Started Jul 30 05:22:24 PM PDT 24
Finished Jul 30 05:22:29 PM PDT 24
Peak memory 217644 kb
Host smart-8a3c755a-7278-474a-b429-d918223d984c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027976816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
027976816
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1187677802
Short name T232
Test name
Test status
Simulation time 1999708927 ps
CPU time 6.64 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:22:31 PM PDT 24
Peak memory 218324 kb
Host smart-5a48214f-66df-4e39-ada9-b573fce7bddb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187677802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1187677802
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.246410778
Short name T221
Test name
Test status
Simulation time 1172930878 ps
CPU time 18.15 seconds
Started Jul 30 05:22:24 PM PDT 24
Finished Jul 30 05:22:42 PM PDT 24
Peak memory 217820 kb
Host smart-03f8278b-a9de-4f23-bcdb-2b4b8b844a8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246410778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.246410778
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2059255296
Short name T141
Test name
Test status
Simulation time 772054978 ps
CPU time 9.51 seconds
Started Jul 30 05:22:21 PM PDT 24
Finished Jul 30 05:22:30 PM PDT 24
Peak memory 217776 kb
Host smart-0fb70a24-15d7-4336-9e1b-1fa840cfb81a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059255296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2059255296
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.752801733
Short name T274
Test name
Test status
Simulation time 3606896059 ps
CPU time 82.42 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:23:48 PM PDT 24
Peak memory 283828 kb
Host smart-68b13351-797e-4f54-bc00-4a41198bb614
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752801733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.752801733
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.222061244
Short name T821
Test name
Test status
Simulation time 2057320548 ps
CPU time 30.53 seconds
Started Jul 30 05:22:18 PM PDT 24
Finished Jul 30 05:22:49 PM PDT 24
Peak memory 250900 kb
Host smart-a070d201-949f-4d43-86af-11b9e67fb791
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222061244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.222061244
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2846197908
Short name T381
Test name
Test status
Simulation time 51260500 ps
CPU time 2.34 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:22:27 PM PDT 24
Peak memory 218368 kb
Host smart-87a341f9-a80c-4533-9dda-ac3f4434b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846197908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2846197908
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2851705665
Short name T603
Test name
Test status
Simulation time 684508204 ps
CPU time 13.3 seconds
Started Jul 30 05:22:27 PM PDT 24
Finished Jul 30 05:22:40 PM PDT 24
Peak memory 217840 kb
Host smart-e28e357d-591b-4141-9acf-abb04b7b070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851705665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2851705665
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3354925247
Short name T266
Test name
Test status
Simulation time 1867126742 ps
CPU time 14.05 seconds
Started Jul 30 05:22:24 PM PDT 24
Finished Jul 30 05:22:38 PM PDT 24
Peak memory 226224 kb
Host smart-42820606-ccb5-40da-8d7e-eb83d5ee2b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354925247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3354925247
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.836878025
Short name T162
Test name
Test status
Simulation time 822361842 ps
CPU time 8.68 seconds
Started Jul 30 05:22:26 PM PDT 24
Finished Jul 30 05:22:35 PM PDT 24
Peak memory 218336 kb
Host smart-e7244f61-1356-4d32-89c7-72e4cefe51ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836878025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.836878025
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3021775765
Short name T481
Test name
Test status
Simulation time 928377575 ps
CPU time 16.06 seconds
Started Jul 30 05:22:28 PM PDT 24
Finished Jul 30 05:22:44 PM PDT 24
Peak memory 218348 kb
Host smart-d4d09909-9e63-49af-ae44-07c113f0ba13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021775765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
021775765
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1517844861
Short name T325
Test name
Test status
Simulation time 215035852 ps
CPU time 8.81 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:22:34 PM PDT 24
Peak memory 225956 kb
Host smart-3d793b7d-da59-498a-a396-036484da90ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517844861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1517844861
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.213745517
Short name T376
Test name
Test status
Simulation time 82493428 ps
CPU time 1.4 seconds
Started Jul 30 05:22:18 PM PDT 24
Finished Jul 30 05:22:19 PM PDT 24
Peak memory 213864 kb
Host smart-a2a77d73-b9ae-42a0-8b78-a7da0881e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213745517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.213745517
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.718534146
Short name T382
Test name
Test status
Simulation time 1136876929 ps
CPU time 30.23 seconds
Started Jul 30 05:22:22 PM PDT 24
Finished Jul 30 05:22:53 PM PDT 24
Peak memory 251052 kb
Host smart-f70efe8d-b9aa-4e00-9a0b-83b6013ceca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718534146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.718534146
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1992458273
Short name T30
Test name
Test status
Simulation time 250278813 ps
CPU time 9.56 seconds
Started Jul 30 05:22:21 PM PDT 24
Finished Jul 30 05:22:31 PM PDT 24
Peak memory 251024 kb
Host smart-9c7fc88f-2a3d-49ef-97fb-7a012ea69a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992458273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1992458273
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3358006178
Short name T862
Test name
Test status
Simulation time 1229621304 ps
CPU time 22.62 seconds
Started Jul 30 05:22:27 PM PDT 24
Finished Jul 30 05:22:50 PM PDT 24
Peak memory 251204 kb
Host smart-a78937b5-1000-4339-adf5-cc8b19d4aee4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358006178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3358006178
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2082818392
Short name T470
Test name
Test status
Simulation time 11636880 ps
CPU time 1.04 seconds
Started Jul 30 05:22:19 PM PDT 24
Finished Jul 30 05:22:20 PM PDT 24
Peak memory 212048 kb
Host smart-3691dece-8730-4964-aea6-6e1fa4d0add8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082818392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2082818392
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.435266850
Short name T448
Test name
Test status
Simulation time 24266109 ps
CPU time 0.91 seconds
Started Jul 30 05:22:28 PM PDT 24
Finished Jul 30 05:22:29 PM PDT 24
Peak memory 208972 kb
Host smart-5c791899-840a-45b5-8331-79bd82cd76a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435266850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.435266850
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.679197590
Short name T197
Test name
Test status
Simulation time 10882260 ps
CPU time 0.89 seconds
Started Jul 30 05:22:26 PM PDT 24
Finished Jul 30 05:22:27 PM PDT 24
Peak memory 208912 kb
Host smart-6f1ab79b-ec55-49be-bfcb-a715ea47e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679197590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.679197590
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3104132489
Short name T461
Test name
Test status
Simulation time 1613864308 ps
CPU time 16.08 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:22:41 PM PDT 24
Peak memory 218412 kb
Host smart-eed721aa-f4de-4016-a995-1d7140cb8329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104132489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3104132489
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2798696513
Short name T409
Test name
Test status
Simulation time 3245167525 ps
CPU time 5.71 seconds
Started Jul 30 05:22:30 PM PDT 24
Finished Jul 30 05:22:36 PM PDT 24
Peak memory 217868 kb
Host smart-333fbd58-9b7d-4441-99dc-c2c6df871157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798696513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2798696513
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.4230699828
Short name T542
Test name
Test status
Simulation time 4290661032 ps
CPU time 115.51 seconds
Started Jul 30 05:22:30 PM PDT 24
Finished Jul 30 05:24:26 PM PDT 24
Peak memory 219180 kb
Host smart-ebeea845-abab-4279-8ed7-ac24224e6f42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230699828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.4230699828
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2839881852
Short name T511
Test name
Test status
Simulation time 934057993 ps
CPU time 10.44 seconds
Started Jul 30 05:22:31 PM PDT 24
Finished Jul 30 05:22:41 PM PDT 24
Peak memory 217848 kb
Host smart-bf6dae88-0137-408a-adc1-d846fdf8c652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839881852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
839881852
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.169096156
Short name T710
Test name
Test status
Simulation time 643172228 ps
CPU time 9.4 seconds
Started Jul 30 05:22:28 PM PDT 24
Finished Jul 30 05:22:38 PM PDT 24
Peak memory 218252 kb
Host smart-9d73438a-2338-4493-99ff-4ad24ae04ceb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169096156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.169096156
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4196552250
Short name T580
Test name
Test status
Simulation time 1019568963 ps
CPU time 31.27 seconds
Started Jul 30 05:22:28 PM PDT 24
Finished Jul 30 05:22:59 PM PDT 24
Peak memory 217780 kb
Host smart-f3eb388e-de35-4b8b-a341-776754c793ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196552250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4196552250
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3628558661
Short name T439
Test name
Test status
Simulation time 2931499550 ps
CPU time 20.02 seconds
Started Jul 30 05:22:27 PM PDT 24
Finished Jul 30 05:22:47 PM PDT 24
Peak memory 217860 kb
Host smart-ef1f8529-9f69-46a3-a0e4-fee1fcaebd09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628558661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3628558661
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.324482180
Short name T388
Test name
Test status
Simulation time 2162714418 ps
CPU time 78.83 seconds
Started Jul 30 05:22:29 PM PDT 24
Finished Jul 30 05:23:48 PM PDT 24
Peak memory 279124 kb
Host smart-529e419a-21d0-4bc1-9548-e5df99e0dd02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324482180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.324482180
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3493893596
Short name T239
Test name
Test status
Simulation time 5506287996 ps
CPU time 16.83 seconds
Started Jul 30 05:22:29 PM PDT 24
Finished Jul 30 05:22:46 PM PDT 24
Peak memory 249376 kb
Host smart-f5108b3e-35eb-48db-bb8e-8ec8e6b20db0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493893596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3493893596
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2047507909
Short name T75
Test name
Test status
Simulation time 65195594 ps
CPU time 3.55 seconds
Started Jul 30 05:22:24 PM PDT 24
Finished Jul 30 05:22:28 PM PDT 24
Peak memory 218416 kb
Host smart-d07140fa-6e72-4bab-b115-527a3dc4a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047507909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2047507909
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2596824034
Short name T416
Test name
Test status
Simulation time 250500960 ps
CPU time 6.83 seconds
Started Jul 30 05:22:23 PM PDT 24
Finished Jul 30 05:22:30 PM PDT 24
Peak memory 217828 kb
Host smart-7a59a0b2-3e12-4534-a1d6-c21a3698ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596824034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2596824034
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3072797161
Short name T242
Test name
Test status
Simulation time 410304792 ps
CPU time 8.17 seconds
Started Jul 30 05:22:29 PM PDT 24
Finished Jul 30 05:22:37 PM PDT 24
Peak memory 226236 kb
Host smart-72d2aced-01f2-4e4c-9907-72818d913243
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072797161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3072797161
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2041047503
Short name T780
Test name
Test status
Simulation time 373626803 ps
CPU time 8.85 seconds
Started Jul 30 05:22:28 PM PDT 24
Finished Jul 30 05:22:37 PM PDT 24
Peak memory 226120 kb
Host smart-54b024d1-90b7-4d9b-8a2e-3b77a200cea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041047503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2041047503
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1668361086
Short name T641
Test name
Test status
Simulation time 1447945968 ps
CPU time 16.54 seconds
Started Jul 30 05:22:31 PM PDT 24
Finished Jul 30 05:22:48 PM PDT 24
Peak memory 218344 kb
Host smart-aecaed5e-6dc2-4997-b0c5-ad194963186d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668361086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
668361086
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2134006842
Short name T450
Test name
Test status
Simulation time 384127078 ps
CPU time 9.53 seconds
Started Jul 30 05:22:24 PM PDT 24
Finished Jul 30 05:22:34 PM PDT 24
Peak memory 218496 kb
Host smart-63db3e87-8f7d-430c-81de-9ab9b15a3d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134006842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2134006842
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2099233684
Short name T851
Test name
Test status
Simulation time 37556886 ps
CPU time 1.58 seconds
Started Jul 30 05:22:25 PM PDT 24
Finished Jul 30 05:22:26 PM PDT 24
Peak memory 213996 kb
Host smart-813a7713-e8e4-4d79-8cf8-ecda3dbff004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099233684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2099233684
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3716032753
Short name T367
Test name
Test status
Simulation time 439166750 ps
CPU time 26.29 seconds
Started Jul 30 05:22:27 PM PDT 24
Finished Jul 30 05:22:53 PM PDT 24
Peak memory 251028 kb
Host smart-3926b0ca-8199-4f8a-8a27-8d0d9d049193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716032753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3716032753
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3840273122
Short name T265
Test name
Test status
Simulation time 887785154 ps
CPU time 9.13 seconds
Started Jul 30 05:22:26 PM PDT 24
Finished Jul 30 05:22:35 PM PDT 24
Peak memory 251008 kb
Host smart-211bcaa3-a1a9-4a13-9461-d876990b4f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840273122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3840273122
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3459319883
Short name T732
Test name
Test status
Simulation time 16470763672 ps
CPU time 170.61 seconds
Started Jul 30 05:22:29 PM PDT 24
Finished Jul 30 05:25:20 PM PDT 24
Peak memory 267560 kb
Host smart-fb3ad4a8-da5a-481c-8174-acec9a9423e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459319883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3459319883
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.4180749087
Short name T163
Test name
Test status
Simulation time 66006967 ps
CPU time 1.01 seconds
Started Jul 30 05:22:23 PM PDT 24
Finished Jul 30 05:22:24 PM PDT 24
Peak memory 218036 kb
Host smart-c1accd1c-b635-44da-b7b6-f2ba72977dff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180749087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.4180749087
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2749831011
Short name T536
Test name
Test status
Simulation time 32394841 ps
CPU time 1.01 seconds
Started Jul 30 05:22:37 PM PDT 24
Finished Jul 30 05:22:39 PM PDT 24
Peak memory 209024 kb
Host smart-14aaa052-5dc1-409f-8561-766356e4b022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749831011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2749831011
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.452728994
Short name T289
Test name
Test status
Simulation time 13325819 ps
CPU time 0.94 seconds
Started Jul 30 05:22:34 PM PDT 24
Finished Jul 30 05:22:35 PM PDT 24
Peak memory 208816 kb
Host smart-b9f357d0-0519-4cb3-9313-206176b6ba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452728994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.452728994
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1537517595
Short name T369
Test name
Test status
Simulation time 963434081 ps
CPU time 11.16 seconds
Started Jul 30 05:22:35 PM PDT 24
Finished Jul 30 05:22:46 PM PDT 24
Peak memory 218404 kb
Host smart-fb4d77d4-eca7-45d7-9c05-26a560259bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537517595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1537517595
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.194481699
Short name T558
Test name
Test status
Simulation time 1393942503 ps
CPU time 9.89 seconds
Started Jul 30 05:22:37 PM PDT 24
Finished Jul 30 05:22:47 PM PDT 24
Peak memory 217408 kb
Host smart-c0ca0f65-bc54-41f1-b9eb-daadb4e4c6b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194481699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.194481699
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1932086790
Short name T407
Test name
Test status
Simulation time 1949132951 ps
CPU time 36.69 seconds
Started Jul 30 05:22:33 PM PDT 24
Finished Jul 30 05:23:10 PM PDT 24
Peak memory 218384 kb
Host smart-54d7dcfe-57d2-4ac9-b007-2084e298358b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932086790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1932086790
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.4260236074
Short name T648
Test name
Test status
Simulation time 117168513 ps
CPU time 3.73 seconds
Started Jul 30 05:22:37 PM PDT 24
Finished Jul 30 05:22:41 PM PDT 24
Peak memory 217864 kb
Host smart-30b9c7d1-0fb3-48cd-a18c-c3481d9bb3e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260236074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.4
260236074
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1318929491
Short name T291
Test name
Test status
Simulation time 78979253 ps
CPU time 3.13 seconds
Started Jul 30 05:22:33 PM PDT 24
Finished Jul 30 05:22:36 PM PDT 24
Peak memory 218312 kb
Host smart-3721eefb-e2f9-474a-8aeb-439575d1cf09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318929491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1318929491
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1554785786
Short name T71
Test name
Test status
Simulation time 1559746898 ps
CPU time 39.56 seconds
Started Jul 30 05:22:34 PM PDT 24
Finished Jul 30 05:23:14 PM PDT 24
Peak memory 217756 kb
Host smart-8d03b225-659f-4576-8ad7-98701a95a922
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554785786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1554785786
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.446873993
Short name T574
Test name
Test status
Simulation time 626225542 ps
CPU time 5.95 seconds
Started Jul 30 05:22:35 PM PDT 24
Finished Jul 30 05:22:41 PM PDT 24
Peak memory 217728 kb
Host smart-a25b9a6e-54ca-4334-b22e-cb31136aa0c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446873993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.446873993
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1163306751
Short name T306
Test name
Test status
Simulation time 3637797020 ps
CPU time 65.48 seconds
Started Jul 30 05:22:34 PM PDT 24
Finished Jul 30 05:23:39 PM PDT 24
Peak memory 253516 kb
Host smart-0731752e-b708-4ff1-a47d-aad27ec01f93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163306751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1163306751
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1289292411
Short name T338
Test name
Test status
Simulation time 1499603031 ps
CPU time 13.3 seconds
Started Jul 30 05:22:34 PM PDT 24
Finished Jul 30 05:22:48 PM PDT 24
Peak memory 250992 kb
Host smart-c064799b-d8f6-4545-861b-1af810cf6332
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289292411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1289292411
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.791346757
Short name T166
Test name
Test status
Simulation time 1790654857 ps
CPU time 3.3 seconds
Started Jul 30 05:22:36 PM PDT 24
Finished Jul 30 05:22:40 PM PDT 24
Peak memory 218380 kb
Host smart-a70add90-6e34-4d2a-80e5-aa1a8022ef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791346757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.791346757
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1281682011
Short name T690
Test name
Test status
Simulation time 263697611 ps
CPU time 13.77 seconds
Started Jul 30 05:22:36 PM PDT 24
Finished Jul 30 05:22:50 PM PDT 24
Peak memory 217856 kb
Host smart-96da8d91-b2a7-4845-ba39-b9db660b02f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281682011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1281682011
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.308018072
Short name T753
Test name
Test status
Simulation time 552798098 ps
CPU time 14.48 seconds
Started Jul 30 05:22:38 PM PDT 24
Finished Jul 30 05:22:52 PM PDT 24
Peak memory 226176 kb
Host smart-da5a68fc-a659-4e60-837c-1db2160677f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308018072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.308018072
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.4120731430
Short name T243
Test name
Test status
Simulation time 183992105 ps
CPU time 8.07 seconds
Started Jul 30 05:22:37 PM PDT 24
Finished Jul 30 05:22:45 PM PDT 24
Peak memory 218320 kb
Host smart-31a703df-3a1e-44a5-bd16-f8da07257505
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120731430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.4120731430
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2714461686
Short name T809
Test name
Test status
Simulation time 675087428 ps
CPU time 13.27 seconds
Started Jul 30 05:22:38 PM PDT 24
Finished Jul 30 05:22:52 PM PDT 24
Peak memory 226128 kb
Host smart-6383c314-d778-40c9-9a64-44f6c369bc36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714461686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
714461686
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2642860713
Short name T782
Test name
Test status
Simulation time 258737858 ps
CPU time 7.66 seconds
Started Jul 30 05:22:36 PM PDT 24
Finished Jul 30 05:22:44 PM PDT 24
Peak memory 225052 kb
Host smart-e9d9b88a-fb90-48b7-8f6c-ab65c0fe937d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642860713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2642860713
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1176408304
Short name T288
Test name
Test status
Simulation time 331145811 ps
CPU time 5.16 seconds
Started Jul 30 05:22:27 PM PDT 24
Finished Jul 30 05:22:32 PM PDT 24
Peak memory 217756 kb
Host smart-8edb5838-a2c1-4f96-a7b0-cd642eed29a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176408304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1176408304
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1658275383
Short name T525
Test name
Test status
Simulation time 871825962 ps
CPU time 26.28 seconds
Started Jul 30 05:22:28 PM PDT 24
Finished Jul 30 05:22:55 PM PDT 24
Peak memory 250928 kb
Host smart-958bf75e-d785-4efd-af69-a589c2a70718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658275383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1658275383
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1693971804
Short name T142
Test name
Test status
Simulation time 170293114 ps
CPU time 4.67 seconds
Started Jul 30 05:22:33 PM PDT 24
Finished Jul 30 05:22:38 PM PDT 24
Peak memory 222768 kb
Host smart-f31de68b-b271-4212-9c5f-c287b81edda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693971804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1693971804
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.368771713
Short name T577
Test name
Test status
Simulation time 5111620494 ps
CPU time 96.58 seconds
Started Jul 30 05:22:41 PM PDT 24
Finished Jul 30 05:24:17 PM PDT 24
Peak memory 280508 kb
Host smart-a508075d-9dcc-46e9-a08e-43fe7b824d68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368771713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.368771713
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.478215951
Short name T268
Test name
Test status
Simulation time 14007565 ps
CPU time 0.95 seconds
Started Jul 30 05:22:30 PM PDT 24
Finished Jul 30 05:22:31 PM PDT 24
Peak memory 212220 kb
Host smart-217bf0ef-4a65-437a-b044-d5c04f0e7564
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478215951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.478215951
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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