Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1433677	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1652021

1

T1

1040

T2

222

T3

834

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2747610	1			T1	1278		T2	193		T3	1404
values[0x0]	168818	1			T1	242		T2	79		T3	76
values[0x1]	169270	1			T1	214		T2	82		T3	91

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1138056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1947642

1

T1

1179

T2

249

T3

985

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9752	1			T1	10		T3	2		T8	28
valid_sources[0x01]	10731	1			T1	10		T3	4		T8	27
valid_sources[0x02]	11262	1			T1	14		T3	10		T8	24
valid_sources[0x03]	21439	1			T1	8		T3	5		T5	17
valid_sources[0x04]	13536	1			T1	12		T3	4		T8	34
valid_sources[0x05]	9922	1			T1	5		T3	9		T8	12
valid_sources[0x06]	9773	1			T1	7		T3	7		T8	9
valid_sources[0x07]	12242	1			T1	9		T3	2		T8	29
valid_sources[0x08]	10117	1			T1	5		T3	10		T5	17
valid_sources[0x09]	69183	1			T1	6		T3	8		T5	59207
valid_sources[0x0a]	9764	1			T1	6		T3	5		T8	31
valid_sources[0x0b]	11558	1			T1	7		T3	7		T8	36
valid_sources[0x0c]	11836	1			T1	10		T3	5		T8	15
valid_sources[0x0d]	9863	1			T1	9		T2	1		T3	5
valid_sources[0x0e]	10953	1			T1	7		T3	8		T5	1037
valid_sources[0x0f]	16601	1			T1	2		T2	21		T3	6
valid_sources[0x10]	9717	1			T1	5		T3	6		T8	22
valid_sources[0x11]	9517	1			T1	7		T3	5		T8	16
valid_sources[0x12]	9826	1			T1	8		T3	8		T5	17
valid_sources[0x13]	11158	1			T1	13		T3	5		T8	39
valid_sources[0x14]	11090	1			T1	7		T3	5		T5	34
valid_sources[0x15]	9970	1			T1	3		T3	8		T8	29
valid_sources[0x16]	9599	1			T1	9		T3	7		T8	21
valid_sources[0x17]	9869	1			T1	6		T3	5		T5	17
valid_sources[0x18]	9743	1			T1	7		T3	8		T8	14
valid_sources[0x19]	9852	1			T1	10		T3	9		T8	32
valid_sources[0x1a]	12165	1			T1	11		T3	7		T8	33
valid_sources[0x1b]	9477	1			T1	4		T2	19		T3	7
valid_sources[0x1c]	9755	1			T1	8		T3	3		T8	18
valid_sources[0x1d]	9601	1			T1	11		T3	8		T8	72
valid_sources[0x1e]	11659	1			T1	1		T2	1		T3	4
valid_sources[0x1f]	9928	1			T1	8		T3	7		T8	29
valid_sources[0x20]	9475	1			T1	6		T3	7		T8	22
valid_sources[0x21]	9776	1			T1	6		T3	7		T8	36
valid_sources[0x22]	9664	1			T1	7		T3	5		T8	31
valid_sources[0x23]	9534	1			T1	6		T3	6		T8	24
valid_sources[0x24]	9820	1			T1	9		T3	4		T8	23
valid_sources[0x25]	9662	1			T1	11		T2	9		T3	4
valid_sources[0x26]	9876	1			T1	5		T2	12		T3	9
valid_sources[0x27]	9825	1			T1	4		T3	10		T8	35
valid_sources[0x28]	9969	1			T1	5		T3	5		T8	42
valid_sources[0x29]	13171	1			T1	3		T3	5		T8	26
valid_sources[0x2a]	10022	1			T1	7		T3	6		T8	9
valid_sources[0x2b]	9888	1			T1	4		T3	6		T8	40
valid_sources[0x2c]	11287	1			T1	16		T3	5		T8	37
valid_sources[0x2d]	9901	1			T1	3		T3	5		T8	23
valid_sources[0x2e]	9556	1			T1	5		T2	15		T3	7
valid_sources[0x2f]	11907	1			T1	4		T2	4		T3	3
valid_sources[0x30]	9610	1			T1	4		T3	7		T8	26
valid_sources[0x31]	9823	1			T1	10		T2	2		T3	9
valid_sources[0x32]	9720	1			T1	6		T2	13		T3	13
valid_sources[0x33]	10654	1			T1	4		T3	10		T8	34
valid_sources[0x34]	9829	1			T1	3		T3	10		T8	43
valid_sources[0x35]	18237	1			T1	9		T3	6		T8	9
valid_sources[0x36]	9764	1			T1	7		T3	4		T5	17
valid_sources[0x37]	10847	1			T1	6		T3	11		T8	40
valid_sources[0x38]	9368	1			T1	5		T3	5		T8	22
valid_sources[0x39]	9706	1			T1	6		T3	2		T8	12
valid_sources[0x3a]	9891	1			T1	7		T3	3		T8	28
valid_sources[0x3b]	11179	1			T1	6		T3	10		T8	27
valid_sources[0x3c]	9690	1			T1	3		T3	10		T8	13
valid_sources[0x3d]	10006	1			T1	11		T3	8		T8	16
valid_sources[0x3e]	9652	1			T1	7		T3	6		T8	33
valid_sources[0x3f]	12283	1			T1	8		T3	4		T8	14
valid_sources[0x40]	9940	1			T1	5		T3	14		T8	15
valid_sources[0x41]	10749	1			T1	11		T3	4		T8	20
valid_sources[0x42]	11822	1			T1	4		T3	5		T8	24
valid_sources[0x43]	9495	1			T1	8		T3	3		T8	20
valid_sources[0x44]	9387	1			T2	9		T3	7		T8	34
valid_sources[0x45]	9836	1			T1	10		T3	4		T8	36
valid_sources[0x46]	12023	1			T1	4		T3	10		T8	36
valid_sources[0x47]	11722	1			T1	5		T3	6		T8	17
valid_sources[0x48]	9682	1			T1	8		T3	14		T8	30
valid_sources[0x49]	9841	1			T1	6		T3	7		T8	20
valid_sources[0x4a]	9545	1			T1	5		T3	4		T8	31
valid_sources[0x4b]	11773	1			T1	5		T3	7		T8	35
valid_sources[0x4c]	9842	1			T1	7		T3	1		T8	28
valid_sources[0x4d]	9924	1			T1	5		T3	4		T8	38
valid_sources[0x4e]	9894	1			T1	6		T3	8		T8	17
valid_sources[0x4f]	12068	1			T1	5		T3	4		T8	54
valid_sources[0x50]	9485	1			T1	6		T3	10		T8	33
valid_sources[0x51]	30455	1			T1	3		T3	3		T8	23
valid_sources[0x52]	9408	1			T1	12		T3	9		T8	37
valid_sources[0x53]	10529	1			T1	15		T3	6		T8	55
valid_sources[0x54]	9441	1			T1	3		T3	3		T8	27
valid_sources[0x55]	14169	1			T1	7		T2	8		T3	3
valid_sources[0x56]	9771	1			T1	7		T3	5		T8	24
valid_sources[0x57]	10909	1			T1	12		T3	2		T8	25
valid_sources[0x58]	10988	1			T1	9		T3	6		T8	10
valid_sources[0x59]	11117	1			T1	8		T3	6		T8	16
valid_sources[0x5a]	10102	1			T1	4		T3	3		T8	42
valid_sources[0x5b]	14277	1			T1	3		T3	7		T8	32
valid_sources[0x5c]	10020	1			T1	7		T2	3		T3	7
valid_sources[0x5d]	9560	1			T1	7		T3	11		T8	27
valid_sources[0x5e]	10342	1			T1	1		T3	4		T8	38
valid_sources[0x5f]	9855	1			T1	8		T3	5		T8	41
valid_sources[0x60]	17813	1			T1	11		T3	2		T8	29
valid_sources[0x61]	11184	1			T1	11		T3	4		T5	17
valid_sources[0x62]	9849	1			T1	4		T3	2		T8	30
valid_sources[0x63]	11225	1			T1	5		T3	9		T4	1479
valid_sources[0x64]	9249	1			T1	4		T2	8		T3	7
valid_sources[0x65]	11492	1			T1	4		T3	6		T8	6
valid_sources[0x66]	12743	1			T1	4		T3	2		T8	9
valid_sources[0x67]	10008	1			T1	12		T3	7		T8	28
valid_sources[0x68]	9655	1			T1	11		T3	5		T8	15
valid_sources[0x69]	13124	1			T1	5		T3	4		T8	10
valid_sources[0x6a]	9992	1			T1	15		T3	5		T8	17
valid_sources[0x6b]	11270	1			T1	8		T3	8		T8	16
valid_sources[0x6c]	13683	1			T1	3		T3	9		T8	45
valid_sources[0x6d]	10470	1			T1	4		T3	3		T8	35
valid_sources[0x6e]	119393	1			T1	6		T3	4		T8	20
valid_sources[0x6f]	9999	1			T1	2		T2	19		T3	9
valid_sources[0x70]	10706	1			T1	5		T3	6		T8	31
valid_sources[0x71]	13210	1			T1	9		T2	18		T3	13
valid_sources[0x72]	9996	1			T1	7		T3	7		T8	24
valid_sources[0x73]	11094	1			T1	14		T3	6		T8	17
valid_sources[0x74]	12963	1			T1	3		T3	6		T8	40
valid_sources[0x75]	9485	1			T1	5		T3	3		T8	27
valid_sources[0x76]	10010	1			T1	5		T3	5		T8	46
valid_sources[0x77]	9816	1			T1	10		T2	1		T3	9
valid_sources[0x78]	10641	1			T1	6		T3	7		T8	37
valid_sources[0x79]	9706	1			T1	8		T3	6		T8	47
valid_sources[0x7a]	10051	1			T1	9		T2	8		T3	9
valid_sources[0x7b]	9340	1			T1	8		T3	6		T8	16
valid_sources[0x7c]	13064	1			T1	4		T2	30		T3	7
valid_sources[0x7d]	9994	1			T1	5		T2	1		T3	15
valid_sources[0x7e]	9772	1			T1	20		T3	6		T8	35
valid_sources[0x7f]	9532	1			T1	3		T3	2		T8	23
valid_sources[0x80]	10888	1			T1	5		T3	7		T8	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1360632

1

T1

641

T2

94

T3

687

values[0x0]

all_enables

biggest_size

146258

1

T1

206

T2

63

T3

66

values[0x1]

all_enables

biggest_size

145131

1

T1

193

T2

65

T3

81