Line Coverage for Module : 
prim_sync_reqack_data
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 7 | 7 | 100.00 | 
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 | 
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 | 
| ALWAYS | 83 | 4 | 4 | 100.00 | 
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 80 | 
1 | 
1 | 
| 81 | 
1 | 
1 | 
| 83 | 
1 | 
1 | 
| 84 | 
1 | 
1 | 
| 85 | 
1 | 
1 | 
| 86 | 
1 | 
1 | 
 | 
 | 
 | 
     MISSING_ELSE | 
| 89 | 
1 | 
1 | 
Cond Coverage for Module : 
prim_sync_reqack_data
 | Total | Covered | Percent | 
| Conditions | 3 | 3 | 100.00 | 
| Logical | 3 | 3 | 100.00 | 
| Non-Logical | 0 | 0 |  | 
| Event | 0 | 0 |  | 
 LINE       80
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
| -1- | -2- | Status | Tests |                       
| 0 | 1 | Covered | T10,T34,T36 | 
| 1 | 0 | Covered | T1,T3,T4 | 
| 1 | 1 | Covered | T1,T3,T4 | 
Branch Coverage for Module : 
prim_sync_reqack_data
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
3 | 
3 | 
100.00 | 
| IF | 
83 | 
3 | 
3 | 
100.00 | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	83	if ((!rst_dst_ni))
-2-:	85	if (gen_data_reg.data_we)
Branches:
| -1- | -2- | Status | Tests | 
| 1 | 
- | 
Covered | 
T1,T2,T3 | 
| 0 | 
1 | 
Covered | 
T1,T3,T4 | 
| 0 | 
0 | 
Covered | 
T1,T2,T3 |