Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106801029	13098	0	0
claim_transition_if_regwen_rd_A	106801029	1439	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106801029	13098	0	0
T5	431022	2	0	0
T8	104115	0	0	0
T9	27034	0	0	0
T10	40624	0	0	0
T11	342355	20	0	0
T12	17305	0	0	0
T14	7118	0	0	0
T15	33030	0	0	0
T25	0	1	0	0
T27	0	10	0	0
T34	29502	0	0	0
T52	20920	0	0	0
T127	0	7	0	0
T128	0	4	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	3	0	0
T132	0	11	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106801029	1439	0	0
T82	126702	0	0	0
T86	0	46	0	0
T87	0	14	0	0
T94	0	12	0	0
T127	297321	11	0	0
T133	0	8	0	0
T134	0	8	0	0
T135	0	27	0	0
T136	0	11	0	0
T137	0	3	0	0
T138	0	28	0	0
T139	28877	0	0	0
T140	23413	0	0	0
T141	60308	0	0	0
T142	93308	0	0	0
T143	8509	0	0	0
T144	19633	0	0	0
T145	3918	0	0	0
T146	138968	0	0	0