Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.64 100.00 55.56 75.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic 75.00 75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic 75.00 75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00


Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Toggle Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
clk1_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
sel_i No No No INPUT
clk_o Yes Yes T2,T3,T5 Yes T2,T3,T5 OUTPUT

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 95618465 95616833 0 0
selKnown1 104580479 104578847 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 95618465 95616833 0 0
T1 58 57 0 0
T2 66030 66028 0 0
T3 262845 262843 0 0
T4 70 68 0 0
T5 530504 530503 0 0
T6 0 47088 0 0
T7 0 32631 0 0
T8 101 99 0 0
T9 71 69 0 0
T10 90 88 0 0
T11 272728 272727 0 0
T12 70 68 0 0
T14 12168 12167 0 0
T15 0 45616 0 0
T16 0 55896 0 0
T17 0 137884 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 104580479 104578847 0 0
T1 37371 37370 0 0
T2 36573 36571 0 0
T3 426538 426536 0 0
T4 33987 33985 0 0
T5 431023 431022 0 0
T6 0 3 0 0
T7 0 3 0 0
T8 104116 104114 0 0
T9 27035 27033 0 0
T10 40625 40623 0 0
T11 342356 342355 0 0
T12 17306 17304 0 0
T14 1 0 0 0
T18 0 5 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 0 2 0 0
T22 0 1 0 0
T23 0 1 0 0
T24 0 1 0 0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
clk1_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
sel_i No No No INPUT
clk_o Yes Yes T2,T3,T5 Yes T2,T3,T5 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
clk1_i Yes Yes T2,T6,T7 Yes T2,T6,T7 INPUT
sel_i No No No INPUT
clk_o Yes Yes T2,T3,T5 Yes T2,T3,T5 OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT2,T3,T5
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T5
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 95561297 95560481 0 0
selKnown1 104579554 104578738 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 95561297 95560481 0 0
T2 66029 66028 0 0
T3 262740 262739 0 0
T4 1 0 0 0
T5 529094 529094 0 0
T6 0 47088 0 0
T7 0 32631 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T11 271862 271862 0 0
T12 1 0 0 0
T14 12168 12167 0 0
T15 0 45604 0 0
T16 0 55896 0 0
T17 0 137884 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 104579554 104578738 0 0
T1 37371 37370 0 0
T2 36568 36567 0 0
T3 426537 426536 0 0
T4 33986 33985 0 0
T5 431022 431022 0 0
T8 104115 104114 0 0
T9 27034 27033 0 0
T10 40624 40623 0 0
T11 342355 342355 0 0
T12 17305 17304 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 57168 56352 0 0
selKnown1 925 109 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 57168 56352 0 0
T1 58 57 0 0
T2 1 0 0 0
T3 105 104 0 0
T4 69 68 0 0
T5 1410 1409 0 0
T8 100 99 0 0
T9 70 69 0 0
T10 89 88 0 0
T11 866 865 0 0
T12 69 68 0 0
T15 0 12 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 925 109 0 0
T2 5 4 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 0 3 0 0
T7 0 3 0 0
T8 1 0 0 0
T9 1 0 0 0
T10 1 0 0 0
T11 1 0 0 0
T12 1 0 0 0
T14 1 0 0 0
T18 0 5 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 0 2 0 0
T22 0 1 0 0
T23 0 1 0 0
T24 0 1 0 0

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