Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1697747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1918862

1

T1

197

T2

744

T3

2119

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3268165	1			T1	157		T2	341		T3	3078
values[0x0]	174061	1			T1	62		T2	313		T3	330
values[0x1]	174383	1			T1	66		T2	335		T3	342

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1349584	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2267025

1

T1

213

T2

802

T3

2469

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10578	1			T1	4		T10	1		T11	2
valid_sources[0x01]	11533	1			T1	2		T11	6		T12	7
valid_sources[0x02]	12456	1			T11	5		T12	7		T14	7
valid_sources[0x03]	10779	1			T1	3		T2	1		T11	3
valid_sources[0x04]	104876	1			T11	3		T12	3		T13	4
valid_sources[0x05]	12430	1			T2	17		T10	1		T11	2
valid_sources[0x06]	48905	1			T11	3		T12	4		T13	6
valid_sources[0x07]	20601	1			T1	2		T11	3		T12	6
valid_sources[0x08]	11122	1			T11	3		T12	6		T13	4
valid_sources[0x09]	10945	1			T1	1		T11	1		T12	5
valid_sources[0x0a]	11503	1			T10	1		T11	1		T12	3
valid_sources[0x0b]	13783	1			T11	4		T12	9		T13	13
valid_sources[0x0c]	11698	1			T1	2		T2	39		T11	3
valid_sources[0x0d]	10615	1			T10	1		T11	4		T12	3
valid_sources[0x0e]	12008	1			T1	2		T11	1		T12	2
valid_sources[0x0f]	11023	1			T11	2		T12	4		T13	3
valid_sources[0x10]	11815	1			T11	3		T12	2		T13	9
valid_sources[0x11]	10747	1			T11	2		T12	2		T13	7
valid_sources[0x12]	13628	1			T2	38		T11	2		T12	3
valid_sources[0x13]	11176	1			T12	4		T13	10		T14	3
valid_sources[0x14]	13162	1			T11	3		T12	2		T13	1
valid_sources[0x15]	10892	1			T11	4		T12	3		T13	2
valid_sources[0x16]	11470	1			T11	3		T12	5		T13	1
valid_sources[0x17]	15045	1			T1	25		T11	2		T12	9
valid_sources[0x18]	11069	1			T11	2		T12	4		T13	2
valid_sources[0x19]	11222	1			T11	1		T12	2		T13	1
valid_sources[0x1a]	10894	1			T11	2		T12	1		T13	1
valid_sources[0x1b]	11273	1			T1	2		T11	3		T12	8
valid_sources[0x1c]	12693	1			T11	5		T12	5		T13	3
valid_sources[0x1d]	11206	1			T11	4		T12	5		T13	4
valid_sources[0x1e]	11188	1			T1	22		T11	1		T12	3
valid_sources[0x1f]	10889	1			T1	3		T11	7		T12	5
valid_sources[0x20]	11005	1			T12	2		T13	2		T14	1
valid_sources[0x21]	11330	1			T11	5		T12	1		T14	9
valid_sources[0x22]	10733	1			T11	2		T12	11		T14	7
valid_sources[0x23]	12658	1			T2	12		T11	1		T12	5
valid_sources[0x24]	29874	1			T11	2		T12	4		T14	6
valid_sources[0x25]	13361	1			T11	3		T12	7		T13	1
valid_sources[0x26]	12622	1			T1	3		T10	1		T11	2
valid_sources[0x27]	11157	1			T2	13		T11	5		T12	2
valid_sources[0x28]	11006	1			T1	4		T11	4		T12	10
valid_sources[0x29]	10731	1			T10	1		T11	2		T12	4
valid_sources[0x2a]	12015	1			T11	2		T12	2		T13	7
valid_sources[0x2b]	11429	1			T11	6		T12	3		T13	6
valid_sources[0x2c]	11374	1			T10	3		T11	1		T12	6
valid_sources[0x2d]	12042	1			T2	55		T10	1		T11	1
valid_sources[0x2e]	11413	1			T11	2		T12	3		T13	3
valid_sources[0x2f]	12109	1			T11	3		T12	8		T13	6
valid_sources[0x30]	18815	1			T11	2		T12	1		T13	1
valid_sources[0x31]	11350	1			T12	3		T13	8		T14	8
valid_sources[0x32]	11036	1			T2	86		T11	3		T12	4
valid_sources[0x33]	14804	1			T11	4		T12	3		T13	6
valid_sources[0x34]	12404	1			T11	3		T12	6		T14	5
valid_sources[0x35]	11012	1			T1	8		T12	1		T13	1
valid_sources[0x36]	10953	1			T11	2		T12	3		T14	7
valid_sources[0x37]	12941	1			T11	1		T12	5		T13	6
valid_sources[0x38]	11378	1			T10	1		T11	3		T12	2
valid_sources[0x39]	13481	1			T11	5		T12	4		T13	3
valid_sources[0x3a]	11171	1			T12	5		T13	3		T14	5
valid_sources[0x3b]	11907	1			T11	3		T12	2		T13	2
valid_sources[0x3c]	11420	1			T11	5		T12	3		T13	6
valid_sources[0x3d]	11565	1			T11	2		T12	1		T13	1
valid_sources[0x3e]	12852	1			T11	3		T12	1		T13	1
valid_sources[0x3f]	11980	1			T11	4		T12	2		T13	1
valid_sources[0x40]	10796	1			T11	4		T12	5		T14	5
valid_sources[0x41]	22574	1			T1	9		T2	38		T11	1
valid_sources[0x42]	11281	1			T11	2		T13	6		T14	3
valid_sources[0x43]	14100	1			T2	110		T10	1		T11	6
valid_sources[0x44]	10961	1			T10	1		T11	2		T12	3
valid_sources[0x45]	11312	1			T1	12		T10	1		T11	1
valid_sources[0x46]	13212	1			T10	5		T11	2		T12	4
valid_sources[0x47]	11159	1			T11	4		T12	3		T14	8
valid_sources[0x48]	11005	1			T1	2		T11	3		T12	4
valid_sources[0x49]	14454	1			T11	1		T12	5		T14	6
valid_sources[0x4a]	11313	1			T11	3		T12	8		T13	1
valid_sources[0x4b]	13216	1			T2	23		T11	5		T12	2
valid_sources[0x4c]	13320	1			T10	1		T11	5		T12	5
valid_sources[0x4d]	11635	1			T12	6		T13	7		T14	7
valid_sources[0x4e]	11014	1			T12	8		T13	5		T14	9
valid_sources[0x4f]	11163	1			T1	8		T11	6		T12	7
valid_sources[0x50]	11010	1			T12	8		T13	1		T14	6
valid_sources[0x51]	10861	1			T1	4		T2	20		T11	4
valid_sources[0x52]	12353	1			T10	1		T11	5		T12	8
valid_sources[0x53]	12669	1			T2	16		T11	3		T12	4
valid_sources[0x54]	15298	1			T11	2		T14	7		T22	5
valid_sources[0x55]	13370	1			T1	4		T10	1		T11	4
valid_sources[0x56]	12181	1			T2	28		T11	3		T12	3
valid_sources[0x57]	10863	1			T10	1		T11	3		T12	1
valid_sources[0x58]	10742	1			T11	1		T12	4		T13	3
valid_sources[0x59]	11131	1			T1	5		T10	2		T11	1
valid_sources[0x5a]	11073	1			T11	1		T12	2		T13	10
valid_sources[0x5b]	11199	1			T11	1		T13	5		T14	6
valid_sources[0x5c]	10948	1			T1	2		T2	5		T11	2
valid_sources[0x5d]	11818	1			T11	2		T12	5		T13	5
valid_sources[0x5e]	13175	1			T11	1		T12	3		T13	1
valid_sources[0x5f]	11099	1			T10	1		T11	3		T12	4
valid_sources[0x60]	10893	1			T11	2		T12	3		T13	5
valid_sources[0x61]	11508	1			T11	3		T12	2		T13	1
valid_sources[0x62]	13304	1			T11	4		T12	4		T14	4
valid_sources[0x63]	10749	1			T1	5		T12	4		T13	5
valid_sources[0x64]	93942	1			T11	1		T12	5		T13	6
valid_sources[0x65]	11346	1			T11	2		T12	2		T13	2
valid_sources[0x66]	10993	1			T2	5		T10	1		T11	3
valid_sources[0x67]	10808	1			T11	1		T12	3		T13	6
valid_sources[0x68]	37498	1			T10	1		T11	3		T12	7
valid_sources[0x69]	11561	1			T11	1		T12	5		T13	1
valid_sources[0x6a]	12654	1			T2	26		T11	4		T12	3
valid_sources[0x6b]	11488	1			T10	1		T11	2		T12	1
valid_sources[0x6c]	10812	1			T11	3		T12	3		T13	4
valid_sources[0x6d]	10775	1			T11	1		T12	4		T13	5
valid_sources[0x6e]	11279	1			T11	1		T12	7		T13	3
valid_sources[0x6f]	11768	1			T1	3		T2	37		T11	8
valid_sources[0x70]	11315	1			T11	3		T12	4		T13	3
valid_sources[0x71]	13718	1			T2	68		T11	5		T12	3
valid_sources[0x72]	11518	1			T1	5		T11	4		T12	4
valid_sources[0x73]	10870	1			T1	5		T11	3		T12	1
valid_sources[0x74]	11152	1			T11	3		T12	5		T13	3
valid_sources[0x75]	10779	1			T11	2		T12	3		T13	5
valid_sources[0x76]	10999	1			T12	4		T13	1		T14	4
valid_sources[0x77]	25528	1			T2	7		T11	1		T12	3
valid_sources[0x78]	12708	1			T2	53		T11	2		T12	9
valid_sources[0x79]	11656	1			T11	2		T12	5		T13	10
valid_sources[0x7a]	11173	1			T11	2		T12	1		T14	5
valid_sources[0x7b]	12109	1			T11	3		T12	9		T14	5
valid_sources[0x7c]	11216	1			T11	3		T12	4		T14	7
valid_sources[0x7d]	24846	1			T11	1		T12	2		T13	2
valid_sources[0x7e]	14381	1			T11	4		T12	5		T14	2
valid_sources[0x7f]	12612	1			T12	4		T14	7		T22	10
valid_sources[0x80]	12654	1			T11	3		T12	9		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1619030

1

T1

80

T2

164

T3

1538

values[0x0]

all_enables

biggest_size

150692

1

T1

55

T2

281

T3

292

values[0x1]

all_enables

biggest_size

149140

1

T1

62

T2

299

T3

289