Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	107704385	16185	0	0
claim_transition_if_regwen_rd_A	107704385	1751	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107704385	16185	0	0
T18	156794	8	0	0
T24	19370	0	0	0
T25	26655	0	0	0
T37	7781	0	0	0
T38	1324	0	0	0
T39	31949	0	0	0
T40	0	2	0	0
T43	0	3	0	0
T44	0	1	0	0
T65	24809	0	0	0
T94	0	1	0	0
T100	20032	0	0	0
T106	0	9	0	0
T142	0	6	0	0
T143	0	17	0	0
T144	0	3	0	0
T145	0	1	0	0
T146	1111	0	0	0
T147	63946	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107704385	1751	0	0
T99	0	3	0	0
T111	0	19	0	0
T114	0	74	0	0
T133	0	46	0	0
T148	333011	12	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	7	0	0
T152	0	20	0	0
T153	0	17	0	0
T154	38236	0	0	0
T155	2039	0	0	0
T156	145363	0	0	0
T157	243136	0	0	0
T158	1194	0	0	0
T159	34106	0	0	0
T160	138180	0	0	0
T161	5816	0	0	0
T162	3396	0	0	0