Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1742215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1965567

1

T1

954

T2

754

T3

103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3358649	1			T1	757		T2	602		T3	93
values[0x0]	174072	1			T1	332		T2	286		T3	54
values[0x1]	175061	1			T1	348		T2	290		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1385070	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2322712

1

T1

1076

T2

847

T3

129

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12645	1			T1	10		T10	3		T5	271
valid_sources[0x01]	13592	1			T1	10		T10	10		T5	323
valid_sources[0x02]	36117	1			T1	3		T3	1		T10	8
valid_sources[0x03]	11999	1			T1	6		T3	2		T10	5
valid_sources[0x04]	11462	1			T1	8		T3	1		T10	2
valid_sources[0x05]	15611	1			T3	1		T10	4		T5	330
valid_sources[0x06]	12126	1			T1	9		T10	2		T5	318
valid_sources[0x07]	11390	1			T1	3		T3	3		T10	6
valid_sources[0x08]	13661	1			T1	9		T10	8		T5	280
valid_sources[0x09]	13466	1			T1	1		T3	3		T10	9
valid_sources[0x0a]	14011	1			T1	6		T10	13		T5	239
valid_sources[0x0b]	13327	1			T1	6		T3	2		T10	3
valid_sources[0x0c]	12852	1			T1	7		T10	1		T5	294
valid_sources[0x0d]	12157	1			T1	9		T10	7		T5	302
valid_sources[0x0e]	14071	1			T1	5		T10	8		T5	265
valid_sources[0x0f]	12302	1			T10	7		T5	250		T6	1
valid_sources[0x10]	40840	1			T1	4		T10	3		T5	296
valid_sources[0x11]	11685	1			T1	16		T10	6		T5	284
valid_sources[0x12]	12959	1			T1	9		T3	1		T10	13
valid_sources[0x13]	12425	1			T3	1		T10	8		T5	330
valid_sources[0x14]	13902	1			T1	3		T10	5		T5	245
valid_sources[0x15]	12124	1			T10	5		T5	285		T6	2
valid_sources[0x16]	12002	1			T1	10		T3	2		T10	3
valid_sources[0x17]	11612	1			T1	4		T3	2		T10	4
valid_sources[0x18]	11998	1			T1	6		T10	3		T5	286
valid_sources[0x19]	13370	1			T1	7		T10	7		T5	255
valid_sources[0x1a]	12546	1			T1	7		T10	3		T5	267
valid_sources[0x1b]	11668	1			T1	7		T10	4		T5	308
valid_sources[0x1c]	13061	1			T1	1		T3	2		T10	2
valid_sources[0x1d]	11265	1			T1	4		T10	3		T5	250
valid_sources[0x1e]	11900	1			T1	6		T10	8		T5	285
valid_sources[0x1f]	12604	1			T1	4		T3	2		T10	6
valid_sources[0x20]	12401	1			T1	11		T3	1		T10	3
valid_sources[0x21]	12020	1			T1	15		T10	1		T5	293
valid_sources[0x22]	13419	1			T1	5		T10	7		T5	293
valid_sources[0x23]	49632	1			T1	5		T10	2		T5	314
valid_sources[0x24]	12299	1			T1	1		T10	7		T5	279
valid_sources[0x25]	11880	1			T1	9		T3	1		T10	2
valid_sources[0x26]	11583	1			T1	6		T3	1		T10	7
valid_sources[0x27]	13704	1			T1	3		T10	8		T5	282
valid_sources[0x28]	15156	1			T1	14		T3	1		T10	3
valid_sources[0x29]	12338	1			T1	8		T10	4		T5	294
valid_sources[0x2a]	12419	1			T1	11		T10	6		T5	266
valid_sources[0x2b]	12057	1			T3	1		T10	5		T5	282
valid_sources[0x2c]	12240	1			T1	8		T3	1		T10	8
valid_sources[0x2d]	11874	1			T1	5		T3	1		T10	7
valid_sources[0x2e]	12854	1			T1	4		T3	1		T10	3
valid_sources[0x2f]	12232	1			T1	13		T10	10		T5	293
valid_sources[0x30]	13949	1			T1	5		T3	1		T10	2
valid_sources[0x31]	15399	1			T1	9		T3	1		T10	2
valid_sources[0x32]	12094	1			T1	6		T10	9		T5	247
valid_sources[0x33]	11914	1			T10	3		T5	289		T12	6
valid_sources[0x34]	21091	1			T1	5		T10	7		T5	299
valid_sources[0x35]	12297	1			T1	5		T3	2		T10	8
valid_sources[0x36]	13186	1			T1	4		T10	7		T5	258
valid_sources[0x37]	15452	1			T1	10		T10	5		T5	292
valid_sources[0x38]	14056	1			T1	11		T3	1		T10	8
valid_sources[0x39]	33537	1			T1	5		T10	9		T5	272
valid_sources[0x3a]	13848	1			T1	5		T3	3		T10	2
valid_sources[0x3b]	11841	1			T1	9		T3	1		T10	10
valid_sources[0x3c]	12133	1			T1	6		T3	1		T10	6
valid_sources[0x3d]	12226	1			T1	6		T10	1		T5	305
valid_sources[0x3e]	11995	1			T1	12		T10	5		T5	257
valid_sources[0x3f]	12010	1			T1	20		T10	5		T5	300
valid_sources[0x40]	16753	1			T3	1		T10	12		T5	285
valid_sources[0x41]	11894	1			T1	6		T10	4		T5	344
valid_sources[0x42]	13067	1			T1	1		T3	1		T10	7
valid_sources[0x43]	13350	1			T1	5		T3	3		T10	11
valid_sources[0x44]	12601	1			T1	8		T10	4		T5	316
valid_sources[0x45]	13698	1			T1	6		T5	295		T12	5
valid_sources[0x46]	11701	1			T1	1		T3	2		T10	4
valid_sources[0x47]	13051	1			T1	5		T3	1		T10	3
valid_sources[0x48]	12438	1			T1	4		T3	1		T10	7
valid_sources[0x49]	14768	1			T1	5		T10	4		T5	279
valid_sources[0x4a]	13440	1			T1	1		T3	1		T10	10
valid_sources[0x4b]	11886	1			T1	10		T10	13		T5	294
valid_sources[0x4c]	12151	1			T1	5		T10	11		T5	273
valid_sources[0x4d]	12588	1			T1	2		T10	13		T5	280
valid_sources[0x4e]	12257	1			T1	2		T10	8		T5	287
valid_sources[0x4f]	12382	1			T1	7		T3	3		T10	12
valid_sources[0x50]	13507	1			T1	4		T10	8		T5	246
valid_sources[0x51]	15395	1			T1	3		T3	1		T10	6
valid_sources[0x52]	11561	1			T1	7		T3	1		T10	9
valid_sources[0x53]	11788	1			T1	2		T3	4		T10	9
valid_sources[0x54]	13966	1			T1	4		T3	2		T10	9
valid_sources[0x55]	13333	1			T1	3		T10	4		T5	293
valid_sources[0x56]	13344	1			T1	7		T3	3		T10	12
valid_sources[0x57]	11864	1			T1	13		T10	2		T5	301
valid_sources[0x58]	12064	1			T1	6		T10	3		T5	320
valid_sources[0x59]	11938	1			T1	1		T10	8		T5	241
valid_sources[0x5a]	11741	1			T1	1		T3	1		T10	7
valid_sources[0x5b]	13681	1			T1	9		T3	1		T10	1
valid_sources[0x5c]	11753	1			T1	5		T10	8		T5	278
valid_sources[0x5d]	11733	1			T1	5		T10	2		T5	325
valid_sources[0x5e]	31487	1			T1	3		T3	1		T10	6
valid_sources[0x5f]	12589	1			T1	12		T3	2		T10	8
valid_sources[0x60]	11764	1			T1	3		T10	5		T5	283
valid_sources[0x61]	13151	1			T1	14		T10	9		T5	209
valid_sources[0x62]	11607	1			T1	9		T10	3		T5	295
valid_sources[0x63]	15823	1			T1	2		T3	1		T10	9
valid_sources[0x64]	28687	1			T1	3		T10	2		T5	303
valid_sources[0x65]	20759	1			T10	5		T5	310		T6	3
valid_sources[0x66]	11774	1			T1	6		T3	2		T10	6
valid_sources[0x67]	13456	1			T1	9		T10	6		T5	261
valid_sources[0x68]	12715	1			T1	6		T10	2		T5	354
valid_sources[0x69]	11906	1			T1	7		T10	3		T5	307
valid_sources[0x6a]	11299	1			T1	9		T10	10		T5	249
valid_sources[0x6b]	12668	1			T1	2		T10	7		T5	237
valid_sources[0x6c]	12122	1			T1	3		T10	4		T5	241
valid_sources[0x6d]	12837	1			T1	8		T3	1		T10	7
valid_sources[0x6e]	11804	1			T1	18		T3	1		T10	9
valid_sources[0x6f]	12239	1			T1	5		T3	3		T10	6
valid_sources[0x70]	12405	1			T1	6		T3	1		T10	6
valid_sources[0x71]	12242	1			T1	7		T10	2		T5	258
valid_sources[0x72]	13513	1			T1	2		T10	7		T5	333
valid_sources[0x73]	11758	1			T1	3		T3	1		T10	7
valid_sources[0x74]	32026	1			T1	7		T3	2		T10	8
valid_sources[0x75]	12048	1			T1	1		T3	1		T10	4
valid_sources[0x76]	12765	1			T1	4		T3	1		T10	3
valid_sources[0x77]	11529	1			T1	1		T10	7		T5	265
valid_sources[0x78]	11812	1			T1	4		T3	3		T10	10
valid_sources[0x79]	12198	1			T1	2		T10	3		T5	314
valid_sources[0x7a]	12949	1			T1	5		T3	3		T10	5
valid_sources[0x7b]	13338	1			T1	6		T3	1		T10	8
valid_sources[0x7c]	13074	1			T1	5		T10	4		T5	301
valid_sources[0x7d]	13728	1			T1	7		T10	5		T5	285
valid_sources[0x7e]	11695	1			T10	4		T5	306		T30	5
valid_sources[0x7f]	11919	1			T1	3		T3	3		T10	9
valid_sources[0x80]	16149	1			T1	2		T3	2		T10	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1665169

1

T1

355

T2

242

T3

32

values[0x0]

all_enables

biggest_size

150744

1

T1

297

T2

252

T3

51

values[0x1]

all_enables

biggest_size

149654

1

T1

302

T2

260

T3

20