Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	116351276	15050	0	0
claim_transition_if_regwen_rd_A	116351276	1733	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116351276	15050	0	0
T5	195107	2	0	0
T6	31218	0	0	0
T11	1987	0	0	0
T12	5630	0	0	0
T13	30493	0	0	0
T14	8457	0	0	0
T16	666	0	0	0
T18	0	1	0	0
T20	22308	0	0	0
T21	19971	0	0	0
T30	28254	0	0	0
T37	0	2	0	0
T48	0	6	0	0
T49	0	11	0	0
T52	0	9	0	0
T97	0	18	0	0
T102	0	10	0	0
T135	0	6	0	0
T136	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116351276	1733	0	0
T108	0	6	0	0
T109	0	21	0	0
T110	0	31	0	0
T121	0	77	0	0
T137	204387	9	0	0
T138	0	7	0	0
T139	0	5	0	0
T140	0	3	0	0
T141	0	18	0	0
T142	0	12	0	0
T143	4016	0	0	0
T144	2200	0	0	0
T145	801	0	0	0
T146	736195	0	0	0
T147	27427	0	0	0
T148	5495	0	0	0
T149	37946	0	0	0
T150	19369	0	0	0
T151	2810	0	0	0