Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1589046	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1819085

1

T2

4926

T3

44

T9

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3049704	1			T2	8419		T3	45		T9	75
values[0x0]	178706	1			T2	382		T3	15		T9	20
values[0x1]	179721	1			T2	418		T3	9		T9	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1260572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2147559

1

T2

5825

T3

52

T9

72

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9787	1			T2	39		T17	5		T21	5
valid_sources[0x01]	10380	1			T2	44		T24	7		T20	3
valid_sources[0x02]	10255	1			T2	26		T9	1		T24	6
valid_sources[0x03]	11707	1			T2	31		T24	2		T20	1
valid_sources[0x04]	10345	1			T2	35		T9	4		T24	2
valid_sources[0x05]	10101	1			T2	37		T24	8		T20	1
valid_sources[0x06]	10097	1			T2	35		T24	3		T20	3
valid_sources[0x07]	10688	1			T2	40		T24	2		T20	2
valid_sources[0x08]	10039	1			T2	37		T24	4		T17	5
valid_sources[0x09]	9526	1			T2	39		T9	1		T17	4
valid_sources[0x0a]	9976	1			T2	20		T24	2		T20	3
valid_sources[0x0b]	11207	1			T2	39		T24	6		T17	4
valid_sources[0x0c]	11654	1			T2	44		T24	4		T17	6
valid_sources[0x0d]	9965	1			T2	28		T24	3		T20	3
valid_sources[0x0e]	44503	1			T2	32		T24	3		T17	8
valid_sources[0x0f]	10586	1			T2	40		T20	1		T18	308
valid_sources[0x10]	10134	1			T2	26		T24	8		T17	7
valid_sources[0x11]	10454	1			T2	34		T24	3		T17	10
valid_sources[0x12]	10127	1			T2	33		T4	11		T24	6
valid_sources[0x13]	10070	1			T2	51		T24	3		T20	2
valid_sources[0x14]	10158	1			T2	33		T20	1		T17	1
valid_sources[0x15]	10595	1			T2	39		T11	8		T24	3
valid_sources[0x16]	12676	1			T2	28		T9	1		T24	4
valid_sources[0x17]	9781	1			T2	38		T9	2		T24	1
valid_sources[0x18]	14210	1			T2	31		T9	1		T24	2
valid_sources[0x19]	10015	1			T2	28		T24	4		T17	5
valid_sources[0x1a]	12813	1			T2	28		T24	1		T17	10
valid_sources[0x1b]	19045	1			T2	35		T24	3		T17	11
valid_sources[0x1c]	9865	1			T2	36		T24	4		T20	4
valid_sources[0x1d]	9597	1			T2	26		T9	1		T24	1
valid_sources[0x1e]	10317	1			T2	36		T4	25		T24	5
valid_sources[0x1f]	11544	1			T2	25		T9	1		T4	1
valid_sources[0x20]	28873	1			T2	46		T9	2		T24	3
valid_sources[0x21]	63552	1			T2	29		T24	3		T17	4
valid_sources[0x22]	9840	1			T2	31		T24	5		T17	5
valid_sources[0x23]	9661	1			T2	29		T4	30		T24	1
valid_sources[0x24]	10178	1			T2	31		T4	1		T24	1
valid_sources[0x25]	10076	1			T2	43		T24	1		T17	6
valid_sources[0x26]	10233	1			T2	32		T9	2		T24	1
valid_sources[0x27]	9945	1			T2	44		T24	4		T20	3
valid_sources[0x28]	12680	1			T2	47		T24	3		T20	1
valid_sources[0x29]	9928	1			T2	29		T9	1		T24	2
valid_sources[0x2a]	10208	1			T2	40		T24	2		T20	1
valid_sources[0x2b]	9678	1			T2	31		T24	7		T17	4
valid_sources[0x2c]	10120	1			T2	28		T24	3		T17	3
valid_sources[0x2d]	10106	1			T2	35		T24	4		T20	2
valid_sources[0x2e]	9784	1			T2	37		T9	2		T24	5
valid_sources[0x2f]	10055	1			T2	41		T24	1		T20	2
valid_sources[0x30]	11018	1			T2	36		T24	4		T20	1
valid_sources[0x31]	10066	1			T2	49		T24	9		T20	1
valid_sources[0x32]	10460	1			T2	42		T24	7		T17	2
valid_sources[0x33]	10813	1			T2	37		T24	2		T17	12
valid_sources[0x34]	9610	1			T2	33		T24	3		T17	4
valid_sources[0x35]	9978	1			T2	38		T9	2		T24	5
valid_sources[0x36]	10049	1			T2	34		T24	1		T20	1
valid_sources[0x37]	9891	1			T2	37		T24	3		T20	1
valid_sources[0x38]	10618	1			T2	29		T24	4		T20	1
valid_sources[0x39]	9362	1			T2	36		T24	2		T17	12
valid_sources[0x3a]	9897	1			T2	46		T9	1		T24	3
valid_sources[0x3b]	15368	1			T2	29		T9	2		T24	2
valid_sources[0x3c]	9870	1			T2	34		T24	3		T17	2
valid_sources[0x3d]	19541	1			T2	39		T9	1		T24	3
valid_sources[0x3e]	11262	1			T2	34		T24	4		T17	2
valid_sources[0x3f]	10127	1			T2	35		T24	3		T20	2
valid_sources[0x40]	9525	1			T2	37		T24	4		T17	5
valid_sources[0x41]	10200	1			T2	37		T24	4		T17	7
valid_sources[0x42]	23184	1			T2	27		T24	3		T20	2
valid_sources[0x43]	10320	1			T2	32		T24	6		T20	2
valid_sources[0x44]	12875	1			T2	33		T24	4		T17	4
valid_sources[0x45]	9711	1			T2	38		T24	5		T20	3
valid_sources[0x46]	17353	1			T2	35		T24	3		T17	15
valid_sources[0x47]	18115	1			T2	23		T24	5		T20	1
valid_sources[0x48]	11416	1			T2	28		T24	2		T20	1
valid_sources[0x49]	9810	1			T2	56		T24	2		T17	6
valid_sources[0x4a]	10296	1			T2	31		T24	5		T17	4
valid_sources[0x4b]	9855	1			T2	28		T24	2		T20	4
valid_sources[0x4c]	9694	1			T2	48		T4	1		T24	3
valid_sources[0x4d]	12902	1			T2	48		T24	3		T17	10
valid_sources[0x4e]	10001	1			T2	29		T24	3		T17	4
valid_sources[0x4f]	10463	1			T2	41		T24	3		T20	3
valid_sources[0x50]	9423	1			T2	33		T24	1		T17	3
valid_sources[0x51]	9723	1			T2	31		T24	3		T17	6
valid_sources[0x52]	11477	1			T2	40		T24	2		T20	3
valid_sources[0x53]	10242	1			T2	28		T9	1		T24	1
valid_sources[0x54]	12546	1			T2	40		T24	2		T17	1
valid_sources[0x55]	10151	1			T2	36		T24	2		T20	4
valid_sources[0x56]	10753	1			T2	33		T24	2		T17	1
valid_sources[0x57]	9889	1			T2	34		T24	2		T20	1
valid_sources[0x58]	14743	1			T2	45		T4	1		T24	4
valid_sources[0x59]	10208	1			T2	31		T4	4		T24	2
valid_sources[0x5a]	10007	1			T2	36		T24	3		T17	4
valid_sources[0x5b]	10377	1			T2	36		T24	1		T17	3
valid_sources[0x5c]	9921	1			T2	38		T24	5		T20	1
valid_sources[0x5d]	20760	1			T2	35		T24	2		T17	4
valid_sources[0x5e]	10624	1			T2	30		T24	2		T20	1
valid_sources[0x5f]	10564	1			T2	34		T9	1		T24	4
valid_sources[0x60]	10471	1			T2	29		T24	1		T17	2
valid_sources[0x61]	11925	1			T2	43		T24	2		T17	7
valid_sources[0x62]	10337	1			T2	35		T9	1		T24	10
valid_sources[0x63]	10040	1			T2	37		T9	2		T4	4
valid_sources[0x64]	9898	1			T2	46		T9	3		T11	1
valid_sources[0x65]	9446	1			T2	46		T24	1		T20	3
valid_sources[0x66]	10127	1			T2	32		T9	1		T24	10
valid_sources[0x67]	10376	1			T2	34		T24	1		T17	4
valid_sources[0x68]	10142	1			T2	33		T4	17		T24	2
valid_sources[0x69]	10266	1			T2	42		T24	2		T17	13
valid_sources[0x6a]	21166	1			T2	43		T24	5		T21	2
valid_sources[0x6b]	28247	1			T2	39		T24	3		T20	3
valid_sources[0x6c]	10054	1			T2	25		T24	4		T20	2
valid_sources[0x6d]	9953	1			T2	37		T24	2		T20	1
valid_sources[0x6e]	12281	1			T2	40		T24	3		T17	8
valid_sources[0x6f]	11195	1			T2	38		T24	4		T17	6
valid_sources[0x70]	9950	1			T2	29		T24	3		T17	8
valid_sources[0x71]	13309	1			T2	37		T24	2		T20	2
valid_sources[0x72]	10061	1			T2	35		T24	2		T17	6
valid_sources[0x73]	12319	1			T2	43		T24	8		T20	1
valid_sources[0x74]	9924	1			T2	41		T24	3		T20	4
valid_sources[0x75]	9740	1			T2	31		T9	1		T24	2
valid_sources[0x76]	9731	1			T2	36		T24	3		T20	2
valid_sources[0x77]	11416	1			T2	41		T4	8		T24	3
valid_sources[0x78]	9648	1			T2	34		T9	1		T24	4
valid_sources[0x79]	14134	1			T2	44		T3	69		T9	2
valid_sources[0x7a]	12550	1			T2	41		T24	3		T20	7
valid_sources[0x7b]	9751	1			T2	33		T9	1		T24	5
valid_sources[0x7c]	9645	1			T2	50		T9	4		T24	4
valid_sources[0x7d]	9592	1			T2	40		T24	6		T20	1
valid_sources[0x7e]	12425	1			T2	36		T9	3		T24	4
valid_sources[0x7f]	12600	1			T2	37		T4	19		T24	1
valid_sources[0x80]	13455	1			T2	33		T9	1		T24	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1510673

1

T2

4217

T3

22

T9

31

values[0x0]

all_enables

biggest_size

154751

1

T2

335

T3

14

T9

16

values[0x1]

all_enables

biggest_size

153661

1

T2

374

T3

8

T9

10