Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	111835915	13717	0	0
claim_transition_if_regwen_rd_A	111835915	1484	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111835915	13717	0	0
T14	552569	13	0	0
T15	24955	0	0	0
T16	42803	0	0	0
T27	226826	0	0	0
T35	33565	0	0	0
T36	20939	0	0	0
T38	0	3	0	0
T55	0	5	0	0
T57	0	20	0	0
T87	25271	0	0	0
T103	0	3	0	0
T104	0	13	0	0
T110	0	11	0	0
T141	0	1	0	0
T144	0	11	0	0
T145	0	4	0	0
T146	1336	0	0	0
T147	1429	0	0	0
T148	1469	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111835915	1484	0	0
T43	24710	0	0	0
T44	36041	0	0	0
T66	2684	0	0	0
T76	43431	0	0	0
T91	609247	8	0	0
T115	0	7	0	0
T116	0	12	0	0
T124	0	22	0	0
T149	0	18	0	0
T150	0	27	0	0
T151	0	10	0	0
T152	0	9	0	0
T153	0	17	0	0
T154	0	14	0	0
T155	133036	0	0	0
T156	68959	0	0	0
T157	12246	0	0	0
T158	4636	0	0	0
T159	219517	0	0	0